Adiabatic Differential Cascode Voltage Switch Logic (A-

DCVSL) for Low Power Applications

Kirti Guptaa, Vishwas Gosainb, Neeta Pandeyc
a
Dept. of Electronics and Communication, Bharati Vidyapeeth’s College of Engineering, New Delhi, India
b
Technology and Design Platform dept., STMicroelectronics, Greater Noida, India
c
Dept. of Electronics and Communication, Delhi Technological University, New Delhi, India

E-mails: Kirtigupta22@gmail.com, gosainvishwas@gmail.com(add ur affiliations and emails)

Abstract: In this paper, a new adiabatic logic family named as adiabatic differential
cascode voltage-switch logic (A-DCVSL) for low power applications is presented. The
family operates on a two-phase split level sinusoidal power clock instead of four-phase
trapezoidal power clock. The proposed A-DCVSL circuits reduce the power dissipation
by charge recovery and minimizing the peak current flow. The behavior of the inverter
is analysed and the power dissipation of A-DCVSL circuit is mathematically modeled.
The performance of A-DCVSL inverters is compared with other existing differential
adiabatic logic families. A full subtractor is also designed to exhibit the benefits at the
application level. The results confirm that the proposed A-DCVSL circuits outperforms
in terms of power dissipation and can be adapted to the design of lower power
applications.

Keywords: DCVSL, Adiabatic, differential, low power, energy recovery.

1. Introduction
Over the last recent years, the emerging paradigms of wearable and pervasive computing are
leading to an exponential growth in portable electronics. The trend is towards deploying
highly complex digital circuits in portable wireless devices. The focus has shifted towards the
design of systems, increased integration density and energy efficiency. Power dissipation is
one of the major hindrances in the design of high performance circuits to be used in portable
devices. Voltage scaling has been adopted in conventional CMOS circuits to reduce power
dissipation. However, it is accompanied by the degradation of circuit performance in terms of
speed and leakage power [1]. As an alternative, circuit design using energy recovering
circuits also referred to as adiabatic circuits, is suggested [2]. In adiabatic circuits,
transformation takes place sufficiently slow such that no gain or loss of heat occurs. The
charging and discharging of a node are made sufficiently slow so as to make it equivalent to a
charging/discharging by a current source. The DC power supply in conventional circuits is
being replaced by power clocks to achieve the goal.

A plethora of adiabatic logic families such as efficient charge recovery logic (ECRL) [3],
positive feedback adiabatic logic (PFAL) [4], 2N2N2P [5], Sense Amplifier Based Logic
(SABL) [6], Improved PFAL (IPFAL) [7] working on energy recovery principle has been
proposed [8]. These are differential families, based on dual-rail logic used primarily in circuit
designs for their high speed characteristics. They use the trapezoidal power clock for periodic
evaluation/recovery and operate in the pipeline with multiple clocks for complete operation.
This paper aims to propose a new adiabatic logic family called differential cascode voltage
switch logic (A-DCVSL) family that operates with spilt-phase sinusoidal power clock to
implement energy efficient structure. The advantage of employing two-phase power clock
lies in its ease of generation as compared with 4 phase trapezoidal clock, reduced layout
complexity, energy dissipation and fewer multiple power-clock generators [9]. A complete
investigation of the behavior of the proposed two-phase A-DCVSL circuits is presented in the
paper.

The rest of the paper is divided as follows: Section 2 provides a review on the basics of
adiabatic logic and different families. Section 3 presents the proposed two-phase adiabatic
differential cascode voltage switch logic family. Its behavior is elaborated and power
dissipation is mathematically modeled. The proposed circuits are simulated and their
performance is compared with the existing adiabatic families. Simulation results and a
discussion is presented in section 4 and 5 while the last section 6 concludes the paper.

2. Background
Adiabatic logic represents a class of logic circuits that reduces the energy dissipated during
the switching events, and exhibits the capability of recycling, or reusing, some of the energy
drawn from the power supply. An adiabatic latch circuit is introduced in [10] to store
information without the need to keep and restore the input signals. The energy can be
recovered from the output nodes through the use of powered power supplies. Several
adiabatic logic families have been proposed with different design goals. Fig.1 lists the
realization of an inverter in different logic families. An ECRL inverter with two cross-
coupled PMOS transistors, an NMOS tree for implementing logic function and its
complementary function is shown in Fig. 1a [3]. An ECRL cascade requires four power
clocks with each succeeding power clock 90O out of phase with the previous power clock.
The circuit dissipates a non–adiabatic power loss of CV2TP due to the threshold voltage of the
pMOS during the charging and recovery phase. The circuit suffers from the problem of
floating nodes during the hold phase due to the threshold voltage of the pMOS devices,
clock-feed through during the hold and recovery stages. The inverter circuit of 2N2N2P logic
family shown in Fig. 1b is faster and dissipates much less power compared to ECRL due to
the adiabatic amplifier formed by cross-coupled inverters [5]. The parallel paths formed by
NMOS transistors help to reduce the resistance offered during the hold phase. A 2N2N2P
cascade requires four power clocks similar to that ECRL for correct operation. This circuit
also suffers from a non-adiabatic loss similar to that of ECRL. The SABL inverter (Fig. 1c)
also uses a trapezoidal clock [6]. In this logic, a fixed amount of charge is used up from the
source before every evaluation cycle. During the cycles when the output does not change
from its previous state, the circuit still takes some fixed amount of time to charge its
capacitance. The limitation of this differential adiabatic logic is that it charges both the output
capacitances in every pre-charge cycle which leads to higher power dissipation. The circuit
diagram for a PFAL inverter is shown in Fig. 1d [4]. While ECRL, SABL and 2N-2N2P use a
pull-down network to realize the logic functions PFAL uses a pull-up network to realize the
logic. The benefit of this is that during the charging of any output node either pair of PMOS
transistors conducts current simultaneously, lowering the effective resistance hence reducing
the power dissipation. The PFAL cascade requires a power clock similar to ECRL for correct
operation. The circuit is free of any floating nodes except due to the threshold limit of PMOS,
thus preventing any possibility of coupling between the nodes. The IPFAL is another
extension to the PFAL structure and shown in Fig 1e [7]. It uses additional PMOS charge
recovery paths connected in parallel with the PMOS transistors of adiabatic amplifier. The
authors claim that the structure is advantageous as it completely recovers the charge from the
load capacitance thereby reducing the power dissipation.

All the above families operate with a four-phase trapezoidal power clocks. In this paper,
efforts are made towards suggesting an adiabatic logic family operating with two-phase
sinusoidal power clocks. A differential cascode voltage switch logic family for being
differential, high noise immunity, compatibility with CMOS design flow is worked upon. A
complete investigation of the behavior of the proposed two-phase adiabatic DCVSL is
presented in the next section.

(a) (b) (c)

(d) (e)

Fig.1 Differential Adiabatic Logic Families Inverters a) 2N-2N2P b)ECRL c)SABL

d)PFAL e)IPFAL

3. Proposed Adiabatic DCVSL

The DCVSL is based on CMOS design methodologies (Fig 2a) and uses a cross-coupled pair
of PMOS and two pull down networks for representing the true and the complementary of the
logic function. The circuit has no static power loss similar to CMOS logic, and uses a latch to
enhance the speed of operation. A low power DCVSL gate is constructed by applying the
principles of adiabatic logic. The proposed A-DCVSL circuit is obtained by employing two-
phase power clock and using an additional NMOS transistor in the footer. The schematic for
a generalized A-DCVSL gate employing a split level sinusoidal power supply is shown in
Fig. 2b. The NMOS in the footer is driven by VPC, is responsible for discharging of output
and show significant power reduction by offering much smaller resistance than other
adiabatic logic families to discharge the output node.

Fig. 2 General block diagram of a a) DCVSL gate b) proposed A-DCVSL gate

The proposed A-DCVSL gate operates in two-phases namely, hold phase and the evaluation
phase depending on the power supply value. In the evaluation phase, VPC goes up and V
goes down whereas in the hold phase VPC goes down and V goes up. In hold phase there is
no switching activity so the output is independent of changes in the inputs of gate.
Alternatively, in the evaluation phase, depending upon the inputs the output follows the
power supply signal. That is, if inputs are such that the PUN is active then the output node
follows the VAC signal (ramps up) otherwise for an activated PDN, the output node follows
the VACBAR (ramps down) signal [11]. The basic inverter realized in the proposed A-DCVSL
family is shown in Fig. 3 and the input, output and clock waveforms are shown in Fig. 4.
 Fig. 3 Proposed A
A-DCVSL Inverter

Fig. 4 Simulation waveforms of the proposed A-DCVSL Inverter

The A-DCVSL circuit consumess dynamic power due to switching either from low to high or
high to low.. To derive the expression for switchi
switching power dissipation in A-DCVSL
DCVSL gates, the
split level sinusoidal power supply is modeled by the equations [12]:

V = sin(ωt + θ) + V

V = sin(ωt + θ) + V (1)

Due to the presence of split level (out-of-phase) sinusoidal clocks, the voltage difference that
charges or discharges the output node is minimized which in turn reduces the peak current
flow and thus reduces the power dissipated. The power dissipated over one time period is
given by:

P = 1/T ∫ v(t). i(t) dt (2)

where T is the time taken for charging/discharging.

charging/discharging In adiabatic logic circuits, the output
capacitance is charged/discharged at a slower rate (due to the presence of sinusoidal power
supply), thus increasing the value of T in the above equation reduc
reduces the overall power
dissipation.
.
The current i(t) in equation (2) can be written as:

()
i( t ) = C (3)

Therefore, the power required to charge the output capacitance is given by:

P= [∫ −(V −V ) C . dt + ∫ (V −V ) C . dt ] (4)

Equation (4) can be further simplifies as:

P= [∫ (V − V ) dV +∫ (V −V ) dV ] (5)

Substituting the limits,

VPC VPC
𝑃= V V − | + V V − | (6)
T
VPC VPC

The equation can be simplified as:

P = V −V V − + + V −V V − + (7)
T

P = [V −V ] (8)
T

As both the charging and recovery cycle would dissipate the same amount of power,
therefore the average power dissipation in adiabatic logic circuit is given by:

Pavg = [V −V ] (9)
T

4. Simulation Results And Performance Analysis

In this section, the performance of the proposed A-DCVSL family is compared with the
adiabatic families ECRL, PFAL, 2N-2N2P, SABL and IPFAL; and the conventional DCVSL
style. The performance of the circuit was compared with other families while varying
parameters like capacitance, frequency, voltage and temperature. The measurements were
done with the W/L ratio of 128nm/32nm for nMOS and 256n/64n for pMOS. After this, a full
subtractor is simulated to display its validity in application design.

4.1 Average Power comparison with varying load capacitance (CL)

The average power dissipation of an inverter realized in different logic families for an input
frequency of 10MHz and varying the output load capacitance from 10fF to 200fF are noted.
The power values at different supply voltage value of 1.2V, 1.5V and 1.8V are listed in Table
I and are represented graphically in Fig. 5. It may be noted that at a particular power supply
the power increases with the increase in load capacitance. Also, the power dissipation
increase as the supply voltage is increased. It is worth noting that the proposed A-DCVSL
inverter consumes the lowest power in all operating conditions.

Table 1: Summary of power dissipation for varying load capacitance

Average Power Dissipation (µW) with VDD=1.2V at freq=10MHz

Family 10fF 30fF 50fF 80fF 100fF 125fF 150fF 200fF

A-DCVSL 0.17 0.48 0.78 1.36 1.81 2.4 3.04 4.45

DCVSL 1.4 2.43 3.51 5.19 6.34 7.78 9.25 12.26
ECRL 0.31 1.04 1.79 2.95 3.73 4.71 5.69 7.67
PFAL 0.21 0.73 1.35 2.39 3.16 4.21 5.39 7.18
 2N2N2P 0.29 1.02 1.78 2.93 3.71 4.69 5.68 7.66
SABL 0.35 0.98 1.62 2.57 3.2 4.01 4.79 5.69
IPFAL 0.21 0.71 1.3 2.23 2.89 3.74 4.62 6.47

Average Power Dissipation (µW) with VDD=1.5V

VDD at freq=10MHz
A-DCVSL 0.39 0.89 1.42 2.22 2.78 3.52 4.32 6.06
DCVSL 2.77 4.5 6.16 8.72 10.48 12.72 14.99 19.59
ECRL 0.38 1.46 2.63 4.39 5.56 7.03 8.5 11.44
PFAL 0.29 1.01 1.87 3.28 4.27 5.53 6.83 9.47
2N2N2P 0.37 1.43 2.61 4.37 5.55 7.02 8.49 11.43
SABL 0.59 1.58 2.59 4.11 5.12 6.38 7.65 10.17
IPFAL 0.29 0.98 1.82 3.17 4.12 5.32 6.54 9.02

Average Power Dissipation (µW) with VDD=1.8V

VDD at freq=10MHz
A-DCVSL 0.97 1.79 2.6 3.85 4.69 5.76 6.84 9.09
DCVSL 5.35 8.02 10.43 14.01 16.44 19.53 22.67 29.02
ECRL 0.98 2.33 4.02 6.55 8.22 10.29 12.35 16.46
PFAL 1.03 1.97 3.14 5.08 6.42 8.14 9.88 13.42
2N2N2P 1.13 2.48 4.17 6.7 8.36 10.43 12.49 16.6
SABL 1.83 3.18 4.6 6.76 8.21 10.01 11.83 15.45
IPFAL 1.21 2.1 3.24 5.11 6.4 8.05 9.73 13.14

(a) (b)

(c)

Fig. 5 Plot of power dissipation of various inverters with varying load capacitance at VDD = a)
1.2 V b) 1.5 V c) 1.8 V
4.2 Average Power comparison with varying clock frequency

The average power dissipation of the inverters is now compared by varying clock frequency
while keeping capacitive load at 10fF. The respective power dissipation values at different
power supply
ly values are listed in Table 2 and are plotted in Fig. 6.. An increasing trend in
power dissipation values with the capacitance is observed.
observe The results identify the proposed
A-DCVSL
DCVSL inverter with least power dissipation.

Table 2: Summary of power dissipation for varying clock frequency

Family 10MHz 20MHz 50MHz 80MHz 100MHz 120MHz 150MHz 180MHz

Average Power Dissipation (µW) with VDD=1.2V and CL=10fF

A-DCVSL 0.17 0.32 0.86 1.53 2.03 2.6 3.45 4.39
DCVSL 1.4 1.99 3.82 5.76 7.08 8.43 10.44 12.47
ECRL 0.31 0.71 1.98 3.33 4.24 5.18 6.58 8.04
PFAL 0.21 0.49 1.61 3.39 4.36 5.38 6.68 8.56
2N2N2P 0.29 0.67 1.89 3.19 4.08 5 6.37 7.82
SABL 0.35 0.7 1.78 2.86 3.58 4.29 5.37 6.45
IPFAL 0.21 0.48 1.5 2.8 3.86 5.36 7.39 9.05

Average Power Dissipation (µW) with VDD=1.5V

VDD and CL=10fF
A-DCVSL 0.39 0.67 1.53 2.42 3.04 3.14 4.77 6.89
DCVSL 2.77 3.77 6.56 9.48 11.5 13.61 16.71 19.87
ECRL 0.38 0.93 2.88 4.92 6.29 9.85 12.81 15.26
PFAL 0.29 0.66 2.14 3.92 5.2 6.3 8.34 10.8
2N2N2P 0.37 0.88 2.76 4.74 6.08 7.42 9.42 11.52
SABL 0.59 1.14 2.85 4.57 5.73 6.89 8.61 10.35
IPFAL 0.29 0.65 2.09 3.79 5.02 6.08 8.02 10.36

Average Power Dissipation (µW) with VDD=1.8V

VDD and CL=10fF
A-DCVSL 0.97 1.44 2.8 4.18 5.1 7.44 10.02 13.78
DCVSL 5.35 6.91 10.93 14.92 17.64 20.49 24.67 29.02
ECRL 0.98 1.59 4.35 7.25 9.19 11.11 17.03 23.12
PFAL 1.03 1.51 3.48 5.82 7.51 9.05 11.64 14.77
2N2N2P 1.13 1.72 4.38 7.19 9.08 10.95 13.75 16.77
SABL 1.83 2.56 4.97 7.43 9.08 10.76 13.41 18.04
IPFAL 1.21 1.67 3.58 5.88 7.53 9.05 11.59 14.67

Fig
Fig 88 a)
a) Power
Power vs.
vs. Capacitance
Capacitance(C
(CLL) @1.2V

(a) (b)
 (c
Fig. 6 Plot of power dissipation of various inverters with varying input clock frequency at
VDD = a) 1.2 V b) 1.5 V c) 1.8 V

4.3 Average power dissipation at varying temperature

Similarly, the effect of temperature variation is studied on power dissipation.. The power of
the inverters at temperatures -40ºC,
40ºC, 25ºC and 125 ºC are measured at listed in Table 33. The
effect of varying the load capacitance from 10fF to 200fF with clock frequency of 10MHz
and supply voltage 1.8V is captured in Fig. 7. It is evident that the A-DCVSL
DCVSL inverter
consumes the least power dissipation at varying temperature values.

Table 3: Power dissipation (µW) for different temperature values

Family Power dissipation (µW)

-40ºC 25ºC 125ºC
A-DCVSL 1.13 0.97 0.81
DCVSL 6.79 4.7 3.07
ECRL 0.96 0.98 1.12
PFAL 2.3 1.83 1.62
2N-2N2P 1.14 1.15 1.2
SABL 2.29 1.83 1.62
IPFAL 1.23 1.26 1.29

8
Power Dissipation (µW)

DCVSL
6 ECRL
PFAL
4 2N-2N2P
SABL
2 IPFAL
A-DCVSL
0
-40 25 125
Temperature(°C)

Fig. 7 Plot of power dissipation of various inverters with varying temperature

5. An Application Example
A full subtractor as an application is chosen as it is often used in arithmetic logic unit for
computations. It is used to subtract three bits. The full subtractor is shown in Fig. 8 requires
AND, OR and XOR logic gates. The implementation of the gates in A-DCVSL DCVSL style is
shown in Fig. 9.. The full subtractor circuit implementation using A A-DCVSL
DCVSL is shown in Fig.Fig
10. To compare the performance of our newly proposed circuit with the conventional one, a
full subtractor is also implemented in A-DCVSL
A and DCVSL style and then their
performance is compared at a constant frequency of input with varying capacitance. The
power dissipation values are listed in Table 4 and the trend is also highlighted through the
plot in Fig. 11. It is observed that the proposed A-DCVSL
A SL full subtractor significantly lower
the power dissipation with respect to conventional DCVSL counterpart.

Fig. 8 Full Subtractor

(a) (b) (c)

Fig. 9 Proposed A-DCVSL
DCVSL based ((a) AND/NAND gate (b) OR/NOR gate (c)) XOR/X-NOR
XOR/X
gate
 Fig. 10 MOS schematic of A-DCVSL full subtractor

Table 4: Power dissipation (µW) vs. Capacitance (fF) for full subtractor

Capacitance Power dissipation (µW)

DCVSL A-DCVSL
10fF 21.12 3.53
30fF 21.32 3.84
50fF 21.85 4.06
80fF 22.47 4.4
100fF 23.24 4.6
125fF 23.65 4.87
150fF 24.09 5.12
200fF 24.49 5.61

Fig 11 Plot of Power dissipation vs. Capacitance @1.2V for a full subtractor

6. Conclusion
This paper presents a new low power adiabatic logic family named as adiabatic differential
cascode voltage-switch logic (A-DCVSL) that is derived from the conventional differential
cascode voltage-switch logic (DCVSL). The two-phase split level sinusoidal power clock
power clock is used in the proposed family in contrast to the four-phase trapezoidal power
clock. An additional NMOS transistor is used in the footer of the gate. The proposed A-
DCVSL circuits offer power saving by charge recovery and minimizing the peak current
flow. Mathematical computation for the power dissipation of A-DCVSL circuit is presented.
The performance comparison of A-DCVSL inverter with other inverters realized in existing
differential adiabatic logic families verifies the low power characteristics. The impact of
variations with respect to power supply and temperature identifies the proposed inverter with
lowest power dissipation at all values. The results clearly indicate the use of proposed A-
DCVSL circuits in lower power applications.

References

[1] B. Davari, R. H. Dennard, And G. G. Shahidi. “CMOS scaling for high performance and
low power”. Proc. IEEE 83, pp. 408 – 425,4 Apr 1995.
[2] Y. C. Chou, “Low-power digital systems based on adiabatic switching principles,” IEEE
Transactions on Very Large Scale Integration (VLSI) Systems, vol. 2, no. 4, pp. 398–407,
1994.
[3] Yong Moon, Deog-Kyoon Jeong, "An efficient charge recovery logic circuit," in Solid-
State Circuits, IEEE Journal of , vol.31, no.4, pp.514-522, Apr 1996.
[4] A. Vetuli, S. Pascoli, L. Reyneri, "Positive feedback in adiabatic logic", Letter on
Electron., vol. 32, pp. 1867-1869, 1996.
[5] Debika Chaudhuri , Atanu Nag, Sukanta Bose , Suchismita Mitra and Hemanta Ghosh
2N2N2P-An Efficient Adiabatic Logic for VLSI Design, National Conf. Emerging
Technology and Applied Science, 2015.
[6] K. Tiri, I. Verbauwhede, "Charge recycling sense amplifier based logic: Securing low
power security ICs against DPA", Proc. Eur. Solid-State Circuits Conf., pp. 179-182, 2004.
[7] Vijayakumar Ponnusamy And K Gunavathi “Energy Efficient Charge Recovery for
Positive Feedback Adiabatic Logic” IETE Technical Review, Vol 24, No 2, pp 127-133,
March-April 2007
[8] Athas, W.C., Svensson, L.J., Koller, J.G., Tzartzanis, N., Ying-Chin Chou, E., "Low-
power digital systems based on adiabatic-switching principles," in Very Large Scale
Integration (VLSI) Systems, IEEE Transactions on , vol.2, no.4, pp. 398-407, Dec. 1994.
[9] N. Anuar, Y.Takahashi and T. Sekine, “Two phase clocked adiabatic static CMOS logic
and its logic family,” Journal of Semiconductor Technology and Science, vol. 10, no. 1, pp.
1–10, 2010
[10] G. Dickinson and J. S. Denker, “Adiabatic dynamic logic,” IEEE Journal of Solid-State
Circuits, vol. 30, no. 3, pp. 311–315,1995
[11] V. Grover, V. Gosain, N. Pandey and K. Gupta, “Arithmetic Logic Unit Using Diode
Free Adiabatic Logic and Selection Unit for Adiabatic Logic Family”. 5th International
Conference on Signal Processing and Integrated Networks (SPIN), pp.777–781, February 22–
23, 2018.
[12] Shipra Upadhyay, R. A. Mishra, R. K. Nagaria, and S. P. Singh, “DFAL: Diode-Free
Adiabatic Logic Circuits,” ISRN Electronics, vol. 2013, Article ID 673601, 12 pages, 2013.