Beruflich Dokumente
Kultur Dokumente
13 6,7,8,9,10,11
RT9026 44
C X4 DMI DDR_VREF_S0 C
INT.MIC C-Link0 1D8V_S3
29
400MHz
DDR_VREF_S3
Line In
Codec
ICH9M RT9018A 44
29 AZALIA
ALC268 6 PCIe ports PCIex1 LAN
Giga LAN TXFM RJ45 1D8V_S3 1D5V_S0
PCI/PCI BRIDGE 26 26
28 88E8071 25 CFXCORE DC/DC
ACPI 2.0
MIC In ISL6263 35,36
4 SATA PWR SW
29 12 USB 2.0/1.1 ports PCIex1 New card INPUTS OUTPUTS
27 G577BR91U27
ETHERNET (10/100/1000MbE)
PCIex1 DCBATOUT
VGFXCORE
High Definition Audio Mini Card 0.7~1.25V
LPC I/F Kedron a/b/g/n 27
29 OP AMP Serial Peripheral I/F CPU DC/DC
APA205729 Matrix Storage Technology(DO)
B
LPC BUS ISL6266A 42 B
INT.SPKR Active Managemnet Technology(DO)
BIOS INPUTS OUTPUTS
Winbond
29
KBC W25X80 LPC DCBATOUT
VCC_CORE_S0
8M Bits 31 0.35~1.5V
Line Out ENE3310 DEBUG
(NO SPDIF) 30 CONN.31
17,18,19,20 Launch CHARGER
MODEM USB Buttom BQ24750 47
RJ11 MDC Card 16
23 Touch INT. INPUTS OUTPUTS
Blue Tooth Camera
(USB) 23 (USB) 14 Pad 30 KB 30 BT+
SATA DCBATOUT
CardReader MS/MS Pro/xD DCBATOUT
HDD SATA
USB USB Realtek /MMC/SD
22
2 Port 23 RTS5158E 27 5 in 1 27
A A
5 4 3 2 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions page 92 Hub strapping configuration
ICH9 EDS 642879 Rev.1.5 and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for nativeCFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
SMBus
EMC2102 Thermal
3D3V_S0 3D3V_S0
3D3V_S0
1
C190 C183 EC58 C463 C235 C459 C465 C231 C462 C246 C195 C214 C453 C198 C234 C184
SC1U16V3ZY-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY DY DY DY DY
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY
2
4 4
3D3V_CLKGEN_S0
PCLK_ICH CLK_ICH14
CLK48_ICH 3D3V_CLKPLL_S0
1
1
1
EC57 EC55
SC5P50V2CN-2GP EC137 3D3V_48MPWR_S0 SC5P50V2CN-2GP
2
2
DY SC5P50V2CN-2GP DY
2
DY
16
46
62
23
19
27
43
52
33
56
4
9
U19
CL=20pF±0.2pF
VDDPCI
VDDREF
VDD48
VDDPLL3
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC
VDDCPU
C177
SC27P50V2JN-2-GP 61 CLK_CPU_BCLK_1 R160 1 2 0R0402-PAD CLK_CPU_BCLK 4
GEN_XTAL_IN R154 2 CPUT0
1 2 DY 1 10MR2J-L-GP CPUC0 60 CLK_CPU_BCLK_1# R166 1 2 0R0402-PAD CLK_CPU_BCLK# 4 CPU
2 1 GEN_XTAL_OUT 3 58 CLK_MCH_BCLK_1 R167 1 2 0R0402-PAD CLK_MCH_BCLK 6
X1 CPUT1_F
1
2 DY 1
RN59 R155 10KR2J-3-GP 37
SRCT9
SRN10KJ-6-GP SRCC9 38
7 CLK_MCH_OE# R150 1 DY 2 PCLKCLK0 8
TPAD30 TP158 475R2F-L1-GP PCLKCLK1 PCI0/CR#_A CLK_PCIE_MINI_1 R192 1
10 PCI1/CR#_B SRCT4 34 2 0R0402-PAD CLK_PCIE_MINI1 27
PCLKCLK2 CLK_PCIE_MINI_1# R193 1 2 0R0402-PAD
11 35 CLK_PCIE_MINI1# 27 MINI1
1
2
3
4
GNDSRC
GNDSRC
GNDSRC
GNDCPU
DREFCLK 7
GNDREF
2
SRCT0/DOTT_96
GNDPCI
DY DREFCLK#_1 R161 1 2 0R0402-PAD
21 NB CLK
GND48
2 SRCC0/DOTC_96 DREFCLK# 7 2
GND
GND
GND
(96 MHz)
ICS9LPRS365BKLFT-GP
ICS9LPRS365BKLFT setting table
18
15
1
22
30
36
49
59
26
65
71.09365.A03
PIN NAME DESCRIPTION 2nd:
71.00875.C03
Byte 5, bit 7 RTM875N-606-LFT QFN 64P
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
PCI0/CR#_A Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default), SEL2 SEL1 SEL0
1= CR#_A controls SRC2 pair CPU FSB
FSC FSB FSA
Byte 5, bit 5
0 = PCI1 enabled (default) PIN NAME DESCRIPTION 100M X
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair 1 0 1
PCI1/CR#_B Byte 5, bit 4 Byte 5, bit 1
133M 533M
0 = CR#_B controls SRC1 pair (default) 0 = SRC3 enabled (default) 0 0 1
1= CR#_B controls SRC4 pair 1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
SRCC3/CR#_D Byte 5, bit 0 0 1 1 166M 667M
0 = Overclocking of CPU and SRC Allowed 0 = CR#_D controls SRC1 pair (default)
PCI2/TME 1 = Overclocking of CPU and SRC NOT allowed 1= CR#_D controls SRC4 pair 0 1 0 200M 800M
3.3V PCI clock output Byte 6, bit 7 0 0 0 266M 1066M
PCI3 0 = SRC7# enabled (default)
SRCC7/CR#_E 1= CR#_F controls SRC6
0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96#
1
PCI4/27M_SEL 1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0# Byte 6, bit 6
1
H_A#[35..3]
6 H_A#[35..3]
H_DINV#[3..0]
H_DINV#[3..0] 6
U33A 1 OF 4 TP57 TPAD30 H_DSTBN#[3..0]
H_DSTBN#[3..0] 6
H_A#3 J4 H1 1D05V_S0 H_DSTBP#[3..0]
A3# ADS# H_ADS# 6 H_DSTBP#[3..0] 6
H_A#4 L5 E2 H_BNR# 6
H_A#5 A4# BNR# H_D#[63..0]
4 L4 A5# BPRI# G5 H_BPRI# 6 H_D#[63..0] 6 4
ADDR GROUP 0
H_A#6 K5 A6#
1
H_A#7 M3 H5 H_DEFER# 6
H_A#8 A7# DEFER# R125 Place testpoint on
N2 F21
CONTROL
A8# DRDY# H_DRDY# 6
H_A#9 J1 E1 56R2J-4-GP H_IERR# with a GND
A9# DBSY# H_DBSY# 6
H_A#10 N3 0.1" away
H_A#11 A10#
P5 F1 H_BREQ#0 6
2
H_A#12 A11# BR0#
P2 A12#
H_A#13 L2 D20 H_IERR# TP95 TPAD30
H_A#14 A13# IERR#
P4 A14# INIT# B3 H_INIT# 17
H_A#15 P1
H_A#16 A15#
R1 A16# LOCK# H4 H_LOCK# 6
M1 H_CPURST# 6,41 U33B 2 OF 4
6 H_ADSTB#0 ADSTB0#
6 H_REQ#[4..0] RESET# C1 H_RS#[2..0] 6
H_REQ#0 K3 F3 H_RS#0 H_D#0 E22 Y22 H_D#32
H_REQ#1 H2 REQ0# RS0# H_RS#1 H_D#1 D0# D32# H_D#33
REQ1# RS1# F4 F24 D1# D33# AB24
H_REQ#2 K2 G3 H_RS#2 H_D#2 E26 V24 H_D#34
H_REQ#3 J3 REQ2# RS2# H_D#3 D2# D34# H_D#35
REQ3# TRDY# G2 H_TRDY# 6 G22 D3# D35# V26
H_REQ#4 L1 H_D#4 F23 V23 H_D#36
REQ4# D4# D36#
DATA GRP0
DATA GRP2
G6 H_HIT# 6 H_THERMDA H_D#5 G25 T22 H_D#37
H_A#17 HIT# H_D#6 D5# D37# H_D#38
Y2 A17# HITM# E4 H_HITM# 6 E25 D6# D38# U25
1
H_A#18 U5 H_D#7 E23 U23 H_D#39
H_A#19 A18# XDP_BPM#0 TP27 TPAD30 C136 H_D#8 D7# D39# H_D#40
H_A#20
R3 A19# BPM0# AD4
XDP_BPM#1 TP25 TPAD30
DY SC2200P50V2KX-2GP H_D#9
K24 D8# D40# Y25
H_D#41
W6 XDP/ITP SIGNALS AD3 G24 W22
2
A20# BPM1# D9# D41#
ADDR GROUP 1
H_A#21 U4 AD1 XDP_BPM#2 TP28 TPAD30 H_THERMDC H_D#10 J24 Y23 H_D#42
H_A#22 A21# BPM2# XDP_BPM#3 TP41 TPAD30 H_D#11 D10# D42# H_D#43
Y5 A22# BPM3# AC4 J23 D11# D43# W24
H_A#23 U1 AC2 XDP_BPM#4 TP30 TPAD30 H_D#12 H22 W25 H_D#44
H_A#24 A23# PRDY# XDP_BPM#5 TP37 TPAD30 H_D#13 D12# D44# H_D#45
R4 A24# PREQ# AC1 F26 D13# D45# AA23
H_A#25 T5 AC5 XDP_TCK TP29 TPAD30 H_D#14 K22 AA24 H_D#46
3 H_A#26 A25# TCK XDP_TDI TP39 TPAD30 1D05V_S0 H_D#15 D14# D46# H_D#47 3
T3 A26# TDI AA6 H23 D15# D47# AB25
H_A#27 W2 AB3 XDP_TDO TP40 TPAD30 J26 Y26 H_DSTBN#2 6
A27# TDO 6 H_DSTBN#0 DSTBN0# DSTBN2#
H_A#28 W5 AB5 XDP_TMS TP44 TPAD30 H26 AA26 H_DSTBP#2 6
A28# TMS 6 H_DSTBP#0 DSTBP0# DSTBP2#
1
H_A#29 Y4 AB6 XDP_TRST# TP34 TPAD30 H25 U22 H_DINV#2 6
A29# TRST# 6 H_DINV#0 DINV0# DINV2#
H_A#30 XDP_DBRESET# TP91 TPAD30 R123
Side Band H_A#31
U2
V4
A30# DBR# C20
68R2-GP
A31#
Non GTL H_A#32
H_A#33
W3 A32#
H_D#16 N22
H_D#17 K25 D16# D48# AE24 H_D#48
H_D#49
AA4 THERMAL AD24
2
H_A#34 A33# H_D#18 P26 D17# D49# H_D#50
H_A#35
AB2 A34# CPU_PROCHOT#
DY H_D#19 R23 D18# D50# AA21
H_D#51
AA3 A35# PROCHOT# D21 1 2 CPU_PROCHOT#_R 34 D19# D51# AB22
V1 A24 H_THERMDA 21 R124 H_D#20 L23 AB21 H_D#52
6 H_ADSTB#1 ADSTB1# THRMDA D20# D52#
B25 H_THERMDC 21 0R2J-2-GP H_D#21 M24 AC26 H_D#53
THRMDC D21# D53#
DATA GRP1
DATA GRP3
17 H_A20M# A6 H_D#22 L22 AD20 H_D#54
A20M# H_D#23 M23 D22# D54# H_D#55
17 H_FERR# A5 FERR# THERMTRIP# C7 PM_THRMTRIP-A# 7,17,32 D23# D55# AE22
ICH
2
TPAD30 TP52 RSVD_CPU_1 M4 should connect to H_D#31 N25 AC23 H_D#63
TPAD30 TP49 RSVD_CPU_2 RSVD#M4 ICH9 and MCH D31# D63#
N5 RSVD#N5 6 H_DSTBN#1 L26 DSTBN1# DSTBN3# AE25 H_DSTBN#3 6
TPAD30 TP48 RSVD_CPU_3 T2 without T-ing R263 M26 AF24 H_DSTBP#3 6
RESERVED
1
TPAD30 TP92 RSVD_CPU_6 RSVD#B2 "CPU_GTLREF0" CPU_GTLREF0 COMP0 R105 27D4R2F-L1-GP
C3 RSVD#C3 AD26 GTLREF COMP0 R26 1 2
TPAD30 TP87 RSVD_CPU_7 D2 0.5" max length. TEST1 C23 MISC U26 COMP1 R104 1 2 54D9R2F-L1-GP
RSVD#D2 TEST1 COMP1
1
TPAD30 TP90 RSVD_CPU_8 D22 TEST2 D25 AA1 COMP2 R98 1 2 27D4R2F-L1-GP
RSVD#D22 TEST2 COMP2
1
2 TPAD30 TP88 RSVD_CPU_9 R266 TPAD30 TP86 RSVD_CPU_12 C24 COMP3 R99 54D9R2F-L1-GP 2
TPAD30 TP72 RSVD_CPU_10
D3 RSVD#D3 2KR2F-3-GP
DY C352 TEST4 TEST3 COMP3 Y1 1 2
F6 RSVD#F6 AF26 TEST4
SC1KP50V2KX-1GP
TPAD30 TP21 RSVD_CPU_13 AF1 E5 H_DPRSTP# 7,17,34
2
TPAD30 TP93 RSVD_CPU_11 TPAD30 TP150 RSVD_CPU_14 A26 TEST5 DPRSTP#
B1 B5 H_DPSLP# 17
2
KEY_NC TEST6 DPSLP#
DPWR# D24 H_DPWR# 6
BGA479-SKT6-GPU6 3,7 CPU_SEL0 B22 D6 H_PWRGD 17,32,41
BSEL0 PWRGOOD
62.10079.001 3,7 CPU_SEL1 B23 BSEL1 SLP# D7 H_CPUSLP# 6
3,7 CPU_SEL2 C21 BSEL2 PSI# AE6 PSI# 34
2nd: 62.10053.401
BGA479-SKT6-GPU6
1D05V_S0 62.10079.001
Layout Note:
Follow Demo Circuit Comp0, 2 connect with Zo=27.4 ohm, make
XDP_TMS R102 1 2 54D9R2F-L1-GP trace length shorter than 0.5" .
Net "TEST4" as short as possible, Comp1, 3 connect with Zo=55 ohm, make
XDP_TDI R101 1 2 54D9R2F-L1-GP trace length shorter than 0.5" .
make sure "TEST4" routing is
XDP_BPM#5 R97 1 2 54D9R2F-L1-GP 1 DY 2 TEST1 reference to GND and away other
R118 1KR2J-1-GP
noisy signals
1 DY 2 TEST2
H_CPURST# R116 1 DY 2 51R2F-2-GP R295 1KR2J-1-GP
2 1 TEST4
XDP_TCK R94 1 2 54D9R2F-L1-GP C351 SCD1U10V2KX-4GP
DY
1
XDP_TRST# R96 1 2 54D9R2F-L1-GP 1
3D3V_S0
All place within 2" to CPU
XDP_DBRESET# R121 1 DY 2 1KR2J-1-GP Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1D05V_S0 Taipei Hsien 221, Taiwan, R.O.C.
Title
XDP_TDO R100 1 DY 2 54D9R2F-L1-GP
CPU (1 of 2)
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 4 of 42
A B C D E
A B C D E
U33D 4 OF 4
VCC_CORE VCC_CORE VCC_CORE
VCC_CORE VCC_CORE
SB
A4 VSS VSS P6
4 A8 VSS VSS P21 4
U33C 3 OF 4 A11 P24
VSS VSS
1
4
C86 C120 C122 C88 C90 C124 C130 C89 A14 R2
VSS VSS
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
A7 AB20 TC9 A16 R5
VCC VCC VSS VSS
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
A9 AB7 DY DY DY DY A19 R22
2
VCC VCC ST900U2D5VM-GP VSS VSS
A10 VCC VCC AC7 CAP CAP CAP CAP A23 VSS VSS R25
A12 AC9 TP22 AF2 T1
2
3
VCC VCC TPAD30 VSS VSS
A13 VCC VCC AC12 77.E9071.001 B6 VSS VSS T4
A15 VCC VCC AC13 NEC B8 VSS VSS T23
A17 VCC VCC AC15 B11 VSS VSS T26
A18 VCC VCC AC17 B13 VSS VSS U3
A20 VCC VCC AC18 B16 VSS VSS U6
B7 VCC VCC AD7 B19 VSS VSS U21
B9 AD9 VCC_CORE B21 U24
VCC VCC VSS VSS
B10 VCC VCC AD10 B24 VSS VSS V2
B12 VCC VCC AD12 C5 VSS VSS V5
B14 VCC VCC AD14 C8 VSS VSS V22
1
B15 AD15 C123 C102 C135 C93 C380 C375 C381 C374 C70 C94 C106 C71 C103 C105 C11 V25
VCC VCC VSS VSS
B17 VCC VCC AD17 C14 VSS VSS W1
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
B18 AD18 DY DY DY DY DY DY DY DY C16 W4
2
VCC VCC VSS VSS
B20 VCC VCC AE9 CAP CAP CAP CAP CAP CAP C19 VSS VSS W23
C9 VCC VCC AE10 C2 VSS VSS W26
C10 VCC VCC AE12 C22 VSS VSS Y3
C12 VCC VCC AE13 C25 VSS VSS Y6
C13 VCC VCC AE15 D1 VSS VSS Y21
C15 VCC VCC AE17 D4 VSS VSS Y24
C17 VCC VCC AE18 D8 VSS VSS AA2
C18 VCC VCC AE20 D11 VSS VSS AA5
D9 VCC VCC AF9 D13 VSS VSS AA8
3 D10 AF10 D16 AA11 3
VCC VCC VSS VSS
D12 VCC VCC AF12 D19 VSS VSS AA14
D14 VCC VCC AF14 D23 VSS VSS AA16
D15 VCC VCC AF15 D26 VSS VSS AA19
D17 VCC VCC AF17 E3 VSS VSS AA22
D18 VCC VCC AF18 E6 VSS VSS AA25
E7 AF20 1D05V_S0 E8 AB1
VCC VCC VSS VSS
E9 G5 E11 AB4
VCC VCCP_1D05 VSS VSS
E10 VCC VCCP G21 1 2 E14 VSS VSS AB8
E12 VCC VCCP V6 E16 VSS VSS AB11
E13 J6 GAP-CLOSE-PWR-2U E19 AB13
VCC VCCP 1D05V_S0 VSS VSS
E15 VCC VCCP K6 E21 VSS VSS AB16
E17 VCC VCCP M6 E24 VSS VSS AB19
1
SCD1U10V2KX-4GP
1
F7 M21 C104 C101 C108 C110 C112 C95 C98 C99 C433 F11 AC3
2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
F10 N6 layout note: "1D5V_VCCA_S0" F16 AC8
2
VCC VCCP VSS VSS
F12 VCC VCCP R21 as short as possible F19 VSS VSS AC11
F14 VCC VCCP R6 DY DY F2 VSS VSS AC14
F15 VCC VCCP T21 F22 VSS VSS AC16
F17 VCC VCCP T6 F25 VSS VSS AC19
F18 V21 1D5V_S0 G4 AC21
VCC VCCP 1D5V_VCCA_S0 VSS VSS
F20 VCC VCCP W21 L11 G1 VSS VSS AC24
AA7 VCC G23 VSS VSS AD2
AA9 VCC VCCA B26 1 2 G26 VSS VSS AD5
AA10 VCC VCCA C26 H3 VSS VSS AD8
1
SC10U6D3V5MX-3GP
Layout Note: M2 A2
BGA479-SKT6-GPU6 R88 VSS VSS TP94
M5 VSS VSS AF6
62.10079.001 100R2F-L1-GP-U VCCSENSE and VSSSENSE lines M22 AF8 TPAD30
should be of equal length. VSS VSS
M25 VSS VSS AF11
N1 AF13
2
VSS VSS
N4 VSS VSS AF16
Layout Note: N23 AF19
Provide a test point (with VSS VSS
N26 VSS VSS AF21
no stub) to connect a P3 A25 TP151
differential probe VSS VSS TPAD30
VSS AF25
between VCCSENSE and TP23
VSSSENSE at the location TPAD30
where the two 54.9ohm BGA479-SKT6-GPU6
resistors terminate the 62.10079.001
55 ohm transmission line.
1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU (2 of 2)
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 5 of 42
A B C D E
5 4 3 2 1
U35A 1 OF 10
H_A#[35..3]
H_A#[35..3] 4
H_D#[63..0] A14 H_A#3
4 H_D#[63..0] H_A#_3
H_D#0 F2 C15 H_A#4
H_D#1 H_D#_0 H_A#_4 H_A#5
G8 H_D#_1 H_A#_5 F16
H_D#2 F8 H13 H_A#6
H_D#3 H_D#_2 H_A#_6 H_A#7
E6 H_D#_3 H_A#_7 C18
H_D#4 G2 M16 H_A#8
1D05V_S0 H_D#5 H_D#_4 H_A#_8 H_A#9
D H_SWING routing Trace width and H6 H_D#_5 H_A#_9 J13 D
H_D#6 H2 P16 H_A#10
Spacing use 10 / 20 mil H_D#_6 H_A#_10
1
H_D#7 F6 R16 H_A#11
R317 H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
221R2F-2-GP H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
H_SWING Resistors and M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
2
Capacitors close MCH H_D#12 J1
H_D#_11 H_A#_15
F17 H_A#16
H_SWING H_D#13 H_D#_12 H_A#_16 H_A#17
500 mil ( MAX ) J2 H_D#_13 H_A#_17 G20
H_D#14 N12 B19 H_A#18
H_D#_14 H_A#_18
1
H_D#15 J6 J16 H_A#19
H_D#_15 H_A#_19
C450 1 R316 H_D#16 P2 H_D#_16 H_A#_20 E20 H_A#20
SCD1U10V2KX-4GP 100R2F-L1-GP-U H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 J20
2
2
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12 H_ADS# 4
C H_D#34 H_D#_33 H_ADS# C
Y6 H_D#_34 H_ADSTB#_0 B16 H_ADSTB#0 4
H_D#35 Y10 G17 H_ADSTB#1 4
H_D#36 H_D#_35 H_ADSTB#_1
Y12 H_D#_36 H_BNR# A9 H_BNR# 4
H_D#37 Y14 F11 H_BPRI# 4
H_D#38 H_D#_37 H_BPRI#
Y7 G12
HOST
H_D#_38 H_BREQ# H_BREQ#0 4
H_D#39 W2 E9 H_DEFER# 4
H_D#40 H_D#_39 H_DEFER#
AA8 H_D#_40 H_DBSY# B10 H_DBSY# 4
H_D#41 Y9 AH7 CLK_MCH_BCLK 3
H_D#42 H_D#_41 HPLL_CLK
AA13 H_D#_42 HPLL_CLK# AH6 CLK_MCH_BCLK# 3
H_D#43 AA9 J11 H_DPWR# 4
H_D#44 H_D#_43 H_DPWR#
AA11 H_D#_44 H_DRDY# F9 H_DRDY# 4
H_RCOMP routing Trace width and H_D#45 AD11 H9 H_HIT# 4
H_D#46 H_D#_45 H_HIT#
AD10 E12 H_HITM# 4
Spacing use 10 / 20 mil H_D#47 AD13
H_D#_46 H_HITM#
H11 H_LOCK# 4
H_D#48 H_D#_47 H_LOCK#
AE12 H_D#_48 H_TRDY# C9 H_TRDY# 4
H_D#49 AE9
H_RCOMP H_D#50 H_D#_49
1 2 AA2 H_D#_50
R312 24D9R2F-L-GP H_D#51 AD8
H_D#52 H_D#_51 H_DINV#[3..0]
AA3 H_D#_52 H_DINV#[3..0] 4
H_D#53 AD3 J8 H_DINV#0
H_D#54 H_D#_53 H_DINV#_0 H_DINV#1
AD7 H_D#_54 H_DINV#_1 L3
H_D#55 AE14 Y13 H_DINV#2
H_D#56 H_D#_55 H_DINV#_2 H_DINV#3
Place them near to the chip ( < 0.5") H_D#57
AF3
AC1
H_D#_56 H_DINV#_3 Y1
H_DSTBN#[3..0]
H_D#_57 H_DSTBN#[3..0] 4
H_D#58 AE3 L10 H_DSTBN#0
H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1
AC3 H_D#_59 H_DSTBN#_1 M7
H_D#60 AE11 AA5 H_DSTBN#2
H_D#61 H_D#_60 H_DSTBN#_2 H_DSTBN#3
AE8 H_D#_61 H_DSTBN#_3 AE6
H_D#62 AG2 H_DSTBP#[3..0]
B H_D#_62 H_DSTBP#[3..0] 4 B
H_D#63 AD6 L9 H_DSTBP#0
H_D#_63 H_DSTBP#_0 H_DSTBP#1
H_DSTBP#_1 M8
AA6 H_DSTBP#2
H_DSTBP#_2 H_DSTBP#3
H_DSTBP#_3 AE5
H_REQ#[4..0] 4
1D05V_S0 B15 H_REQ#0
H_SWING H_REQ#_0 H_REQ#1
C5 H_SWING H_REQ#_1 K13
H_RCOMP E3 F13 H_REQ#2
H_RCOMP H_REQ#_2
2
B13 H_REQ#3
R322 H_REQ#_3 H_REQ#4
4,41 H_CPURST# C12 H_CPURST# H_REQ#_4 B14
1KR2F-3-GP E11
4 H_CPUSLP# H_CPUSLP# H_RS#[2..0] 4
B6 H_RS#0
H_RS#_0 H_RS#1
F12
1
C455
R318 SCD1U16V2ZY-2GP CANTIGA-GM-GP-U-NF
2KR2F-3-GP
2
71.CNTIG.00U
2
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cantiga (1 of 6)
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 6 of 42
5 4 3 2 1
5 4 3 2 1
U35B 2 OF 10
U35C 3 OF 10 1D05V_S0
M36
1
D C477 BB36 M_CKE3 13 E38 U43 D
SB_CKE_1 LVDS_VREFL PEG_RX#_8
RSVD
R338 C475 B31 14 GMCH_TXACLK- C41 Y43
SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP RESERVED#B31 LVDSA_CLK# PEG_RX#_9
3K01R2F-3-GP B2 BA17 M_CS0# 12 14 GMCH_TXACLK+ C40 Y48
2
RESERVED#B2 SA_CS#_0 LVDSA_CLK PEG_RX#_10
M1 RESERVED#M1 SA_CS#_1 AY16 M_CS1# 12 14 GMCH_TXBCLK- B37 LVDSB_CLK# PEG_RX#_11 Y36
AV16 M_CS2# 13 14 GMCH_TXBCLK+ A37 AA43
2
LVDS
SM_RCOMP_VOL AR13 M_CS3# 13 AD37
SB_CS#_1 PEG_RX#_13
AY21 RESERVED#AY21 14 GMCH_TXAOUT0- H47 LVDSA_DATA#_0 PEG_RX#_14 AC47
1
1
C470 BD17 M_ODT0 12 14 GMCH_TXAOUT1- E46 AD39
R334 C472 SA_ODT_0 LVDSA_DATA#_1 PEG_RX#_15
SA_ODT_1 AY17 M_ODT1 12 14 GMCH_TXAOUT2- G40 LVDSA_DATA#_2
1KR2F-3-GP SCD01U16V2KX-3GP SC2D2U6D3V3MX-1-GP BF15 A40 H43
GRAPHICS
M_ODT2 13
2
2
SB_ODT_0 LVDSA_DATA#_3 PEG_RX_0
BG23 RESERVED#BG23 SB_ODT_1 AY13 M_ODT3 13 PEG_RX_1 J44
BF23 14 GMCH_TXAOUT0+ H48 L43
2
1
BF17 SM_REXT 1R328 2 C487 Y37
SM_REXT PEG_RX_11
SCD1U10V2KX-4GP
BC36 TP_SM_DRAMRST# 499R2F-2-GP 14 GMCH_TXBOUT0+ B42 AA42
SM_DRAMRST# TP120
TPAD30 LVDSB_DATA_0 PEG_RX_12
14 GMCH_TXBOUT1+ G38 AD36
2
1D8V_S3 DREFCLK LVDSB_DATA_1 PEG_RX_13
DPLL_REF_CLK B38 DREFCLK 3 14 GMCH_TXBOUT2+ F37 LVDSB_DATA_2 PEG_RX_14 AC48
PCI-EXPRESS
A38 DREFCLK# K37 AD40
DPLL_REF_CLK# DREFSSCLK DREFCLK# 3 LVDSB_DATA_3 PEG_RX_15
DPLL_REF_SSCLK E41 DREFSSCLK 3
F41 DREFSSCLK# J41
DPLL_REF_SSCLK# PEG_TX#_0
1
DREFSSCLK# 3
PEG_TX#_1 M46
R331 F43 TVA_DAC F25 M47
CLK
PEG_CLK CLK_MCH_3GPLL 3 TVA_DAC PEG_TX#_2
80D6R2F-L-GP E43 CLK_MCH_3GPLL# 3 TVB_DAC H25 M40
PEG_CLK# TVC_DAC TVB_DAC PEG_TX#_3
K25 TVC_DAC PEG_TX#_4 M42
R48
2
M_RCOMPP PEG_TX#_5
H24 TV_RTN PEG_TX#_6 N38
TV
AE41 DMI_TXN0 T40
DMI_RXN_0 DMI_TXN1 DMI_TXN0 18 PEG_TX#_7
DMI_RXN_1 AE37 DMI_TXN1 18 PEG_TX#_8 U37
M_RCOMPN AE47 DMI_TXN2 U40
DMI_RXN_2 DMI_TXN3 DMI_TXN2 18 PEG_TX#_9
DMI_RXN_3 AH39 C31 TV_DCONSEL_0 PEG_TX#_10 Y40
1
DMI_TXN3 18
E32 TV_DCONSEL_1 PEG_TX#_11 AA46
R330 AE40 DMI_TXP0 AA37
80D6R2F-L-GP DMI_RXP_0 DMI_TXP1 DMI_TXP0 18 PEG_TX#_12
3,4 CPU_SEL0 T25 CFG_0 DMI_RXP_1 AE38 DMI_TXP1 18 PEG_TX#_13 AA40
3,4 CPU_SEL1 R25 AE48 DMI_TXP2 AD43
CFG_1 DMI_RXP_2 DMI_TXP3 DMI_TXP2 18 PEG_TX#_14
C 3,4 CPU_SEL2 P25 AH40 AC46 C
2
DMI
CFG5 C25 AE43 DMI_RXN1 L46
CFG6 CFG_5 DMI_TXN_1 DMI_RXN2 DMI_RXN1 18 GMCH_GREEN PEG_TX_1
N24 CFG_6 DMI_TXN_2 AE46 DMI_RXN2 18 15 GMCH_GREEN G28 CRT_GREEN PEG_TX_2 M48
CFG7 M24 AH42 DMI_RXN3 M39
CFG_7 DMI_TXN_3 DMI_RXN3 18 PEG_TX_3
CFG
E21 15 GMCH_RED GMCH_RED J28 M43
CFG9 CFG_8 DMI_RXP0 CRT_RED PEG_TX_4
C23 CFG_9 DMI_TXP_0 AD35 DMI_RXP0 18 PEG_TX_5 R47
VGA
3D3V_S0 CFG10 C24 AE44 DMI_RXP1 G29 N37
CFG_10 DMI_TXP_1 DMI_RXP2 DMI_RXP1 18 CRT_IRTN PEG_TX_6
N21 CFG_11 DMI_TXP_2 AF46 DMI_RXP2 18 PEG_TX_7 T39
CFG12 P21 AH43 DMI_RXP3 15 GMCH_DDCCLK GMCH_DDCCLK H32 U36
CFG13 CFG_12 DMI_TXP_3 DMI_RXP3 18 GMCH_DDCDATA CRT_DDC_CLK PEG_TX_8
T21 CFG_13 15 GMCH_DDCDATA J32 CRT_DDC_DATA PEG_TX_9 U39
R207 1 DY 2 4K02R2F-GP CFG19 R20 CFG_14 15 GMCH_HSYNC 1 2 GMCH_HS J29 CRT_HSYNC PEG_TX_10 Y39
M20 R213 33R2F-3-GP E29 Y46
CFG_15 CRT_TVO_IREF PEG_TX_11
R208 1 DY 2 4K02R2F-GP CFG20 CFG16 L21 CFG_16 GFX_VID[4..0] 38 15 GMCH_VSYNC 1 2 GMCH_VS L29 CRT_VSYNC PEG_TX_12 AA36
GRAPHICS VID
H21 R211 33R2F-3-GP AA39
CFG_17 PEG_TX_13
P29 CFG_18 PEG_TX_14 AD42
CFG19 R28 1 2 CRT_IREF AD46
CFG20 CFG_19 GFX_VID0 R347 1K02R2F-1-GP PEG_TX_15
T28 CFG_20 GFX_VID_0 B33
B32 GFX_VID1
GFX_VID_1
R345 1 DY 2 2K21R2F-GP CFG5 GFX_VID_2 G33 GFX_VID2 CANTIGA-GM-GP-U-NF
F33 GFX_VID3 71.CNTIG.00U
GFX_VID_3
R186 1 DY 2 2K21R2F-GP CFG6 18 PM_SYNC# PM_SYNC# R29 PM_SYNC# GFX_VID_4 E33 GFX_VID4
4,17,34 H_DPRSTP# H_DPRSTP# B7 FOR Cantiga: 1.02k_1% ohm
PM_DPRSTP#
R188 1 DY 2 2K21R2F-GP CFG7 PM_EXTTS#0 N33 PM_EXT_TS#_0 Teenah: 1.3k ohm
R354 0R2J-2-GP PM_EXTTS#1 P32 PM_EXT_TS#_1
PM
18,34 VGATE_PWRGD 1 DY 2 PWROK_GD AT40 C34 GFXVR_EN GFXVR_EN 38 CRT_IREF routing Trace
RSTIN# PWROK GFX_VR_EN 1D05V_S0
18,32 PWROK 2 1 AT11
R332 1 DY 2 2K21R2F-GP CFG9 R353 0R0402-PAD PM_THRMTRIP-A# T20
RSTIN# width use 20 mil
THERMTRIP#
2
18,25,27,30,31 PLT_RST1# 1 2 PM_DPRSLPVR R32 DPRSLPVR
R336 1 DY 2 2K21R2F-GP CFG10 R140 300R2F-GP R355
SB AH37 1KR2F-3-GP R201
CL_CLK CL_CLK0 18
1
PWROK 18,32
1
NC#BG48 CL_PWROK
R190 1 DY 2 2K21R2F-GP CFG12 BF48 AJ35 0R0402-PAD
CL_RST#0 18
2
NC#BF48 CL_RST#
BD48 NC#BD48 CL_VREF AH34 MCH_CLVREF R202
R185 1 DY 2 2K21R2F-GP CFG13 BC48 NC#BC48
GMCH_GREEN 1 2
1
BH47 150R2F-1-GP
NC#BH47
1
4,17,32 PM_THRMTRIP-A# BG47 C270 R356
NC#BG47
SCD1U10V2KX-4GP
BE47 N28 SA 511R2F-2-GP R200
18,34 PM_DPRSLPVR NC#BE47 DDPC_CTRLCLK
BH46 M28 TP115 TPAD30 GMCH_RED 1 2
2
B NC#BH46 DDPC_CTRLDATA 150R2F-1-GP B
BF46 G36
2
NC#BF46 SDVO_CTRLCLK
NC
BC1 RN63
SRN10KJ-5-GP NC#BC1 GMCH_LCDVDD_ON
F1 NC#F1 1 8
A47 GMCH_BL_ON 2 7
NC#A47 GFXVR_EN 3 6
4 5
CANTIGA-GM-GP-U-NF 1D05V_S0
SRN100KJ-8-GP 3D3V_S0
71.CNTIG.00U
1
R216
RN33
R324 LIBG 1 2
56R2J-4-GP 2K37R2F-GP LCTLB_DATA 5 4
LCTLA_CLK 6 3
CLK_MCH_OE# 7 2
2
MCH_TSATN# 8 1
SRN10KJ-6-GP
A A
Cantiga (2 of 6)
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 7 of 42
5 4 3 2 1
5 4 3 2 1
U35D 4 OF 10 U35E 5 OF 10
M_A_DQ[63..0] M_B_DQ[63..0]
12 M_A_DQ[63..0] 13 M_B_DQ[63..0]
M_A_DQ0 AJ38 BD21 M_A_BS#0 12 M_B_DQ0 AK47 BC16 M_B_BS#0 13
M_A_DQ1 SA_DQ_0 SA_BS_0 M_B_DQ1 SB_DQ_0 SB_BS_0
AJ41 SA_DQ_1 SA_BS_1 BG18 M_A_BS#1 12 AH46 SB_DQ_1 SB_BS_1 BB17 M_B_BS#1 13
M_A_DQ2 AN38 AT25 M_A_BS#2 12 M_B_DQ2 AP47 BB33 M_B_BS#2 13
M_A_DQ3 SA_DQ_2 SA_BS_2 M_B_DQ3 SB_DQ_2 SB_BS_2
AM38 SA_DQ_3 AP46 SB_DQ_3
M_A_DQ4 AJ36 BB20 M_A_RAS# 12 M_B_DQ4 AJ46
M_A_DQ5 SA_DQ_4 SA_RAS# M_B_DQ5 SB_DQ_4
AJ40 SA_DQ_5 SA_CAS# BD20 M_A_CAS# 12 AJ48 SB_DQ_5 SB_RAS# AU17 M_B_RAS# 13
M_A_DQ6 AM44 AY20 M_A_WE# 12 M_B_DQ6 AM48 BG16 M_B_CAS# 13
M_A_DQ7 SA_DQ_6 SA_WE# M_B_DQ7 SB_DQ_6 SB_CAS#
AM42 SA_DQ_7 AP48 SB_DQ_7 SB_WE# BF14 M_B_WE# 13
D M_A_DQ8 AN43 M_B_DQ8 AU47 D
M_A_DQ9 SA_DQ_8 M_B_DQ9 SB_DQ_8
AN44 SA_DQ_9 AU46 SB_DQ_9
M_A_DQ10 AU40 M_A_DM[7..0] M_B_DQ10 BA48
SA_DQ_10 M_A_DM[7..0] 12 SB_DQ_10
M_A_DQ11 AT38 AM37 M_A_DM0 M_B_DQ11 AY48 M_B_DM[7..0]
SA_DQ_11 SA_DM_0 SB_DQ_11 M_B_DM[7..0] 13
M_A_DQ12 AN41 AT41 M_A_DM1 M_B_DQ12 AT47 AM47 M_B_DM0
M_A_DQ13 SA_DQ_12 SA_DM_1 M_A_DM2 M_B_DQ13 SB_DQ_12 SB_DM_0 M_B_DM1
AN39 SA_DQ_13 SA_DM_2 AY41 AR47 SB_DQ_13 SB_DM_1 AY47
M_A_DQ14 AU44 AU39 M_A_DM3 M_B_DQ14 BA47 BD40 M_B_DM2
M_A_DQ15 SA_DQ_14 SA_DM_3 M_A_DM4 M_B_DQ15 SB_DQ_14 SB_DM_2 M_B_DM3
AU42 SA_DQ_15 SA_DM_4 BB12 BC47 SB_DQ_15 SB_DM_3 BF35
M_A_DQ16 AV39 AY6 M_A_DM5 M_B_DQ16 BC46 BG11 M_B_DM4
M_A_DQ17 SA_DQ_16 SA_DM_5 M_A_DM6 M_B_DQ17 SB_DQ_16 SB_DM_4 M_B_DM5
AY44 SA_DQ_17 SA_DM_6 AT7 BC44 SB_DQ_17 SB_DM_5 BA3
A
M_A_DQ18 BA40 AJ5 M_A_DM7 M_B_DQ18 BG43 AP1 M_B_DM6
B
M_A_DQ19 SA_DQ_18 SA_DM_7 M_A_DQS[7..0] M_B_DQ19 SB_DQ_18 SB_DM_6 M_B_DM7
BD43 SA_DQ_19 M_A_DQS[7..0] 12 BF43 SB_DQ_19 SB_DM_7 AK2
M_A_DQ20 AV41 AJ44 M_A_DQS0 M_B_DQ20 BE45 M_B_DQS[7..0]
SA_DQ_20 SA_DQS_0 SB_DQ_20 M_B_DQS[7..0] 13
M_A_DQ21 AY43 AT44 M_A_DQS1 M_B_DQ21 BC41 AL47 M_B_DQS0
M_A_DQ22 SA_DQ_21 SA_DQS_1 M_A_DQS2 M_B_DQ22 SB_DQ_21 SB_DQS_0 M_B_DQS1
BB41 BA43 BF40 AV48
MEMORY
M_A_DQ23 SA_DQ_22 SA_DQS_2 M_A_DQS3 M_B_DQ23 SB_DQ_22 SB_DQS_1 M_B_DQS2
MEMORY
BC40 SA_DQ_23 SA_DQS_3 BC37 BF41 SB_DQ_23 SB_DQS_2 BG41
M_A_DQ24 AY37 AW12 M_A_DQS4 M_B_DQ24 BG38 BG37 M_B_DQS3
M_A_DQ25 SA_DQ_24 SA_DQS_4 M_A_DQS5 M_B_DQ25 SB_DQ_24 SB_DQS_3 M_B_DQS4
BD38 SA_DQ_25 SA_DQS_5 BC8 BF38 SB_DQ_25 SB_DQS_4 BH9
M_A_DQ26 AV37 AU8 M_A_DQS6 M_B_DQ26 BH35 BB2 M_B_DQS5
M_A_DQ27 SA_DQ_26 SA_DQS_6 M_A_DQS7 M_A_DQS#[7..0] M_B_DQ27 SB_DQ_26 SB_DQS_5 M_B_DQS6
AT36 SA_DQ_27 SA_DQS_7 AM7 M_A_DQS#[7..0] 12 BG35 SB_DQ_27 SB_DQS_6 AU1
M_A_DQ28 AY38 AJ43 M_A_DQS#0 M_B_DQ28 BH40 AN6 M_B_DQS7 M_B_DQS#[7..0]
SA_DQ_28 SA_DQS#_0 SB_DQ_28 SB_DQS_7 M_B_DQS#[7..0] 13
M_A_DQ29 BB38 AT43 M_A_DQS#1 M_B_DQ29 BG39 AL46 M_B_DQS#0
M_A_DQ30 SA_DQ_29 SA_DQS#_1 M_A_DQS#2 M_B_DQ30 SB_DQ_29 SB_DQS#_0 M_B_DQS#1
AV36 SA_DQ_30 SA_DQS#_2 BA44 BG34 SB_DQ_30 SB_DQS#_1 AV47
M_A_DQ31 AW36 BD37 M_A_DQS#3 M_B_DQ31 BH34 BH41 M_B_DQS#2
M_A_DQ32 SA_DQ_31 SA_DQS#_3 M_A_DQS#4 M_B_DQ32 SB_DQ_31 SB_DQS#_2 M_B_DQS#3
BD13 SA_DQ_32 SA_DQS#_4 AY12 BH14 SB_DQ_32 SB_DQS#_3 BH37
M_A_DQ33 AU11 BD8 M_A_DQS#5 M_B_DQ33 BG12 BG9 M_B_DQS#4
M_A_DQ34 SA_DQ_33 SA_DQS#_5 M_A_DQS#6 M_B_DQ34 SB_DQ_33 SB_DQS#_4 M_B_DQS#5
BC11 SA_DQ_34 SA_DQS#_6 AU9 BH11 SB_DQ_34 SB_DQS#_5 BC2
M_A_DQ35 BA12 AM8 M_A_DQS#7 M_B_DQ35 BG8 AT2 M_B_DQS#6
SYSTEM
M_A_DQ36 SA_DQ_35 SA_DQS#_7 M_A_A[14..0] M_B_DQ36 SB_DQ_35 SB_DQS#_6 M_B_DQS#7
SYSTEM
AU13 SA_DQ_36 M_A_A[14..0] 12 BH12 SB_DQ_36 SB_DQS#_7 AN5
C M_A_DQ37 AV13 BA21 M_A_A0 M_B_DQ37 BF11 M_B_A[14..0] C
SA_DQ_37 SA_MA_0 SB_DQ_37 M_B_A[14..0] 13
M_A_DQ38 BD12 BC24 M_A_A1 M_B_DQ38 BF8 AV17 M_B_A0
M_A_DQ39 SA_DQ_38 SA_MA_1 M_A_A2 M_B_DQ39 SB_DQ_38 SB_MA_0 M_B_A1
BC12 SA_DQ_39 SA_MA_2 BG24 BG7 SB_DQ_39 SB_MA_1 BA25
M_A_DQ40 BB9 BH24 M_A_A3 M_B_DQ40 BC5 BC25 M_B_A2
M_A_DQ41 SA_DQ_40 SA_MA_3 M_A_A4 M_B_DQ41 SB_DQ_40 SB_MA_2 M_B_A3
BA9 SA_DQ_41 SA_MA_4 BG25 BC6 SB_DQ_41 SB_MA_3 AU25
M_A_DQ42 AU10 BA24 M_A_A5 M_B_DQ42 AY3 AW25 M_B_A4
M_A_DQ43 SA_DQ_42 SA_MA_5 M_A_A6 M_B_DQ43 SB_DQ_42 SB_MA_4 M_B_A5
AV9 SA_DQ_43 SA_MA_6 BD24 AY1 SB_DQ_43 SB_MA_5 BB28
M_A_DQ44 BA11 BG27 M_A_A7 M_B_DQ44 BF6 AU28 M_B_A6
M_A_DQ45 SA_DQ_44 SA_MA_7 M_A_A8 M_B_DQ45 SB_DQ_44 SB_MA_6 M_B_A7
BD9 SA_DQ_45 SA_MA_8 BF25 BF5 SB_DQ_45 SB_MA_7 AW28
M_A_DQ46 AY8 AW24 M_A_A9 M_B_DQ46 BA1 AT33 M_B_A8
M_A_DQ47 SA_DQ_46 SA_MA_9 M_A_A10 M_B_DQ47 SB_DQ_46 SB_MA_8 M_B_A9
BA6 SA_DQ_47 SA_MA_10 BC21 BD3 SB_DQ_47 SB_MA_9 BD33
M_A_DQ48 M_A_A11 M_B_DQ48 M_B_A10
DDR
DDR
M_A_DQ49 AV7 BH26 M_A_A12 M_B_DQ49 AU3 AW33 M_B_A11
M_A_DQ50 SA_DQ_49 SA_MA_12 M_A_A13 M_B_DQ50 SB_DQ_49 SB_MA_11 M_B_A12
AT9 SA_DQ_50 SA_MA_13 BH17 AR3 SB_DQ_50 SB_MA_12 AY33
M_A_DQ51 AN8 AY25 M_A_A14 M_B_DQ51 AN2 BH15 M_B_A13
M_A_DQ52 SA_DQ_51 SA_MA_14 M_B_DQ52 SB_DQ_51 SB_MA_13 M_B_A14
AU5 SA_DQ_52 AY2 SB_DQ_52 SB_MA_14 AU33
M_A_DQ53 AU6 M_B_DQ53 AV1
M_A_DQ54 SA_DQ_53 M_B_DQ54 SB_DQ_53
AT5 SA_DQ_54 AP3 SB_DQ_54
M_A_DQ55 AN10 M_B_DQ55 AR1
M_A_DQ56 SA_DQ_55 M_B_DQ56 SB_DQ_55
AM11 SA_DQ_56 AL1 SB_DQ_56
M_A_DQ57 AM5 M_B_DQ57 AL2
M_A_DQ58 SA_DQ_57 M_B_DQ58 SB_DQ_57
AJ9 SA_DQ_58 AJ1 SB_DQ_58
M_A_DQ59 AJ8 M_B_DQ59 AH1
M_A_DQ60 SA_DQ_59 M_B_DQ60 SB_DQ_59
AN12 SA_DQ_60 AM2 SB_DQ_60
M_A_DQ61 AM13 M_B_DQ61 AM3
M_A_DQ62 SA_DQ_61 M_B_DQ62 SB_DQ_61
AJ11 SA_DQ_62 AH3 SB_DQ_62
M_A_DQ63 AJ12 M_B_DQ63 AJ3
SA_DQ_63 SB_DQ_63
B CANTIGA-GM-GP-U-NF CANTIGA-GM-GP-U-NF B
71.CNTIG.00U 71.CNTIG.00U
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cantiga (3 of 6)
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 8 of 42
5 4 3 2 1
5 4 3 2 1
7 OF 10 VCC_GFXCORE
1D8V_S3 U35G
1
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AY32 V23 Y34
800MTS 3000mA AW32
VCC_SM
VCC_SM
VCC_AXG_NCTF
VCC_AXG_NCTF AM21 V34
VCC
VCC
AV32 AL21 U34
2
VCC_SM VCC_AXG_NCTF VCC
AU32 VCC_SM VCC_AXG_NCTF AK21 DY DY DY DY AM33 VCC
D AT32 W21 VCC_GFXCORE AK33 D
VCC_SM VCC_AXG_NCTF VCC
AR32 VCC_SM VCC_AXG_NCTF V21 AJ33 VCC
POWER
AP32 VCC_SM VCC_AXG_NCTF U21 AG33 VCC
AN32 VCC_SM VCC_AXG_NCTF AM20 AF33 VCC
BH31 VCC_SM VCC_AXG_NCTF AK20
BG31 VCC_SM VCC_AXG_NCTF W20 AE33 VCC
VCC CORE
BF31 U20 C167 C225 C244 C157 C249 C233 C248 C236 AC33
VCC_SM VCC_AXG_NCTF VCC
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
SC1U10V3ZY-6GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
BG30 AM19 TC18 Coupling CAP 370 mils from the Edge AA33
VCC_SM VCC_AXG_NCTF VCC
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
BH29 AL19 SE220U2D5VDM-3GP DY DY DY Y33
2
VCC_SM VCC_AXG_NCTF VCC
BG29 VCC_SM VCC_AXG_NCTF AK19 W33 VCC
BF29 VCC_SM VCC_AXG_NCTF AJ19 V33 VCC
BD29 VCC_SM VCC_AXG_NCTF AH19 U33 VCC
VCC SM
BC29 VCC_SM VCC_AXG_NCTF AG19 AH28 VCC
BB29 VCC_SM VCC_AXG_NCTF AF19 AF28 VCC
BA29 VCC_SM VCC_AXG_NCTF AE19 AC28 VCC
1
AY29 AB19 C438 C434 AA28
VCC_SM VCC_AXG_NCTF VCC
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
AW29 VCC_SM VCC_AXG_NCTF AA19 Place on the Edge Coupling CAP AJ26 VCC
AV29 Y19 DY DY AG26
2
VCC_SM VCC_AXG_NCTF VCC
AU29 VCC_SM VCC_AXG_NCTF W19 AE26 VCC
AT29 VCC_SM VCC_AXG_NCTF V19 AC26 VCC
AR29 VCC_SM VCC_AXG_NCTF U19 AH25 VCC
AP29 VCC_SM VCC_AXG_NCTF AM17 AG25 VCC
VCC_AXG_NCTF AK17 AF25 VCC
BA36 VCC_SM/NC VCC_AXG_NCTF AH17 AG24 VCC
POWER
BB24 VCC_SM/NC VCC_AXG_NCTF AG17 AJ23 VCC
BD16 AF17 AH23 1D05V_S0
VCC GFX NCTF
VCC NCTF
AH20 VCC_AXG FOR VCC SM VCC_NCTF V30
AF20 VCC_AXG VCC_NCTF U30
AE20 1D8V_S3 AL29
VCC_AXG VCC_NCTF
AC20 VCC_AXG VCC_NCTF AK29
AB20 VCC_AXG VCC_NCTF AJ29
AA20 VCC_AXG VCC_NCTF AH29
1
T17 VCC_AXG VCC_NCTF AG29
T16 C254 C253 C266 C252 TC19 C255 C258 C259 AE29
VCC_AXG VCC_NCTF
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
AM15 DY DY AC29
2
VCC_AXG VCC_NCTF
SE330U2D5VDM-LGP
AL15 VCC_AXG DY DY VCC_NCTF AA29
AE15 VCC_AXG VCC_NCTF Y29
AJ15 VCC_AXG VCC_NCTF W29
AH15 VCC_AXG VCC_NCTF V29
AG15 VCC_AXG VCC_NCTF AL28
AF15 VCC_AXG VCC_NCTF AK28
AB15 VCC_AXG VCC_NCTF AL26
AA15 VCC_AXG VCC_NCTF AK26
VCC GFX
SCD1U10V2KX-4GP
SCD22U10V2KX-1GP
SCD47U16V3ZY-3GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
SCD22U10V2KX-1GP
B AJ14 B
38 VCC_AXG_SENSE VCC_AXG_SENSE
AH14
2
38 VSS_AXG_SENSE VSS_AXG_SENSE
CANTIGA-GM-GP-U-NF
71.CNTIG.00U
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cantiga (4 of 6)
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 9 of 42
5 4 3 2 1
5 4 3 2 1
1
2 0R0603-PAD C478 U13 C257 C261 C256 C260 1 C187 C175
GND VTT
1
SCD01U16V2KX-3GP
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
SC2D2U6D3V3MX-1-GP
SC4D7U6D3V3KX-GP
SCD47U6D3V2KX-GP
3 4 T13 SCD1U10V2KX-4GP
EN/EN# NC#4 C476 C479 VTT 2
B27 U12
2
SC22U16V0KX-1GP SCD1U10V2KX-4GP VCCA_CRT_DAC VTT
A26 T12
2
VCCA_CRT_DAC VTT
1
1
RT9198-33PBR-GP EC153 U11
VTT
SC1U16V3ZY-GP
EC154 74.09198.G7F T11
SC1U16V3ZY-GP M_VCCA_DAC_BG A25 VTT
U10
CRT
2
2
3D3V_S0_DAC VCCA_DAC_BG VTT
D B25 VSSA_DAC_BG VTT T10 D
U9
1 2 5mA VTT
VTT T9
R342 U8
0R0603-PAD M_VCCA_DPLLA VTT
F47 VCCA_DPLLA VTT T8
1
U7
VTT
1D05V_S0 C474 M_VCCA_DPLLB VTT
L48 VCCA_DPLLB VTT T7
SCD1U10V2KX-4GP U6 1D05V_S0 D22
2
M_VCCA_HPLL VTT
AD1 T6
65mA
PLL
R358 VCCA_HPLL VTT 3D3V_S0 3D3V_HV_S0
VTT U5 1
1 2 M_VCCA_DPLLA 1D8V_TXLVDS_S3 M_VCCA_MPLL AE1 T5 R350
0R0603-PAD VCCA_MPLL VTT 1D05V_HV_S0 1
VTT V3 2 2 2 1
1
1
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP
C277 DY U2 10R2F-L-GP
13.2mA
A LVDS
2
SC1KP50V2KX-1GP VTT
J47 T2
2
1D5V_S0 VSSA_LVDS VTT
VTT V1
R351 U1
0R0402-PAD VTT
2 1 VCCA_PEG_BG AD48
R357 65mA VCCA_PEG_BG
1
1 2 M_VCCA_DPLLB C482
0R0603-PAD SCD1U10V2KX-4GP 1D05V_S0
A PEG
1
2
SC10U6D3V5MX-3GP
1
1D05V_S0
SC1U10V3KX-3GP
0R0603-PAD C159 C171 C224 C219 C227 AR20 SC10U6D3V5MX-3GP
VCCA_SM
1
SC10U6D3V5MX-3GP
SC10U6D3V5MX-3GP
SC4D7U6D3V3KX-GP
SC1U10V3KX-3GP
SC1U10V3KX-3GP
DY DY AP20 VCCA_SM DY
C AN20 C
POWER
2
VCCA_SM
2
2 AR17
2
R310 VCCA_SM
AP17 VCCA_SM
0R0603-PAD AN17 VCCA_SM
AT16 VCCA_SM
1D05V_SUS_MCH_PLL2 AR16
A SM
1
VCCA_SM
AP16 VCCA_SM
L13 24mA 1D05V_S0
1 2 M_VCCA_HPLL 26mA
FCM1608KF-1-GP 1 2 1D05V_SM_CK
1
1
SC4D7U6D3V3KX-GP
1
SCD1U10V2KX-4GP 0R0603-PAD C237 C245 C241 1D8V_SUS_SM_CK 1D8V_S3
120ohm 100MHz
SC10U6D3V5MX-3GP
SC2D2U6D3V3MX-1-GP
SCD1U10V2KX-4GP
AP28 R179
124mA
2
VCCA_SM_CK
DY AN28 B22 1 2
2
2
VCCA_SM_CK VCC_AXF 0R0603-PAD
139.2mA DY AP25 B21
AXF
L12 VCCA_SM_CK VCC_AXF
AN25 VCCA_SM_CK VCC_AXF A21
1
1 2 M_VCCA_MPLL AN24 R183
FCM1608KF-1-GP VCCA_SM_CK 1D8V_SUS_SM_CK_RC
AM28 VCCA_SM_CK_NCTF 1 2 1 2
1
A CK
2
VCCA_SM_CK_NCTF SCD1U10V2KX-4GP 1R2F-GP C222
120ohm 100MHz DY 3D3V_S0_DAC
AM25 VCCA_SM_CK_NCTF
SC10U6D3V5MX-3GP
SM CK
3D3VTVDAC VCCA_SM_CK_NCTF VCC_SM_CK
1 2 AL24 VCCA_SM_CK_NCTF VCC_SM_CK BG20
0R0603-PAD AM23 BF20 1D8V_TXLVDS_S3 1D8V_S3
VCCA_SM_CK_NCTF VCC_SM_CK
1
C469 1 2
SCD01U16V2KX-3GP 0R0603-PAD
2
1
DY K47 3D3V_HV_S0
B L15 50mA B24
VCC_TX_LVDS C275 B
1 2 1D05V_RUN_PEGPLL A24
VCCA_TV_DAC
C35 106mA C276 SC1U10V3KX-3GP
TV
2
FCM1608CF-221T02-GP VCCA_TV_DAC VCC_HV SC1KP50V2KX-1GP
B35
HV
VCC_HV
68.00217.521 50mA VCC_HV A35
1
HDA
V48
1782mA
2
VCC_PEG
VCC_PEG U48
V47
PEG
VCC_PEG
1
U47 C447 C262 C439 C440
D TV/CRT
VCC_PEG
SC4D7U6D3V3KX-GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
1D5VRUN_TVDAC M25 U46 SC10U6D3V5MX-3GP
1D5V_S0 VCCD_TVDAC VCC_PEG
35mA DY DY
2
R196 1D05V_SUS_MCH_PLL2 1D5VRUN_QDAC L28 DY
1D5VRUN_TVDAC VCCD_QDAC
1 2 AH48
0R0603-PAD 157.2mA AF1
VCC_DMI
AF48 1D05V_S0
DMI
VCCD_HPLL VCC_DMI
1
AH47
C242 1D05V_RUN_PEGPLL AA47
VCCD_PEG_PLL
VCC_DMI
VCC_DMI AG47 456mA
1
SCD1U10V2KX-4GP C186
2
1
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
SCD1U10V2KX-4GP M38 SC10U6D3V5MX-3GP
VTTLF
2
VCCD_LVDS
LVDS
L37 A8 VTTLF1
2
2
VCCD_LVDS VTTLF VTTLF2
L2 VTTLF L1
AB2 VTTLF3
1D5VRUN_QDAC VTTLF
1 2
PBY160808T-181Y-GP
68.00206.041 CANTIGA-GM-GP-U-NF C185 C202
1
1D8V_S3 71.CNTIG.00U 1 1 1
180ohm 100MHz
SCD47U6D3V2KX-GP
SCD47U6D3V2KX-GP
C239 R212 C445
SCD1U10V2KX-4GP 1 2 1D8V_SUS_DLVDS SCD47U6D3V2KX-GP 2 2 2
A A
2
0R0603-PAD
60.3mA
1
C271 C274
Wistron Corporation
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
Title
Cantiga (5 of 6)
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 10 of 42
5 4 3 2 1
5 4 3 2 1
U35J 10 OF 10
U35I 9 OF 10 BG21 AH8
VSS VSS
L12 VSS VSS Y8
AU48 VSS VSS AM36 AW21 VSS VSS L8
AR48 VSS VSS AE36 AU21 VSS VSS E8
AL48 VSS VSS P36 AP21 VSS VSS B8
BB47 VSS VSS L36 AN21 VSS VSS AY7
AW47 VSS VSS J36 AH21 VSS VSS AU7
AN47 VSS VSS F36 AF21 VSS VSS AN7
AJ47 VSS VSS B36 AB21 VSS VSS AJ7
D AF47 VSS VSS AH35 R21 VSS VSS AE7 D
AD47 VSS VSS AA35 M21 VSS VSS AA7
AB47 VSS VSS Y35 J21 VSS VSS N7
Y47 VSS VSS U35 G21 VSS VSS J7
T47 VSS VSS T35 BC20 VSS VSS BG6
N47 VSS VSS BF34 BA20 VSS VSS BD6
L47 VSS VSS AM34 AW20 VSS VSS AV6
G47 VSS VSS AJ34 AT20 VSS VSS AT6
BD46 VSS VSS AF34 AJ20 VSS VSS AM6
BA46 VSS VSS AE34 AG20 VSS VSS M6
AY46 VSS VSS W34 Y20 VSS VSS C6
AV46 VSS VSS B34 N20 VSS VSS BA5
AR46 VSS VSS A34 K20 VSS VSS AH5
AM46 VSS VSS BG33 F20 VSS VSS AD5
V46 VSS VSS BC33 C20 VSS VSS Y5
R46 VSS VSS BA33 A20 VSS VSS L5
P46 VSS VSS AV33 BG19 VSS VSS J5
H46 VSS VSS AR33 A18 VSS VSS H5
F46 VSS VSS AL33 BG17 VSS VSS F5
BF44 VSS VSS AH33 BC17 VSS VSS BE4
AH44 VSS VSS AB33 AW17 VSS
AD44 P33 AT17 BC3
AA44
Y44
VSS
VSS
VSS
VSS
VSS
VSS
L33
H33
R17
M17
VSS
VSS
VSS
VSS VSS
VSS
VSS
AV3
AL3
U44 VSS VSS N32 H17 VSS VSS R3
T44 K32 C17 P3
M44
F44
VSS
VSS
VSS
VSS VSS
VSS
VSS
F32
C32 BA16
VSS
VSS
VSS
VSS
VSS
F3
BA2
BC43 VSS VSS A31 VSS AW2
C AV43 AN29 AU16 AU2 C
VSS VSS VSS VSS
AU43 VSS VSS T29 AN16 VSS VSS AR2
AM43 VSS VSS N29 N16 VSS VSS AP2
J43 VSS VSS K29 K16 VSS VSS AJ2
C43 VSS VSS H29 G16 VSS VSS AH2
BG42 VSS VSS F29 E16 VSS VSS AF2
AY42 VSS VSS A29 BG15 VSS VSS AE2
AT42 VSS VSS BG28 AC15 VSS VSS AD2
AN42 VSS VSS BD28 W15 VSS VSS AC2
AJ42 VSS VSS BA28 A15 VSS VSS Y2
AE42 VSS VSS AV28 BG14 VSS VSS M2
N42 VSS VSS AT28 AA14 VSS VSS K2
L42 VSS VSS AR28 C14 VSS VSS AM1
BD41 VSS VSS AJ28 BG13 VSS VSS AA1
AU41 VSS VSS AG28 BC13 VSS VSS P1
AM41 VSS VSS AE28 BA13 VSS VSS H1
AH41 VSS VSS AB28
AD41 VSS VSS Y28 VSS U24
AA41 VSS VSS P28 AN13 VSS VSS U28
Y41 VSS VSS K28 AJ13 VSS VSS U25
U41 VSS VSS H28 AE13 VSS VSS U29
T41 VSS VSS F28 N13 VSS
M41 VSS VSS C28 L13 VSS
G41 VSS VSS BF26 G13 VSS VSS_NCTF AF32
B41 VSS VSS AH26 E13 VSS VSS_NCTF AB32
BG40 VSS VSS AF26 BF12 VSS VSS_NCTF V32
BB40 VSS VSS AB26 AV12 VSS VSS_NCTF AJ30
AV40 VSS VSS AA26 AT12 VSS VSS_NCTF AM29
AN40 VSS VSS C26 AM12 VSS VSS_NCTF AF29
B B
H40 B26 AA12 AB29
VSS NCTF
VSS VSS VSS VSS_NCTF
E40 VSS VSS BH25 J12 VSS VSS_NCTF U26
AT39 VSS VSS BD25 A12 VSS VSS_NCTF U23
AM39 VSS VSS BB25 BD11 VSS VSS_NCTF AL20
AJ39 VSS VSS AV25 BB11 VSS VSS_NCTF V20
AE39 VSS VSS AR25 AY11 VSS VSS_NCTF AC19
N39 VSS VSS AJ25 AN11 VSS VSS_NCTF AL17
L39 VSS VSS AC25 AH11 VSS VSS_NCTF AJ17
B39 VSS VSS Y25 VSS_NCTF AA17
BH38 VSS VSS N25 Y11 VSS VSS_NCTF U17
BC38 VSS VSS L25 N11 VSS
BA38 J25 G11
A3,C1,A48,BH1,BH48
VSS VSS VSS TP163 TPAD30
AU38 VSS VSS G25 C11 VSS NCTF_VSS_SCB#BH48 BH48
AH38 E25 BG10 BH1 TP155 TPAD30
NC
VSS VSS VSS NC#B45
AJ37 VSS VSS F24 BH8 VSS NC#C46 C46
A H37 VSS VSS E24 BB8 VSS NC#D47 D47 A
C37 VSS VSS BH23 AV8 VSS NC#B47 B47
BG36 VSS VSS AG23 AT8 VSS NC#A46 A46
BD36
AK15
VSS
VSS
VSS
VSS
Y23
B23
NC#F48
NC#E48
F48
E48 Wistron Corporation
AU36 A23 C48 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VSS VSS NC#C48 Taipei Hsien 221, Taiwan, R.O.C.
VSS AJ6 NC#B48 B48
Title
CANTIGA-GM-GP-U-NF CANTIGA-GM-GP-U-NF
71.CNTIG.00U 71.CNTIG.00U Cantiga (6 of 6)
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 11 of 42
5 4 3 2 1
A B C D E
DM2
DDR_VREF_S3
PARALLEL TERMINATION 8 M_A_A[14..0]
M_A_A0
M_A_A1
M_A_A2
102
101
A0
A1
/RAS
/WE
108
109
M_A_RAS# 8
M_A_WE# 8
4 100 A2 /CAS 113 M_A_CAS# 8 4
RN29 Put decap near power(0.9V) and pull-up resistor M_A_A3 99
M_A_A12 M_A_A4 A3
8 1 98 A4 /CS0 110 M_CS0# 7
7 2 M_CKE0 M_A_A5 97 115 M_CS1# 7
M_A_BS#2 M_A_A6 A5 /CS1
6 3 94 A6
5 4 M_A_A8 M_A_A7 92 79 M_CKE0 7
M_A_A8 A7 CKE0
93 A8 CKE1 80 M_CKE1 7
SRN56J-5-GP M_A_A9 91
M_A_A10 A9
105 A10/AP CK0 30 M_CLK_DDR0 7
RN16 M_A_A11 90 32 M_CLK_DDR#0 7
M_A_A13 M_A_A12 A11 /CK0
8 1 89 A12
7 2 M_ODT0 M_A_A13 116 164 M_CLK_DDR1 7
M_CS0# M_A_A14 A13 CK1
6 3 86 A14 /CK1 166 M_CLK_DDR#1 7
5 4 M_A_RAS# TPAD30 TP112 M_A_A15 84 A15 M_A_DM[7..0] 8
8 M_A_BS#2 85 10 M_A_DM0
SRN56J-5-GP A16/BA2 DM0 M_A_DM1
DM1 26
8 M_A_BS#0 107 52 M_A_DM2
BA0 DM2 M_A_DM3
RN23 8 M_A_BS#1 106 67
M_A_BS#1 BA1 DM3 M_A_DM4
8 1 DM4 130
7 2 M_A_A0 M_A_DQ0 5 147 M_A_DM5
M_A_A2 M_A_DQ1 DQ0 DM5 M_A_DM6
6 3 8 M_A_DQ[63..0] 7 DQ1 DM6 170
5 4 M_A_A4 M_A_DQ2 17 185 M_A_DM7
M_A_DQ3 DQ2 DM7
19 DQ3
SRN56J-5-GP M_A_DQ4 4 195 SMBD_ICH 3,13,20
M_A_DQ5 DQ4 SDA 3D3V_S0
6 DQ5 SCL 197 SMBC_ICH 3,13,20
RN13 M_A_DQ6 14
M_A_CAS# M_A_DQ7 DQ6
8 1 16 DQ7 VDDSPD 199
7 2 M_A_DQ8 23
M_ODT1 M_A_DQ9 DQ8
6 3 25 DQ9 SA0 198
1
5 4 M_CS1# M_A_DQ10 35 200
M_A_DQ11 DQ10 SA1 C115
37 DQ11
SRN56J-5-GP M_A_DQ12 20 50 SCD1U16V2ZY-2GP
2
M_A_DQ13 DQ12 NC#50
22 DQ13 NC#69 69 DY
RN24 M_A_DQ14 36 83
M_A_A9 M_A_DQ15 DQ14 NC#83
8 1 38 DQ15 NC#120 120
7 2 M_A_A14 M_A_DQ16 43 163
M_A_A5 M_A_DQ17 DQ16 NC#163/TEST
6 3 45 DQ17
5 4 M_A_A3 M_A_DQ18 55
M_A_DQ19 DQ18
57 81
REVERSE TYPE
SRN56J-5-GP M_A_DQ20 DQ19 VDD
44 DQ20 VDD 82
M_A_DQ21 46 87
M_A_DQ22 DQ21 VDD
3 RN28 56 88 3
M_A_A6 M_A_DQ23 DQ22 VDD
8 1 58 DQ23 VDD 95
7 2 M_A_A7 M_A_DQ24 61 96
M_A_A11 M_A_DQ25 DQ24 VDD
6 3 63 DQ25 VDD 103
5 4 M_CKE1 M_A_DQ26 73 104
M_A_DQ27 DQ26 VDD
75 DQ27 VDD 111
SRN56J-5-GP M_A_DQ28 62 112 1D8V_S3
M_A_DQ29 DQ28 VDD
64 DQ29 VDD 117
RN19 M_A_DQ30 74 118
M_A_BS#0 M_A_DQ31 DQ30 VDD
8 1 76 DQ31
7 2 M_A_A1 M_A_DQ32 123 3
M_A_A10 M_A_DQ33 DQ32 VSS
6 3 125 DQ33 VSS 8
5 4 M_A_WE# M_A_DQ34 135 9
M_A_DQ35 DQ34 VSS
137 DQ35 VSS 12
SRN56J-5-GP M_A_DQ36 124 15
M_A_DQ37 DQ36 VSS
126 DQ37 VSS 18
M_A_DQ38 134 21
M_A_DQ39 DQ38 VSS
136 DQ39 VSS 24
M_A_DQ40 141 27
M_A_DQ41 DQ40 VSS
143 DQ41 VSS 28
M_A_DQ42 151 33
M_A_DQ43 DQ42 VSS
153 DQ43 VSS 34
M_A_DQ44 140 39
M_A_DQ45 DQ44 VSS
142 DQ45 VSS 40
M_A_DQ46 152 41
M_A_DQ47 DQ46 VSS
M_A_DQ48
154
157
DQ47 VSS 42
47 1D8V_S3 Place these Caps near DM2
M_A_DQ49 DQ48 VSS
159 48
Decoupling Capacitor M_A_DQ50
M_A_DQ51
173
175
DQ49
DQ50
DQ51
VSS
VSS
VSS
53
54
1
M_A_DQ52 158 59 C200 C454 C458 C457 C169
DDR_VREF_S3 DQ52 VSS
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
M_A_DQ53 160 60
Put decap near power(0.9V) M_A_DQ54 174
DQ53 VSS
65 DY DY
2
M_A_DQ55 DQ54 VSS
and pull-up resistor M_A_DQ56
176
179
DQ55 VSS 66
71
M_A_DQ57 DQ56 VSS
181 DQ57 VSS 72
M_A_DQ58 189 77
DQ58 VSS
1
C191 C189 C207 C181 C209 C218 C223 C192 C201 C173 C170 M_A_DQ59 191 78
DQ59 VSS
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
1
M_A_DQS#1 29 138 C448 C193 C179 C216
8 M_A_DQS#[7..0] /DQS1 VSS
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_A_DQS#2 49 139
M_A_DQS#3 /DQS2 VSS
68 144 DY DY
2
M_A_DQS#4 /DQS3 VSS
129 /DQS4 VSS 145
M_A_DQS#5 146 149
M_A_DQS#6 /DQS5 VSS
167 /DQS6 VSS 150
M_A_DQS#7 186 155
/DQS7 VSS
VSS 156
M_A_DQS0 13 161
M_A_DQS1 DQS0 VSS
8 M_A_DQS[7..0] 31 DQS1 VSS 162
M_A_DQS2 51 165
M_A_DQS3 DQS2 VSS
70 DQS3 VSS 168
M_A_DQS4 131 171
M_A_DQS5 DQS4 VSS
148 DQS5 VSS 172
M_A_DQS6 169 177
M_A_DQS7 DQS6 VSS
188 DQS7 VSS 178
DDR_VREF_S3_1 183
VSS
7 M_ODT0 114 ODT0 VSS 184
7 M_ODT1 119 ODT1 VSS 187
VSS 190
1 VREF VSS 193
2 VSS VSS 196
1
DY C279
C278 202 201
GND GND
SCD1U16V2ZY-2GP
SC4D7U6D3V3KX-GP
2
SKT-SODIMM20022U2GP
62.10017.691
High 5.2mm
2nd: 62.10017.911
1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
DDR2 Socket 1 (DM2)
Size Document Number Rev
Cathedral Peak SB
Date: Wednesday, March 12, 2008 Sheet 12 of 42
A B C D E
A B C D E
DM1
8 M_B_A[14..0]
M_B_A0 102 108 M_B_RAS# 8
M_B_A1 A0 RAS#
101 109
DDR_VREF_S3
PARALLEL TERMINATION M_B_A2
M_B_A3
M_B_A4
100
99
A1
A2
A3
WE#
CAS# 113
M_B_WE# 8
M_B_CAS# 8
1
SRN56J-5-GP M_B_DQ10 35 200 DDRB_SA0 2 1
M_B_DQ11 DQ10 SA1 R114 C117
37 DQ11
RN22 M_B_DQ12 20 50 10KR2J-3-GP SCD1U16V2ZY-2GP
2
M_B_BS#1 M_B_DQ13 DQ12 NC#50
8 1 22 DQ13 NC#69 69 DY
7 2 M_B_A2 M_B_DQ14 36 83
REVERSE TYPE
M_B_A0 M_B_DQ15 DQ14 NC#83
6 3 38 DQ15 NC#120 120
5 4 M_B_A4 M_B_DQ16 43 163
M_B_DQ17 DQ16 NC#163/TEST
45 DQ17
SRN56J-5-GP M_B_DQ18 55
M_B_DQ19 DQ18
57 DQ19 VDD 81
RN27 M_B_DQ20 44 82
M_B_A14 M_B_DQ21 DQ20 VDD
8 1 46 DQ21 VDD 87
7 2 M_B_A11 M_B_DQ22 56 88
M_B_A7 M_B_DQ23 DQ22 VDD
3 6 3 58 DQ23 VDD 95 3
5 4 M_B_A6 M_B_DQ24 61 96
M_B_DQ25 DQ24 VDD
63 DQ25 VDD 103
SRN56J-5-GP M_B_DQ26 73 104
M_B_DQ27 DQ26 VDD
75 DQ27 VDD 111
RN12 M_B_DQ28 62 112 1D8V_S3
M_B_BS#0 M_B_DQ29 DQ28 VDD
8 1 64 DQ29 VDD 117
7 2 M_B_CAS# M_B_DQ30 74 118
M_CS3# M_B_DQ31 DQ30 VDD
6 3 76 DQ31
5 4 M_CS2# M_B_DQ32 123 3
M_B_DQ33 DQ32 VSS
125 DQ33 VSS 8
SRN56J-5-GP M_B_DQ34 135 9
M_B_DQ35 DQ34 VSS
137 DQ35 VSS 12
M_B_DQ36 124 15
M_B_DQ37 DQ36 VSS
126 DQ37 VSS 18
M_B_DQ38 134 21
M_B_DQ39 DQ38 VSS
136 DQ39 VSS 24
M_B_DQ40 141 27
M_B_DQ41 DQ40 VSS
143 DQ41 VSS 28
M_B_DQ42 151 33
M_B_DQ43 DQ42 VSS
153 DQ43 VSS 34
M_B_DQ44 140 39
M_B_DQ45 DQ44 VSS
142 DQ45 VSS 40
M_B_DQ46 152 41
M_B_DQ47 DQ46 VSS
154 DQ47 VSS 42
M_B_DQ48 157 47
M_B_DQ49 DQ48 VSS
159 DQ49 VSS 48
M_B_DQ50 173 53
M_B_DQ51 DQ50 VSS
175 DQ51 VSS 54
M_B_DQ52 158 59
M_B_DQ53 DQ52 VSS
160 DQ53 VSS 60
M_B_DQ54 174 65
M_B_DQ55 176
DQ54 VSS
66 1D8V_S3 Place these Caps near DM1
M_B_DQ56 DQ55 VSS
179 DQ56 VSS 71
M_B_DQ57 181 72
Decoupling Capacitor M_B_DQ58 189
DQ57
DQ58
VSS
VSS 77
1
M_B_DQ59 191 78 C449 C451 C174 C199 C158
DQ59 VSS
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
SC2D2U6D3V3MX-1-GP
M_B_DQ60 180 121
Put decap near power(0.9V) M_B_DQ61 182
DQ60 VSS
122 DY DY
2
DDR_VREF_S3 M_B_DQ62 DQ61 VSS
and pull-up resistor M_B_DQ63
192
194
DQ62 VSS 127
128
2 DQ63 VSS 2
VSS 132
M_B_DQS#0 11 133
M_B_DQS#1 DQS0# VSS
8 M_B_DQS#[7..0] 29 DQS1# VSS 138
1
C205 C180 C166 C196 C215 C197 C221 C217 C160 C220 C172 M_B_DQS#2 49 139
DQS2# VSS
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
M_B_DQS#3 68 144
M_B_DQS#4 DQS3# VSS
DY DY DY 129 145
2
1
M_B_DQS#7 186 155 C203 C461 C456 C452
DQS7# VSS
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
VSS 156
M_B_DQS0 13 161 DY DY
2
M_B_DQS1 DQS0 VSS
8 M_B_DQS[7..0] 31 DQS1 VSS 162
M_B_DQS2 51 165
M_B_DQS3 DQS2 VSS
70 DQS3 VSS 168
M_B_DQS4 131 171
M_B_DQS5 DQS4 VSS
148 DQS5 VSS 172
M_B_DQS6 169 177
M_B_DQS7 DQS6 VSS
188 DQS7 VSS 178
DDR_VREF_S3_1 183
VSS
7 M_ODT2 114 OTD0 VSS 184
7 M_ODT3 119 OTD1 VSS 187
VSS 190
1 VREF VSS 193
2 VSS VSS 196
1
C281 DY C280
SCD1U16V2ZY-2GP
DDR2-200P-23-GP-U1
62.10017.A71
High 9.2mm
2nd: 62.10017.B51
1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
1
0R0402-PAD 41 C4 C3 2 Vin
USBPN8_R 2 1 DY DY SCD1U25V3ZY-1GP
C5 SCD1U25V3ZY-1GP 3 Brightness
2
18 USBPP8 2 R7 1 USBPP8_R 4 3
0R0402-PAD 6 5 SC10U10V5ZY-1GP 4 BLON
3D3V_S0 8
10
12
7
9
11
GMCH_TXBCLK+
GMCH_TXBCLK-
GMCH_TXBCLK+ 7
GMCH_TXBCLK- 7
5 GND Cover Up Switch
14 13 GMCH_TXBOUT2+ GMCH_TXBOUT2+ 7 6 GND
7 CLK_DDC_EDID CLK_DDC_EDID 16 15 GMCH_TXBOUT2- GMCH_TXBOUT2- 7 3D3V_AUX_S5
7 DAT_DDC_EDID DAT_DDC_EDID 18 17 GMCH_TXBOUT1+ GMCH_TXBOUT1+ 7
20 19 GMCH_TXBOUT1- GMCH_TXBOUT1- 7
1
CCD_PWR 22 21 GMCH_TXBOUT0+ GMCH_TXBOUT0+ 7 CCD Pin
SB 24 23 GMCH_TXBOUT0- GMCH_TXBOUT0- 7 R253
R457 BRIGHTNESS_CN 26 25 GMCH_TXACLK+ GMCH_TXACLK+ 7 Pin Symbol DY 10KR2J-3-GP
U4
BLON_OUT 1 2BLON_OUT_1 28 27 GMCH_TXACLK- GMCH_TXACLK- 7
30 29 GMCH_TXAOUT2+ GMCH_TXAOUT2+ 7 1 CCD_PWR 2 LID_CLOSE#
LID_CLOSE# 30
2
33R2J-2-GP GMCH_TXAOUT2- OUT
32 31 GMCH_TXAOUT2- 7
34 33 GMCH_TXAOUT1+ GMCH_TXAOUT1+ 7 2 USB- 3
DCBATOUT GMCH_TXAOUT1- GND
36 35 GMCH_TXAOUT1- 7
2
F2 38 37 GMCH_TXAOUT0+ GMCH_TXAOUT0+ 7 3 USB+ 1 EC93
PWR_INVERTER GMCH_TXAOUT0- VDD SCD1U16V2ZY-2GP
1 2 40 39 GMCH_TXAOUT0- 7 DY
42 4 GND
1
ME268-002-GP
POLYSW-1D1A24V-GP
1
2
SC10U25V6KX-1GP
SCD1U50V3ZY-GP
20.F0993.040 EC92
2
DY SCD1U16V2ZY-2GP
2nd: 20.F1048.040
1
R241
3nd: 20.F1084.040 2 DY 1 L_BKLTCTL 7
0R2J-2-GP
1
C306 C305
SC100P50V2JN-3GP
SC100P50V2JN-3GP
R240
DY DY 10KR2J-3-GP
2
2
1
2
RN1
2
SRN2K2J-1-GP
4
3
CLK_DDC_EDID
DAT_DDC_EDID
3D3V_S0
LCDVDD
U1
C6 C2
1
SC1U10V3ZY-6GP
SCD1U16V2ZY-2GP
DY G5281RC1U-GP C7
2
74.05281.093 SC1U10V3ZY-6GP
2
F3
1 2 3D3V_S0
FUSE-1D1A6V-8GP
69.41101.021
CCD_PWR
1
C309 C308
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
DY Wistron Corporation
2
Title
LCD CONN
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 14 of 42
A B C D E
Layout Note:
Place these resistors Hsync & Vsync level shift
close to the CRT-out 5V_S0
connector
Ferrite bead impedance: 10 ohm@100MHz
L7
1 2 CRT_R
7 GMCH_RED
1
FCB1608CF-GP
68.00230.021 C314
SCD1U16V2ZY-2GP
L6
2
4 4
1 2 CRT_G
7 GMCH_GREEN FCB1608CF-GP
14
1
68.00230.021
L4
2 3 CRT_HSYNC1
CRT_B 7 GMCH_HSYNC
7 GMCH_BLUE 1 2
FCB1608CF-GP U32A
1
R261 R258 R255 EC109 EC106 EC96 68.00230.021 C336 C326 C321 TSAHCT125PW-GP
14
7
4
SC3P50V2CN-1-GP
SC3P50V2CN-1-GP
SC3P50V2CN-1-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
SC6D8P50V2DN-GP
150R2F-1-GP
150R2F-1-GP
150R2F-1-GP
2
5 6 CRT_VSYNC1
7 GMCH_VSYNC
DY DY
1
U32B
C342 C341 TSAHCT125PW-GP
7
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
2
2
5V_S0
D20 2
CRT_R 3 DY
Layout Note:
* Must be a ground return path between this ground and the ground on 1
3
the VGA connector. BAV99PT-GP-U
3
Pi-filter & 150 Ohm pull-down resistors should be as close as to CRT D18 2
CONN. RGB will hit 75 Ohm first, pi-filter, then CRT CONN.
CRT_G 3
DY
1
BAV99PT-GP-U
D17 2
CRT_B 3 DY
1
BAV99PT-GP-U
2
2 3D3V_S0 5V_CRT_S0 2
6 D2
1 BAS16PT-GP
5V_CRT_S0 7
3
CRT1 F1
2 1 2 5V_CRT_DDC
3
4
9 NP1
VCC_CRT NP1 8
8
7
6
5
NP2 RN41 FUSE-1D1A6V-4GP-U
C315 NP2 SRN2K2J-1-GP RN2
3 69.50007.691
CRT_R 1 11 SRN10KJ-6-GP
CRT_R NC#11
SCD01U16V2KX-3GP CRT_G
CRT_B
2 CRT_G NC#4 4 9
3 Q15
2
1
CRT_B
4
1
2
3
4
5 CRT_IN#_R
CRT_VSYNC1 14 JVGA_VS
GND
GND 6 10 4 3 DAT_DDC1_5
CRT_HSYNC1 13 7
JVGA_HS GND 5
1
C316 8 5 2
GND
GND 10
SC18P50V2JN-1-GP
CLK_DDC1_5 15 16 6 1
7 GMCH_DDCDATA
2
DDCCLK_ID3 GND
1
C323 DAT_DDC1_5 12 17
DDCDATA_ID1 GND
1
SC18P50V2JN-1-GP
C317
1
C19
7 GMCH_DDCCLK
2
2N7002DW-1-GP
SC100P50V2JN-3GP
DY SC100P50V2JN-3GP VIDEO-15-78-GP-U1
2
DY 20.20717.015
2
1
3nd: 20.20334.015 1
SB 5V_S0
R254
30 CRT_DEC#
1 2 CRT_IN#_R D16 Wistron Corporation
2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
470R2J-2-GP Taipei Hsien 221, Taiwan, R.O.C.
1
C313 3 DY
C578 BAV99PT-GP-U Title
SC220P50V2JN-3GP DY SC100P50V2JN-3GP 1
CRT Connector
2
Q31
PWRLED#_DB 3D3V_AUX_S5
R1
C SB
30 FRONT_PWRLED B SB
E
Power Button
1
R2 3D3V_S5
PDTC143ZU-GP-U LED5 R9
84.00143.E1K R451 10KR2J-3-GP
1 2 FRONT_PWRLED#_R 3 1
56R2J-4-GP
2
Q30 R450 SW1 R8
C STDBY_LED#_BD 1 2 STDBY_LED#_R 4 2 1 3 KBC_PWRBTN#_1 1 2 KBC_PWRBTN# KBC_PWRBTN# 30
D B R1 56R2J-4-GP D
30 STDBY_LED 470R2J-2-GP
E 5
1
R2 LED-GY-14-GP
PDTC143ZU-GP-U 83.00195.I70 2 4 EC5
84.00143.E1K SC1KP50V2KX-1GP
2
SW-TACT-122-GP DY
Q29 62.40009.681
C DC_BATFULL#
R1 3D3V_S5
30 DC_BATFULL B SB 2nd: 62.40009.671
E
R2
PDTC143ZU-GP-U LED6 SB
84.00143.E1K R449
1 2 DC_BATFULL#_R 3 1 LED1 3D3V_S5
56R2J-4-GP R2
Q28 R448 PWRLED#_DB 1 2 FRONT_PWRLED#_R_1 2
C CHARGE_LED# 1 2 CHARGE_LED#_R 4 2 56R2J-4-GP
B R1 56R2J-4-GP 3
30 CHARGE_LED R1
E
R2 LED-GY-14-GP STDBY_LED#_BD 1 2 STDBY_LED#_R_1 1
PDTC143ZU-GP-U 83.00195.I70 56R2J-4-GP
84.00143.E1K
3D3V_S0 LED-YG-49-GP
27 WLAN_LED#_MC WLAN_LED#_1
R34 83.01222.H70
GND
IN
R40 LED3 SB
1 2 WLAN_LED# 1 2 WLAN_LED#_R 2 1
1
D
CHDTA143ZUPT-GP 83.00190.S70 PWRLED#_DB 1 2 FRONT_PWRLED#_R_2 2
R2
Q5 56R2J-4-GP
84.00143.J11 2N7002-11-GP 3
R5
R1
30 WLAN_TEST_LED G
STDBY_LED#_BD 1 2 STDBY_LED#_R_2 1
56R2J-4-GP
S
3 OUT
LED-YG-49-GP
83.01222.H70
RN30
LED4 5V_S0 1 4 WIRELESS_BTN#
Q18 R311 2 3 BT_BTN# 3D3V_S0
3D3V_S0
C BT_LED# 1 2 BLT_LED#_1_R K A
B R1 100R2J-2-GP SRN10KJ-5-GP C116
30 BT_LED
1
E LED-B-98-GP EC22 SC1U16V3ZY-GP
1
R2 83.00193.A70 SCD1U16V2ZY-2GP DY
PDTC143ZU-GP-U LEDCN1
2
84.00143.E1K 7
2
1
Volume_Up#_1
2
WIRELESS_BTN#_1 MEDIA_LED# 3
Volume_Up# 17 MEDIA_LED# CAP_LED#
1 8 Volume_Up# 30 30 CAP_LED# 4
BT-BTN#_1 2 7 BT_BTN# BT_BTN# 30 NUM_LED# 5
WIRELESS_BTN# 30 NUM_LED# INT_MIC
3 6 WIRELESS_BTN# 30 28 INT_MIC 6
Volume_Down#_1 4 5 Volume_Down# Volume_Down# 30
B B
8
SRN470J-3-GP
RN26 DY PTWO-CON6-GP
Volume Up Volume Down WLAN Bluetooth
5
6
7
8
INT_MIC 1 2 20.K0286.006
RN20 EC149 SC220P50V2JN-3GP
Button Button Button Button SRN470J-3-GP NUM_LED#
2nd: 20.K0227.006
DY 1 2
3nd: 20.K0228.006
EC121 SC220P50V2JN-3GP
4
3
2
1
5 5 5 5 MEDIA_LED# 1 2
EC123 SC220P50V2JN-3GP
2 4 2 4 2 4 2 4
Cathedral Peak SB
Date: Wednesday, March 12, 2008 Sheet 16 of 42
5 4 3 2 1
5 4 3 2 1
C91
1 2 RTC_X1
SC12P50V2JN-3GP
4
3D3V_AUX_S5 X2
1
D9 X-32D768KHZ-38GPU R95
D 2 RTC_AUX_S5 82.30001.691 10MR2J-L-GP D
2
1
RTC_BAT_R
C74
1 SC1U16V3ZY-GP
1D05V_S0
2
CH715FPT-GP C92 U16A 1 OF 6 LPC_LAD[0..3]
LPC_LAD[0..3] 30,31
83.R0304.B81 1 2
1
C23 K5 LPC_LAD0
RTC1 SC12P50V2JN-3GP RTC_X2 RTCX1 FWH0/LAD0 LPC_LAD1
C24 RTCX2 FWH1/LAD1 K4
R265 LPC_LAD2 R297
RTC_BAT R272 1 FWH2/LAD2 L6 DY
PWR 1 1 2 2 20KR2J-L2-GP RTC_RST# A25 RTCRST# FWH3/LAD3 K2 LPC_LAD3 56R2J-4-GP
RTC
LPC
2 1KR2J-1-GP R81 1 2 20KR2J-L2-GP SRTC_RST# F20
2
GND INTRUDER# SRTCRST# H_DPSLP#
MH1 MH1 1 2 C22 INTRUDER# FWH4/LFRAME# K3 LPC_LFRAME# 30,31
MH2 R282 1MR2J-1-GP
MH2
1
1
DY C353
SCD1U16V2ZY-2GP C73
C354
SC1U16V3ZY-GP
INTVRMEN
LAN100_SLP
B22 INTVRMEN LDRQ0# J3 LDRQ0#
3D3V_LDRQ1_S0
TP146 TPAD30
TP50 TPAD30
A22 LAN100_SLP LDRQ1#/GPIO23 J1
SC1U16V3ZY-GP
2
2
BAT-CON2-U3-GP E25 N7 KA20GATE 30
GLAN_CLK A20GATE
22.70031.001 A20M# AJ27 H_A20M# 4
TPAD30 TP143 LAN_RSTYNC C13 LAN_RSTSYNC H_DPRSTP#
DPRSTP# AJ25 H_DPRSTP# 4,7,34
LAN / GLAN
F14 LAN_RXD0 DPSLP# AE23 H_DPSLP# 4
G13 1D05V_S0
LAN_RXD1 H_FERR#_R
D14 AJ26 RN8
LAN_RXD2 FERR# H_THERMTRIP_R 1 8
D13 LAN_TXD0 CPUPWRGD AD22 H_PWRGD 4,32,41 2 7
D12 4 H_FERR# 3 6 H_FERR#_R
LAN_TXD1
GLAN_COMP place within 500 mil of ICH9M 1D5V_S0
E13 LAN_TXD2 IGNNE# AF25 H_IGNNE# 4 4 5
CPU
C C
ACZ_RST#_R STPCLK#
DY 23,28 ACZ_RST# 2 3 AE7 HDA_RST#
SRN33J-5-GP-U AG26 H_THERMTRIP_R 1 2 PM_THRMTRIP-A# 4,7,32
THRMTRIP#
28 ACZ_SDATAIN0 AF4 HDA_SDIN0 ICH_TP8 TP96 TPAD30
DY R300 Layout note: R373 needs to placed
23 ACZ_SDATAIN1 AG4 HDA_SDIN1 PECI AG27
54D9R2F-L1-GP within 2" of ICH9, R379 must be
IHDA
AH3 HDA_SDIN2
AE5 placed within 2" of R373 w/o stub
3D3V_S0 R309 HDA_SDIN3
SATA4RXN AH11
23,28 ACZ_SDATAOUT 1 2 ACZ_SDATAOUT_R AG5 AJ11
33R2J-2-GP HDA_SDOUT SATA4RXP
SATA4TXN AG12
1 DY 2 HDA_DOCK_EN# AG7 AF12
TPAD30 TP148 HDA_DOCK_RST# R302 8K2R2J-3-GP HDA_DOCK_EN#/GPIO33 SATA4TXP
AE8 HDA_DOCK_RST#/GPIO34
SATA5RXN AH9
16 MEDIA_LED# AG8 SATALED# SATA5RXP AJ9
SATA5TXN AE10
22 SATA_RXN0 C146 1 2 SCD01U50V2KX-1GP SATA_RXN0_C AJ16 AF10
C145 SCD01U50V2KX-1GP SATA_RXP0_C SATA0RXN SATA5TXP
1 2 AH16
SATA
22 SATA_RXP0
3D3V_S0
HDD 22
22
SATA_TXN0
SATA_TXP0
C147
C148
1
1
2
2
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SATA_TXN0_C
SATA_TXP0_C
AF17
AG17
SATA0RXP
SATA0TXN
SATA0TXP
SATA_CLKN
SATA_CLKP
AH18
AJ18
CLK_PCIE_SATA# 3
CLK_PCIE_SATA 3
R299
22 SATA_RXN1 C149 1 2 SCD01U50V2KX-1GP SATA_RXN1_C AH13 AJ7 SATARBIAS
B MEDIA_LED# C150 SCD01U50V2KX-1GP SATA_RXP1_C SATA1RXN SATARBIAS# B
1 2 22 SATA_RXP1 1 2 AJ13 AH7 2 1
10KR2J-3-GP
ODD 22
22
SATA_TXN1
SATA_TXP1
C144
C143
1
1
2
2
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SATA_TXN1_C
SATA_TXP1_C
AG14
AF14
SATA1RXP
SATA1TXN
SATA1TXP
SATARBIAS R301
24D9R2F-L-GP
2
1
71.ICH9M.00U
RN14
SRN10KJ-5-GP
RTC_AUX_S5 RTC_AUX_S5
3
4
1
H_INIT#_G
R90 R93
330KR2F-L-GP 330KR2F-L-GP
integrated VccSus1_05,VccSus1_5,VccCL1_5
B
2
integrated VccLan1_05VccCL1_05
DY R91 DY R92
0R2J-2-GP 0R2J-2-GP LAN100_SLP MMBT3904-3-GP
High=Enable Low=Disable
2
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
ICH9-M (1 of 4)
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 17 of 42
5 4 3 2 1
5 4 3 2 1
U16C 3 OF 6
U16B 2 OF 6
G16 AH23 SATA0GP RN11
20,27 SMB_CLK SMBCLK SATA0GP/GPIO21
D11 F1 PCI_REQ#0 A13 AF19 SATA1GP 5 4
AD0 REQ0# 20,27 SMB_DATA SMBDATA SATA1GP/GPIO19
PCI_GNT#0 RN4 SMB_LINK_ALERT# E17 GPIO36
C8 PCI G4 AE21 6 3
SATA
AD1 GNT0# LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36
GPIO
SMB
D9 B6 PCI_REQ#1 1 4 SMLINK0 C17 AD20 GPIO37 7 2
AD2 REQ1#/GPIO50 SMLINK1 B18 SMLINK0 SATA5GP/GPIO37
E12 AD3 GNT1#/GPIO51 A7 3D3V_S5 2 3 SMLINK1 8 1
E9 F13 PCI_REQ#2 H1 CLK_ICH14 3
AD4 REQ2#/GPIO52 SRN10KJ-5-GP PM_RI# CLK14 SRN10KJ-6-GP
C9 F12 F19 AF3 CLK48_ICH 3
Clocks
AD5 GNT2#/GPIO53 PCI_REQ#3 RI# CLK48
E10 AD6 REQ3#/GPIO54 E6
B7 F6 PCI_GNT#3 PM_SUS_STAT# R4 P1 PM_SUS_CLK 21
AD7 GNT3#/GPIO55 TPAD30 TP147 DBRESET# SUS_STAT#/LPCPD# SUSCLK
C7 AD8 G19 SYS_RESET#
C5 AD9 C/BE0# D8 SLP_S3# C16 PM_SLP_S3# 27,30,32,36,37,38
G11 AD10 C/BE1# B4 7 PM_SYNC# M6 PMSYNC#/GPIO0 SLP_S4# E16 PM_SLP_S4# 27,30,36,37
F8 D6 (GPIO6,GPIO22) G17 SLPS5#
D AD11 C/BE2# SMB_ALERT# A17 SLP_S5# TP144 TPAD30 D
F11 AD12 C/BE3# A5 SMBALERT#/GPIO11
E7 C10 S4_STATE#
AD13 PCI_IRDY#
ICS (0, 1) S4_STATE#/GPIO26 TP141 TPAD30
A3 AD14 IRDY# D3 3 PM_STPPCI# A14 STP_PCI#
PCI_PAR Realtek (1, 1)
SYS GPIO
D2 AD15 PAR E3 3 PM_STPCPU# E19 STP_CPU# PWROK G20 PWROK 7,32
F10 R1 TP142 TPAD30 Seligo (1, 0)
AD16 PCIRST# PCI_DEVSEL# PM_DPRSLPVR
D5 AD17 DEVSEL# C6 30 PM_CLKRUN# L4 CLKRUN# DPRSLPVR/GPIO16 M2 PM_DPRSLPVR 7,34
D10 E4 PCI_PERR# R289 1 DY 2
AD18 PERR#
Power MGT
B3 C2 PCI_LOCK# 25,27 PCIE_WAKE# E20 B13 PM_BATLOW#_R 100KR2J-1-GP
AD19 PLOCK# WAKE# BATLOW#
2
F7 J4 PCI_SERR# M5
AD20 SERR# 30 INT_SERIRQ SERIRQ
C3 A4 PCI_STOP# DY C357 21 THRM# AJ23 R3 PWRBTN#_ICH 1 PM_PWRBTN# 30,41
AD21 STOP# PCI_TRDY# 3D3V_S0 THRM# PWRBTN#
F3 F5 SC100P50V2JN-3GP
1
AD22 TRDY# PCI_FRAME# D21
F4 AD23 FRAME# D7 7,34 VGATE_PWRGD D21 VRMPWRGD LAN_RST# D20 3
C1 R271 BAS16PT-GP
AD24
1
G7 AD25 PLTRST# C14 PLT_RST#_R 2 1 PLT_RST1# 7,25,27,30,31 ICS+RTL 1R89 2 ICH_TP7 A20 SST RSMRST# D22 RSMRST#_SB 2
1
H7 D4 0R2J-2-GP RTL+SEL R305 DY 0R2J-2-GP
AD26 PCICLK R135 1KR2J-1-GP SB_GPIO1
D1 AD27 PME# R2 AG19 TACH1/GPIO1 CK_PWRGD R5 CLK_PWRGD 3
G5 R141 1KR2J-1-GP CLK_SEL_1 AH21 3D3V_S0
AD28 10KR2J-3-GP TACH2/GPIO6
H6 PCLK_ICH 3 30 ECSCI#_1 AG21 R6 PWROK 7,32
2
AD29 ICH_PME# TACH3/GPIO7 CLPWROK
G1 30 ECSWI# A21
2
AD30 TP56 TPAD30 GPIO12 GPIO8
H3 AD31 C12 LAN_PHY_PWR_CTRL/GPIO12 SLP_M# B16 PM_SLP_M#
1
TPAD30 TP140 SB_GPIO13 C21 TP31 TPAD30
PSW_CLR# AE18 ENERGY_DETECT/GPIO13 R281
INT_PIRQA# J5
Interrupt I/F H4 INT_PIRQE# GPIO18 K1
TACH0/GPIO17 CL_CLK0 F24
B19
CL_CLK0 7
3K24R2F-GP
INT_PIRQB# PIRQA# PIRQE#/GPIO2 INT_PIRQF# TPAD30 TP51 GPIO20 GPIO18 CL_CLK1
E1 PIRQB# PIRQF#/GPIO3 K6 AF8 GPIO20
INT_PIRQC# J6 F2 INT_PIRQG# ICS TPAD30 TP149 CLK_SEL_0 AJ22 F22 CL_DATA0 7
2
PIRQC# PIRQG#/GPIO4 SCLOCK/GPIO22 CL_DATA0
1
INT_PIRQD# INT_PIRQH# R136
Controller Link
C4 G2 SEL A9 C19
GPIO
PIRQD# PIRQH#/GPIO5 GPIO27 CL_DATA1
1
G10 1KR2J-1-GP R306 D19
1KR2J-1-GP GPIO28 CL_VREF0_ICH
L1 SATACLKREQ#/GPIO35 CL_VREF0 C25
ICH9M-GP-NF PCB_VER0 AE19 A19 CL_VREF1_ICH
GAP-OPEN PCB_VER1 AG22 SLOAD/GPIO38 CL_VREF1
71.ICH9M.00U
2
SDATAOUT0/GPIO39
1
C RP5 SDATAOUT1 AF21 F21 3D3V_S5 C365 C
3D3V_S0 CL_RST#0 7
2
SDATAOUT1/GPIO48 CL_RST0#
SCD1U10V2KX-4GP
PCI_PERR# 1 10 RP4 GPIO49 AH24 D18 R283
3D3V_S0 GPIO49 CL_RST1#
1
INT_PIRQE# 2 9 INT_PIRQH# PCI_REQ#3 1 10 TPAD30 TP152 GPIO57 A8 453R2F-1-GP
GPIO57/CLGPIO5
1
PCI_LOCK# 3 8 PCI_REQ#0 INT_PIRQF# 2 9 INT_PIRQD# A16 GPIO24 TP32
GPIO24/MEM_LED TPAD30
INT_PIRQA# 4 7 INT_PIRQC# INT_PIRQG# 3 8 PCI_IRDY# 28 ACZ_SPKR M7 C18 GPIO10 R275
2
INT_PIRQB# PCI_SERR# PCI_TRDY# SPKR GPIO10/SUS_PWR_ACK GPIO14 3K24R2F-GP
3D3V_S0 5 6 4 7 7 MCH_ICH_SYNC# AJ24 MCH_SYNC# GPIO14/AC_PRESENT C11
5 6 ECSCI#_1 ICH_TP3 B21 C20 GPIO9 DY
3D3V_S0 TP3 GPIO9/WOL_EN
MISC
SRN8K2J-2-GP-U TPAD30 TP138 AH20 TP139 TPAD30
2
PWM0
RP3 3D3V_S0 SRN8K2J-2-GP-U GPIO49 should be pulled down to AJ20 PWM1
PCI_REQ#2 1 10 GND only when using Teenah. When AJ21 PWM2
1
PCI_REQ#1 2 9 INT_SERIRQ using Cantiga, this ball should
1
3 8 PCI_DEVSEL# C360 R274
be left as No Connect.
SCD1U10V2KX-4GP
PM_CLKRUN# 4 7 PCI_STOP# 453R2F-1-GP
5 6 PCI_FRAME# ICH9M-GP-NF DY
3D3V_S0
2
71.ICH9M.00U DY
2
SRN8K2J-2-GP-U No Reboot Strap
U16D 4 OF 6 SPKR LOW = Defaule RP2 3D3V_S5
High=No Reboot USB_OC#1 1 10
25 PCIE_RXN1 N29 V27 DMI_RXN0 7 PM_BATLOW#_R 2 9 USB_OC#5
PERN1 DMI0RXN 3D3V_S5 ECSWI# SMB_LINK_ALERT#
Direct Media Interface
1
10KR2J-3-GP
10KR2J-3-GP
SRN10KJ-5-GP
R298
27 PCIE_RXN5 E29
E28
PERN5 DMI_CLKN T26
T25
CLK_PCIE_ICH# 3
24D9R2F-L-GP
DY
PlanarID
27 PCIE_RXP5 PERP5 DMI_CLKP CLK_PCIE_ICH 3
27 PCIE_TXN5 C372 SCD1U10V2KX-5GP 2
C379 SCD1U10V2KX-5GP 2
1
1
TXN5
TXP5
F27
F26
PETN5
AF29
(1,0)
27 PCIE_TXP5
2
2
PETP5 DMI_ZCOMP
NEW CARD DMI_IRCOMP AF28 DMI_IRCOMP_R
R288
PCB_VER0
PCB_VER1
SA: 0,0 3D3V_S5
C29
C28
PERN6/GLAN_RXN
PERP6/GLAN_RXP USBP0N AC5 USBPN0 23 USB PWROK 1 2 R133 R145 SB: 0,1 R74
1
10KR2J-3-GP
10KR2J-3-GP
D27 AC4 10KR2J-3-GP 1 2
D26
PETN6/GLAN_TXN
PETP6/GLAN_TXP
USBP0P
USBP1N AD3
USBPP0
USBPN1
23
23 Pair Device SC: 1,0 0R2J-2-GP R73
AD2 DY 10KR2J-3-GP
D23
USBP1P
AC1
USBPP1
USBPN2
23
23 0 USB1 SD: 1,1
SPI_CLK USBP2N
D24 AC2 USBPP2 23 D7
2
SPI_CS#1 SPI_CS0# USBP2P RSMRST#_SB
F23 SPI_CS1#/GPIO58/CLGPIO6 USBP3N AA5 1 USB4 1
USBP3P AA4
D25 SPI_MOSI USBP4N AB2 USBPN4 23 2 USB2 30 RSMRST#_KBC 2 DY
1
SPI
2
USB_OC#3 OC2#/GPIO41 USBP6P
P6 OC3#/GPIO42 USBP7N Y3 USBPN7 27 5 Bluetooth 0 1 SPI
23 USB_OC#4 USB_OC#4 M1 Y2 USBPP7 27 1 0 PCI
A USB_OC#5 OC4#/GPIO43 USBP7P A
N2 OC5#/GPIO29 USBP8N W1 USBPN8 14 6 NC 1 1 LPC(Default)
USB_OC#6 M4 W2 USBPP8 14 A16 swap override strap
USB_OC#7 OC6#/GPIO30 USBP8P
M3 OC7#/GPIO31 USBP9N V2 USBPN9 27 7 MINIC1
USB_OC#8 N3 V3 low = A16 swap override enable
USB_OC#9 N1
OC8#/GPIO44
OC9#/GPIO45
USBP9P
USBP10N U5
USBPP9 27
USBPN10 24 8 WEBCAM PCI_GNT#3 high = default Wistron Corporation
USB_OC#10 P5 U4 USBPP10 24 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
USB_OC#11 OC10#/GPIO46 USBP10P PCI_GNT#0 1KR2J-1-GP Taipei Hsien 221, Taiwan, R.O.C.
P3 OC11#/GPIO47 USBP11N U1 9 NEW1 1 2 DY
U2 R286
R130 USBP11P
USB_RBIAS_PN AG2 10 CardReader SPI_CS#1 1 1KR2J-1-GP
2 DY Title
USBRBIAS R287
2 1 AG1 USBRBIAS#
11 NC GNT0 and SPI_CS#1 PCI_GNT#3 1 1KR2J-1-GP
2 DY ICH9-M (2 of 4)
22D6R2F-L1-GP R285 Size Document Number Rev
ICH9M-GP-NF have a weak internal pull up
71.ICH9M.00U Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 18 of 42
5 4 3 2 1
5 4 3 2 1
U16F 6 OF 6
RTC_AUX_S5
6uA in G3 A23 A15
VCCRTC VCC1_05
VCC1_05 B15 1.63A 1D05V_S0
V5REF_S0 A6 C15 Layout Note: Place near ICH9M
V5REF VCC1_05
1
C358 C359 D15
VCC1_05
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
V5REF_S5 AE1 E15
V5REF_SUS VCC1_05
1
F15 C405 C407 C396 C409 C398 C367 DY C382 C411 C377
2
VCC1_05
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AA24 VCC1_5_B VCC1_05 L11
AA25 L12
2
VCC1_5_B VCC1_05
AB24 VCC1_5_B VCC1_05 L14
AB25 VCC1_5_B VCC1_05 L16
1D5V_S0 AC24 L17
646mA AC25
VCC1_5_B
VCC1_5_B
VCC1_05
VCC1_05 L18
AD24 VCC1_5_B VCC1_05 M11
D AD25 M18 D
VCC1_5_B VCC1_05
1
C389 C422 C390 C412 C417 C423 AE25 P11
VCC1_5_B VCC1_05
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SC4D7U6D3V3MX-2GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY DY AE26 VCC1_5_B VCC1_05 P18
AE27 T11 1D5V_DMIPLL_ICH_S0
L10 23mA
2
2
VCC1_5_B VCC1_05 1D5V_S0
AE28 VCC1_5_B VCC1_05 T18
AE29 VCC1_5_B VCC1_05 U11 1 2
F25 U18 IND-1D2UH-10-GP
CORE
VCC1_5_B VCC1_05
1
G25 VCC1_5_B VCC1_05 V11 DY 68.1R220.10D
H24 V12 C400 C401
VCC1_5_B VCC1_05 SCD01U16V2KX-3GP SC4D7U6D3V3MX-2GP
H25 V14
2
VCC1_5_B VCC1_05
J24 VCC1_5_B VCC1_05 V16
J25 VCC1_5_B VCC1_05 V17
K24 V18 1D05V_S0
K25
VCC1_5_B
VCC1_5_B
VCC1_05
1 R294 2 48mA
1
SCD1U10V2KX-4GP
SC10U6D3V5MX-3GP
L23 R29 C413 C414 0R0603-PAD
VCC1_5_B VCCDMIPLL C415
*Within a given well, 5VREF needs to be up before the L24 VCC1_5_B DY
corresponding 3.3V rail L25 W23 1D05V_DMI_ICH_S0 DY SC4D7U6D3V3KX-GP
2
VCC1_5_B VCCDMI
M24 VCC1_5_B VCCDMI Y23
M25 1D05V_S0
N23
VCC1_5_B
AB23 2mA
47mA N24
VCC1_5_B
VCC1_5_B
V_CPU_IO
V_CPU_IO AC23
3D3V_S0 5V_S0 1D5V_S0 1D5V_APLL_S0 N25 3D3V_S0
L1 VCC1_5_B
1
P24 AG29 C406 C392 C393
VCC1_5_B VCC3_3
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1 2 P25 SC4D7U6D3V3KX-GP
VCC1_5_B
2
VCCA3GP
D10 IND-1D2UH-10-GP R24 AJ6 C430 C426 DY
2
VCC1_5_B VCC3_3
1
R276 68.1R220.10D R25 SCD1U10V2KX-4GP SCD1U10V2KX-4GP
2
CH751H-40PT 100R2J-2-GP C151 VCC1_5_B
R26 AC10
2mA VCC1_5_B VCC3_3
SC1U16V3ZY-GP
C152 R27
VCC3_3=308mA 3D3V_S0
2
SC10U6D3V5MX-3GP VCC1_5_B
T24 AD19
1
1
C T28 VCC1_5_B VCC3_3 AG24 C
1
VCCP_CORE
2
VCC1_5_B
U25 B9
2
VCC1_5_B VCC3_3
1
V24 F9 C378 C373 C370 C387
VCC1_5_B VCC3_3 11mA
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
V25 VCC1_5_B VCC3_3 G3 DY 3D3V_S0
1
U23 G6
2
Layout Note: 3D3V_S5 5V_S5 VCC1_5_B VCC3_3 C431
Place near ICH9
W24 VCC1_5_B VCC3_3 J2 DY SCD1U10V2KX-4GP
W25 J7
2
VCC1_5_B VCC3_3
K23 VCC1_5_B VCC3_3 K7
2
Y24
PCI
D13 R122 VCC1_5_B
CH751H-40PT Y25 VCC1_5_B VCCHDA AJ4
100R2J-2-GP 1D5V_S0
2mA 1.34A AJ19 VCCSATAPLL VCCSUSHDA AJ3 11mA 3D3V_S5
1
C376
1
2
VCC1_5_A VCCSUS1_05
1
ARX
SCD1U16V2ZY-2GP AE15 AD8
2
VCC1_5_A VCCSUS1_5
SC1U16V3ZY-GP
SC1U16V3ZY-GP
DY AF15 SCD1U10V2KX-4GP
2
VCC1_5_A 1D5V_S5
AG15 VCC1_5_A VCCSUS1_5 F18 1D5V_S5
1
AH15 C385
VCC1_5_A SCD1U10V2KX-4GP
AJ15 VCC1_5_A
A18 3D3V_S5
2
VCCSUS3_3
AC11 VCC1_5_A VCCSUS3_3 D16
AD11 VCC1_5_A VCCSUS3_3 D17
VCCPSUS
AE11 VCC1_5_A VCCSUS3_3 E22
1
ATX
AF11 C366 C369 C371
VCC1_5_A
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AG10 SCD1U10V2KX-4GP
VCC1_5_A
AG11 AF1 DY
2
VCC1_5_A VCCSUS3_3
AH10
B VCC1_5_A VCCSUS3_3=212mA B
1
SCD1U10V2KX-4GP
VCCSUS3_3 T2
AC9 T3 3D3V_S5
2
VCC1_5_A VCCSUS3_3
VCCSUS3_3 T4
DY AC18 VCC1_5_A VCCSUS3_3 T5
AC19 VCC1_5_A VCCSUS3_3 T6
1
U6 C410 C404 C402
VCCSUS3_3
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
AC21 U7 SCD1U10V2KX-4GP
VCC1_5_A VCCSUS3_3
V6
2
VCCSUS3_3
G10 V7 DY
VCCPUSB
VCC1_5_A VCCSUS3_3
G9 VCC1_5_A VCCSUS3_3 W6
VCCSUS3_3 W7
AC12 VCC1_5_A VCCSUS3_3 Y6
AC13 VCC1_5_A VCCSUS3_3 Y7
1D5V_S0 AC14 T7
USBPLL=11mA VCC1_5_A VCCSUS3_3
AJ5 VCCUSBPLL VCCCL1_05 G22 VccSus1_05[3] C386
1
DY SCD1U10V2KX-4GP
1
C418 C429 C416 AA7 VCC1_5_A VCCCL1_5 G23 VccSus1_5[3] TP145 TPAD28
3D3V_S0
SCD1U10V2KX-4GP
USB CORE
2
VCC1_5_A
DY AB7 A24
2
VCC1_5_A VCCCL3_3
AC6 VCC1_5_A VCCCL3_3 B24
3D3V_S0 AC7 VCC1_5_A
19mA in S0;78mA in S3/S4/S5 VccLan1D05 A10
19mA in S0;73mA in S3/S4/S5
VCCLAN1_05
1
SCD1U10V2KX-4GP DY A12
2
VCCLAN3_3
B12
23mA
2
VCCLAN3_3
A A
A27 VCCGLANPLL
1
GLAN POWER
C368 3D3V_S0
SC4D7U6D3V3KX-GP DY C383 1mA ICH9M-GP-NF ICH9-M (3 of 4)
SCD1U10V2KX-4GP 71.ICH9M.00U Size Document Number Rev
2
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 19 of 42
5 4 3 2 1
A B C D E
U16E 5 OF 6
8
7
6
5
AF5 VSS VSS R14
AF7 R15 RN43
VSS VSS
AF9 VSS VSS R16 SRN2K2J-2-GP
AG13 VSS VSS R17
AG16 VSS VSS R18
AG18 R28
1
2
3
4
VSS VSS
AG20 VSS VSS T12
AG23 VSS VSS T13
AG3 VSS VSS T14
AG6 VSS VSS T15
AG9 T16 5V_S0
VSS VSS
AH12 VSS VSS T17
AH14 VSS VSS T23
AH17 VSS VSS B26
AH19 VSS VSS U12
AH2 VSS VSS U13 Q6
AH22 VSS VSS U14
AH25 VSS VSS U15
AH28 VSS VSS U16 18,27 SMB_CLK 3 4 SMBC_ICH 3,12,13
AH5 VSS VSS U17
AH8 VSS VSS AD23 2 5
2 2
AJ12 VSS VSS U26
AJ14 VSS VSS U27 1 6 2N7002DW-1-GP
AJ17 VSS VSS U3
AJ8 VSS VSS V1
B11 VSS VSS V13 18,27 SMB_DATA
B14 VSS VSS V15 SMBD_ICH 3,12,13
B17 VSS VSS V23
B2 VSS VSS V28
B20 VSS VSS V29
B23 V4
B5
VSS
VSS
VSS
VSS V5 SMBUS
B8 VSS VSS W26
C26 VSS VSS W27
C27 VSS VSS W3
E11 VSS VSS Y1
E14 VSS VSS Y28
E18 VSS VSS Y29
E2 VSS VSS Y4
E21 VSS VSS Y5
E24 VSS VSS AG28
E5 VSS VSS AH6
E8 VSS VSS AF2
F16 VSS VSS B25
F28
AH1,AJ1,AJ2,AH29,AJ28,AJ29
1 VSS NCTF_VSS#A28 1
G24 B29 TP45 TPAD30
VSS NCTF_VSS#B29 TP98 TPAD30
G26 VSS NCTF_VSS#AJ1 AJ1
TP101 TPAD30
G27
G8
VSS
VSS
NCTF_VSS#AJ2
NCTF_VSS#AH1
AJ2
AH1 TP99 TPAD30 Wistron Corporation
H2 AJ28 TP102 TPAD30 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VSS NCTF_VSS#AJ28 TP100 TPAD30 Taipei Hsien 221, Taiwan, R.O.C.
H23 VSS NCTF_VSS#AJ29 AJ29
H28 AH29 TP97 TPAD30
VSS NCTF_VSS#AH29 Title
H29 VSS
ICH9-M (4 of 4)
ICH9M-GP-NF Size Document Number Rev
71.ICH9M.00U Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 20 of 42
A B C D E
3D3V_S0 5V_S0 D11 FAN1
RN7 SSM14PT-GP-U
1 4 EMC2102_FAN_TACH_1 5
5V_S0 2 3 EMC2102_FAN_TACH A K EMC2102_FAN_TACH_1 3
2
SRN10KJ-5-GP 83.1R004.E8M
EMC2102_FAN_DRIVE 1
*Layout* 15 mil 4
K
1
1
C107 C109 C332 D19 ACES-CON3-GP-U1
SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SC22U6D3V5MX-2GP SSM14PT-GP-U 20.F0714.003
2
83.1R004.E8M
2nd: 20.D0246.103
A
3D3V_S0 3nd: 20.F1000.003
R115 SMBC_Therm 30
SMBD_Therm 30
1 2 EMC2102_VDD_3D3
49D9R2F-GP
29
28
27
26
25
24
23
22
2
C118 U15
SMCLK
SMDATA
GND
FANa
FANb
TACH
VDD_5Va
VDD_5Vb
SCD1U16V2KX-3GP
1
4 H_THERMDC
1
Layout notice :
C119 Both H_THERMDA and THERMDC routing 1 21
SC470P50V3JN-2GP 10 mil trace width and 10 mil spacing VDD_3V NC#21
2
EMC2102_DP3 7 15
E
THERMTRIP#
POWER_OK#
SYS_SHDN#
Q12 B DY SC470P50V3JN-2GP SC470P50V3JN-2GP
FAN_MODE
SHDN_SEL
1
TRIP_SET
MMBT3904-3-GP
84.03904.L06 C373 must be near EMC2102
C
NC#8
2.System Sensor, Put between CPU and NB. GND = Channel 1
OPEN = Channel 3 SA
10
11
12
13
14
C375 must be near Q8 +3.3V = Disabled EMC2102-DZK-GP
74.02102.A73
Layout notice : Both DN3 and DP3 routing R113 3D3V_S0
E
Q7 B C83
MMBT3904-3-GP DY SC470P50V3JN-2GP C121 EMC2102_CLK_SEL 5 4
10KR2J-3-GP THRM#
84.03904.L06 SC470P50V3JN-2GP 6 3
1
C
10KR2J-3-GP SRN10KJ-6-GP
SCD1U16V2ZY-2GP
1
1
R290
C397 10KR2F-2-GP
2
PURE_HW_SHUTDOWN#
2
GND = Fan is OFF TRIP_SET Pin Voltage
RUN_POWER_ON V_DEGREE
OPEN = Fan is at 60% full-scale V_DEGREE
SCD1U16V2ZY-2GP
+3.3V = Fan is at 75% full-scale =(((Degree-75)/21)
1
1
Q10 R110
G
2
18 PM_SUS_CLK D S CLK_32K_R 1 2 CLK_32K
2
5 4 PURE_HW_SHUTDOWN#
1
6 3 T8 90 degree
R106 3D3V_AUX_S5 7 2 RSMRST#
2N7002-11-GP 240KR3-GP 8 1 EMC2102_FAN_mode
84.27002.N31
2
3D3V_AUX_S5 SRN10KJ-6-GP
32K suspend clock output
SA
2
D12
DY BAT54-7-F-GP
83.R2003.F81
3D3V_S0
1
Q11
RSMRST# 30,32
Wistron Corporation
G
(dummy, KBC already delay) 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1
Thermal/Fan Controllor
2
ODD1
SATA1
23
17 SATA_RXP1 S6 B+ GND 9 NP1
17 SATA_RXN1 S5 B- GND 8 1
GND P6
GND P5 2
17 SATA_TXP1 S2 A+ GND S7 3
17 SATA_TXN1 S3 A- GND S4 4
S1 5 5V_S0
5V_S0 GND
6
P3 P1 ODD_DP 7
+5V DP ODD_MD TP161 TPAD30
P2 +5V MD P4 8
9
K
1
1
10
K
1
SKT-SATA7P+6P-30-GP R199 11 TC23 C499 D23
DY C229 TC10 62.10065.441 10KR2J-3-GP 12 SSM24PT-GP
2
SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U16V2ZY-2GP
D15 2 13
2
14
A
2
SSM24PT-GP 15
A
16
17
18 SATA_RXP0 17
19 SATA_RXN0 17
20
C 21 SATA_TXN0 17 C
22 SATA_TXP0 17
NP2
24
SKT-SATA22P-27-GP
62.10065.471
B B
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5V_S5
USB1
5V_USB1_S0
RN44 USB1 U34 100 mil
2
5 3 IN#3 OUT#8 8
1 2 IN#2 OUT#7 7
1
6 TC15 TC14 EC114 EC115
OUT#6
ST150U6D3VDM-18GP
ST150U6D3VDM-18GP
SCD1U16V2ZY-2GP
SC1000P50V3JN-GP
D USB_0- 2 C424 DY DY D
18 USBPN0
DY USB_0+ 3 SC4D7U10V3KX-GP 5 DY
18 USBPP0
2
USB_PWR_EN# OC#
4 4 1
2
EN/EN# GND
6
DLW21HN900SQ2LGP G545A2P8U-GP
74.00545.A79
3
SKT-USB-198-GP
22.10218.W51 2nd source 74.09711.079
18 USB_OC#0
2 1 EC124
1
2nd: 22.10218.T51 SCD1U16V2ZY-2GP
R279 DY
0R0402-PAD 3nd: 22.10218.P01
2
R292
0R0402-PAD
2 1
5V_USB1_S0
USB2
RN48 USB2 USBCN1
1
5 16
1
1
USB_2- 2 USB4
18 USBPN2
DY USB_2+ 3 2
18 USBPP2
4 3 USBPN1 18
6 4 USBPP1 18
C 5 C
E-BUTTON# TP13 TPAD30 6 USB3
USBPN4 18
4
1
0R0402-PAD 14 C45
15 E-BUTTON# DY EC14 SC1U16V3ZY-GP
E-BUTTON# 30
SCD1U16V2ZY-2GP
Co-Layout Common Mode Choke and 0 Ohm
2
2
17 DY
EC13
JST-CON15-1-GP
SC220P50V2JN-3GP
1
21.D0214.115
2nd: 20.F1035.015
BLUETOOTH MODULE 1 11
B 1.5A / High Active Voltage 2V MDC 1.5 CONN 13 16 B
2
C297
14 17
SC4D7U10V5ZY-3GP 15 18
1
MDC1 2 12
3D3V_BT_S0 13 15
U26 3D3V_S0 C573 NP1 14
SC4D7U10V5ZY-3GP 1 2 3D3V_S5
3D3V_BT_S0 1 5 1 2 DY
VOUT VIN ACZ_SDATAOUT
2 GND 17,28 ACZ_SDATAOUT 3 4
3 4 39R2J-L-GP 5 6 3D3V_S5
NC#3 EN/EN#
1
ACZ_BTCLK_MDC 17
74.09711.A7F 17,28 ACZ_RST# 2 1ACZ_RST#_MDC NP2 17
R232 16 18
1
0R0402-PAD R398 C296
2nd:74.05240.A7F
1
2 1 SB 0R0402-PAD TYCO-CONN12A-2-GP-U1
1
SC4D7U10V5ZY-3GP
EC21 put near 20.F0917.012 R222 C295
(G5240B1T1U-GP)
100KR2J-1-GP
C542 DUMMY-C2
BLUE1 / all DY SC22P50V2JN-4GP 1 C531
2
2
choke near DY
2
4
BLUE1
6
1 3D3V_BT_S0
Wistron Corporation
1
20.D0197.104
USB_5- TP134 TPAD30 Title
2 1 USB_5+ TP136 TPAD30
2nd: 20.F0984.004 3D3V_BT_S0 TP133 TPAD30 USB/BLUETOOTH/MDC
R233 Size Document Number Rev
3nd: 20.F0689.004 0R0402-PAD
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 23 of 42
5 4 3 2 1
5 4 3 2 1
R400
3D3V_S0 3D3V_D_S0 3D3V_A_S0 0R2J-2-GP
SD_DAT1/XD_D3/MS_D1_1 2 DY 1 SD_DAT1/XD_D3/MS_D1
SD_DAT1/XD_D3/MS_D1_1
R428 R418
SD_CLK/XD_D1/MS_CLK
SD_DAT0/XD_D6/MS_D0
SD_DAT7/XD_D2/MS_D2
SD_DAT6/XD_D7/MS_D3
0R0603-PAD 0R0603-PAD
1 2 1 2 XD_D4 2 1
SD_DAT4/XD_WP#
SD_DAT3/XD_WE#
SD_DAT2/XD_RE#
SD_DAT5/XD_D0
R410
XD_CD#
SD_CD#
SD_WP
XD_D5/MS_BS
XD_D4
0R0402-PAD
D D
MS_INS#
XD_R/B#
XD_CLE
XD_CE#
XD_ALE
CARD_3D3V_S0
2
C539
DY SC1U10V3KX-3GP
1
3D3V_D_S0
U43
19
20
21
23
25
26
27
28
29
31
34
35
37
38
39
40
41
42
43
SP1
SP2
SP3
SP4
SP5
SP6
SP7
SP8
SP9
SP10
SP11
SP12
SP13
SP14
SP15
SP16
SP17
SP18
SP19
2
C544
2
SC1U10V3KX-3GP C524 U52
R409 SCD1U16V2ZY-2GP 9 24
1
0R0603-PAD CARD_3V3 MS_D5 EECS
22 1 DY VCC 8
1
VREG AV_PLL MS_D4 EESK S
1 2 1 AV_PLL 2 C DU 7
2
EEDO 3 6 C565
R423 VREG EEDI D ORG SCD1U16V2ZY-2GP
10 VREG 4 Q GND 5
0R0603-PAD 30 DY
1
3V_VBUS_S0 NC#30
3D3V_S0 1 2 8 3V3_IN NC#7 7 3D3V_A_S0
3 M93C46-WMN6TP-GP
NC#3
1
3D3V_D_S0 33 D3V3
1
1
SC4D7U6D3V5KX-3GP SCD1U16V2ZY-2GP C529 SCD1U16V2ZY-2GP
2
DY C548 SCD1U16V2ZY-2GP
2
SCD1U16V2ZY-2GP
2
MODE_SEL 45
R429 LED7 SD_CMD MODE_SEL
36 SD_CMD GND 6
3D3V_S0 1 DY 2 VBUS_R ADY K VBUS_LED 14 12
R394 GPIO0 GND
2 RREF GND 32
XTAL_CTR
C 68R2-GP LED-W-23-GP 1 2 RREF 44 46 C
RST# GND
EEDO
EECS
EESK
XTLO
6K19R2F-GP RST#
EEDI
XTLI
3D3V_D_S0
DM
-4
DP
DY C516
RTS5158E-GR-GP SC5D6P50V2CN-1GP
5
4
13
47
48
17
16
15
18
1
1
R386
1
2
XDAL_CTR
100KR2J-1-GP C511 INS61335435 1 USB_10+ R388
EEDO
2
EECS
EESK
EEDI
SC47P50V2JN 10KR2J-3-GP 18 USBPP10 R396 0R0402-PAD 270KR2F-GP X4
DY DY
2
RST# DY DY 1USB_10-
12M_XO
2 XTAL-12MHZ-11GP
2
12M_XI
18 USBPN10 R395 0R0402-PAD DY 82.30006.191
2
1
1
C510 2 1 12M_XO
SC1U10V3KX-3GP R416
0R0402-PAD C515
2
3D3V_D_S0 2 1 SC5D6P50V2CN-1GP
R393
0R0402-PAD
3 CLK48_5158E 2 1 12M_XO
B B
CARD_3D3V_S0 23 25 SD_DAT0/XD_D6/MS_D0
CARD_3D3V_S0 SD_VCC SD_DAT0
14 29 SD_DAT1/XD_D3/MS_D1
MS_VCC SD_DAT1 SD_DAT2/XD_RE#
33 XD_VCC SD_DAT2 10
11 SD_DAT3/XD_WE#
SD_DAT3
1
CARD-PUSH-36P-4-GP Title
20.I0081.001
CARDREADER- RTS5158E
2nd: 20.I0067.001 Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 24 of 42
5 4 3 2 1
5 4 3 2 1
3D3V_LAN_S5
DY 3D3V_LAN_S5
3D3V_LAN_S5 1 R61 2
1
2
3
4
0R2J-2-GP 8Kbit
RN3
R66 SRN4K7J-10-GP
U13
1 0R0603-PAD
2 LANPWR 2 R49 1 VPD_DATA
LAN_CLKREQ#
3D3V_S0
4K7R2J-2-GP VPD_CLK
1 8
8
7
6
5
3D3V_LAN_S5 1D8V_LAN_S5 A0 VCC
2 A1 WP 7
3 6 VPD_CLK
A2 SCL VPD_DATA
4 GND SDA 5
1D8V_LAN_S5 LANLOM
D D
AT24C256BN-SH-T-GP
72.24256.R01
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
U8 Pull up for AT24C08 another pull low
TESTMODE
SMDATA
SPI_CS
SPI_DI
VPD_DATA
VPD_CLK
SPI_CLK
CLKREQ#
SPI_DO
VDD
VMAIN_AVLBL
VDDO_TTL
VDD
VDDO_TTL
VDD
VDD
18 PCIE_RXP1 C55 SCD1U10V2KX-5GP 2 1 PCIE_RXP1_LAN 49 32 Main source:72.24C08.I01
TX_P NC#32
18 PCIE_RXN1 C56 SCD1U10V2KX-5GP 2 1 PCIE_RXN1_LAN 50 31 2nd source:72.24C08.E01
TX_N MDIN3 MDI3- 26
51 NC#51 MDIP3 30 MDI3+ 26
52 NC#52 RESERVED#29 29
3D3V_S5 54 27
18 PCIE_TXP1 RX_P MDIN2 MDI2- 26
SMB_ALERT#_LAN 58 23
VDD AVDD
26 LAN_ACT_LED# 59 LED_ACT# AVDD 22
C
DY
R70 LAN_LED_10/100/1G C
26 10M/100M/1G_LED# 1 2 60 LED_LINK10/100# MDIN1 21 MDI1- 26
0R2J-2-GP
61 VDDO_TTL MDIP1 20 MDI1+ 26
63 18
LOM_DISABLE#
LED_DUPLEX# MDIN0 MDI0- 26
PERST#/TSTPT
SWITCH_VAUX
DY
SWITCH_VCC
VAUX_AVLBL
AVDDH/3_3V
64 17 MDI0+ 26
VDDO_TTL
SC1KP50V2KX-1GP SMCLK MDIP0
CTRL12
CTRL18
WAKE#
65
XTALO
GND
XTALI
RSET
VDD
VDD
VDD
PLACE PNP TO CHIP ACAP 88E8071-B0-GP
10
11
12
13
14
15
16
CTRL12 PIN TRACE IS 25MIL 71.88071.A03
R270
3D3V_LAN_S5 1 2 3D3V_LAN_S5_2
0R0603-PAD 1D2V_LAN_S5
1
C72 C356
R79 SC4D7U6D3V3KX-GP R36
4K7R2J-2-GP DY SCD1U10V2KX-4GP CTRL12 LANRSET 1 2
2
B B
84.00069.A1B
1
C68 DY
SCD1U10V2KX-4GP C75 R41
SC10U6D3V5KX-1GP 1 2
18,27 PCIE_WAKE#
2
LANX1 10MR2J-L-GP
LANX2 X1 82.30020.571
LANX2 1 2 LANX1
1
PLACE PNP TO CHIP ACAP XTAL-25MHZ-67GP
3D3V_S5 3D3V_LAN_S5 CTRL25 PIN TRACE IS 25MIL SB
R68 C30 C23
2
1 2 SC15P50V2JN-2-GP SC15P50V2JN-2-GP
0R0603-PAD
1
SC10U6D3V5KX-2GP
SC10U6D3V5KX-2GP
SCD1U10V2KX-4GP
4K7R2J-2-GP
SC4D7U6D3V3KX-GP
DY 2 2
2
CTRL18 1 1 2 1 2 1 2
B
4 C345 SC1KP50V2KX-1GP C330 SCD1U10V2KX-4GP C343 SC1U6D3V2KX-GP
C
Q9 2 1 2 1 2 1 2
C
DCP69A-13-GP C338 DY SC1KP50V2KX-1GP C327 SCD1U10V2KX-4GP C333 SC1U6D3V2KX-GP
84.00069.A1B 1D8V_LAN_S5 1 2 1 2 1 2
C337 SC1U6D3V2KX-GP C328 SC1KP50V2KX-1GP C25 SC1KP50V2KX-1GP
1
C69 1 2 1 2 1 2
C77 SCD1U10V2KX-4GP C340 SC1U6D3V2KX-GP C57 DY SC1KP50V2KX-1GP C339 SC1KP50V2KX-1GP
A
SC10U6D3V5KX-1GP 1 2 1 2 1 2 A
2
88E8071
Size Document Number Rev
A3
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 25 of 42
5 4 3 2 1
A B C D E
LAN Connector
1.route on bottom as differential pairs. LAN_ACT_LED#
2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
3.No vias, No 90 degree bends. 10M/100M/1G_LED#
Co-Layout Common Mode Choke and 0 Ohm
4.pairs must be equal lengths.
5.6mil trace width,12mil separation.
4 4
6.36mil between pairs and any other trace. R250
7.Must not cross ground moat,except 0R0402-PAD DY DY
2 1 C311 C310
RJ-45 moat. SC1KP50V2KX-1GP SC1KP50V2KX-1GP
XF1
1 24 RJ45_1_1
25 MDI0+
RN39
2
1D8V_LAN_S5
R31
1 2 V_DAC
0R0603-PAD
25 MDI0- 2
3
23
22
RJ45_2_1
MCT1
RJ45_1_1
RJ45_2_1 DY
RJ45_1
RJ45_2 LAN Connector
4 21 MCT2 DLW21HN900SQ2LGP RJ1
5 20 RJ45_3_1 9
25 MDI1+
3
DY A1
1
C9 C10 CONN_PWR A2
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
25 10M/100M/1G_LED# A3
RJ45_1 1 A3:GREEN
2
2 1
RJ45_2
6 19 RJ45_6_1 R251 RJ45_3
2
3
B2:Orange
25 MDI1-
0R0402-PAD RJ45_4 4
7 18 RJ45_4_1 RJ45_5 5
25 MDI2+
R248 RJ45_6 6
0R0402-PAD RJ45_7 7
3 2 1 RJ45_8 8 3
CONN_PWR2 B1
25 LAN_ACT_LED# B2
8 17 RJ45_5_1 10
25 MDI2-
9 16 MCT3 RN38
2
RJ45-124-GP-U1
10 15 MCT4 22.10277.011
11 14 RJ45_7_1
25 MDI3+
RJ45_3_1 RJ45_3 2nd: 22.10277.061
DY RJ45_6_1 DY RJ45_6
1
SCD1U10V2KX-4GP
3
12 13 RJ45_8_1 LAN Data: Yellow(B2), when LAN is
25 MDI3-
transfering data.
XFORM-270-GP-U
68.69241.301
2 1
R246 R249
0R0402-PAD 0R0402-PAD
2 1 DOC_TIP,DOC_RING,TIP,RING:
W/S : 10/100 @ Surface layers
RN37
10/20 @ Inner layers
1
2 2
RJ45_4_1 RJ45_4
RJ45_5_1 DY RJ45_5
3D3V_LAN_S5 1 2 CONN_PWR2
DLW21HN900SQ2LGP R243 470R2J-2-GP
1 2 CONN_PWR
4
R252 470R2J-2-GP
2
EC90 EC87
1
SC100P50V2JN-3GP
SC100P50V2JN-3GP
2 1 R244 DY DY
0R0402-PAD MCT1
R247 2 1 MCT2
0R0402-PAD MCT3
MCT4
8
7
6
5
RN36 RN40
1
SRN75J-1-GP
RJ45_7_1 RJ45_7
1
2
3
4
RJ45_8_1 DY RJ45_8
MCT_R
1
DLW21HN900SQ2LGP 1
4
2
C312
SC1KP2KV8KX-GP Wistron Corporation
1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2 1 Taipei Hsien 221, Taiwan, R.O.C.
R245 Title
0R0402-PAD
LAN CONN
Size Document Number Rev
A3
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 26 of 42
A B C D E
A B C D E
CARDBUS-SKT107-GP
21.H0168.001
2nd: 21.H0182.001 1D5V_S0 3D3V_MINI
4 4
NEW1 3D3V_MINI
MINIC1
NP2
26 53
18 PCIE_TXP5 25 NP1
24 TPAD30 TP12 MINI_WAKE# 1 2
18 PCIE_TXN5
23
18 PCIE_RXP5 22 3 4
18 PCIE_RXN5 21 5 6
20 7 8
3 CLK_PCIE_NEW 19 9 10
3D3V_NEW_S0 18 11 12
3 CLK_PCIE_NEW# CPPE# 3 CLK_PCIE_MINI1#
17 3 CLK_PCIE_MINI1 13 14
TP127 NEW_PIN16 16 15 16 R78
2
15 DY 1 DY 2
14 C80
3D3V_NEW_LAN_S5 TPS2231_PERST# 13 17 18 SC100P50V2JN-3GP 10KR2J-3-GP
1
30 E51_RxD
12 30 E51_TxD 19 20 WIRELESS_EN 30
18,25 PCIE_WAKE# 1DY 2 PCIE_WAKE#_NEW 11 21 22 PLT_RST1#_WLAN 1 2
R219 0R2J-2-GP PLT_RST1# 7,18,25,30,31
1D5V_NEW_S0 10 18 PCIE_RXN2 23 24
RN34 9 18 PCIE_RXP2 25 26 R85
1 DY 4 SMB_DATA_NEW 8 27 28 RN5 300R2F-GP SB
18,20 SMB_DATA
2 3 SMB_CLK_NEW 7 29 30 SMB_CLK_WLAN 1 DY 4
18,20 SMB_CLK SMB_CLK 18,20
SRN33J-5-GP-U CONN_TP1 6 18 PCIE_TXN2 31 32 SMB_DATA_WLAN2 3 SMB_DATA 18,20
TP123 CONN_TP2 5 18 PCIE_TXP2 33 34 SRN33J-5-GP-U
TP122 CPUTSB# 4 35 36 USBPN7 18
3 37 38 USBPP7 18
18 USBPP9 2 39 40
3D3V_MINI
3 18 USBPN9 41 42 LED_WWAN# 1 TPAD28 TP36 3
1 20.F0789.026 43 44 WLAN_LED#_MC 16
NP1 45 46 LED_WPAN# 1
2nd: 62.10081.131 47 48 TPAD28 TP42
49 50
FCI-CON26-5-GP 5V_S5 51 52
NP2 SB
54
3D3V_S5
SKT-MINI52P-15-GP
RN54
CPUTSB# 2 3 20.F1049.052 R454 0R2J-2-GP
CPPE# 1 DY 4 3D3V_S0 1 2 3D3V_MINI
2nd: 62.10043.511
TPS2231_PERST# SRN100KJ-6-GP R455 0R2J-2-GP
18,30,36,37 PM_SLP_S4# R369 3nd: 62.10043.461 3D3V_S5 1 DY 2
PLT_RST1#_NEWCARD 2 1 PLT_RST1# 7,18,25,30,31
100R2J-2-GP
U38
20
10
1 2
8
9
SC100P50V2JN-3GP SB
3D3V_S0 1D5V_S0 3D3V_S5
1
2 TC8 C97 C87 C96 2
21 THERMAL_PAD 1.5VOUT 11 1D5V_NEW_S0 DY DY
SCD1U16V2ZY-2GP
17 C27 C576
AUXIN 3D3V_S5
SC1U6D3V2KX-GP
SC1U6D3V2KX-GP
SCD1U16V2ZY-2GP
15 ST330U6D3VDM-17GP SCD1U16V2ZY-2GP
3D3V_NEW_LAN_S5
2
AUXOUT
7 GND
NC#16
NC#14
NC#13
NC#5
NC#4
TPS2231RGP-GP
74.02231.073
16
14
13
5
4
1D5V_S0 3D3V_S0
1D5V_NEW_S0 3D3V_NEW_S0
1
C493 1
1
C509 C283
SCD1U16V2ZY-2GP
Title
A B C D E
5 4 3 2 1
5V_S0
4.75V / 300mA
U21
1 5 5VA_S0
EN NC#5
2 GND
D 3 VIN VOUT 4 D
1
RT9198-4GPBG-GP
1
C272 74.09198.A7F C267
SC1U10V3KX-3GP 74.09091.F3F SC10U10V5ZY-1GP
2
G9091-475T12U-GP
2
3D3V_S0 5VA_S0
C182 "VAUX" Pull high to enable standby mode
29 AMP_BEEP 1 2 AMP_BEEP_1
SCD47U16V3ZY-3GP RN21
DY 4 5 C213 C247
1
3 6 C208 SCD1U10V2KX-4GP SC10U10V5ZY-1GP
1
KBC_BEEP_1 2 7 AUDIO_BEEP 1 2AUDIP_PC_BEEP C206 DY C240
1 8 SC10U10V5ZY-1GP SCD1U10V2KX-4GP SB
2
SC1U10V3KX-3GP
2
C188 SRN47KJ-1-GP C210 SC100P50V2JN-3GP
1
30 KBC_BEEP 1 2 1 2
SCD47U16V3ZY-3GP R159 C204 R162
C194 10KR2J-3-GP SC100P50V2JN-3GP RESET# 2 1 ACZ_RST# 17,23
2
18 ACZ_SPKR 1 2 SPKR_SB_1 100R2J-2-GP
ACZ_SYNC 17,23 R178
2
SCD47U16V3ZY-3GP BCLK 2 R164 1 ACZ_BITCLK 17 1 2 LINEOUT_JD# 29
0R0402-PAD 39K2R2F-L-GP
1 2
C C212 DY R172 C
SC22P50V2JN-4GP ALC268_SENSE 1 2 LINEIN_JD# 29
10KR2F-2-GP
C211
2DY R175
25
38
12
11
10
33
44
43
34
13
1
1
9
6
U20 1 2 MIC_JD# 29
SC22P50V2JN-4GP 20KR2F-L-GP
PCBEEP
BCLK
SENSE_B
SENSE_A
DVDD-IO
AVDD1
AVDD2
RESET#
SYNC
DVDD
NC#33
NC#44
NC#43
Sense resistors need close codec
1
1 2 SEL_MIC 31
1KR2F-3-GP GPIO1
ALC268 NC#45 45
SB D14
BAW56-7-F-GP
2
29 AUD_MICIN_L SC4D7U10V3KX-GP 2 1 C232 MIC1-L_PORT-B 21 46
29 AUD_MICIN_R SC4D7U10V3KX-GP 2 1 C238 MIC1-R_PORT-B 22
MIC1-L_PORT-B DMIC-CLK R187 DY
SC1U16V3ZY-GP C226 IMT_MIC1-L MIC1-R_PORT-B 0R0402-PAD 2ND = 83.00056.G11
1 2 16
3
16 INT_MIC SC1U16V3ZY-GP C228 IMT_MIC1-R MIC2-L_PORT-F
1 2 17 MIC2-R_PORT-F HP-OUT-L_PORT-A 39 FRONTL 29
41 FRONTR 29 R170
1
HP-OUT-R_PORT-A
RN46
1 8 MIC1V_R 32 29 ALC268_EAPD 1 2 3D3V_S0
MIC1V_L MIC1-VREFO-R
2 7 28 35
MIC1-VREFO-L LINE-OUT-L_PORT-D SOUNDL 29 DY
DMIC-12/GPIO0
DMIC-34/GPIO3
3 6 MIC2-VREFO 30 36 SOUNDR 29
B MIC2-VREFO LINE-OUT-R_PORT-D 10KR2J-3-GP B
4 5
MONO-OUT
2
SC4D7U10V5ZY-3GP
SC4D7U10V5ZY-3GP
DVSS
DVSS
VREF
CD-G
CD-R
CD-L
1
ALC268-GR-GP
26
42
4
7
27
40
37
2
3
18
20
19
71.00268.00G
SB
SB
2
JDREF
Change to 71.00268.A0G
R165
MONO-OUT 10KR2F-2-GP
VREF DY
1
TP116
1
1
TPAD30
1
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Azalia codec ALC268
Size Document Number Rev
A3
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 28 of 42
5 4 3 2 1
A B C D E
C132 R129
AUDIO OP AMPLIFIER 5V_S0
SA
1
1 2 2 1 INR_A SB
28 SOUNDR R137
16KR2F-GP
C133 R127 5V_S0 3D3V_S0
SC1U10V3KX-3GP 0R0402-PAD
2
4 1 2 2 1 INL_A SET 4
28 SOUNDL
1
C138 C137 C161
SCD1U16V2ZY-2GP
SC10U6D3V5MX-3GP
C128 R128 SC1U10V3KX-3GP
1
SC3D3U10V5ZY-1GP 40K2R2F-GP
2
R138
1 2 1 2 INR_H 30KR2F-GP
28 FRONTR
2
C129 R126
SC3D3U10V5ZY-1GP 40K2R2F-GP
28 FRONTL 1 2 1 2 INL_H
R143
R139 DY 0R2J-2-GP
0R2J-2-GP HP_EN 2 1 AMP_SHUTDOWN# 28,30
U18 2 1 AMP_BEEP 28
2
5V_S0
DY C163
GND 29 1 2 ALC268_EAPD 28
1 28 SCD1U16V2ZY-2GP R142
1
VDD BEEP SPK_EN# 0R0402-PAD
INR_A
2 GND AMP_EN# 27
SET
DY 5V_S0
3 INR_A SET 26
C168 INR_H 4 25 BIAS
SC2D2U6D3V3MX-1-GP INL_A INR_H BIAS HP_EN
5 INL_A HP_EN 24
1
INL_H 6 23
INL_H PGND SPKR_R+ R147
1 2 7 PGND ROUT+ 22
SPKR_L+ 8 21 SPKR_R- 10KR2J-3-GP
BIAS SPKR_L- LOUT+ ROUT-
9 LOUT- PVDD 20 5V_S0
10 19 3D3V_S0
2
3 PVDD HVDD SPKR_L+1 SPK_EN# 3
1 2 11 CVDD HP_L 18
12 17 SPKR_R+1
C162 CP+ HP_R Q14
13 16
D
CGND HVSS
1
1
APA2057ARI-TRL-GP C153 G AMP_SHUTDOWN# 28,30
74.02057.01G SC1U10V3KX-3GP
S
2
Internal Speaker EC60 MIC IN MICIN1 Analog Int. Mic
5
INTSPK1
SPKR_R+
DY
2 1 remove to LED Board
1
SC1KP50V2KX-1GP NP2 SB
SPKR_R- 2 NP1
SPKR_L+ 3 5
2 SPKR_L- 28 MIC_JD# RN66 2
4 4
2 3 AUD_MIC_R 3
28 AUD_MICIN_R
1 4 6 5V_S0 5V_S0 For ESD
ACES-CON4-1-GP-U1 AUD_MIC_L 2
6
28 AUD_MICIN_L
1
1
EC1 EC2 EC3 EC4 20.D0197.104 SRN1KJ-7-GP 1
1
SPKR_L- TP1 TPAD30 DY DY DY D28 D27
SHIELDING
SPKR_L+ TP2 TPAD30 DY R321 R326 EC140 EC145 DY 1SS400PT 1SS400PT
2
SC1KP50V2KX-1GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC1KP50V2KX-1GP
SPKR_R- TP3 TPAD30 2nd: 20.F0984.004 10KR2J-3-GP DY 10KR2J-3-GP PHONE-JK233-GP-U2 DY
2
SPKR_R+ TP4 TPAD30 DY DY DY 22.10133.B01
2
3nd: 20.F0689.004 2
2
2nd: 22.10251.491 SPKR_L_A1
2
AUD_MICIN_R TP160 TPAD30
AUD_MICIN_L TP159 TPAD30 U55 U56 DY
LINEIN_JD# TP105 TPAD30 SD05C-1-GP SD05C-1-GP
LOUT1
NP2 SB
LINE_IN_R
LINE_IN_L
TP154
TP153
TPAD30
TPAD30 DY
2
EC52
1 LINE IN LINEIN1 DY
1
NP1 SC1KP50V2KX-1GP NP2
5 LINEOUT_JD# LINEOUT_JD# 28 NP1
4 28 LINEIN_JD# 5
3 SPKR_R_A1 RN68 SPKR_R+1 RN67 4
6 1 4 2 3 AUD_LINE_R 3
SPKR_L_A1 SPKR_L+1 28 LINE_IN_R
2 2 3 1 4 6
1 1 AUD_LINE_L 2 1
EC152 28 LINE_IN_L SRN1KJ-7-GP
SRN68J-5-GP 1
2
SHIELDING
C466 C473 R329 1
Wistron Corporation
1
SC1KP50V2KX-1GP
SHIELDING
PHONE-JK235-GP-U2 DY SC680P50V2KX-2GP DY R335
SC680P50V2KX-2GP
1KR2J-1-GP
22.10133.B21 1KR2J-1-GP R303 EC127 EC128 PHONE-JK234-GP-U2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
A B C D E
A
D24
6 1 KBRCIN#_KBC
17 KBRCIN#
5 2 KA20GATE_KBC
17 KA20GATE
3D3V_AUX_S5
4 3 ECSCI#_KBC
18 ECSCI#_1
U39
1
CH731UPT-GP C528 C535 C533 3D3V_AUX_S5 3D3V_S0
SA
1
17,31 LPC_LAD[0..3] SCD1U16V2ZY-2GP
DY C520 INT_SERIRQ 3 22 SC10U10V5ZY-1GP
2
PCLK_KBC 18 INT_SERIRQ LPC_LFRAME# SERIRQ VCC L16 SCD1U16V2ZY-2GP
2 1 4 LFRAME# VCC 33
17,31 LPC_LFRAME# PCLK_KBC 12 125 BLM11P600S
3 PCLK_KBC PCICLK VCC
8
7
6
5
SC4D7P50V2CN-1GP PM_CLKRUN# 38 111
18 PM_CLKRUN# CLKRUN# VCC
LPC_LAD0 10 96 RN55
2
5V_S5 LPC_LAD1 LAD0 VCC C498 SCD1U16V2ZY-2GP
8 LAD1 VCC 9 SRN4K7J-12-GP
4
R372 LPC_LAD2 7 67 AVCC 1 2 4
1
2
3
4
GND
2
10KR2J-3-GP C514 ECRST# 37 24 R375
SC100P50V2JN-3GP KBRCIN#_KBC ECRST# GND 0R0603-PAD BAT_SCL
2 KBRST# GND 35 SMBC_Therm 21
SA ECSCI#_KBC 20 BAT_SDA
SMBD_Therm 21
1
KA20GATE_KBC SCI#
1 GA20 GND 113
2 R392 1 PLT_RST1#_1 13 94
7,18,25,27,31 PLT_RST1# PCIRST# GND
2 R376 1 SPI_WP_R# 0R0402-PAD
31 SPI_WP# 0R0402-PAD 77
KBC_BEEP SCL1 BAT_SCL 39,40
28 KBC_BEEP 21 PWM0 SDA1 78 BAT_SDA 39,40
TP172 CHG_I_PWM 23 80 SMBD_Therm
TP171 KBC_GPIO12 PWM1 SDA2 SMBC_Therm
26 FANPWM1 SCL2 79
SPI_WP_R# 27
FOR KBC DEBUG 28
FANPWM2
KBC_GPIO15 FANFB1 CCD_ON TP168
R360 29 FANFB2 GPO3C 68
DY 70 USB_PWR_EN# USB_PWR_EN# 23
KCOL2 GPO3D KBC_GPIO3E TP170
1 2 GPO3E 71
KCOL0 39 72 CHG_BCTL1 TP173
0R2J-2-GP KCOL1 KSO0 GPO3F AD_IA
40 KSO1 AD0 63 AD_IA 39
KCOL2 41 64
KCOL3 KSO2 AD1
R359 42 KSO3 AD2 65
DY KCOL4 43 66
KCOL3 KCOL5 KSO4 AD3
1 2 44 KSO5
ECRST# KCOL6 45
3D3V_AUX_S5 0R2J-2-GP KCOL7 KSO6 FLASH_SEL TP176
46 KSO7 GPXIOA0 97
Q19 KCOL8 47 98 WIRELESS_BTN# WIRELESS_BTN# 16
RN53 KSO8 GPXIOA1
1
2
1
R381
2 DY 1 KBC_GPIO0C PM_SLP_S3# 6 128
18,27,32,36,37,38 PM_SLP_S3# GPIO4 SPICS# SPICS# 31
120 SPIDO 31 RN57
10KR2J-3-GP KBC_PWRBTN# WR# SRN10KJ-5-GP
16 KBC_PWRBTN# 14 GPIO7 RD# 119 SPIDI 31 R380
PM_SLP_S4# 15 89 AC_IN# DY
18,27,36,37 PM_SLP_S4# GPIO8 GPIO50 AC_IN# 39
76 KBC_MATRIX0# 2 1 3D3V_AUX_S5
3
4
AD5 CHARGE_LED Volume_Down#
GPIO52 90 CHARGE_LED 16
40 BAT_IN# BAT_IN# 17 Volume_Up#
KBC_GPIO0C GPIO0B E51_TxD 10KR2J-3-GP
18 GPIO0C GPIO16 30 E51_TxD 27
1
GMCH_BL_ON 19 31 E51_RxD E51_RxD 27 DY DY
7 GMCH_BL_ON GPIO0D GPIO17
14 BRIGHTNESS BRIGHTNESS 25 SA C545 C546
3D3V_AUX_S5 GPIO11 NUM_LED# SC100P50V2JN-3GP SC100P50V2JN-3GP
36 NUM_LED# 16
2
RN56 GPIO1A CAP_LED#
34 GPIO19 GPIO53 91 CAP_LED# 16
1 4 LID_CLOSE# 93 FRONT_PWRLED 5V_AUX_S5
GPIO55 FRONT_PWRLED 16
2 3 BAT_IN# R364
75 E51_RxD 1 2
SRN100KJ-6-GP STDBY_LED AD4 KBC_XI 10KR2J-3-GP
16 STDBY_LED 92 GPIO54 XCLKI 122
27 WIRELESS_EN WIRELESS_EN 95 123 KBC_XO
BLUETOOTH_EN GPIO56 XCLKO C543
23 BLUETOOTH_EN 121 GPIO57
SPICLK 126 124 1 2 SC3D3U10V5KX-2GP
31 SPICLK SPICLK V18R
CHG_ON# 127 SB
39 CHG_ON# GPIO59 3D3V_AUX_S5
RN69
LID_CLOSE# 16 74 SEL_CP
14 LID_CLOSE# GPIO0A GPIO41
ECSWI# 32 73 KBC_GPIO40 TP174 C537 1 4 KBC_THERMALTRIP#
18 ECSWI# GPIO18 GPIO40 SC27P50V2JN-2-GP 3D3V_S0 2 3 E-BUTTON#
71.03310.00G
3
SB
X5
change to 71.03310.A0G X-32D768KHZ-38GPU
82.30001.691 SA
R379
SEL_CP 1 2
2
10KR2J-3-GP
27
1
TPAD30 TP65 KCOL13 EC36 1 2SC220P50V2JN-3GP 1 12
1
KB1
EC129 EC132
SCD1U10V2KX-4GP
T/P
SCD1U10V2KX-4GP
KROW7
1
2
14
2
RN52 12 EC130 EC131
TPAD30 TP77 KCOL4 EC27 1 2SC220P50V2JN-3GP 11
KCOL10
KCOL11
KCOL12
KCOL13
KCOL14
KCOL15
KCOL16
KCOL17
SRN10KJ-5-GP
KCOL0
KCOL1
KCOL2
KCOL3
KCOL4
KCOL5
KCOL6
KCOL7
KCOL8
KCOL9
1
SC100P50V2JN-3GP
SC100P50V2JN-3GP
TPAD30 TP76 KCOL2 EC25 1 2SC220P50V2JN-3GP TP_CLK 9 DY DY
SC220P50V2JN-3GP
SC220P50V2JN-3GP
TPAD30 TP60 KCOL1 EC24 1 2SC220P50V2JN-3GP 8
4
3
7
TP_RIGHT 6
RN50 5
TPAD30 TP74 KROW0 EC41 1 2SC220P50V2JN-3GP TPDATA 1 4 TP_DATA 4
1
TPAD28 TP67 KCOL17 EC40 1 2SC220P50V2JN-3GP TPAD30 TP71 KROW7 EC48 1 2SC220P50V2JN-3GP TPCLK 2 3 TP_CLK 3
1
3D3V_AUX_S5
4 4
5
6
7
8
RN58
3D3V_AUX_S5
SRN10KJ-6-GP
4
3
2
1
2
SPI_HOLD# ER2
0R0603-PAD
U50
1
30 SPICS# 1 8 3D3V_AUX_S5_SPI_ROM
CS# VCC
30 SPIDI 2 ER1 1 SPIDI_ROM 2 DO HOLD# 7 SPI_HOLD# ER4
0R0603-PAD SPI_WP# 3 6 SPICLK_ROM 1 20R2J-2-GP SPICLK 30
WP# CLK SPIDO_ROM
30 SPI_WP# 4 GND DIO 5 2 1 SPIDO 30
ER3 0R0603-PAD
1
1
EC160 EC159 W25X16VSSIG-GP
1
SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP 72.25X16.001 EC167
2
DY DY EC166
SC4D7P50V2CN-1GP
SC4D7P50V2CN-1GP
16M Bits
2
DY
SPI FLASH ROM
3 3
MXIC: 72.25165.A01
WinBond: 72.25X16.001
TOP VIEW
LPC_LAD[0..3]
17,30 LPC_LAD[0..3]
2 A15 (B1) GOLDEN FINGER FOR DEBUG BOARD 2
A14 (B2)
5V_S0 5V_S0
....
U27
....
A1 A1 B1 B1
A2 (B14) PLT_RST1# A2 B2 PLT_RST1#
7,18,25,27,30 PLT_RST1# LPC_LFRAME# A2 B2 LPC_LFRAME#
17,30 LPC_LFRAME# A3 A3 B3 B3
A1 (B15) PCLK_FWH
A4 A4 B4 B4
PCLK_FWH
3 PCLK_FWH A5 A5 B5 B5
A6 A6 B6 B6
1
FWH_INIT# A7 B7 FWH_INIT#
R444 DY 17 FWH_INIT# A7 B7
A8 A8 B8 B8
100R2J-2-GP LPC_LAD3 A9 B9 LPC_LAD3
LPC_LAD2 A9 B9 LPC_LAD2
A10 B10
(BOTTOM VIEW) LPC_LAD1 A11
A10 B10
B11 LPC_LAD1
2
FOX-GF30
ZZ.GF030.XXX
PCLK_FWH
1
1 1
EC171
SC5P50V2CN-2GP
2
DY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BIOS/GOLDEN FINGER
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 10, 2008 Sheet 31 of 42
A B C D E
Aux Power 3D3V_AUX_S5
Run Power
5V_AUX_S5 I min = 300 mA
3D3V_AUX_S5 5V_S0 5V_S5
DY U40
U22
1 5 DY 1 S D 8
VIN VOUT C273 S D
2 GND 2 7
3 4 1 2 3 S D 6
EN/EN# NC#4 G D
Q26 4 5
SC1U16V3ZY-GP
SC1U16V3ZY-GP
DCBATOUT SCD1U25V3KX-GP
1
1
DY C517 RT9198-33PBR-GP NDS0610-NL-GP RUN_POWER_ON AO4468-GP
C522 R435 84.04468.037
3D3V_AUX_S5_EN
DY 1 2 Z_12V S D
74.09198.G7F
2
K
1
1
3D3V_S0 10KR2J-3-GP 1
R439 C572 R438 D26
G
5V_AUX_S5 3D3V_S0
SCD22U25V3KX-GP
3D3V_S5
10KR2J-3-GP
2 PDZ9D1B-GP
330KR2J-L1-GP
R383 R442 83.9R103.C3F U53
0R0402-PAD R430 1 2 Z_12V_G3 1 S D 8
A
2
2
2 1 100R5J-3-GP 2 S D 7
1
330KR2J-L1-GP S D
DY 3 6
1
R445 4 G D 5
3D3V_runpwr 2
C508 DY 100KR2J-1-GP
SCD1U10V2KX-4GP AO4468-GP
2
Z_12V_D4 84.04468.037
2
Q32
Z_12V_D3
Q27
4 3
D
2N7002-11-GP
DY
5 2
G Z_12V_D3 6 1
S
2N7002DW-1-GP
R103
84.27002.D3F
EMC2102_PWROK 2 PWROK PM_SLP_S3# 18,27,30,36,37,38
DY 1
SB 0R2J-2-GP
3D3V_S5
SCD1U16V2KX-3GP
U14 C579
EMC2102_PWROK 1 1 2
21 EMC2102_PWROK B
VCC 5 DY
2 A
18,27,30,36,37,38 PM_SLP_S3# Y 4 PWROK 7,18
3 1D05V_S0
GND
74LVC1G08GW-1-GP
1
1D05V_S0 R426
2K2R2J-2-GP
DY
2
2
R425
56R2J-4-GP
C561
1
PM_THRMTRIP-A# 4,7,17 1 2
DY SCD1U16V2ZY-2GP
B
DY
R440 E C
E
KBC_THERMALTRIP# 30
C574
SCD1U16V2ZY-2GP
2
SA
2
D25
BAS16PT-GP 3 RSMRST# 21,30
30,35,41 S5_ENABLE 1
DY
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
RUN POWER and 3D3V_AUX_S5
Size Document Number Rev
Cathedral Peak SB
Date: Monday, March 17, 2008 Sheet 32 of 42
5 4 3 2 1
2
C15 C37 C38 C331
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
GAP-CLOSE-PWR GAP-CLOSE-PWR H_VID[6..0] 5 SCD1U50V3KX-GP
5
6
7
8
0R0402-PAD
499R2F-2-GP
G38 G37 DY
1
D
D
D
D
1 2 TC13 1 2 R26 U30 Id=35A
H_VID6
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID0
ST15U25VDM-1-GP
0R2J-2-GP
DY 10R3F-GP SI7686DP-T1-GP
2
GAP-CLOSE-PWR GAP-CLOSE-PWR Qg=17~26nC
1 0R2J-2-GP
G31 G36 Rdson=11~14mohm Vcc_core
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
0R0402-PAD
D 1 2 1 2 D
G
S
S
S
POWER SB
Iomax=38A
1
GAP-CLOSE-PWR GAP-CLOSE-PWR
4
3
2
1
1
R18 1
1
G30 G29 Cyntec 10*10*4
R16
R17
1 2 TC1 1 2 6266A_UGATE1
ST15U25VDM-1-GP DCR=1.05+-5%mohm, Irating=30A
R19
R20
R21
R22
R23
R24
R25
DY
2 C13 DY
GAP-CLOSE-PWR GAP-CLOSE-PWR Isat=60A
6266A_DPRSTP# 2
6266A_DPRSLPVR2
R456
R456
SCD1U10V2KX-4GP VCC_CORE
6266A_VR_ON 2
2
L8
2
6266A_PHASE1 1 2
6266A_3V3
3D3V_S0 IND-D36UH-9-GP
6266A_D6
6266A_D5
6266A_D4
6266A_D3
6266A_D2
6266A_D1
6266A_D0
1
5 5 TC2 TC16 TC3
U11 6 6
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SE330U2VDM-L-GP
Id=19.5A SI4634DY-T1-E3-GP 7 7 CAP CAP CAP
2
1
U5 8 8
R27 Qg=21.5~33nC,
49
48
47
46
45
44
43
42
41
40
39
38
37
2
1K91R2F-1-GP Rdson=5.5~6.7mohm 6266A_ LGATE1 4 4
1D05V_S0 G40
VID5
VID4
VID3
VID2
VID1
VID0
GND
3V3
CLK_EN#
DPRSTP#
VID6
DPRSLPVR
VR_ON
POWER SB 1 1 GAP-CLOSE G4
2
2 2 GAP-CLOSE
R29 3 3
1
1 36 6266A_BOOT1 1 2
7,18 VGATE_PWRGD PGOOD BOOT1
1
SCD1U25V3KX-GP 1 26266A_RBIAS4 33
RBIAS PGND1
1
C R32 147KR2F-GP TC7 TC5 C
5 32 6266A_ LGATE1 6266A_VSUM 1 R67 2 3K65R2F-1-GP 6266A_ISEN1_P1_VCORE ST560U2VDM-GP ST560U2VDM-GP
4 CPU_PROCHOT#_R VR_TT# LGATE1 C18 CAP
1 R259 26266A_NTC_R1 R35 2 6266A_NTC 6 NTC PVCC 31 5V_S0 1 2 6266A_ISEN1 1 R39 2 10KR2F-2-GP CAP
NTC-470K-1-GP 4K02R2F-GP C26 one phase
3
C21 1 26266A_SOFT_1
1 R458 26266A_SOFT 7 30 6266A_LGATE2 SC2D2U16V3KX-GP
SCD015U50V3KX-GP 0R2J-2-GP SOFT LGATE2 6266A_VO
1 2 1 R46 2 1R2F-GP 6266A_ISEN2_P1_VCORE
SCD01U25V2KX-3GP 6266A_VO 1 26266A_OCSET8 29
R38 12KR3F-GP OCSET PGND2 6266A_ISEN2 1 R48 2 10KR2F-2-GP POWER SA
C28 1 2 SC1000P50V3JN-GP 6266A_VW 9 28 6266A_PHASE2 C20 DCBATOUT_6266A
VW PHASE2 2
SCD22U25V3KX-GP
one phase POWER SB
POWER SA POWER SB 6266A_COMP 6266A_UGATE2
10 COMP UGATE2 27
R37
1 one phase
1 2
C33 R44 10K5R2F-GP 6266A_FB 11 26 6266A_BOOT2 1 26266A_BOOT2_R
FB BOOT2 2D2R2J-GP POWER SB
1 2
2
one phase SC100P50V2JN-3GP 6266A_FB2 12 25 one phase
FB2 NC#25
5
6
7
8
C36 C319 C14 C322
D
D
D
D
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
DROOP
1
1
VSUM
VDIFF
ISEN2
ISEN1
VSEN
GND
VDD
RTN
DFB
VIN
97K6R2F-GP SC270P50V2KX-1GP R52
VO
1KR2F-3-GP Qg=17~26nC
ISL6266AHRZ-GP Rdson=11~14mohm
16266A_DROOP
13
14
6266A_RTN 15
16
6266A_DFB 17
18
6266A_VSUM 19
6266A_VIN 20
21
22
23
24
G
S
S
S
6266A_VDIFF
6266A_ISEN2
74.06266.073
6266A_VSEN
2
4
3
2
1
2 6266A_FB2_R 1 6266A_ISEN1 26266A_VO
6266A_VDD
1 2 1
100R2F-L1-GP-U Cyntec 10*10*4
6266A_VO
R459
1
POWER SB
1 2 one phase
2
1
0R2J-2-GP U7 6 6 TC6 TC4
1
C43 SI4634DY-T1-E3-GP 7 7
2
SE330U2VDM-L-GP
SE330U2VDM-L-GP
SC180P50V2JN-1GP
2
1
SC330P50V2KX-3GP C39
2
SCD01U25V2KX-3GP
5V_S0 6266A_LGATE2 4 4
R50
2
2
R57 1 2 Id=19.5A 1 1
1
C34
one phase
2
1
SC330P50V2KX-3GP U28
SI4634DY-T1-E3-GP
2
5 VSS_SENSE 2 1
R58 R64 one phase
0R0402-PAD 1 2 one phase
1
0R0402-PAD R62
C42 6266A_VSUM 1 2 3K65R2F-1-GP
SCD01U25V2KX-3GP R56 6266A_ISEN2_P2_VCORE
2
6266A_ISEN2 1 2 10KR2F-2-GP
POWER SB
6266A_VSUM R45
one phase
6266A_VO 1R2F-GP
one phase 6266A_ISEN1_P2_VCORE
1 2
1
A
R42 A
R69 6266A_ISEN1 1 2 10KR2F-2-GP
1
R47=1.2K, R63=5.6K DCBATOUT 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
one phase 6266A_VSUM_R_VO Taipei Hsien 221, Taiwan, R.O.C.
C33=47p, C49=0.15u, C52=0.1u
2
2
R260 EC110 Title
NTC-10K-9-GP SCD1U50V3KX-GP
1
DY ISL6266A_CPU_CORE
Size Document Number Rev
2
6266A_VO A3
Cathedral Peak SB
Date: Wednesday, March 12, 2008 Sheet 34 of 42
5 4 3 2 1
5 4 3 2 1
POWER SA
DCBATOUT DCBATOUT_51125
G79 3D3V_PWR 3D3V_S5
1 2 5V_AUX_S5 5V_PWR 5V_S5
G98 G12
GAP-CLOSE-PWR 1 2 1 2
G27
3
4
1 2 GAP-CLOSE-PWR Q20 GAP-CLOSE-PWR
Q21
G99 RN60 G14
GAP-CLOSE-PWR 1 2 SRN100KJ-6-GP 1 2
G28 51125_ENTIP2 3 4 4 3 51125_ENTIP1
D 1 2 GAP-CLOSE-PWR GAP-CLOSE-PWR D
G93 30,32,41 S5_ENABLE 2 5 5 2 S5_ENABLE 30,32,41 G16
2
1
GAP-CLOSE-PWR 1 2 1 2
G83 1 6 6 1
1 2 GAP-CLOSE-PWR GAP-CLOSE-PWR
G101 51125_ENTIP2 51125_ENTIP1 G13
1
1
ST15U25VDM-3-GP 1 2 GAP-CLOSE-PWR C495 C291 GAP-CLOSE-PWR
2
1
SC18P50V2JN-1-GP
SC18P50V2JN-1-GP
G91 DY R361 R221 DY G15
GAP-CLOSE-PWR 1 2 110KR3F-GP 100KR3F-GP 1 2
G26
2
1 2 GAP-CLOSE-PWR GAP-CLOSE-PWR
2
G95 POWER SB POWER SB G18
GAP-CLOSE-PWR 1 2 1 2
G25
1 2 GAP-CLOSE-PWR GAP-CLOSE-PWR
G97 G17
GAP-CLOSE-PWR 1 2 1 2
GAP-CLOSE-PWR GAP-CLOSE-PWR
DCBATOUT_51125 DCBATOUT_51125
DCBATOUT_51125
C518 C521
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
C294 C292 C532
1
C C290 C526 C523 DY C
1
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
2
D Id=7A D DY
2
8
7
6
5
5
6
7
8
DY DY Id=7A Qg=8.7~13nC
D
D
D
D
D
D
D
D
Qg=8.7~13nC Rdson=23~30mohm
16
SI4800BDY-T1
DCR=30mohm, Irating=6A Rdson=23~30mohm U37 SI4800BDY-T1
Isat=13.5A
VIN
C507 Iomax=5A
SCD1U25V3KX-GP Cyntec 7*7*3
S
S
S
G
G
S
S
S
Iomax=5A C293
G S
1
2
3
4
4
3
2
1
51125_VBST2 51125_VBST1 DCR=30mohm, Irating=6A
S G 2 1 9 VBST2 VBST1 22 1 2
Isat=13.5A
3D3V_PWR SCD1U25V3KX-GP 51125_DRVH2 10 21 51125_DRVH1 5V_PWR
L20 DRVH2 DRVH1 L3
1 2 51125_LL2 11 20 51125_LL1 1 2
IND-3D3UH-57GP LL2 LL1
51125_DRVL2 51125_DRVL1 IND-3D3UH-57GP
D 12 DRVL2 DRVL1 19
1
C570 DY TC12
D
8
7
6
5
5
6
7
8
U49 U25
SCD1U10V2KX-4GP
ST220U6D3VDM-20GP
GAP-CLOSE-PWR-3-GP
D
D
D
D
D
D
D
D
7 24
2
VO2 VO1
1
SI4812BDY-T1-E3-GP
TC11
SI4812BDY-T1-E3-GP
GAP-CLOSE-PWR-3-GP
SCD1U10V2KX-4GP
51125_FB2 5 2 51125_FB1 DY
VFB2 VFB1
ST220U6D3VDM-15GP
2
2
1
2
1 2 51125_EN 13 23 51125_PGOOD
S
S
S
G
G
S
S
S
G75 R384 820KR2F-GP EN0 PGOOD
G S
1
2
3
4
4
3
2
1
51125_ENTIP2 6 51125_ENTIP1
S G 1
2
3 15 POWER SB
VREF GND
1
SCD22U6D3V2KX-1GP
1
Id=7.7A
2
Qg=8.5~13nC
1
14 18 51125_VCLK R373 DY
Qg=8.5~13nC SKIPSEL VCLK
1
1
R374 51125_SKIPSEL Rdson=16.5~21mohm 0R2J-2-GP
DY 0R2J-2-GP Rdson=16.5~21mohm R370
VREG3
VREG5
1 2
6K65R2F-GP TPS51125RGER-GP 51125_FB1_R
1 2
51125_FB2_R 74.51125.073
2
2
C501 C500 DY
3D3V_AUX_S5_5_51125 8
17
3D3V_S5
DYSC18P50V2JN-1-GP SC18P50V2JN-1-GP
2
3D3V_AUX_S5 5V_AUX_S5
G77 G78
2
1
1 2 1 2
15V_AUX_S5_51125
1
R365 R377
R366 0R0402-PAD GAP-CLOSE-PWR-3-GP GAP-CLOSE-PWR-3-GP 100KR2J-1-GP R363
10KR2F-2-GP 51125_VREF 2 1 20KR2F-L-GP
Close to VFB Pin (pin2)
2
R362
2
2 1
3D3V_AUX_S5 DY
0R2J-2-GP
1
C506 C512
R390 SC10U10V5KX-2GP SC10U10V5KX-2GP
2 1
51125_VREF DY
2
A
0R2J-2-GP A
1D5V_S0
Iomax=2.5A
D D
1D8V_S3
5V_S5
DY G7
1
1 2
C126 C127
1
SC10U10V5ZY-1GP SC10U10V5ZY-1GP C131 GAP-CLOSE-PWR
2
SC1U16V3ZY-GP G9
1 2
2
Vo(cal.)=1.5024V GAP-CLOSE-PWR
G8
1 2
1D5V_LDO
GAP-CLOSE-PWR 1D5V_S0
R117 G6
9
PM_SLP_S3# 2 15912_EN_U111 1 2
18,27,30,32,37,38 PM_SLP_S3#
0R2J-2-GP
GND
4 5 GAP-CLOSE-PWR
VDD NC#5
1
3 6 C154 DY
VIN VOUT R132 C156 C155
2 EN ADJ 7
SC100P50V2JN-3GP
SC10U10V5ZY-1GP
1 8 18KR2J-GP
2
3D3V_S0 PGOOD GND
SC10U10V5ZY-1GP
2
5912_FB_U111
U17
1
RT9018A-25PSP-GP
C R119 74.09018.A3D R131 C
2K2R2J-2-GP 20K5R2F-GP
2
R120
2 1 5912_POK_U111
34,37,38 CPUCORE_ON
0R2J-2-GP
Vo=0.8*(1+(R1/R2))
B B
Iomax=1A
5V_S5 1D8V_S3 OCP>2A
1
DDR_VREF_PWR DDR_VREF_S3
1
SC1U10V3ZY-6GP
2
GAP-CLOSE-PWR
G20
U23 1 2
R220 10 1 GAP-CLOSE-PWR
9026_S5 VIN VDDQSNS G21
18,27,30,37 PM_SLP_S4# 2 1 9 S5 VLDOIN 2
R218 0R2J-2-GP 8 3 1 2
9026_S3 GND VTT
2 1 7 S3 PGND 4
DDR_VREF_S3_1 0R2J-2-GP 6 5 GAP-CLOSE-PWR
VTTREF VTTSNS
GND
1
C284
SC1U10V2ZY-GP RT9026PFP-GP C285 C286
2
11
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
5 4 3 2 1
5 4 3 2 1
1D8V_PWR 1D8V_S3
G52
DCBATOUT DCBATOUT_51124 1 2
G94 GAP-CLOSE-PWR
1 2
Vtrip(mV)=Rtrip(Kohm)*10(uA) G49
Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin)) 1 2
GAP-CLOSE-PWR
G90 I/P cap: 10U 25V K1206 X5R/ 78.10622.52L GAP-CLOSE-PWR
1 2 G57
1 2
1
GAP-CLOSE-PWR DCBATOUT_51124
D DY TC26 G89 GAP-CLOSE-PWR
D
ST15U25VDM-3-GP 1 2 G58
2
1 2
2
GAP-CLOSE-PWR C549
SCD1U50V3KX-GP
G88 C560 C553 GAP-CLOSE-PWR
5
6
7
8
1 2 SC10U25V6KX-1GP SC10U25V6KX-1GP DY G55
1
D
D
D
D
1 2
GAP-CLOSE-PWR
G92 GAP-CLOSE-PWR
1 2 U45 Cyntec 10*10*4 G56
SI4800BDY-T1 1 2
GAP-CLOSE-PWR Id=7A DCR=4.2mohm, Irating=16A
G
S
S
S
G96 Isat=33A GAP-CLOSE-PWR
4
3
2
1
1 2 Qg=8.7~13nC G54
Rdson=23~30mohm 1D8V_PWR 1 2
L18
GAP-CLOSE-PWR
1 2 GAP-CLOSE-PWR
IND-1D5UH-34-GP G50
1
5V_S5 C304 C504 TC22 1 2
SCD1U10V2KX-4GP
R239
5
6
7
8
SE330U2D5VDM-LGP
SC18P50V2JN-1-GP
30KR2F-GP DY GAP-CLOSE-PWR
DY
2
G53
D
D
D
D
2
1 2
51124RGER_PG1
51124RGER_PG2
2
1
R446 51124_VFB1
1 R230 0R2J-2-GP U44 GAP-CLOSE-PWR
1
3D3R3J-L-GP 1D05V_PWR 2 1 SI4812BDY-T1-E3-GP G51
C557 1D8V_PWR CPUCORE_ON 34,36,38 R235 1 2
G
S
S
S
SC4D7U10V5KX-1GP 51124_VFB2 2 1 21K5R3F-GP
2
4
3
2
1
C 51124_VFB1 R447 GAP-CLOSE-PWR C
0R2J-2-GP G48
1D8V Iomax=10A
2
1
C559 1 2
OCP>15A
24
SC1U10V3KX-3GPU54
2
5
1
6
7
R443 Id=7.7A GAP-CLOSE-PWR
2
2 1 G59
VFB1
VFB2
VO1
VO2
PGOOD1
PGOOD2
18,27,30,36 PM_SLP_S4# Qg=8.5~13nC
0R2J-2-GP 1 2
DY1 BC2
SCD47U6D3V2KX-GP
DRVH1 21
20
51124_DRVH1
51124_LL1
Rdson=16.5~21mohm
GAP-CLOSE-PWR
2 51124_V5FILT LL1 51124_DRVL1
15 V5FILT DRVL1 19
16 V5IN
51124_EN1 23
51124_EN2 EN1 DCBATOUT_51124
8 EN2
3 1D05V_PWR 1D05V_S0
GND 51124_DRVH2 G71
25 GND DRVH2 10
1
R441 13 11 51124_LL2 1 2
PGND2 LL2
2
TONSEL
2 1 18 12 51124_DRVL2 C563 C550
VBST1
VBST2
18,27,30,32,36,38 PM_SLP_S3# PGND1 DRVL2
5
6
7
8
TRIP1
TRIP2
SCD1U50V3KX-GP
0R2J-2-GP C556 GAP-CLOSE-PWR
2
SC10U25V6KX-1GP SC10U25V6KX-1GPDY G70
D
D
D
D
1
1 2
TPS51124RGER-GPU1
17
14
22
9
4
DY1 BC1
SCD47U6D3V2KX-GP 51124_TRIP1
74.51124.073 U47
SI4800BDY-T1
Cyntec 10*10*4 GAP-CLOSE-PWR
G69
51124_TRIP2 DCR=4.2mohm, Irating=16A
2 51124_TONSEL Id=7A 1 2
G
S
S
S
1
Isat=33A
4
3
2
1
Qg=8.7~13nC
1
GAP-CLOSE-PWR
R420 R424 Rdson=23~30mohm 1D05V_PWR G67
B 20KR3F-GP L19 B
17K8R3F-1-GP 1 2
1 2
2
IND-D56UH-12-GP GAP-CLOSE-PWR
2
1
POWER SB C303 C503 TC21 G65
1
POWER SB 1 2
ST330U2D5VDM-9GP
SC18P50V2JN-1-GP
SCD1U10V2KX-4GP
C571 R237
DY
2
2
5
6
7
8
51124_LL1 2 1 51124_VBST1 10K7R2F-GP DY GAP-CLOSE-PWR
2
DY R238 G63
D
D
D
D
2
SCD1U16V2KX-3GP 0R2J-2-GP
DY R234 51124_VFB2
1 2
1
51124_LL2 2 1 51124_VBST2 SI4812BDY-T1-E3-GP G46
Id=7.7A R236 1 2
G
S
S
S
SCD1U16V2KX-3GP 30KR2F-GP
4
3
2
1
Qg=8.5~13nC GAP-CLOSE-PWR
51124_V5FILT Rdson=16.5~21mohm G60
1D05V Iomax=10.5A
2
1 2
OCP>20A GAP-CLOSE-PWR
G61
1 2
Title
TPS51124_1D8V_1D05V
Size Document Number Rev
A3
Cathedral Peak SB
Date: Tuesday, March 11, 2008 Sheet 37 of 42
5 4 3 2 1
5 4 3 2 1
GFX
C555 SA
1 2 POWER_MONITOR
SA DCBATOUT_6263A DCBATOUT
SCD01U50V2KX-1GP
1
G62 0R3-0-U-GP G86
R417 GFX_VID[4..0] 7
1 2 1 2
R427 GFX 10KR2J-3-GP NO GFX
7 GFXVR_EN 2 1 GFX GAP-CLOSE-PWR
D D
0R2J-2-GP G64 0R3-0-U-GP G82
2
PL on P.7 1 2 1 2
NO GFX
R415 0R0402-PAD GAP-CLOSE-PWR
6236A_VID4 2 1 GFX_VID4 1D05V_S0 G66 0R3-0-U-GP VCC_GFXCORE G80
R413 0R0402-PAD 1 2 1 2
R421 6236A_VID3 2 1 GFX_VID3 NO GFX
18,27,30,32,36,37 PM_SLP_S3# 1 2 R411 0R0402-PAD GAP-CLOSE-PWR
0R2J-2-GP 6236A_VID2 GFX_VID2 G68 0R3-0-U-GP G87
DY 2 1
1
R408 0R0402-PAD
6236A_VID1 2 1 GFX_VID1
1
NO GFX
2 1 2
DYTC24
R224 R404 0R0402-PAD GAP-CLOSE-PWR ST15U25VDM-1-GP
2
1 DY 2 6236A_VID0 2 1 GFX_VID0 G85
0R2J-2-GP 1 2
R225 GAP-CLOSE-PWR
1 2 G84
3D3V_S0
10KR2F-2-GP 1 2
GFX
R431 GAP-CLOSE-PWR
3D3V_S0 1 2
1K91R2F-1-GP
GFX
R433
34,36,37 CPUCORE_ON 1 DY 2
6236A_VR_ON
6236A_AF_EN
6236A_GOOD
6236A_PMON
0R2J-2-GP
SB VGFXCORE VCC_GFXCORE
GFX GFX
DCBATOUT_6263A
R403 G47
2
0R0402-PAD C530 C536
33
32
31
30
29
28
27
26
25
1 2
U51 2 1 C525
5V_S0
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP GAP-CLOSE-PWR
FDE
GND_T
PGOOD
VID4
VID3
VID2
AF_EN
VR_ON
PMON
1
5
6
7
8
POWER SB R434 GFX GFX G45
150KR2F-L-GP U42
D
D
D
D
1 2
C 1 2 6236A_RBIAS 1 24 SI4800BDY-T1 C
RBIAS VID1 GAP-CLOSE-PWR
R227 C569 1 2 6236A_SOFT 2 23 GFX G44
10K5R3F-GP SOFT VID0
GFX GFX SCD01U50V2KX-1GP C541 GFX Id=7A Cyntec 7*7*3 1 2
6263A_VCC_PRM 6236A_OCSET
1 2 3 22
Qg=8.7~13nC DCR=8mohm, Irating=13A GFX CORE
G
S
S
S
OCSET PVCC
2
GAP-CLOSE-PWR
4
3
2
1
C301 C566 1 2
SC1KP50V2JN-2GP
6236A_VW 4
VW GFX LGATE 21 6236A_LGATE SC2D2U10V3KX-1GP Rdson=23~30mohm Isat=24A Iomax=8.7A G43
1 2 GFX GFX 1 2
6236A_COMP 5 COMP PGND 20 L17 OCP>15A
SC68P-GP 1 R437 2 GAP-CLOSE-PWR
R231 C302 GFX 6K98R3F-GP 6 19 6236A_PHASE 1 2 VGFXCORE G42
6236A_COMP_R FB PHASE COIL-D82UH-2-GP
1 2 1 2GFX 6236A_FB 1 2
GFX 7 18 6236A_UGATE GFX
374KR3-GP SC180P50V2JN-1GP VDIFF UGATE GAP-CLOSE-PWR
DROOP
8 17 6236A_BOOT
1 2 1 2 G41
VSEN BOOT
VSUM
R401
6236A_BOOT_R
1 2
VDD
RTN
DFB
VSS
VIN
5
6
7
8
1 2 6236A_VDIFF GFX SCD22U16V3KX-2-GP GAP-CLOSE-PWR
GFX 2K21R3F-L-GP U41
D
D
D
D
GFX
9
6236A_DROOP 10
11
12
13
14
15
16
1
1
GFX R436
6236A_VSUM
GFX GFX
6263A_VCC_PRM
6236A_VDD
6236A_DFB
G
S
S
S
R26 for Intel GPU/With Load line
4
3
2
1
2
R27 for ATI GPU/Without Load
line
C564 C547 R405
SC1KP50V2JN-2GP 1 2 1 2 5V_S0
GFX 10R2F-L-GP
1 2 SC1U16V3KX-2GP
2
GFX
1
1
SC1KP50V2JN-2GP
B B
SC330P50V2KX-3GP
GFX
R229
1
1 2
2
1
POWER SA C298 0R0402-PAD
SCD01U25V2KX-3GP TC20
2
GFX SE330U2VDM-L-GP
2
1
GFX
G102 GAP-CLOSE-PWR R419
9 VCC_AXG_SENSE 1 2 1KR3F-GP
GFX
2
1
GFX
R228 R226 SCD1U50V3KX-GP G23 G22
10R3F-GP 10R3F-GP R414 GAP-OPEN-PWR GAP-OPEN-PWR
DY DY 1 2
2
GFX 4K53R2F-1-GP
2
VSS_AXG_SENSE_OUTCAP
VCC_AXG_SENSE_OUTCAP
A A
Eiger
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
ISL6263A_GFX CORE
Size Document Number Rev
C
Cathedral Peak SB
Date: Tuesday, March 11, 2008 Sheet 38 of 42
5 4 3 2 1
5 4 3 2 1
DCBATOUT
NEAR
2
AD+
EC108
U3
SCD1U50V3KX-GP
1
8 D S 1 DY
7 D S 2 DCBATOUT BT+
6 D S 3
1
5 D G 4 U6
R12 R13
D 100KR2J-1-GP AD+_TO_SYS 1 2 1 S D 8 D
P2003EVG-GP S D
2 7
D01R2512F-4-GP AD+ 3 S D 6
2
4 G D 5
AD+_G_2
P2003EVG-GP
2
2
1
R10 10KR2F-2-GP
10KR2F-2-GP
1
1 G1 G2
2
2
2
AD+_G_1 D6 R43
1
1SS4000GPT-GP 470KR2J-2-GP
GAP-CLOSE-PWR GAP-CLOSE-PWR
2
Power SA
1
AD+ POWER SB
1
DC_IN_D
Q3 C54
DCBATOUT
SC1U25V5KX-1GP
2N7002DW-1-GP C580
2
C79
6
2 1 BQ24745_CSSP 2 1 1 2
1
R267 SCD1U50V3KX-GP C66 SCD1U25V3KX-GP
309KR3F-GP CHG_AGND SCD1U50V3KX-GP
C350 C61 C349 C58
1
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
AC_OK U12 CHG_AGND SCD1U25V2ZY-1GP
2
C C
ICREF
BQ24745_DCIN 22 28
2
DCIN CSSP
5
6
7
8
U9 DY DY
BQ24745_ACIN
D
D
D
D
2 ACIN
27 BQ24745_CSSN
CSSN TP137 D8 C48
3D3V_AUX_S5 11 VDDSMB ICOUT 26
K A 1 2
G
S
S
S
BOOT
1
4
3
2
1
R84 AC_OK VDDP
1 2BQ24745_ACOK 13 ACOK
1
5
6
7
8
CHG_AGND U10
C24 C22 C324 C325 C318
D
D
D
D
1
14 19 G34 G33
NC#14 PGND
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SC10U25V6KX-1GP
SCD1U50V3KX-GP
CHG_AGND
18
2
CSOP
GAP-CLOSE-PWR
GAP-CLOSE-PWR
C50
1
R76 CHG_AGND 17
G
S
S
S
BQ24745_IINP CSON SI4800BDY-T1
1 2 8 2 1
4
3
2
1
30 AD_IA 0R0402-PAD SC150P50V2JN-3GP VICM
C85 R82
B SCD1U50V3KX-GP B
1 2 BQ24745_FBO_RC 1 2BQ24745_FBO
R87 4K7R2J-2-GP
1 2 6 FBO
200KR2F-L-GP BQ24745_EAI 5 16
EAI NC#16
1
BQ24745_EAO 4
C65 C84 R86 BQ24745_VREF EAO
3 VREF
SC220P50V2KX-3GP SC2200P50V2KX-2GP 7K5R2F-1-GP BQ24745_CHG_ON 7
2
CE
2 1BQ24745_EAO_RC2 1 12 15 BATT_SENSE
GND
C82 MAX8731A_CSIP
SC1U10V3KX-3GP
1 2 BQ24745RHDR-GP MAX8731A_CSIN
2
29
C78
1
SC56P50V2JN-2GP 74.24745.073 C51
SCD1U25V2ZY-1GP
2
R83
1 2
CHG_AGND 0R0402-PAD
CHG_AGND
CHG_AGND
BQ24745_VREF
RN61
1 8 AC_OK
2 7 CHG_ON# Q16
3D3V_AUX_S5 3 6 AC_IN#
4 5 BQ24745_CHG_ON
A
BQ24745_CHG_ON 3 4 Eiger A
SRN100KJ-8-GP
DY AC_OK 2 5 CHG_ON#
CHG_ON# 30
1
C355
SCD1U10V2KX-4GP 1 6 AC_IN#
AC_IN# 30
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
AC_IN# to KBC
2
BQ24745 Charger
Size Document Number Rev
A3
Cathedral Peak SB
Date: Tuesday, March 11, 2008 Sheet 39 of 42
5 4 3 2 1
A B C D E
K
3 3 S D 6
1
4 NP1 C1 D1 AD+_2 4 G D 5 4
SCD1U50V3ZY-GP P4SSMJ24PT-GP
DC-JACK131-GP P2003EVG-GP
2
22.10037.F11
A
R14 C8
1
200KR2F-L-GP SC1U50V5ZY-1-GP
EC6
SCD1U50V3KX-GP Q2
2
R2
DY E
AD_OFF#_JK B R1
C
1
PDTA124EU-1-GP
Q1 R15
AD_JK TP6 TPAD30 C 100KR2J-1-GP
AD_JK TP5 TPAD30 B R1
E
2
R2
30 AD_OFF PDTC124EU-1-GP
3 3
D4 D5
D3 BAV99PT-GP-U BAV99PT-GP-U
BAV99PT-GP-U DY DY DY
2 BAT1 2
8
SB 1
3
RN42
1 8 2
2 7 BATA_SDA_1 3
30,39 BAT_SDA
3 6 BATA_SCL_1 4
30,39 BAT_SCL
4 5 BAT_IN#_1 5
6
BT+ SRN33J-7-GP 7
30 BAT_IN# 9
EC99 EC98
1
1
SC10P50V2JN-4GP
SC10P50V2JN-4GP
DY DY DY SYN-CON7-16-GP-U1
1
20.80697.007
K
2
SC1000P50V3JN-GP
SC1000P50V3JN-GP
SCD1U50V3ZY-GP SCD1U50V3ZY-GP
2
DY D29
DY
BZG05C3V3-GP-U1
A
1
Wistron Corporation 1
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
R257
Title
39 BATT_SENSE 1 2
0R0402-PAD
Size
AD/BATT CONN
Document Number Rev
Cathedral Peak SB
Date: Tuesday, March 11, 2008 Sheet 40 of 42
A B C D E
5 4 3 2 1
5V_S0 5V_S0 H28 H38 H22 H24 H4 H12 H6 H21 H9 H34 H10 H8 H37 H36 H29 H32 H41 H44 H14 H16 H3 H7 H20 H25 H27 H26 H30 H5 H1 H2 H17 H35
HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE
14
10
14
13
9 8 12 11
1
U32C U32D
7
7
TSAHCT125PW-GP TSAHCT125PW-GP
D D
DCBATOUT VCC_GFXCORE DCBATOUT_51125 VCC_CORE H13 H19 H23 H45 H46 H47 H48
HOLE HOLE HOLE HOLE HOLE HOLE HOLE
1
1
EC89 EC107 EC79 EC76 EC75 EC63 EC59 EC12 EC94 EC10 EC7 EC8 EC21 EC133 EC157 EC51 EC113 EC17 EC16
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY
2
1
3D3V_S0 1D05V_S0 1D2V_LAN_S5 3D3V_LAN_S5
1
1
EC9 EC18 EC150 EC155 EC172 EC170 EC168 EC164 EC120 EC169 EC146 EC158 EC148 EC54 EC126 EC119 EC20 EC50 EC53 EC69 EC71 EC112 EC117 EC88 EC91 EC100 EC111 EC116
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY
2
2
C C
5V_S0 1D8V_S3
1
1
EC151 EC68 EC163 EC74 EC61 EC84 EC73 EC118 EC162 EC65 EC77 EC62 EC147 EC136 EC165 EC70 EC156 EC138 EC173 EC174 EC175 EC176 EC177 EC178 EC179
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY
2
2
5V_S5 BT+
1
1
EC15 EC19 EC49 EC66 EC72 EC82 EC85 EC81 EC83 EC78 EC64 EC139 EC67 EC125 EC105 EC95 EC97
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
SCD1U25V2ZY-1GP
DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY DY
2
2
B B
TOP BOTTOM
GND2 GND1 GND13 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND14
SPRING-36-GP SPRING-36-GP SPRING-36-GP SPRING-12-GP-U SPRING-48-GP SPRING-7 SPRING-7 SPRING-7 SPRING-12-GP-U SPRING-23-GP SPRING-23-GP SPRING-7 SPRING-7 SPRING-12-GP-U
34.4B542.001 34.4B542.001 34.4B542.001 34.41Y19.001 34.43G01.002 34.49U26.001 34.49U26.001 34.49U26.001 34.41Y19.001 34.39S07.001 34.39S07.001 34.49U26.001 34.49U26.001 34.41Y19.001
1
1
DY DY DY DY DY DY DY DY DY DY DY DY DY
1
34.4G502.001
34.4G502.001
34.4G502.001
34.4G502.001
34.42Y01.011
34.42Y01.011
34.42Y01.011
34.42Y01.011
34.42Y01.011
TP183 TPAD30
18,30 PM_PWRBTN#
TP184 TPAD30
Wistron Corporation
4,17,32 H_PWRGD 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
TP185 TPAD30 Taipei Hsien 221, Taiwan, R.O.C.
30,32,35 S5_ENABLE
TP186 TPAD30 Title
4,6 H_CPURST#
SA to SB
1.No Power.
change KBC to BO (71.03310.A0G)
2.XD Card function fail
Cut CARD1 pin27. connect to R400 pin2
3.leakage
GFX power VDD connect to S0
4.Gain=8db.1.83W R137=16K.R138=30K
5.Int_MIC voice to small
D
add VREF C577=4.7U D
6.Realtek Audio report
change R327=68 ohm.R333=68 ohm.merge to RN68
7.SIV reset
R140=300,R55=100.C44=100p,R398=0,R369=100.C502=100p,R85=300,R162=100.C210=100p,R392=0,
8.SIV Azalia
DY C542
BITCLK rise and fall time fail RN10 change to R453=22ohm(MDC).R452=0ohm(codec)
9.add MINICard power option for customer ask
R454.R455
10.interfere HDD
C390.C401.C419. change 0603 4.7U
11.power team
R38=12K.R47=2.74K .R361=110K.R221=100K.R237=10.7K .R424=20K.R420=17.8K .R227=10.5K
R48=10K.R29=2.2 .R37=2.2 .R401=3.3 .C49=0.1u.add R456.add C580.D8=83.R0203.08F .
TC11 change to 77.C2271.00L
TC9 change to 77.E9071.001 (power ripple)
add R458=1K.R459=1k.R460
12.Oscillation
C30=15p.C23=15P.C537=27p.C538=22p
13.audio S3.S4 resume bobo sound
R143 DY. R187 0ohm pad
14.AC mode have hight frequency noise
C R390 DY.R389 0ohm pad C
15.ESD issue
BAT_IN# series 33 ohm
RN42 change to 8p4r
add R457.D27.D28.D29.U55.U56.C578.R457.
16.noise
DY C523.TC25 change to 77.C1561.01L
20.LED brightness
R2.R1.R4.R5.R451.R450.R449.R448=56
EMI
1.EC23 ~~EC48.EC134.EC135.EC167.EC121.EC122.EC123.
2.EC89.EC12.EC8.EC119.EC156.EC173.
3.EC174~~~EC179.
4.GND13.GND14.
Merge
1.R313.R314.R315.R319.R320.R149. change to RN59
2.RN6.RN46. change to RN6
3.R341.R343.R344 change to RN46
4.R385 change to 100K merge R382 to RN56
5.RN53.RN56. change to RN53
6.Q20.Q21 change to Q21. Q21.Q23 change to Q21.
B B
7.R367.R368 change to RN60
8.Q16.Q17 change to Q16
9.R262.R264.R268.R277 change to RN61
10.R205.R204.R206 change to RN62
11.RN33.R215 change to RN33
12.R209.R210.R348 change to RN63
13.R280=10K.merge R269 to RN64
14.R109.R112.R111.R290 change to RN65
15.R325.R323 change to RN66
16.R304.R307 change to RN67
17.U14 change to 73.01G08.L04 .add C579
18.R51.R399 vhange to RN69.
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Change List
Size Document Number Rev
Cathedral Peak SB
Date: Wednesday, March 12, 2008 Sheet 42 of 42
5 4 3 2 1