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Facultad de Ingeniería

Departamento de Electrónica y Ciencias de la Computación

Carrera de Ingeniería Electrónica


Arquitectura de Computadores

VHDL Sequential Circuits


Septiembre 2013

Tek
VHDL Synthesis
Introduction

• Synthesis software does not know your intention

• Synthesis software cannot obtain the optimal solution

• Synthesis should be treated as transformation and a “local


search” in the “design space”

• Good VHDL code provides a good starting point for the local
search
VHDL – Sequential Circuits

Inference of Basic Memory Elements – D latch


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dlatch is
port
(
  c: in  std_logic;
  d: in  std_logic;
  q: out std_logic
);
end dlatch;

architecture arch of dlatch is
begin
  process ( c, d )
  begin
    if ( c = '1' ) then
      q <= d;
    end if;
  end process;
end arch;
VHDL – Sequential Circuits
Inference of Basic Memory Elements – Positive Edge-Triggered D Flip-Flop
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff is
port
(
  clk: in  std_logic;
  d:   in  std_logic;
  q:   out std_logic
);
end dff;

architecture arch of dff is
begin
  process ( clk )
  begin
    if ( clk'event and clk = '1' ) then
      q <= d;
    end if;
  end process;
end arch;

Note: A left-hand-side signal within the


  if ( clk’event and clk = ’1’ ) then
branch causes a register inference.
VHDL – Sequential Circuits
Inference of Basic Memory Elements – Positive Edge-Triggered D Flip-Flop with Asynchronous
Reset

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff is
port
(
  clk,
  clr: in  std_logic;
  d:   in  std_logic;
  q:   out std_logic
);
end dff;

architecture arch of dff is
begin
  process ( clk, clr )
  begin
    if ( clr = '1' ) then
      q <= '0';
    elsif ( clk'event and clk = '1' ) then
      q <= d;
    end if;
  end process;
end arch;
VHDL – Sequential Circuits
Inference of Basic Memory Elements – Pos. Edge-Triggered DFF with Synch Reset and ClkEn

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dff is
port
(
  clk,
  clr,
  ce:  in  std_logic;
  d:   in  std_logic;
  q:   out std_logic
);
end dff;

architecture arch of dff is
begin
  process ( clk )
  begin
    if ( clk'event and clk = '1' ) then
      if ( clr = '1' ) then
        q <= '0';
      elsif ( ce = '1' ) then
        q <= d;
      end if;
    end if;
  end process;
end arch;
VHDL – Sequential Circuits

Inference of Basic Memory Elements – Register

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity reg8 is
port
(
  clk,
  clr: in  std_logic;
  d:   in  std_logic_vector (7 downto 0);
  q:   out std_logic_vector (7 downto 0)
);
end reg8;

architecture arch of reg8 is
begin
  process ( clk, clr )
  begin
    if ( clr = '1' ) then
      q <= ( others => '0' );
    elsif ( clk'event and clk = '1' ) then
      q <= d;
    end if;
  end process;
end arch;
VHDL – Sequential Circuits

Inference of Basic Memory Elements – Single-Port RAM With Asynchronous


Read
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ramar is
port
(
  clk,
  we:  in  std_logic;
  a:   in  std_logic_vector (5 downto 0);
  di:  in  std_logic_vector (15 downto 0);
  do:  out std_logic_vector (15 downto 0)
);
end ramar;

architecture arch of ramar is
  type   ram_type is array ( 0 to 63 ) of std_logic_vector ( 15 downto 0 );
  signal RAM: ram_type;
begin
  process ( clk )
  begin
    if ( clk'event and clk = '1' ) then
      if ( we = '1' ) then
        RAM ( conv_integer ( a ) ) <= di;
      end if;
    end if;
  end process;
  do <= RAM ( conv_integer ( a ) );
end arch;
VHDL – Sequential Circuits

Inference of Basic Memory Elements – Single-Port RAM With Synchronous


Read
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ramar is
port
(
  clk,
  we:  in  std_logic;
  a:   in  std_logic_vector (5 downto 0);
  di:  in  std_logic_vector (15 downto 0);
  do:  out std_logic_vector (15 downto 0)
);
end ramar;

architecture arch of ramar is
  type   ram_type is array ( 0 to 63 ) of std_logic_vector ( 15 downto 0 );
  signal RAM:   ram_type;
  signal a_reg: std_logic_vector ( 5 downto 0 );
begin
  process ( clk )
  begin
    if ( clk'event and clk = '1' ) then
      if ( we = '1' ) then
        RAM ( conv_integer ( a ) ) <= di;
      end if;
      a_reg <= a;
    end if;
  end process;
  do <= RAM ( conv_integer ( a_reg ) );
end arch;
VHDL – Sequential Circuits
Inference of Basic Memory Elements – Single-Port ROM With Registered
Output
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity romro is
port
(
  clk,
  en:     in  std_logic;
  a:      in  std_logic_vector (5 downto 0);
  do_reg: out std_logic_vector (15 downto 0)
);
end romro;

architecture arch of romro is
  type   rom_type is array ( 0 to 63 ) of std_logic_vector ( 15 downto 0 );
  signal ROM: rom_type := ( X"0200A", X"00300", X"08101", X"04000",
                                                :
                            X"0030D", X"02341", X"08201", X"0400D" );
begin
  process ( clk )
  begin
    if ( clk'event and clk = '1' ) then
      if ( en = '1' ) then
        do_reg <= ROM ( conv_integer ( a ) );
      end if;
    end if;
  end process;
end arch;
VHDL – Sequential Circuits

Synchronous Circuits - Basic Block Diagram

– State Register (memory elements)

– Next State Function (combinational circuit)

– Output Function (combinational circuit)


VHDL – Sequential Circuits

Synchronous Circuits - Operation

– At the rising edge of clk, state_next is sampled and stored into the
register (and becomes the new value of state_reg)

– The Next State Function determines the new value (new state_next)
and the Output Function generates the Outputs

– At the rising edge of clk, the new value of state_next is sampled


and stored into the register)
VHDL – Sequential Circuits

Synchronous Circuits - Types

– Not formally defined, just for coding...

– Three types:
• “Regular”: State representation and state transitions have a simple,
regular pattern. E.g., counter, shift register.
• “Random”: State transitions are more complicated and there is no special
relation between the states and their binary representations. E.g., FSMs.
• “Combined”: Consist of both a regular sequential circuit and an FSM. E.g.,
FSM with a Data path, FSMD.
VHDL – Sequential Circuits

Synchronous Circuits Example – A 4-bit Shift-Right Register

– 4 flip-flops.
– Serial-In, Serial-Out (SISO)
– Every clock cycle:
• The bit on the far left (i.e. d) is shifted into r_reg(3).
• Data stored is shifted right one stage.
• The bit on the far right (i.e. q) is shifted out and lost.
VHDL – Sequential Circuits

Synchronous Circuits Example – A 4-bit Shift-Right Register

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shr4b is
port
(
  clk,
  rst: in  std_logic;
  d:   in  std_logic;
  q:   out std_logic
);
end shr4b;

architecture arch of shr4b is
  signal r_reg,
         r_next: std_logic_vector ( 3 downto 0 );
begin
  ­­ register
  process ( clk, rst )
  begin
    if ( rst = '1' ) then   ­­ next state function (shift right 1 bit)
      r_reg <= ( others => '0' );   r_next <= d & r_reg ( 3 downto 1 );
    elsif ( clk'event and clk = '1' ) then   ­­ output function
      r_reg <= r_next;   q <= r_reg ( 0 );
    end if; end arch;
  end process;
VHDL – Sequential Circuits

Synchronous Circuits Example – An N-bit Counter

– N flip-flops.
– Increment the count every clock cycle.
– Counts from 0 to 2N−1 and then repeats.
– When the counter is in the all-one state, a pulse signal is
asserted.
VHDL – Sequential Circuits

Synchronous Circuits Example – An N-bit Counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bcount_pulse is
generic
(
  WIDTH: natural := 2
);
port
(
  clk,
  rst:   in  std_logic;
  pulse: in  std_logic;
  q:     out std_logic_vector ( WIDTH ­ 1 downto 0 )
);
end bcount_pulse;

architecture behavioural of bcount_pulse is
  signal r_reg,
         r_next: std_logic_vector ( WIDTH ­ 1 downto 0 );
begin
  ­­ register
  process ( clk, rst )
  begin   ­­ next state function
    if ( rst = '1' ) then   r_next <= r_reg + 1;
      r_reg <= ( others => '0' );   ­­ output function
    elsif ( clk'event and clk = '1' ) then
      r_reg <= r_next;
  q <= r_reg;
    end if;   pulse <= '1' when ( r_reg = 2**WIDTH ­ 1 ) else
  end process;            '0';
end behavioural;
VHDL – Sequential Circuits

Synchronous Circuits Example – An N-bit Counter


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity bcount_pulse_demo is
port
(
  clk,
  rst:   in  std_logic;
  pulse: out std_logic;
  q4b:   out std_logic_vector (3 downto 0)
);
end bcount_pulse_demo;

architecture structural of bcount_pulse_demo is
component bcount_pulse
  generic
  ( begin
    WIDTH: natural := 2 four_bit: bcount_pulse
  );   generic map
  port   (
  (     WIDTH => 4
    clk,   );
    rst:   in  std_logic;   port
    pulse: out std_logic;   (
    q:     out std_logic_vector ( WIDTH ­ 1 downto 0 )     clk   => clk,
  );     rst   => rst,
end component;     pulse => pulse,
    q     => q4b
  );
end structural;
VHDL – Sequential Circuits

Synchronous Circuits – A Moore Machine Example


– 4 states: s1, s2, s3, s4
– 5 transitions
– 1 input: x
– 1 output: outp
VHDL – Sequential Circuits
Synchronous Circuits – A Moore Machine Example
Using One Process architecture behavioural of moore1 is
  type   state_type is ( s1, s2, s3, s4 );
library IEEE;   signal state_reg: state_type;
use IEEE.STD_LOGIC_1164.ALL; begin
  process ( clk, reset )
entity moore1 is   begin
port     if ( reset = '1' ) then
(       state_reg <= s1;
  clk,       outp      <= '1';
  reset: in  std_logic;     elsif ( clk'event and clk = '1' ) then
  x:     in  std_logic;       case ( state_reg ) is
  outp:  out std_logic         when s1 =>
);           if ( x = '1' ) then
end moore1;             state_reg <= s2;
            outp      <= '1';
          else
            state_reg <= s3;
            outp      <= '0';
          end if;
        when s2 =>
          state_reg <= s4;
          outp      <= '1';
        when s3 =>
          state_reg <= s4;
          outp      <= '0';
        when s4 =>
          state_reg <= s1;
          outp      <= '0';
      end case;
    end if;
  end process;
end behavioural;
VHDL – Sequential Circuits

Synchronous Circuits – A Moore Machine Example


Using One Process architecture behavioural of moore1 is
  type   state_type is ( s1, s2, s3, s4 );
library IEEE;   signal state_reg: state_type;
use IEEE.STD_LOGIC_1164.ALL; begin
  process ( clk, reset )
entity moore1 is   begin
port     if ( reset = '1' ) then
(       state_reg <= s1;
  clk,       outp      <= '1';
  reset: in  std_logic;     elsif ( clk'event and clk = '1' ) then
  x:     in  std_logic;       case ( state_reg ) is
  outp:  out std_logic         when s1 =>
);           if ( x = '1' ) then
end moore1;             state_reg <= s2;
            outp      <= '1';
          else
            state_reg <= s3;
            outp      <= '0';
          end if;
        when s2 =>
Caution: One register is           state_reg <= s4;
          outp      <= '1';
inferred for outp...         when s3 =>
          state_reg <= s4;
          outp      <= '0';
        when s4 =>
          state_reg <= s1;
          outp      <= '0';
      end case;
    end if;
  end process;
end behavioural;
VHDL – Sequential Circuits
Synchronous Circuits – A Moore Machine Example
Using Two Processes   process1: process ( clk, reset )
  begin
library IEEE;     if ( reset = '1' ) then
use IEEE.STD_LOGIC_1164.ALL;       state_reg <= s1;
    elsif ( clk'event and clk = '1' ) then
entity moore2 is       case ( state_reg ) is
port         when s1 =>
(           if ( x = '1' ) then
  clk,             state_reg <= s2;
  reset: in  std_logic;           else
  x:     in  std_logic;             state_reg <= s3;
  outp:  out std_logic           end if;
);         when s2 =>
end moore2;           state_reg <= s4;
        when s3 =>
architecture behavioural of moore2 is           state_reg <= s4;
  type   state_type is ( s1, s2, s3, s4 );         when s4 =>
  signal state_reg: state_type;           state_reg <= s1;
begin       end case;
  process2: process ( state_reg )     end if;
  begin   end process;
    case ( state_reg ) is end behavioural;
      when s1 =>
        outp <= '1';
      when s2 =>
        outp <= '1';
      when s3 =>
        outp <= '0';
      when s4 =>
        outp <= '0';
    end case;
  end process;
VHDL – Sequential Circuits
Synchronous Circuits – A Moore Machine Example
Using Three Processes   process1: process ( state_reg )
  begin
library IEEE;     case ( state_reg ) is
use IEEE.STD_LOGIC_1164.ALL;       when s1 =>
        if ( x = '1' ) then
entity moore3 is           state_next <= s2;
port         else
(           state_next <= s3;
  clk,         end if;
  reset: in  std_logic;       when s2 =>
  x:     in  std_logic;         state_next <= s4;
  outp:  out std_logic       when s3 =>
);         state_next <= s4;
end moore3;       when s4 =>
        state_next <= s1;
architecture behavioural of moore3 is     end case;
  type   state_type is ( s1, s2, s3, s4 );   end process;
  signal state_reg,
         state_next: state_type;   process3: process ( state_reg )
begin   begin
  process2: process ( clk, reset )     case ( state_reg ) is
  begin       when s1 =>
    if ( reset = '1' ) then         outp <= '1';
      state_reg <= s1;       when s2 =>
    elsif ( clk'event and clk = '1' ) then         outp <= '1';
      state_reg <= state_next;       when s3 =>
    end if;         outp <= '0';
  end process;       when s4 =>
        outp <= '0';
    end case;
  end process;
end behavioural;
VHDL – Summary

         V
Think of H(ardware)
         D
     not L(anguage)!
Further Reading
• CHU, Pong P. RTL Hardware Design Using VHDL – Coding for
Efficiency, Portability, and Scalability. IEEE – John Wiley &
Sons, Inc., 2006. Chapters 8, 9, 10.