Karthik Vasudeva Shankar

Phone: 248-421-7144 510 Mansion Court

Email: karti.shankar@gmail.com Apartment 201
Santa Clara, CA, 95054

SUMMARY
Software Engineer with 5+ years of experience in design and development of device drivers and firmware

EDUCATION
Dept of ECE, University of Arizona, Tucson, AZ, USA
Masters of Science in Electrical and Computer Engineering Graduated in 05/2010
GPA: 4.0/4.0
Bangalore University (UVCE), Bangalore, India
Bachelor of Engineering in Electronics and Communication Graduated in 05/2005
Aggregate: 79.12% (CGPA: 3.8/4.0)
Relevant coursework:
 Introduction to Computer Architecture  Introduction to parallel processing
 Computer-Aided Logic design  Operating systems
 Embedded systems design and modeling  Distributed computing
 Digital VLSI Design  Advanced embedded microcontrollers

EXPERIENCE
Senior Software engineer
NVIDIA Corporation, Santa Clara, CA 11/2011 – Present
 Part of Graphics Firmware Group responsible for developing and maintaining video BIOS for NVIDIA Graphics chips
 Developed Bootloader for Power Management Unit for notebook SKUs
 Developed voltage controlling methodology for power states during boot
 Designed and developed DisplayPort firmware and link training
 Lead GK110, GK208 and GM107 chips during bring up; creating and maintaining firmware for different chip SKUs
 Designed and developed firmware architecture for PLX8747 bridge chips
 Developed tools required for flashing bios images on EEPROM
 Extensively involved in design and implementation of different features on power management and security of graphics
firmware.

Research Assistant
LPH research group, Dept of ECE, University of Texas, Austin, TX 01/2011 – 11/2011
 As a PhD student worked on research on fault tolerant computer architecture

Graduate Intern Technical

Intel Corporation, Austin, TX 06/2011 – 08/2011
 Ported few common interrupt service routines from one generation to other for Intel Atom SOC
 Developed scripts to process log and xml files from an internal test tool
 Developed webpages to display the above information using ruby on rails

Research Assistant
Embedded Systems Design Lab, Dept of ECE, University of Arizona, Tucson, AZ 05/2008 – 05/2010
 Developed a dynamic application profiler with multitasking application support that can be used for hardware/software
co-design
 Developed an error detection model utilizing application profiler information
Software Engineer
Mindtree Consulting LTD, Bangalore, India 09/2005 – 12/2007
 Worked on development and maintenance of On Board Diagnostics (OBD) vehicle scanner
 Involved in porting the board support package from FreeScale 68k processor to FreeScale 5232 processor
 Developed drivers for devices like CAN, UART etc
 Designed, developed and tested the embedded UI for the scanner using CPEG library
ACADEMIC PROJECTS
 Porting FreeRTOS. Under Prof. Mark Mcdermot. Ported FreeRTOS for LPC2148 and developed test applications on it
 LC-3b simulator. Under Dr. Yale Patt. Developed a cycle accurate simulator for LC-3b micro architecture as part of a course
 ALU design. Under Dr. Jacob Abraham. Developed Adder, Shifter, Comparator and Logical units
 4-bit SRAM cell. Under Dr. Jacob Abraham. Developed an area optimized 4-bit SRAM cell layout as part of class laboratory
 Operating systems. Under Dr. John Hartman. Developed the kernel, interrupt handlers, system calls, drivers, etc. for an
operating system during a course
 Load balancing for power optimized operation in distributed systems. Under Dr. Salim Hariri. Developed sender initiated and
receiver initiated load balancing algorithms to optimize power consumption in distributed systems
 Reconfigurable computing using multicore architectures. Under Dr. Ahmed Louri. Surveyed different existing approaches of
reconfigurable computing utilizing multicore architectures and suggested improvements for a few techniques
 Power aware communication for Network-On-Chips. Under Dr. Ahmed Louri. Detailed analysis of network on chips and the
power consumed by its individual components. Also suggested techniques to reduce the power consumption
 An independent study on self-healing systems. Under Dr. Roman Lysecky. A survey of various techniques involved in self-
healing systems

PUBLICATIONS
 K. Shankar, R. Lysecky. Non-Intrusive Dynamic Application Profiling for Multitasked Applications. Design Automation
Conference (DAC), 2009.
 J. Sun, R. Lysecky, K. Shankar, A. Kodi, A. Louri, J. Wang. Workload Assignment Considering NBTI Degradation in
Multi-core Systems. Asia and South-Pacific Design Automation Conference, 2010.
 A. Nair, K. Shankar, R. Lysecky. Efficient Hardware-Based Non-Intrusive Dynamic Application Profiling. ACM
Transactions in Embedded Computing Systems (TECS), 2010.
 K. Shankar, R. Lysecky. Control Focused Soft Error Detection for Embedded Application. IEEE Embedded Systems
Letters, Dec, 2010.
 K. Shankar, R. Lysecky. Methods for Non-Intrusive Dynamic Application Profiling and Soft Error Detection. Book chapter
to be published through CRC Press.

TECHNICAL SKILLS
 Programming:
o C, C++
o Perl, Ruby (Ruby on Rails)
o Assembly level programming (x86, ARM, MIPS64 simulator, etc.)
o MPI, OpenMP Programming
 Operating Systems:
o LINUX, DOS, Windows
o RTOS – RTEMS, SMX
 Other tools:
o NVIDIA in-house debuggers, GDB
o Perforce, GIT
o Simplescalar and MIPS64 instruction simulators

AWARDS AND ACTIVITIES

 Presented active research work involving Dynamic Application Profiler for multi-tasked applications at the
ACM/EDAC/IEEE Design and Automation Conference (DAC) ’09, San Francisco, USA
 Awarded financial assistance in the form of teaching assistance for PhD at the University of Texas at Austin
 Graduate Student Member of Institute of Electrical and Electronics Engineers (IEEE)
 Received “Spot award” at Mindtree Consulting for extraordinary performance in the project
 Awarded the title “learning catalyst” at Mindtree Consulting LTD for mentoring and sharing knowledge among new recruits
for over a year