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Scott Kellerman

ScottH.Kellerman@gmail.com
st
1704 1 Avenue West Phone: 941 748-0646
Bradenton, Florida
34205

Summary
OVER 15 YEARS EXPERIENCE AS A DIGITAL LOGIC DESIGNER - designing, integrating, debugging,
and supporting complex FPGA and custom ASIC designs, embedded TMS320 DSPs, real-time
software as well as high speed (>100Mhz ), multi-layered, dual strip-line PCBs.

Skills and Specialties


 Languages: Verilog, VHDL, AHDL, TI and Intel Assembly, FORTRAN, C/C++, Perl,
TCL/Expect, CVS and ClearCase.
 Tools: Synplify Pro, ModelSim, TI Code Composer, Cadence/Allegro, ViewLogic,
Xilinx EDK, Altera Quartus II and MaxPlus II, GCC, Eclipse, Telnet, SSH
 Program and integration of: TI TMS320 DSPs, MSP430, Intel I960, PPC405, Hitachi
65/7615, SparcLite, Intel 8051 and 8085 processors.
 Environments: UNIX, Linux, Windows, and Cisco IOS and CatOS.
 Design to 10/100/1000 Ethernet; 802.3ah, 802.3af, and 802.3at standards.

Career History
CISCO SYSTEMS INC – SAN JOSE CA AND BRADENTON FL - 1999 - PRESENT
HARDWARE DESIGN ENGINEER III
Responsible for design and development of high-speed digital circuit boards for Gigabit Ethernet
switching and routing applications using embedded processors, DSPs, FPGAs, custom ASICs
and high speed, low voltage discrete logic. Created Functional Specifications, cost estimates,
time-to-completion estimates, parts lists, schematics, and other documentation.

Design contributions at Cisco include:

 802.3at PoE PSE daughter card for 48 port GigE blade


 802.3af PoE PSE daughter card
 Test platform for 144Mb, 6.25GHz, SerDes based Network Memory ASICs
implementing Xilinx Virtex 4 and Vitex 5 FPGAs.
 802.3af/at PD Emulation platform for real-time, standards based PSE verification - First
in Industry.
SENTIENT NETWORKS - SAN JOSE CA AND SARASOTA FL - 1995 – 1999
DIGITAL DESIGN ENGINEER
Contributed to the design of a digital printed circuit boards for Gigabit Ethernet switching
applications. Specifically; the embedded Intel I960 processor sub-systems and VHDL FPGA,
and AHDL PLD designs. Designed and wrote the board and system level power-on diagnostics.
Created schematics, performed FPGA and board level simulation, verification and synthesis.

1995 and earlier

LORAL DATA SYSTEMS, Formerly known as FAIRCHILD WESTON, now L3 -


SARASOTA FL, ET AL:

TELEMETRY SYSTEMS - SARASOTA FL


TELEMETRY SYSTEMS ENGINEER
Designed, developed, and installed a multi-rack ‘Majority Vote’ launch data acquisition and
control system for Lockheed Martin's Titan IV launch platform.

TELEMETRY SYSTEMS – 2 YRS, SACRAMENTO CA


FIELD SERVICE ENGINEER
Providing technical support, training, and maintenance for a Flight Data Acquisition and
Test system (FDAT) created for the USAF F111 Aircraft Modernization Program (AMP)

TELEMETRY SYSTEMS
SR. ENGINEERING TECHNICIAN
FPGA, PLD, and printed circuit board design for the CPS100 Telecom Switch Program.
Created Schematic and performed gate-level simulation, debug, and design verification.

AVIATION FLIGHT RECORDERS


SR. ENGINEERING TECHNICIAN
Design, simulated and debugged FPGA, and PLD design for commercial aviation flight
recorders including the first generation of solid-state recorders. Schematics and BOM’s.

SIGNAL PROCESSING SYSTEMS (SPS)


SUPERVISOR, ENGINEERING TEST TECHNICIAN – Supervising 6 technicians.
Test, verification, and component level repair of NSA classified telemetry acquisition and
analysis platforms. PCM/FSK-AM/PM, Spread Spectrum, etc. NSA/DoD secret clearance,

Military Experience
AVIATION ELECTRICIANS MATE, PETTY OFFICER 2ND CLASS, UNITED STATES NAVY
Flight deck troubleshooter - Maintained and repaired Grumman A6E Intruder aircraft electrical
distribution systems, engine and flight controls, and instrumentation systems.
Attended Navy A & B schools; BE&E, AE A school, Aircraft Instrumentation.