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Operational Amplifier Stability

Part 9 of 15: Capacitive Load Stability: Output Pin Compensation


by Tim Green
Linear Applications Engineering Manager, Burr-Brown Products from Texas Instruments

Part 9 of this series is the fifth verse of our familiar electrical engineering tune, “There must be six
ways to leave your capacitive load stable.” The six ways are: Riso, High Gain & CF, Noise Gain,
Noise Gain & CF, Output Pin Compensation, and Riso w/Dual Feedback. In Part 9, here, we cover
Output Pin Compensation. This stability technique is NOT the same as an output op amp snubber
network, which is often used on the output of power operational amplifiers (with all-npn output stages)
to stop undesired, high-frequency oscillations when driving capacitive loads. Details of the use of the
snubber network will be discussed in a later part of this article series.

t
ne
Sometimes, in the real world, we do not always have access to the –input and/or +input of the op amp
to allow us to use other compensation tricks in our analog tool box. Here we will derive the Output Pin

s.
Compensation technique for both emitter-follower output op amps and also CMOS RRO op amps. The

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emitter-follower application will entail a reference output on a unique 4 - 20 mA building block

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integrated circuit. The CMOS RRO application involves a difference amplifier used in the feedback for
a power supply. Both of these definition-by-example cases are real-world applications where we will
-G
conclude our only stability option is Output Pin Compensation. In addition to first-order analysis and
EN
TINA Spice simulation, real-world implementation has been completed with as-predicted results.
on

Bipolar Emitter-Follower: Output Pin Compensation


d

Our bipolar emitter-follower Output Pin Compensation case is shown in Fig. 9.1. The XTR115/XT116
he

is a two-wire, 4 - 20 mA IC that can translate an input voltage change into an analog 4 - 20 mA signal.
is

Since the 4 - 20 mA transmitter is intended to drive long wires, it needs a wide operating voltage range
bl

of 7.5 V to 36 V. Additionally, the XTR115/XTR116 has a sub-regulator to provide 5 V to power


sensor conditioning circuitry and a precision reference of 2.5 V (XTR115) or 4.096 V (XTR116).
Pu

The 4 - 20 mA signal range is a well-established industrial standard intended to transmit analog signals
As

over long distances (over 1 mile or 1.6 km) in noisy environments, such as factories, where 50 Hz or
60 Hz large voltage noise is prevalent. Since the standard is a current controlled transmission, it is
immune to voltage noise coupling into its two wires. Power and signal are transmitted over the same
two wires. Since the useable analog signal range is defined as 4 - 20 mA, up to 4 mA is allowed to
power the signal conditioning circuitry and excite a sensor at the transmitter end of the two wires.
Power is provided by the receiver which also receives the analog 4 - 20 mA signal, which has been
scaled to correspond to a sensor’s measurement of real-world parameters such as pressure from a
bridge pressure sensor. At the receiver end, the 4 - 20 mA signal is often converted to a voltage (1 V to
5 V) across a resistor (250 ) to be read by an ADC.

Often times in such a 4 - 20 mA sensor transmitter a microcontroller is used to read and apply
linearization constants to the real-world sensor. The microcontroller must be low power to allow some
current to excite the sensor since our total conditioning circuit current budget must be less than 4 mA.
The MSP430F2003 provides a low-voltage, low-quiescent current microcontroller and has an on-board
ADC to read the bridge changes. After the microcontroller applies its linearization constants it talks to
the DAC8832, a low-power DAC to create the required analog input voltage to the XTR115/XTR1116.
The DAC8832 is buffered by a zero-drift, low-power, single-supply op amp, OPA333. Since we have
an absolute system we can power everything from the accurate VREF pin of the XTR115/XTR116.
We choose the XTR115 (2.5-V VREF) since the MSP430F2003 can only operate from 1.8 V to 3.3 V.
Now the on-board ADC of the MSP430F2003, as well as the DAC8832, will use the precision 2.5-V
reference of the XTR115. Our total, typical conditioning circuit quiescent current is 562 A, which
leaves up to 3.4 mA to excite our bridge sensor. Our only challenge now is that we need to add many
local bypass capacitors for good, high-frequency bypass near the many ICs powered from the VREF
pin of the XTR115. Will the XTR115 VREF pin be stable?

Transmitter
V REF 0.1 μF V REF V REF 0.1μF 0.1 μF
V REF
0.1 μF STABLE

t
C5 C4 C2 V REF

ne
C1
Bridge
I RET DV cc A V cc C3 0.1 μF
Pressure
Sensor VREF V DD
MSP430F2003

s.
DAC8832 -

iu
A DC +

OPA333

en
DV ss A V ss

-G
IRET
EN
on
d

V REF
he

Receiver
is
bl

V LO O P
Pu
As

IRET

Fig. 9.1: 4 - 20-mA Bridge Sensor Application


In Fig. 9.2 we detail the key specifications for the ICs used in our 4 - 20 mA bridge sensor conditioner
application.
XTR115/XTR116 DAC8832
2-Wire 4-20mA Current Loop Transmitter 16-Bit, Ultra-Low Power, Voltage-Output, Digital-to-Analog Converter

Parameter Specification Parameter Specification


Supply Voltage Range 7.5V to 36V Resolution 16 Bit
Quiescent Current 240uA typical Supply 2.5V to 5.5V
SubRegulator 5V Quiescent Current 5uA typical
VREF for Sensor Excitation 2.5V (XTR115), 4.096V (XTR116) Linearity Error +/-0.5LSB typical
VREF Accuracy +/-0.05% typical Differential Linearity Error +/-0.5 typical
VREF Drift +/-20ppm/C typical Gain Error +/-+/-1LSB typical
VREF PSR +/-1ppm/V (V+ = 7.5V to 36V) Gain Drift +/-0.1ppm/C typical
VREF vs Load +/-100ppm/mA (IREF = 0mA to 2.5mA) Zero Code Error +/-0.25LSB typical
VREF Noise 10uVpp typical (0.1Hz to 10Hz) Zero Code Drift +/-0.05ppm/C
Span Error 0.05% typical Package QFN-14
NonLinearity Error 0.003% typical
Package SO-8

t
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OPA333 MSP430F2003
1.8V, microPower CMOS Operational Amplifier, Zero-Drift Series 1.8V, microPower CMOS Operational Amplifier, Zero-Drift Series

s.
Parameter Specification Parameter Specification

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Supply Voltage 1.8V to 5.5V Supply Voltage 1.8V to 3.6V
Quiescent Current 17uA typical Quiescent Current 300uA typical (Active Mode, 1MHz)

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Offset Voltage 2uV typical Architecture 16-bit RISC
Offset Drift 0.02uV/C typical A/D Converter 16-Bit Sigma-Delta
Input Bias Current
Input Voltage Noise
Input Voltage Range
+/-70pA typical
1.1uVpp (0.1Hz to 10Hz)
(V-)-0.1V to (V+)+0.1V
Flash
RAM
-G
Watchdog Timer
1k Byte + 256 Byte
128 Byte
EN
Gain-Bandwidth Product 350kHz Port 1 8 I/O
Slew Rate 0.16V/us Port 2 Xtal or 2 I/O
Voltage Output Swing from Rail 30mV typical (RL=10k) Interface Universal Serial (SPI, I2C), Port 1
Package SOT23-5, SC70-5, SO-8, DFN-8 Clock Internal, External 32kHz crystal
on

Package TSSOP-14, DIP-14, QFN-16

Fig. 9.2: Key Specifications For 4 - 20-mA Conditioning Circuit ICs


d
he

The XTR115 VREF pin is the output of an emitter-follower output topology as shown in Fig. 9.3.
is
bl
Pu
As

Fig. 9.3: XTR115 VREF Pin: Emitter-Follower Output Op Amp


Fig. 9.4 shows the equivalent circuit of the XTR115 VREF pin. VREF is a buffered 1.25-V bandgap
reference which is amplified by x2 to yield the XTR115 2.5V reference output. The emitter-follower
output stage has an Ro of 4.7 k. This information, along with values for RF and RI and the Aol curve
of U1, were obtained from the factory as it is not given in the data sheet. Our total capacitive load, CL,
is seen to be 500 nF. Ro will interact with CL to form a second pole, fpu1, in the modified Aol curve
for the XTR115 VREF op amp. Note that we have no access to the –input or +input of U1 since it is
internal to the XTR115. This leaves us with only one pin to compensate the amplifier for stability (the
output pin: VREF). Also note that we want the VREF pin to remain extremely accurate, and so putting
any resistance in series with this pin before CL is not an acceptable solution.
Op Amp Aol Curve is Modified by
extra pole (fpu1) due to Ro and CL

CL = C1+C2+C3+C4+C5

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ne
RF114k
fpu1 = 1/(2 *Ro*CL)

s.
fpu1 = 1/(2 *4.7k*500nF)

iu
fpu1 = 67.73Hz
RI114k U1!OPAMP

en
- Ro4.7k
VREF
++ -G
V+24V
EN
Vbg 1.25V C1100nF C2100nF C3100nF C4100nF C5100nF

XTR115 VREF Equiv alent Circuit


on

VREF = 2.5V
d

Fig. 9.4: XTR115 VREF Pin: Capacitive Load, Equivalent Schematic


he

We will use the TINA Spice circuit of Figure 9.5 to examine the Aol curve of the op amp and the
is

modified Aol curve due to CL. We use our Spice ac analysis trick by using LT, short at dc and an open
bl

at ac frequencies of interest, and CT, open at dc and a short at ac frequencies of interest.


Pu

CT1TF VT
+
As

RF114k LT1TH
Aol = VOA/VM
VM Modif ied Aol = VREF/VM
1/Beta = VT/VM
Loop Gain = VREF/VT
RI114k VOA
- Ro4.7k
U1!OPAMP VREF
++
Vbg1.25V V+24V CL500nF

Fig. 9.5: Ac Stability Check: Original Circuit


Fig. 9.6 shows the op amp Aol curve and the modified Aol curve due to CL. At fcl1, we see a
40 dB/decade rate-of-closure which is unstable by our first-order stability criteria. Our predicted fpu1
due to CL was 67.73 Hz which from inspection looks to be correct in this plot.
T
100.00

80.00

60.00
Aol

40.00
Modified Aol
fcl1
20.00
Gain (dB)

0.00
1/Beta

t
STABLE

ne
-20.00

s.
-40.00

iu
-60.00

en
-80.00
-G
-100.00
EN

1 10 100 1k 10k 100k 1M 10M


Frequency (Hz)
on

Fig. 9.6: Aol And Modified Aol: Original Circuit


A loop-gain plot in Fig. 9.7 confirms our concerns with phase margin almost zero (0.442°!) at fcl1.
d
he

a
T 100
is

80 Gain:
60 Loop A:(5.79k;-167.74m) B:(5.76k;-82.95m)
bl

40 Loop Gain Phase :


Loop A:(5.79k;436.85m) B:(5.76k;442.2m)
Pu

20
Gain (dB)

-20
As

-40

-60

-80

-100
1 10 100 1k fcl1 10k 100k 1M 10M
Frequency (Hz)

b
180

135

Loop Gain STABLE


90
Phase [deg]

45

-45

-90
1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)

Fig. 9.7: Loop-Gain Plot: Original Circuit


In Figure 9.8 we do a transient stability test by injecting a small square wave into our closed loop
circuit with CL of 500 nF attached.
RF114k

VM

RI 114k VOA
- Ro4.7k
U1!OPAMP VREF
++

Vbg 1.25V V+24V CL500nF

t
ne
VG1

s.
+ 50mVp

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100Hz

en
-G
Fig. 9.8: Transient Stability Test: Original Circuit
EN

Our transient stability plots in Figure 9.9 indicate, again, that our circuit is not stable. Our op amp
output never settles in response to a small step change. Note that VOA is transitioning about 2.5 V,
on

indicating that our dc levels are correct for this circuit.


d

T 1.00m
he

VG1
is
bl

-1.00m
1.25268
Pu

VM
As

1.24740 STABLE
2.84161
VOA

2.23870
2.50422
VREF

2.49348
0.00 1.00m 2.00m
Time (s)

Fig. 9.9: Transient Stability Plots: Original Circuit


In Fig. 9.10 we identify the technique for Output Pin Compensation for bipolar emitter-follower output
amps. First we modify the op amp’s original Aol curve with fpu1, the pole due to Ro and CL (see
Curve 1). Once this curve is created, we plot a second curve (Curve 2) which starts where the Curve 1
intersects 0 dB. From this starting point we plot back at -20 dB/decade to a point which is one decade
above fp1 (the op amp Aol low frequency pole) where we change the slope to -40 dB/decade. At fp1
frequency we change the slope back to –20 dB/decade until we intersect the dc Aol value of the op
amp. This proposed modified Aol curve (Curve 2) meets all of our rule-of-thumb criteria by keeping
poles and zeros within one decade of each other to keep loop gain phase from dipping below 45°
within the loop-gain bandwidth. Our proposed modified Aol curve (Curve 2) will also meet our first-
order stability criteria of 20 dB/decade rate-of-closure at fcl2.
120
First pass at stability:
fpc1 fp1
100 Aol
Create Modified Aol with Ro, RCO, CCO

t
(Curve 2) which is less in frequency at all

ne
fpu1
80 fpc2 points than Modified Aol with Ro, CL (Curve 1).

s.
1/ intersects with Modified Aol from Ro, RCO,

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60
CCO (Curve 2). Therefore CL effect is never
Gain (dB)

seen for loop gain stability!

en
40 Proposed
Modified Aol fzc1

20
2 1 fcl1
-G
EN
10dB

0 fp2
Acl fcl2
on

-20
d

Modified Aol due fpc4


he

-40 to CL and RO
is

-60
1 10 100 1K 10K 100K fpu2 1M 10M
bl

Frequency (Hz)
Pu

Curve 1 STABLE Curve 2 STABLE


As

Fig. 9.10: Output Pin Compensation: Bipolar Emitter-Follower

Fig. 9.11 shows how we will get our proposed modified Aol curve by using RCO and CCO. There will
be an additional pole we will have to also consider since, at some high frequency, CCO will become a
short and CL and RCO will form an additional high-frequency pole. If this pole occurs beyond fcl2, we
will still be okay.
CT1TF VT
+

RF114k LT1TH
Aol = VOA/VM
VM Modif ie d Aol = VREF/VM
1/Beta = VT/VM
Lo op Gain = VREF/VT
RI114k VOA
- Ro4.7k
U1!OPAMP VREF
++
Vbg1.25V V+24V RCO75 CL500nF

t
ne
s.
CCO22uF

iu
en
Fig. 9.11: Ac Stability Check: Output Pin Compensation
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Since we know Ro and CL we can use the formulae in Fig. 9.12, in conjunction with our proposed
EN

modified Aol curve in Fig. 9.10 (Curve 2), to compute our compensation components RCO and CCO
along with the extra high-frequency pole formed by RCO and CL.
on

Ro = 4.7k _ , RCO = 75 _ , CCO = 22 F, CL = 500nF


d
he

fpc1 = 1/[2 *(Ro+RCO )*CCO]


fpc1 = 1/[2 *(4.7k _ +75_ )*22 F] = 1.5Hz
is
bl

fpc2 = fp1 = 10Hz


Pu

(Low frequency pole from op amp Aol curve)


As

fzc1 = 1/(2 *RCO*CCO)


fzc1 = 1/(2 *75 _ *22 F) = 96.5Hz

fpc3 = 1/[2 *(Ro//RCO)*CL]


fpc3 = 1/{2 *[(Ro*RCO)/( Ro+RCO )]*CL}

If: RCO < 10*Ro and CCO > 10*CL


Then: fpc3 ~ 1/[2 *RCO*CL]
fpc3 ~ 1/[2 *75 _ *500nF] = 4.2kHz

fpc4 = fp2 = 1MHz


(High frequency pole from op amp Aol curve)

Fig. 9.12: Output Pin Compensation Formulae: Bipolar Emitter-Follower


In Fig. 9.13 we plot our predicted curves using Output Pin Compensation. Since our closed-loop op
amp inside the XTR115 runs at a gain of x2 (6 dB), the closed-loop VREF/VIN curve will remain flat
until it intersects with our modified Aol at fcl2, where it will then follow the modified Aol curve on
down since loop gain has gone to zero.

120

fpc1 fp1
100 Aol

80 fpc2

60
Gain (dB)

40 Final
fzc1

t
Modified Aol

ne
20 1/ STABLE fcl2

s.
fpc3

iu
0
fp2

en
VREF/VIN
-20

-40
-G
-40 dB/decade
EN
slope
-60
1 10 100 1K 10K 100K 1M 10M
on

Frequency (Hz)

fpc4
d
he

Fig. 9.13: Final Predicted Curves: Output Pin Compensation


is
bl

Fig. 9.14 is the result of our ac stability analysis TINA Spice simulation using the circuit of Fig. 9.11.
Pu

At fcl2 it looks like 20 dB/decade rate-of-closure, but we should look at a phase plot for more detail.
As
T
100

80
Aol

60

40

1/Beta fcl2
20
Gain (dB)

0
??? Final
STABLE Modified Aol
-20 ???

-40

-60

t
ne
-80

s.
-100

iu
1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)

en
Fig. 9.14: Aol And Modified Aol: Output Pin Compensation
-G
EN
Our loop gain plot shown in Figure 9.15 confirms that our Output Pin Compensation will yield a stable
circuit. At fcl2 we have a 40º phase margin with phase not dipping much below 45º inside the loop
gain bandwidth. If we wanted to we could adjust Output Pin Compensation values slightly to gain
on

more phase margin at fcl2.


d

a
T 100
he

80 Gain :
Loop Gain
60 Loop A:(4.96k; 8.14m) B:(4.95k; 27.84m)
is

Phase:
40
Loop A:(4.96k; 40.37) B:(4.95k; 40.41)
bl

20
Gain (dB)

0
Pu

-20

-40
As

-60

-80

-100
1 10 100 1k fcl2 10k 100k 1M 10M
Frequency(Hz)

b
180

135
STABLE
Loop Gain
90
Phase [deg]

45

-45

-90
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)

Fig. 9.15: Loop Gain: Output Pin Compensation


The circuit in Fig. 9.16 uses our transient stability test to check our final circuit using Output Pin
Compensation.
RF114k
VM

RI114k VOA
- Ro4.7k
U1!OPAMP VREF
++
Vbg1.25V V+24V RCO75 CL500nF

VG1

t
+

ne
1mVp
1kHz

s.
CCO22uF

iu
en
Fig. 9.16: Transient Stability Test: Output Pin Compensation
-G
EN
Our transient stability test results in Fig. 9.17 confirm our loop-gain check that our Output Pin
Compensation produced a stable circuit. A small overshoot and one undershoot with no excessive
ringing looks close to a typical 45° phase margin compensated circuit.
on

T 1.00m
d
he

VG1
is
bl

-1.00m
1.25174
Pu

VM
As

1.24845
2.84662

VOA

2.22992
2.50229

VREF

2.49564

0.00 1.00m 2.00m


Time (s)

Fig. 17: Transient Stability Plot: Output Pin Compensation


The TINA Spice circuit in Fig. 9.18 allows us to see if our final VREF/VIN closed-loop ac response is
as we predicted in Fig. 9.13.
RF114k

RI114k VOA
- Ro4.7k
U1!OPAMP VREF
++
Vbg1.25V V+24V RCO75 CL500nF

VIN +

t
AC

ne
1Vpk CCO22uF

s.
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Fig. 9.18: VREF/VIN Ac Circuit: Output Pin Compensation

en
From Fig, 9.13 we estimate fcl2 to be at around 5 kHz and thus expect a sharp roll-off at this point for
-G
VREF/VIN. In Fig. 9.19 we see the closed-loop ac response is as predicted. There is a slight peaking
EN
which, for this application, causes no concern but if we desired to reduce it we would need to go
through one more pass of our Compensation and increase the phase margin at fcl2 to greater than 40°.
on

T 20
d

0
he

VREF/VIN
-20
Gain (dB)

is

-40
bl

-60
Pu

-80
As

-100
1 10 100 1k fcl2 10k 100k 1M 10M
Frequency(Hz)

-45
VREF/VIN

-90
Phase [deg]

-135

-180

-225
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)

Fig. 9.19: VREF/VIN Ac Response: Output Pin Compensation


CMOS RRO: Output Pin Compensation

Our CMOS RRO Output Pin Compensation case is shown in Fig. 9.20. This real-world power supply
application uses an OPA569 power op amp as a programmable power supply. For accurate power
supply voltage across the load a difference amplifier, INA152, is used to monitor the voltage
differentially across the load.

The closed-loop system then will correct for any losses due to wire drops in either the positive or
negative connection from the programmable power supply to the load. The current limit on the
OPA569 is set for 2 A. In our actual application this power supply has flexible configurations, and as a
result can end up with up 10 nF of capacitance on the output of the difference amplifier.

Is this going to result in a stable operation of our programmable power supply?

t
ne
VDIFF 3.299 972V -
Sense
???

s.
STABLE

iu
???
CX10nF U1INA152 +

en
+
Ref

k
VFB 3.299 971V 6
7
0 CF100nF
-G
VCC
5
EN
.
7
5
N
T
on

O M
E
M 1
S
R
R
d

1
he

VOUT 3.299 844V


RI100k R
- Iset Imon Iflag
is

U2OPA569
+ +
bl

En Ta
lf g RLoad1.8
M
Vadjust3.3V
Pu

1
VCC 2
VCC5V
R
As

Figure 9.20: Programmable Power Supply Application

In Fig. 9.21 are the key specifications for the ICs used in our programmable power supply application.
INA152 OPA569
Single Supply Difference Amplifier Rail-to-Rail I/O, 2A Power Amplifier

Parameter Specification Parameter Specification


Supply Voltage 2.7V to 20V Thermal Protection Shutdown at +150C
Quiescent Current 500uA typical Adjustable Current Limit +/-0.2A to +/-2.2A
Offset Voltage +/-250uV typical Current Limit Warning Flag Normal = V+, Current Limit = V-
Offset Drift +/-3uV/C typical Temperature Warning Flag Low = >+147C, High =<+130C
Input Impedance Differential 80k typical Shutdown w/Output Disable >(V-)+2.5V = enabled, <(V-)+0.8 = disabled
Input Impedance Differential 80k typical Current Monitor Pin Imonitor = Iout/450
Common Mode Rejection 94dB typical Supply Voltage 2.7V to 5.5V
Output Voltage Noise 2.4uVpp (0.1Hz to 10Hz) Quiescent Current 9mA typical, 0.01mA in Shutdown
Output Voltage noise 10nV/rt-Hz (10kHz) Offset Voltage +/-0.5mV typical
Input Voltage Range 2(V-) to 2(V+)-2V Offset Drift +/-1.3uV/C typical
Bandwidth 800kHz Input Bias Current +/-1pA typical
Slew Rate 0.4V/us Input Voltage Noise 8uVpp (0.1Hz to 10Hz)
Gain 1V/V typical Input Voltage noise 12nV/rt-Hz (1kHz)
Gain Error +/-0.01% typical Input Voltage Range (V-)-0.1V to (V+)+0.1V
Gain Drift +/-1ppm/C typical Gain-Bandwidth Product 1.2MHz
NonLinearity +/-0.002%FS Slew Rate 1.2V/us

t
ne
Voltage Output Swing from Rail 20mV typical (RL=10k) Voltage Output Swing from Rail 150mV typical (Iout=+/-2A)
Package MSOP-8 Package SO-20 Power Pad

s.
Fig. 9.21: Key Specifications For Programmable Power Supply ICs

iu
en
The INA152 difference amplifier we use for feedback is a CMOS RRO topology (see Fig.9.22).
-G
EN
on
d
he
is
bl
Pu
As

Fig. 9.22: INA152 Difference Amplifier: CMOS RRO

We use the TINA Spice circuit in Fig. 9.23 to check for stability of our programmable power supply.
Our dc output is set by Vadjust to be 3.3 V and a small transient square wave will be applied to look
for overshoot and ringing.
VDIFF Sense
-

CX10nF U1INA152 +
+
Ref

k VCC
VFB 6 CF1nF
7 0
. 5
5 7
T N
E M
O 1
S M
R R 1
VOUT
RI 10k R
- Iset Imon Iflag

t
U2OPA569

ne
+ + RLoad1.8
En Ta
lf g
M

s.
Vadjust 3.3V 1
VCC

iu
D C = 0V 2
VG1 + Transient:
VCC5V
R

en
100mVpk
1kH z
10ns rise & f all -G
EN
Fig. 9.23: Transient Stability Test: Original Circuit

In Fig. 9.24 the results of our transient stability test are clearly undesirable. This is not a circuit we
on

want to go to production without some additional stability compensation.


d

T 3.50
he

VDIFF
is

STABLE
bl

3.03
3.41
Pu

VFB
As

3.18
100.00m

VG1

-100.00m
3.42

VOUT

3.17

0.00 350.00u 700.00u


Time (s)

Fig.9.24: Transient Stability Plot: Original Circuit


The TINA Spice circuit in Fig. 9.25 is used to see if the instability in our original circuit is due to the
CX load on the output of the INA152. We will use a transient stability test for a quick check.

VDIFF 2.50005V Sense


-

CX10nF U1INA152 +
Ref +

VCC
VCC
VCC5V

t
ne
s.
iu
Vdc2.5V
DC = 0V

en
Trans ient:
RLoad1.8
+ VG1
100mVpk
1kHz
10ns rise & fall
-G
EN

Fig. 9.25: Difference Amplifier Feedback: Original Circuit


on

Fig. 9.26 confirms our theory of CX causing instability on the difference amplifier INA152.
T 2.68
d
he
is

VDIFF
bl

STABLE
Pu

2.26
As

100.00m

VG1

-100.00m
0.00 350.00u 700.00u
Time (s)

Fig. 9.26: Transient Plots: Difference Amp Feedback, Original Circuit

The difference amplifier consists of an op amp and four precision ratio-matched resistors. This
presents us with a challenge for analysis since we do not have direct access to the –input or +input of
the internal op amp. In Fig. 9.27 we see the equivalent circuit for the difference amplifier and a clever
way we can measure the Aol. We will use LT to break open the feedback for any ac frequencies of
interest and still retain an accurate dc operating point (LT is short for dc, open for ac frequencies of
interest). By connecting the Ref pin of the INA152 to the VIN+ pin we create a non-inverting input
amplifier. By placing LT between Sense and VOA we will essentially be driving the op amp open loop
at any ac frequency of interest. VM, the internal node for the INA152 op amp will be at zero for ac
frequencies of interest. VP will simply be VG1 and we easily can measure Aol = VOA/VG1. Note that
we scale the dc operating point by setting VdcBias to 1.25 V to yield 2.5 V on VOA for dc.
V15V
+V
7
At DC LT = Short
INA152_TG VOA dc = VdcBias  (1+R2/R1)
VOA dc = 1.25  (1 + 40k/40k) = 2.5V
2 R140k R240k 5
VIN- Sense
At any f requency of interest LT f orces op amp

t
LT1TH open loop and VM is esentially 0V AC.

ne
INA152OpAmp VP = VG1 since VIN+ and Ref are connected to VG1
VM - 6
VOA

s.
+ Theref ore:
VP
Aol = VOA/VG1
VdcBias1.25V

iu
3 R340k R440k 1
VIN+ Ref

en
VG1 +
DC = 0V
AC = 1Vpk 4
-G
EN
-V
on

Figure 9.27: INA152 Aol Test Circuit Concept


d
he

We translate our INA152 Aol Test Circuit Concept of Figure 9.27 into a TINA Spice circuit here (see
Fig. 9.28. We know that the TINA Spice macro-model for the INA152 is a Bill Sands [Consultant,
is

Analog & RF Models, http://www.home.earthlink.net/%7Ewksands/ ] macro-model and, thus, will


bl

accurately match the real silicon.


Pu

Aol = VOA/VG1

LT1T
As

- Sense

VOA 2.499925V
+ U1INA152
+
Ref

VdcBias1.25 V15

VG1 +
DC = 0V
AC = 1Vpk

Fig. 9.28: TINA Spice INA152 Aol Test Circuit


Fig. 9.29 gives us the detailed Aol curve for the INA152 from our TINA Spice simulation. Note that
there is a second pole in the Aol curve at about 1 MHz with some higher-order poles beyond that based
on the Aol phase curve which, beyond 1 MHz, shows a slope steeper than –45°/decade.
T 120

100 INA152 Op Amp Aol

80

60
Gain (dB)

40

20

-20

-40

-60
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)

t
fp1=3.64Hz

ne
-45 INA152 Op Amp Aol
45 degree/decade slope
-90

s.
-135

iu
Phase [deg]

-180 fp2? = 1MHz

en
-225

-270

-315
-G
EN
-360
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)
on

Fig. 9.29: INA152 Aol TINA Spice Results


d

Since we know the INA152 is a CMOS RRO difference amplifier, in addition to the Aol curve, we will
he

need Zo to attempt any analytical stability analysis. In Fig. 9.30 we develop a Zo Test Circuit Concept.
is

Similar to our Aol Test Circuit of Fig. 9.28, we can force the internal op amp of the INA152 to be open
loop for any ac frequencies of interest through the use of LT and the circuit connections as shown.
bl

Now we will drive the output with an ac current source, set to 1 Apk, and measure Zo directly by the
Pu

voltage at VOA.
V15V
As

+V
7 At D C L T = Sho rt
IN A152 _TG VOA dc = Vd cBias  (1+R 2/R 1)
VOA dc = 1.25  (1 + 40k/40 k) = 2 .5 V
2 R140k R240k 5
VIN- Sense At an y freque ncy o f interest LT force s op amp op en lo op
Sinc e IT = 1 Apk
INA152OpAmp LT1TH
Zo = VOA
VM - 6
VOA
VP +
VdcBias1.25V 1
3 R340k R440k
VIN+ Ref
DC = 0A
IT
4 AC = 1Apk

-V

Fig. 9.30: INA152 Zo Test Circuit Concept


In Fig. 9.31 we build our TINA Spice INA152 Zo Test Circuit. A quick dc analysis confirms we are at
the proper dc operating point for the INA152. It is always a good idea to perform a dc analysis before
running an ac one in Spice to confirm that the circuit is not saturated at either supply rail -- causing an
erroneous ac analysis results.

- Sense
LT 1T

VF1 2.499925V
+ U1INA152
+
Ref

t
VdcBias 1.25 IG1

ne
V15

s.
iu
en
Fig. 9.31: INA152 Zo TINA Test Circuit
-G
EN
T 100k

Zo :
VOA A:(4.052664;22.546871k) B:(76.172667;2.165303k)
on

10k Phase :
VOA A:(4.052664;-45.24079) B:(76.172667;-45.321206)
Zo (ohms)

d
he

1k
is
bl

100
Pu

1 10 100 1k 10k 100k 1M


Frequency (Hz)

a b
0
As
Phase [deg]

-45

-90
1 10 100 1k 10k 100k 1M
Frequency (Hz)

Fig. 9.32: INA152 TINA Zo Curves

The results of our TINA Zo test in Fig. 9.32 show a typical CMOS RRO response for Zo. We see a
zero at fz = 76.17 Hz and a pole at fp = 4.05 Hz.
a
T 100k

Zo :
VOA A:(552.168823k; 1.448248k)
10k
Zo (ohms)

1k

100
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)

t
Phase [deg]

ne
-45

s.
iu
en
-90
1 10 100 1k 10k 100k 1M 10M
-G
Frequency(Hz)

Fig. 9.33: INA152 Tina Ro Measurement


EN

In Fig. 9.33 we measure Ro from our Zo curves created by TINA Spice. Ro = 1.45 k.
on

From our measured Zo plots we know Ro, fz, and fp. This information allows us to build our
d

equivalent Zo model for the INA152 (see Fig. 9.34).


he

RX
is

RO = 1.45k _
bl

fz = 76.16Hz CO
Pu

fp = 4.05Hz
As

+ VOUT
-IN -
Aol +
+ RO
+IN -
GM2 GMO
-

fz = 1 fp = 1
2* *RO*CO 2* *RX*CO

76.16Hz = 1 4.05Hz = 1
2 * *1.45k*CO 2 *  *RX* 1.44 F
CO = 1.44 F RX = 27.29k _

Fig. 9.34: INA152 Zo Model


We can use our TINA Spice simulator to quickly check the accuracy of our equivalent Zo model
against the actual INA152 Zo. The equivalent Zo model results are shown in Fig. 9.36 with a
comparison shown in Fig. 9.35. We see that our equivalent Zo model is close enough to proceed with
our stability analysis.
RX27.29k VOA

RO1.45k CO1.44uF
IT
D C =0A

t
AC = 1Apk

ne
s.
Zo fz fp

iu
INA152 Measured 76.16Hz 4.05Hz

en
Equivalent Model 71.2Hz -G 4.56Hz
EN

Fig. 9.35: Zo Equivalent Model Vs INA152 Zo


on

T 100.00k

Zo :
VOA A:(4.56; 19.11k) B:(71.2; 2.18k)
d

Phase :
he

10.00k VOA A:(4.56; -45.14) B:(71.2; -45.21)


Zo (ohms)

RO = 1.45k ohm
is
bl

1.00k
Pu
As

100.00
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)

a b
0
Phase [deg]

-45

-90
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)

Fig. 9.36: TINA Plots: Equivalent ZO Model for INA152


We can now analyze the effect of load capacitance, CL, on the output of the INA152 using our Zo
equivalent model. We see an additional pole in the Aol curve at 10.98 kHz as shown in Fig. 9.37.
RX 27.29k

RX has no effect on fp2 since its


im pedance is shunted by CO at
frequencies > 4.05Hz CO 1.44μF

VOUT
+
-IN -
Aol +
+ RO CL
+IN - GM2 1.45k GMO 10nF
-

t
fp2 = 1 fp2 = 1 = 10.98kHz

ne
2* *Ceq *RO 2* *10nF *1.45k

s.
iu
where: Ceq = CO * CL CL<1.44 μF CL dominates: Ceq CL

en
CO + CL CL>1.44 μF CO dominates: Ceq CO
remember:
1) capacitors in series are like resistors in parallel -G
2) XC = 1/sC
EN

3) XCeq = 1/sCO +1/sCL


4) Ceq = 1/XCeq
on

Fig. 9.37: Computing The Pole (fp2) Due To Zo And CL


d

In Fig. 9.38 we add the CL of 10 nF to our equivalent Zo model for the INA152.
he
is

RX27.29k VOA
bl
Pu

IG1
CL10nF
D C =0A RO1.45k CO1.44uF
As

AC = 1Apk

Fig. 9.38: TINA Circuit For Analysis Of fp2

From Fig. 9.39 we see the simulation results place fp2 at 11.01 kHz, which is close enough to our
predicted 10.98 kHz to proceed forward.
T 80

60
Gain (dB)

40
Gain:
VOA A:(11.01k;60.17)
Phase :
20
VOA A:(11.01k;-44.85)

0
1 10 100 1k 10k 100k 1M 10M
Frequency (Hz) fp2
a
0
Phase [deg]

t
ne
-45

s.
iu
en
-90
1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)

-G
Fig. 9.39: fp2 Plot For Zo And CL = 10 nF
EN

Aol = VOA/VG1
on

LT1T
- Sense
d

VOA
he

+ U1INA152
+
is

Ref
CL10n
bl

VdcBias1.25 V15
Pu

VG1 +
As

DC = 0 V
AC = 1Vpk

Fig. 9.40: TINA Circuit For Modified Aol Curve With CL = 10 nF

Now we can run a TINA simulation the actual INA152 with CL = 10 nF and compare it to our
predicted response using the circuit of Fig. 9.40.

The TINA simulation results in Fig. 9.41 show a low-frequency pole due to the INA152 op amp
original Aol at 3.4 Hz (fp1) and a second pole due to Zo and CL = 10 nF at fp2 = 11.02 kHz.
Remember, we predicted fp2 = 10.9 kHz by first-order analysis and fp2 = 11.01 kHz by equivalent Zo
model simulated with CL = 10 nF.
T 120

100
Modified Aol Curve due to CL
80

60
Gain (dB)

40
Gain :
20 VOA A:(3.4; 107.03) B:(11.02k; 37.11)
0 Phase :
-20 VOA A:(3.4; -43.15) B:(11.02k; -135.39)

-40

-60
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)

a b
0

-45
fp1
-90

t
-135
Phase [deg]

ne
fp2
-180

s.
-225

-270

iu
-315

en
-360
1 10 100 1k 10k 100k 1M 10M
-G
Frequency(Hz)

Fig. 9.41: TINA Plots For Modified Aol Curve With CL = 10 nF


EN

T
120
on

100
d
he

80
is

60
bl

fpc2
Pu

fp2
40
Gain (dB)

Final INA152 Aol


Modified Aol
As

20
fzc1
1/Beta

0
Modified Aol
w/CL = 10nF
-20

-40

-60

1 10 100 1k 10k fcl 100k 1M 10M


F (H )

Fig. 9.42: Output Pin Compensation: CMOS RRO

In Fig. 9.42 we identify the technique for Output Pin Compensation for CMOS RRO op amps. The
graphical part of this technique will be similar to that for bipolar emitter-follower op amps. First we
modify the op amp’s original Aol curve with fp2, the pole due to Zo and CL (Fig. 9.41). Once this
curve (modified Aol with CL = 10 nF) is created we plot a second curve (final modified Aol) which
starts where the modified Aol with CL = 10 nF curve intersects 0 dB. From this starting point we plot
back at –20 dB/decade to a point which is one decade less than the zero dB intersection of the modified
Aol curve with CL = 10 nF (100 kHz).Here at fzc1 we change the slope to –40 dB/decade. At fpc2 we
intersect the original INA152 Aol curve. This proposed final modified Aol curve meets all of our rule-
of-thumb criteria by keeping poles and zeros within one decade of each other to keep loop-gain phase
from dipping below 45° within the loop-gain bandwidth. Our proposed final modified Aol curve also
meets our first-order stability criteria of 20 dB/decade rate-of-closure at fcl.

Fig. 9.43 details the formulae based on Zo and the desired final modified Aol curve. In addition, we
notice another high-frequency pole due to RCO interacting with CL when CCO becomes a short.
CO 1.44μF

t
ne
+ VOUT
-IN

s.
-
Aol + CCO CL
+ RO 10nF

iu
+IN - GM2 1.45k GMO 100nF
-

en
RCO
150

Assume: CCO > 10*CL


-G
EN
Set: fpc2 = 1kHz, fzc1 = 10kHz

fpc2 = 1 fpc2 = 1 = 1kHz


on

2* *Ceqo*RO 2* * CCO *1.45k


CCO = 109.76nF  use 100nF
where: Ceqo = CCO * CL
d

CCO + CL
he

CCO < 1.44μF CCO dominates: Ceqo CCO


is
bl

fzc1 = 1 fzc1 = 1 = 10kHz


Pu

2* *Ceqo*RCO 2* * 100nF*RCO
RCO = 159.15  use 150
where: Ceqo = CCO * CL
As

CCO + CL
CCO < 1.44μF CCO dominates: Ceqo CCO

At High Frequency CCO becomes a short


Another pole, fpc3 is formed by RCO and CL

fpc3 = 1 fpc3 = 1 = 106kHz


2* *CL*RCO 2* * 10nF*150

Fig. 9.43: Output Pin Compensation Formulae: CMOS RRO

In Fig. 9.44 we build a TINA Spice circuit to confirm our formulae, which predict effects on the Aol
curve due to Zo, CCO, RCO, and CL.
RX27.29k VOA

IG1 CL10nF RCO150


DC=0A RO1.45k CO1.44uF
AC = 1Apk

CCO100nF

Fig. 9.44: TINA Circuit For Modified Aol Effects By Zo, CCO, RCO, CL
T 80.00

VOA

t
ne
60.00

s.
Gain (dB)

40.00

iu
en
20.00

0.00

1 10 100 1k
-G 10k 100k 1M 10M
EN
Frequency (Hz)

0.00
on

fpc3=105.80kHz
Phase [deg]

-45.00
he

fpc2=1.23kHz
fzc1=10.25kHz
is
bl

-90.00
Pu

1 10 100 1k 10k 100k 1M 10M


Frequency (Hz)
As

Fig. 9.45: Modified Aol Effects By Zo, CCO, RCO, CL

In Fig. 9.45 we see the results of simulation to check our formulae for Aol modification due to Zo,
CCO, RCO, and CL. Predicted fpc2 = 1 kHz, actual fpc2 = 1.23 kHz. Predicted fzc2 = 10 kHz, actual
fzc2 = 10.25 kHz. Predicted fpc3 = 106 kHz, actual fpc3=105.80 kHz. Based on our equivalent Zo
model our predictions match close enough to the simulated results.

Based on our analysis of Fig. 9.43 and simulation confirmation we can create a final modified Aol
prediction as shown in Fig. 9.46. The final closed-loop response, Vout/Vin, is predicted to be flat until
loop gain goes to zero at fcl upon which it is expected to follow the modified Aol curve as shown.
T
120

100

80

60
fpc2

40
Gain (dB)

INA152 Aol
Final
Modified Aol
20 1/Beta
fzc1

0 fpc3
Modified Aol
Vout/Vin w/CL = 10nF

t
-20

ne
s.
-40

iu
-60

en
1 10 100 1k 10k fcl 100k 1M 10M
Frequency (Hz)
-G
Fig. 9.46: Final Modified Aol Predictions
EN

Our ac stability test circuit using our final Output Pin Compensation is shown in Fig. 9.47. The result
on

will be a modified Aol curve due to the Output Pin Compensation and CL.
d
he

LT1T
-
is

Sense
bl

Aol = VOA/VG1 VOA


Pu

+ U1INA152
+ Ref
RCO150
CL10n
As

VdcBias1.25 V15

CCO100n
VG1 +
DC = 0 V
AC = 1Vpk

Fig. 9.47: Ac Stability Circuit: Output Pin Compensation

The results of our final modified Aol using the Output Pin Compensation technique are shown in this
Fig. 9.48 and match our first-order predictions from Fig. 9.46.
T 120.00
20dB/decade
100.00

80.00
Straight line Approximation
60.00 Final Modified Aol
40dB/decade
Gain (dB)

40.00
20dB/decade
20.00

0.00 40dB/decade
-20.00

-40.00

-60.00
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)

-45

t
-90

ne
-135
Phase [deg]

s.
-180

iu
-225

en
-270

-315

-360
-G
EN
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)

Fig. 9.48: Ac Stability Plots: Output Pin Compensation


on

We will use the circuit of Fig. 9. 49 to run a transient stability test with our final Output Pin
d

Compensation in place.
he

VDIFF 2.50005V Sense -


is
bl

U1INA152
Pu

CX10nF +
+
Ref
RCO150
As

VCC
CCO100nF
VCC
VCC5V

Vdc 2.5V
D C = 0V
Trans ient: RLoad1.8
+ VG1
100m Vpk
1kH z
10ns rise & f all

Fig. 9.49: Transient Stability Test: Output Pin Compensation


Our transient stability results (Fig. 9.50) assure us that we have properly chosen the right compensation
values for the Output Pin Compensation technique on this CMOS RRO difference amplifier.
T 2.63

VDIFF

2.35
100.00m

t
ne
VG1

s.
iu
en
-100.00m

0.00 350.00u 700.00u


-G
Time (s)
EN
Fig. 9.50: Transient Stability Results: Output pin Compensation

TINA circuit of Fig. 9.51 enables confirmation of predicted Vout/Vin transfer function of Fig. 9.46.
on

VDIFF 2.50005V Sense -


d
he

CX10nF U1INA152 +
is

+
RCO150 Ref
bl

VCC
Pu

CCO100nF
VCC
VCC5V
As

Vdc2.5V
RLoad1.8
VG1 +
DC = 0V
AC = 1Vpk

Fig. 9.51: Vout/Vin Ac Response Circuit: Output Pin Compensation

In Fig. 9.52 we see the Vout/Vin ac closed-loop response for our INA152 circuit compensated by the
Output Pin Compensation technique. A comparison with Fig. 9.46 shows predicted response matching
the simulated results with a roll-off in the closed-loop response plot beginning just above 35 kHz.
T 20

-20 Vout/Vin
Gain :
Gain (dB)

VDIFF A:(35.571848k; 1.228223)


-40 Phase :
VDIFF A:(35.571848k; -45.236075)
-60

-80

-100
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz)
fcl
a
0

-45

-90

t
-135
Phase [deg]

ne
-180

-225

s.
-270

iu
-315

en
-360
1 10 100 1k 10k 100k 1M 10M
Frequency(Hz) -G
EN
Fig. 9.52: Vout/Vin Ac Response: Output Pin Compensation
In Figure 9.53 we return to our original CMOS RRO application and add the Output Pin Compensation
on

on the INA152, and close the entire loop to check for stability using our transient stability test.
VDIFF 3.299 971V
d

Sense
-
he

CX10nF U1INA152 +
is

+
Ref
RCO150
bl

k
6 VCC
VFB 3.299 971V0
Pu

7 CF1nF
CCO100nF 5
.
7
5
As

N
T
O M
E
M 1
S
R
R
1 3.299 843V
VOUT
RI10k R
- Iset Imon Iflag

U2OPA569
+ + Ta
lf g RLoad1.8
En
M
Vadjust3.3V 1

100 m Vpk VCC 2


VG1 + VCC5V
1kH z R
10n s rise & f a ll

Fig. 9.53: Programmable Power Supply: Output Pin Compensation


Fig. 9.54 confirms that by fixing the capacitive load instability on the output of the INA152 through
Output Pin Compensation we were able to create a stable programmable power supply.
T 3.45

VDIFF

3.11
3.41

VFB

3.18
100.00m

VG1

-100.00m
3.42

t
ne
VOUT

s.
3.16

iu
0.00 300.00u 600.00u

en
Time (s)

Fig. 9.54: Programmable Power Supply: Transient Stability With Output Pin Compensation
-G
EN
A Word About Tantalum Capacitors

When capacitor values exceed about 1 F, many times Tantalum capacitors are used for their larger
on

values of capacitance in a relatively small size. Tantalum capacitors are not just pure capacitance. They
also have an ESR or resistive component along with smaller parasitic inductances and resistances (Fig.
d

9.55). The most dominant component after their capacitance is their ESR. When using the Output Pin
he

Compensation technique for stability ensure ESR < RCO/10 to guarantee that RCO is the dominant
is

resistance to set the zero in the modified Aol curve.


bl
Pu
As

The Real Tantalum Capacitor

Check ESR < RCO/10

Fig. 9.55: A Word About Tantalum Capacitors And Output Pin Compensation
About the Author

After earning a BSEE from the University of Arizona in 1981, Tim Green has worked as an analog and
mixed-signal board/system level design engineer for over 24 years, including brushless motor control,
aircraft jet engine control, missile systems, power op amps, data acquisition systems and CCD
cameras. Tim's recent experience includes analog & mixed-signal semiconductor strategic marketing.
Currently he is the Linear Applications Engineering Manager for Texas Instruments, Tucson, AZ.

t
ne
s.
iu
en
-G
EN
on
d
he
is
bl
Pu
As

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