752 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO.
4, AUGUST 2002
Diode-Clamped Multilevel Converters: A Practicable
Way to Balance DC-Link Voltages
Mario Marchesoni, Member, IEEE, and Pierluigi Tenca, Member, IEEE
Abstract—The converter topologies identified as diode-clamped
multilevel (DCM) or, equivalently, as multipoint clamped (MPC),
are rarely used in industrial applications, owing to some serious
drawbacks involving mainly the stacked bank of capacitors that
constitutes their multilevel dc link. The balance of the capacitor
voltages is not possible in all operating conditions when the MPC
converter possesses a passive front end. On the other hand, in
ac/dc/ac power conversion, the back-to-back connection of a
multilevel rectifier with a multilevel inverter allows the balance
of the dc-link capacitor voltages and, at the same time, it offers
the power-factor-correction capability at the mains ac input. An
effective balancing strategy suitable for MPC conversion systems
with any number of dc-link capacitors is presented here. The
strategy has been carefully studied to optimize the converter effi-
ciency. The simulation results related to a high-power conversion
system (up to 10 MW) characterized by four intermediate dc-link
capacitors are shown.
Index Terms—High-power drives, medium-voltage drives,
multipoint-clamped converters, multilevel converters, pulsewidth
modulation.
I. INTRODUCTION
T HE converters named diode-clamped multilevel (DCM)
or, equivalently, multipoint clamped (MPC), appeared
in the technical literature in 1991 [1], [2]. Their intermediate
dc link has a total voltage and is composed of
stacked capacitors whose accessible terminals make available
in total phase voltage levels characterized by the values
. The well-known neutral-point-clamped
(NPC) structure [3] could be thought of as the simplest special
case of this one when . Since 1991, many studies have
been proposed [4]–[13], but the MPC structure has been
investigated mainly by academic researchers and it does not
seem attractive for the industry. This can be imputed to two
main reasons. The first is the complexity of the structure, which
has not been carefully investigated as far as all the necessary
aspects for its practical realization in the high-power industry.
The second reason concerns the difficulty to balance the dc-link
capacitor voltages and constitutes the topic of this paper from
now onward. If a single conversion stage, dc/ac or ac/dc, is
used, the voltages balance in all the operating conditions is
Manuscript received August 20, 2001; revised December 30, 2001. Abstract
published on the Internet May 16, 2002.
M. Marchesoni is with the Dipartimento di Ingegneria Elettrica, Università
degli Studi di Genova, 16145 Genoa, Italy (e-mail: marchesoni@die.unige.it).
P. Tenca was with the Dipartimento di Ingegneria Elettrica, Univer-
sità degli Studi di Genova, 16145 Genoa, Italy. He is now with Siemens
AG Transportation Systems, 91052 Erlangen, Germany (e-mail: pier-
luigi.tenca@siemens.com).
Publisher Item Identifier 10.1109/TIE.2002.801237.
0278-0046/02$17.00 © 2002 IEEE
not possible without using additional passive and/or active
components. This issue has been discussed in some papers [4],
[6], [11] and the theoretical/practical limits are reported in [14],
as functions of the converter modulation index and the load fun-
damental displacement power factor. On the other hand, when
an ac/dc/ac conversion is needed, two ac/dc MPC structures can
be usefully employed in a back-to-back configuration, where
one acts as rectifier and the other as inverter [8], [9]. Fig. 1
shows the case for . The idea is that the interconnection
of an MPC rectifier and an MPC inverter might lead to a natural
compensation of the capacitor-voltage unbalancing tendency
which is otherwise observed (with opposite signs) when the
inverter and rectifier are operated separately. However, in the
technical literature, it has not been pointed out adequately that
correct voltage sharing is really only possible when a suitable
modulation strategy, which exploits the redundant switching
configurations [4], is adopted. In [7], [9], and [10] this problem
is also not faced, because quasi-square voltage waveforms are
produced by the conversion systems and a different concept
of balance is achieved. Dealing with pulsewidth-modulation
(PWM)-controlled systems and redundant switching configu-
rations, an interesting study is reported in [8] where, however,
balancing strategies are not deeply discussed. No papers
concerning the additional problems caused by the exploitation
of redundant switching configurations are known. The great
advantage brought by all the modulation strategies based
on redundancy is the avoidance of additional hardware, but,
unfortunately, the drawback is the switching losses increment
which is especially undesired in high-power applications. In
this paper, an MPC ac/dc/ac converter structure, with any
number of dc-link capacitors, is studied. In particular, an
optimized balancing strategy that minimizes power losses
is illustrated and some results related to a 10-MVA ac/dc/ac
converter system with four dc-link capacitors are shown. Using
a four-quadrant active rectifier on the mains side implies higher
costs. A passive rectifier (excluding the additional components
required for the voltage balance) which supplies the same
inverter stage, costs about 35% less with respect to the active
rectifier. The additional components lead to a 5%–10% cost
increase for the considered passive rectifier. However, other
advantages should be considered when using an active front
end. Firstly, the resulting MPC ac/dc/ac converter system is
intrinsically capable of bidirectional energy conversion, when
the operating conditions allow it. This property is straightfor-
wardly deducible by looking at the topology structure and the
type of switches used in it. About this subject, a more detailed
analysis for a bidirectional NPC system is reported in [15].
Then, additionally, this conversion structure is able to draw
MARCHESONI AND TENCA: DIODE-CLAMPED MULTILEVEL CONVERTERS 753

Fig. 1. AC/DC/AC MPC topology with four dc-link capacitors.

Fig. 2. Generalized dc-link capacitor bank model.

almost sinusoidal phase currents from the mains, with almost of the sinusoidal voltage source , characterized by
zero reactive power demand. the amplitude and frequency , together with its
series inductance and resistance, named and ,
respectively. The mains phase current is defined with the
II. AC/DC/AC MPC CONVERTER STRUCTURE IS NOT
reference direction shown in Fig. 2 and its fundamental phase
SELF-STABILIZING
displacement with respect to is maintained at the
The potential performance and limitations of using standard desired value (often is ) by the power-factor-correction
PWM modulation strategies, at both sides of the capacitors (PFC) control subsystem. The bank capacitors all have the same
bank in MPC ac/dc/ac converters, are investigated here by capacitance and share the total dc-link voltage equally. As
computing the average current flowing into each capacitor as a is well known, the networks of switches present at both ends of
function of its position in the bank. A suitable model for MPC the capacitors bank are functionally equivalent to a set of taps,
converters has been purposely developed and Fig. 2 shows its one for each phase, independently movable along the whole
characteristic quantities, some of which are marked with the bank. When these taps are controlled by a standard multilevel
subscripts rec or inv in order to point out their belonging to the PWM modulator, all is equivalent as they move symmetrically
rectifier or inverter side, respectively. A -phase -connected around the bank middle point , and the effects of each phase
symmetrical mains and a -phase -connected equilibrated involved in the analysis are equivalent to those of a fictitious
linear load are assumed, making it possible to consider in the bipole, whose first terminal is one of the aforementioned
reasoning only one phase at both converter ends, as Fig. 2 moving taps and the other terminal is permanently connected
shows. The linear load at the inverter end is represented by a in O. The two voltages, and , synthesized at the
per-phase impedance having modulus and phase angle . two capacitors bank ends by the standard multilevel PWM
Its phase current is referred to the direction depicted modulators, are characterized by fundamental sinusoids of pe-
in Fig. 2. The mains phase at the rectifier end is composed riods and ( rational) and by phase
754 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

modulation indexes and ( , ), so side in . Furthermore, both of these two average currents
that their peak values are and , can be imagined as the sums of the infinite others, injected or
respectively. Due to the necessary presence of the mains extracted in the bank by the phase movable taps when they
impedance the voltage differs from are connected at the bank voltage levels above the point ,
, then, in order to achieve the desired phase displacement during their sliding movement along the bank. Despite the
between and , this last current must have infinite number of such voltage levels, the aforementioned total
a phase displacement , with respect to . average currents and can be computed
Fig. 2 shows the vectors corresponding to these sinusoidal straightforwardly because each phase current—i.e., or
quantities indicated with a dot. The angle is straightforwardly —gives its contribution to the average when, and only
computable from the knowledge of , , , when, the correspondent phase movable tap is present above
and the fundamental amplitude of which, in turn, can , i.e., connected to voltage levels higher than that of the
be derived from the equivalence between the average powers capacitor at such position. During this interval of time, which
at both ends of the capacitors bank, when the converter losses is named in the period at the rectifier side
are neglected. The proposed model associates a fictitious geo- and in the period at the inverter side, the
metrical length to the whole capacitors electrical charges and expressed by (3) and
bank, in order to create a set of one-to-one correspondences (4) are injected in the bank by or extracted from it by
between the positions of the capacitors and/or of the movable , respectively. It follows that the averages and
taps with suitably defined abscissas, which can then be used can be computed by the relationship (5) and (6)
to parameterize geometrically the interesting quantities. The leading, after some steps, to the current —the final goal
existence of a one-to-one correspondence between two quan- of the analysis—as reported in expression (7) which is valid
tities is indicated by the symbol “ ” in Fig. 2. The abscissa when the average powers at the two bank sides equate. The
, whose origin is conventionally located at the bank upper detailed steps to reach (7) can be found in [17]
end (point ), parameterizes the capacitor position along the
bank and, in turn, the capacitor average current which is (1)
the ultimate goal of this analysis. Following these assumptions
is and the bank middle point is located at (2)
distance from . The positions of the two-phase movable
taps, one at the rectifier and the other at the inverter side, are
parameterized by the abscissas and , (3)
respectively. Their origins are both in leading to ,
. Various standard multilevel PWM
modulation schemes exist [16], whose groups of triangular (4)
carriers differ for the mutual phase displacements between
the carriers, but, despite these differences, previous work has
shown the same diverging behavior of the capacitors voltages. (5)
The aim of this model and analysis is to obtain a general
result describing intrinsic properties of this topology and (6)
independent from the specific group of triangular waveforms
chosen. To achieve such goal, it is necessary to overcome the The case implies regardless
otherwise necessary analytical determination of the intersection of the others parameters confirming that, when equal modu-
instants between a chosen group of triangular carriers and the lation indexes are used, the voltage balance in ac/dc/ac MPC
modulating waveform. The model fulfills these requirements converters is possible for every load because every capacitor
by assuming an infinite number of equal bank capacitors then, along the bank has its average current equal to zero. On the
consequently, the total dc-link voltage is the sum of the other hand, when and does
infinite and uniformly distributed contributions represented by not vanish identically to zero, showing that there are some seg-
their voltages. The voltage of a capacitor lying in a specific ments in the bank where capacitors are charging due to a pos-
position in the bank is in one-to-one correspondence with the itive average current and other segments where the capacitors
abscissa , now free to assume continuous real values. Under are discharging because of their negative average current. To
the hypothesis of infinite capacitors, and are give an example, Fig. 3 shows the plot of the function (7)—i.e.,
also continuous valued and their one-to-one correspondences the average current in the bank capacitor as function of
with the voltages and can be expressed by its position along the bank—with the following set of parame-
relationships (1) and (2), respectively. The average current ters: m (purely conventional value); kV;
of the capacitor located at the position , ( , defined in ; ; ; and .A
principle over the generalized period ) is the three-phase load with these parameters draws an average power
difference between the total average current entering of 10 MW. Fig. 3 clearly shows that the capacitor voltages di-
the bank at the rectifier side inside the segment —i.e., in verges; indeed, those inside the interval have negative av-
the whole part of the bank above the position —and the total erage currents, which decrease their voltages, while the oppo-
average current leaving the bank at the inverter site happens to the capacitors located outside . See (7) at
MARCHESONI AND TENCA: DIODE-CLAMPED MULTILEVEL CONVERTERS 755

By substituting the equality constraint (9) inside (8), the new

functional reported in (11) is derived, whose free
variables are organized in the vector defined by (10). It is now
possible to search for the unconstrained minimum of in
where it possesses derivatives of any order
(10)

(11)

The expansion of (11), as reported in expression (12), leads

straightforwardly to the computation of the gradient vector for
the functional reported in (13)
Fig. 3. Average capacitor current as a function of the capacitor position in the
bank.
the bottom of the page. The analysis of reported in (7)
evidences that, in practice, it is generally not possible to reach
a perfect capacitor voltage balance by using a simple standard (12)
multilevel PWM modulation scheme, when different modula-
tion indexes are present at the two converter ends. Therefore, in
general, more complex modulation strategies are needed when
, even though this type of AC/DC/AC converter (13)
appears to have an intrinsic balance capability at first glance.
In order to find the possible stationary points of the derivable
III. A PROPERTY OF THE CAPACITORS BANK ENERGY USEFUL functional , it is necessary to examine where all the el-
IN DEFINING A BALANCING STRATEGY ements of the gradient vector (13) become nullified by equating,
independently from each other, all relationships in (13)
The authors want to prove here that the total energy of a
to zero. Doing so and moving the constant terms to the
capacitors bank, composed of equal capacitances and char-
right-hand side as (14) shows, it is possible to observe that all el-
acterized by a constant total dc-link voltage assumes its
ements of the gradient vector can vanish to zero when and only
constrained minimum exactly when all capacitor voltages are
when relationship (15) applies
equal, i.e., balanced. The total energy of the -capacitors bank
depends on the capacitor voltages only, as
expressed by (8), and it represents the functional, of such vari-
ables (i.e., ) in , whose minimum has to be found under
the equality constraint represented by (9)
(14)
(8)

(9)
(15)

for for

for for
where

(7)
756 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

Expression (15) can be reduced to (16). Then, by recalling (13), the standard PWM modulation strategy, which, in general, does
(17) can be finally derived not have a balancing capability as proven previously. In order
(16) to achieve such requirement without any additional hardware,
the optimal controller can exploit only the redundant switching
(17) states, eventually available at both converter ends, which guar-
Expression (17) proves that the only stationary point is defined antee the same line-to-line voltages of the standard PWM ones.
by the equivalence among all capacitor voltages. This point cor- The proposed balancing control strategy minimizes at every
responds to the unique absolute extreme of which is a min- time step the goal function (20) by choosing online, among
imum, as the computation of the by Hessian matrix of the redundant switching states available in this time step, the
reported in (18) proves. Following the reasoning and proof one giving the minimum value to the goal function derivative
given here, the minimum , assumed by the total energy (21). If such a minimum value of the derivative is negative,
, is written in (19) the goal function (20) is driven toward its absolute minimum
in this time step, that is, the converter is driven toward the
capacitor voltages balance. When the operating conditions of
the whole conversion system are such that the derivative (21)
(18) is negative for most of the time (i.e., for most of the controller
.. .. .. .. ..
. . . . . time steps), the goal function (20) converges toward its absolute
minimum and the balance of the capacitor voltages is achieved.
The derivative of the goal function is the only necessary
(19)
quantity to be computed by the optimal controller, which can
be realized in practice by common digital signal processor
IV. BALANCING STRATEGY BASED ON THE (DSP) subsystems, for example. Multiplying expression (21)
MINIMUM-ENERGY PROPERTY by the positive-valued capacitance , it is straightforward to
The most interesting aspect in the previously illustrated obtain the quantity reported in (22), which is proportional
property of is that the energy assumes its minimum to the derivative (21) but much more suitable to be directly
exactly when all capacitor voltages are in the condi- computed by the real controller. Indeed, in expression (22),
tion requested for the proper operation of the MPC ac/dc/ac only the capacitor currents and the capacitor voltages
converters, i.e., when they are balanced. This, together with appear. The capacitor voltages can be directly measured
the appliable operative methodology of reaching this bal- but their currents do not need any direct measurement; indeed,
anced-voltages condition by minimizing a proper functional, they can be easily evaluated by the measure of the mains and
makes the illustrated minimum-energy property very suitable load phase currents only, with the additional knowledge of the
to be used as the basic principle for an optimal controller. Such instantaneous phase movable taps positions
optimal controller should try to minimize online its goal func-
tion , thus achieving asymptotically the desired capacitor (22)
voltages balance. In order to implement an easier controller,
it is better to provide a positive-definite goal function whose
effects are equivalent to those of , but possessing zero as the
absolute minimum value, instead of reported in (19). It
should be noted that the capacitor voltages are (23)
time dependent because they evolve dynamically toward their
balance, making and any equivalent goal function ultimately Depending on the possible different positions of the phase mov-
time dependent as well. The authors chose as a goal function for able taps, the values of the currents may be very
the optimal controller the one reported in (20), which derives different, even for the same values of the instantaneous mains
directly from expressed in (8) after a linear substition of and load phase currents. Exactly this dependence of from the
variables. The positive scale factor can be neglected positions of the phase movable taps, which differ from one avail-
because it does not affect the control strategy principle. The able redundant switching state to another, creates the hidden de-
goal function is a positive-definite quadratic form that pendence of (22) from such redundancies and allows the optimal
reduces to zero only at the point , and its controller to operate effectively following the minimum-energy
total time derivative is reported in (21) principle previously explained. The necessary electrical quanti-
ties to be measured for the proper operation of the optimal con-
(20) troller for the capacitors voltages balance are, then, capacitor
voltages, independent mains phase currents, and in-
dependent load phase currents.
(21) As an index aimed to quantify the process of convergence of
the capacitor voltages toward the balance, it is useful to use the
The balancing modulation strategy must preserve the moving time average of the scaled derivative (22). This quantity
line-to-line voltages, synthesized at the rectifier and in- called is defined in (23) for and it converges to the
verter sides of the capacitors bank, equal to those deriving from constant average value of (22) for .
MARCHESONI AND TENCA: DIODE-CLAMPED MULTILEVEL CONVERTERS
Fig. 4. Block diagram illustrating the principle of the MPC converter control system.
V. APPLICATION OF THE BALANCING STRATEGY TO AN MPC
CONVERTER: FIRST RESULTS
In order to test the devised balancing strategy, a dynamic
model of the MPC ac/dc/ac conversion system and its related
control system have been developed. The block diagram
showing the main functional blocks in which such control
system can be subdivided and the interactions among them are
represented in Fig. 4, where, in principle, two nested control
loops are present. The inner one is constituted by the optimal
controller for the capacitor voltages balance, which operates
following the balancing strategy described in Section IV. Its
key inputs are the electrical quantities
listed before and the phase movable tap positions, as
they would be imposed by the standard PWM modulators [16].
Additionally, other quantities (minlev, maxlev, maxdif), devoted
to the reduction of the switching losses, can act on the controller
optimum decision, as will be explained in Sections VI–VIII.
The outputs of the optimal controller for the capacitor voltages
balance are two positional offsets, one to be added to all
standard phase tap positions at the rectifier side and the other
to all the standard phase tap positions at the inverter side.
The phase movable tap positions, resulting from these sums,
define the two optimum redundant switching states, one for
each side of the capacitors bank. Each optimum redundant
switching state preserves the line-to-line voltages, because the
related offset is added to all standard tap positions belonging
to its side. This is equivalent to a rigid displacement of the
taps along the capacitor bank that preserves the differences
between the bank voltage levels to which such taps are con-
nected. The outer loop of the control system has its main block
constituted by the PFC controller, which assures that the phase
displacement between and is the desired angle
757
(often is ). The PFC controller computes the necessary
phase voltages to be synthesized at the rectifier side of the
capacitors bank from the knowledge of the mains voltages,
mains series impedance, and the estimation of the necessary
amplitude of the phase mains current. This estimation involves
a first term derived from the equivalence between the average
powers at the two bank sides and a second corrective term,
dependent on the error between the reference and actual total
bank energy. The aim of such correction is to compensate the
uncertainty about the converter losses. To improve the system
dynamics, an additional set of corrective voltages, based on a
current-tracking action of the mains phase currents, is added
to the phase voltages computed by the PFC controller. The
well-known third harmonic contribution is added to all the
sinusoidal reference phase voltages at both converter sides,
before being synthesized by the respective standard PWM
modulators. This technique allows the synthesized line-to-line
voltages to fully exploit the dc-link voltage by increasing the
phase modulation indexes up to the value . The
inverter-side phase modulation index is a key input of the
control system because it defines the desired amplitude of the
load phase voltages. On the other hand, the rectifier-side phase
modulation index cannot be independently imposed, but
its correct value derives from the average power balance and
PFC actions performed by the outer control loop.
The values of the main parameters defining the investigated
converter are briefly listed as follows and some significant re-
sults are illustrated by Figs. 5–9:
• number of dc-link capacitors: 4, with total dc-link voltage
V;
• fundamental frequency of the three-phase systems at both
converter ends: 50 Hz;
758 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

Fig. 5. Four dc-link capacitor voltages balanced by the strategy. (a)m = Fig. 7. Expression (22) together with its moving average (23) for (a), (b)
1:1. (b) m = 0:8. m = 1:1 and (c), (d) m = 0:8 [V 1 A versus s axis].

load for which the capacitor voltages balance is most difficult,

as was confirmed by the analysis in Section II. Additionally,
due to the chosen value for which is close to ,
the modulation index is always very high in this converter,
leading to operating conditions where the global availability of
redundant switching states for both bank sides is far more crit-
ical. The PFC capability of the whole control system is illus-
trated by Fig. 6, where the mains phase-a voltage and current
are displayed. Fig. 7(a) and (c) shows the scaled derivative (22)
of the goal function, which is computed online by the optimal
controller, with the two previously used values and
, respectively. Fig. 7(b) and (d) shows the corre-
sponding previously defined in (23). From Fig. 7(b) and
(d), it appears that is negative for both chosen values of
. This proves that, for the most part of the system evolution,
the goal function (20) decreases its value going toward its ab-
solute minimum or, which is the same, the proposed strategy is
effective in achieving the capacitor voltage balance even at high
values of the phase modulation indexes. Figs. 8 and 9 show how
Fig. 6. Mains phase-a voltage and current.
the switching sequences of the rectifier-side phase-b movable
tap and of the inverter-side phase-b movable tap, respectively,
• m , mH, V; are developed by the optimal controller operating with the min-
• capacitance of every dc-link capacitor: mF; imum-energy balancing strategy. They are compared with the
• frequency of the triangular carriers used by both standard sequences developed by the standard PWM modulators which
PWM modulators: 1050 Hz; are indicated by thicker lines in the same figures. The results
• three-phase -connected load with and evidenced in these figures are characterized by the value 0.3 of
at 50 Hz. the inverter-side modulation index . The authors chose this
Fig. 5 shows the transient behavior of the four dc-link ca- value in order to make available several redundant switching
pacitor voltages and the correct balanced value reached (2 kV) states at this side of the capacitors bank and, consequently, to
in steady state, when the estimation of the mains phase current better highlight the difference between the optimal controller ac-
amplitude starts with a zero value. The upper graph in Fig. 5 is tion in comparison with the standard PWM one, as Fig. 9 clearly
related to the case when the high value 1.1 for is used, shows. As has been explained before, the rectifier-side modula-
while the lower one is related to the case . It is tion index always assumes high values with consequently less
worth observing the increased difficulty in achieving the capac- redundant switching states available at this side. Indeed, Fig. 8
itor voltage balance when assumes high values. This is due shows that the switching sequences developed by the two mod-
to the fact that, the higher the phase modulation index, the fewer ulation strategies are more similar here. However, Figs. 8 and 9
redundant switching states are available for the balancing action. also demonstrate the main drawback of the balancing strategies
The minimum-energy-based balancing strategy has been tested based on the exploitation of the redundant switching states only,
with an almost purely resistive load because this is the type of that is, the increasing of the semiconductor switching losses
MARCHESONI AND TENCA: DIODE-CLAMPED MULTILEVEL CONVERTERS
Fig. 8. Switching sequences of the rectifier-side phase-b movable tap position developed by the standard PWM modulator (thicker lines) and the minimum-energy
m
modulation strategy (thinner lines) ( = 0.3).
Fig. 9. Switching sequences of the inverter-side phase-b movable tap position developed by the standard PWM modulator (thicker lines) and the minimum-energy
m
modulation strategy (thinner lines) ( = 0.3).
and dynamical stresses. In standard multilevel PWM [16], every
phase movable tap experiences only commutations among adja-
cent levels of the capacitors bank. Conversely, the use of redun-
dant switching configurations implies variations, wider than one
single level, in the positions of the movable taps and, therefore,
also in the synthesized phase voltages. In addition, the six phase
terminals must switch between different taps with a greater fre-
quency than that related to the standard PWM. Indeed, the need
to follow the modulation pattern that guarantees the correct ca-
pacitors voltage balance requires, in general, simultaneous com-
mutations of more than one terminal during every switching
event imposed by the line-to-line voltages synthesis. The com-
bination of these two effects may lead to an effective switching
frequency of semiconductor devices several times greater than
the switching frequency peculiar to standard PWM.
759
VI. MODIFICATION OF THE BASIC STRATEGY TO REDUCE THE
ADDITIONAL SWITCHING LOSSES
The pure strategy proposed in Section IV and tested in
Section V does not try to reduce the number of commutations
of the semiconductor switches, but, at every time step of the
optimal controller, it is devoted only to search for the best
possible switching state that guarantees the maximum tendency
toward the capacitor voltages balance by giving the minimum
possible value to the scaled derivative (22). For this reason,
it will be named in the following as total-balancing strategy.
A suboptimal balancing strategy has been carefully studied,
which takes care of the previously highlighted issue about the
switching losses reduction. The proposed suboptimal strategy
still prioritizes the choice of a redundant switching state
760 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002
that makes (22) negative when possible. However, instead of
selecting the one that minimizes (22), this modified criterion
picks out the redundant switching state which reduces the
necessary number of commutations in the change from the
previous one. By choosing so, the bank energy is still driven
toward its minimum, but such evolution usually takes longer
than using the total-balancing strategy which always selects
the redundant switching states assuring the most negative value
of (22), when it exists. This is the key difference between the
total-balancing strategy and this suboptimal one, which will
be named as the commutation-saving strategy in the following.
The minimization of the total number of commutations in the
whole conversion system is equivalent to minimize the sum
of all the amplitudes of the “jumps” performed by the phase
movable taps, between different voltage levels of the capacitors
bank. Indeed, the wider that a “jump” is between two time-con-
secutive voltage levels that a load or line phase movable tap
must undertake under the controller action, the more elements
in the MPC network of semiconductor switches must commute,
in order to realize this desired phase voltage level change,
equivalent to the displacement of the fictitious movable tap.
Obviously, the action performed by the commutation-saving
strategy is a suboptimal compromise, because choosing to
reduce the total sum of “jumps” amplitudes, the “effectiveness”
of the capacitor voltages balancing action may be decreased in
comparison with the total-balancing strategy.
VII. OPTIMAL COMBINED STRATEGY TO ACHIEVE VOLTAGES
BALANCE AND REDUCED COMMUTATIONS
The total-balancing strategy and the commutation-saving
strategy are clearly mutually exclusive in the same instant,
but they can be combined in different instants to optimize the
converter behavior. In Section II, it has been proved that the
standard PWM strategy is not able to guarantee the correct
capacitor voltages balance, except for some rare cases. How-
ever, on the other hand, as was anticipated before, the standard
PWM strategy is characterized by the minimum number of
commutations, a property that makes it also a good reference
to judge other strategies about such aspect. Following these
considerations, the synonym minimum-commutation strategy
will be used for the standard PWM strategy from now onwards
and, if allowed by the actual values of the capacitor voltages,
it can be combined with the other two balancing strategies in
order to achieve a further reduction in the number of com-
mutations. The optimal combination of these three strategies,
which is called “actual criterion” in Figs. 10–12, has been
obtained by introducing two thresholds named maxlev and
minlev (maxlev minlev 0) as Fig. 4 schematically shows.
In every time step of the optimal controller operation, such
thresholds affect the decision policy about what is the capac-
itor voltages balance strategy to be actually used (from this
comes the adjective “actual”). The values of these thresholds
represent the maximum tolerated percentage deviations of the
capacitor voltages from the balanced voltage , beyond
which the optimal controller switches to a different balancing
strategy. The optimal controller decides, at every time step
characterizing its operation, the intensity and effectiveness
of the balancing action, by comparing these thresholds with
the quantity maxdif, which is defined as the maximum among
all the quantities: . If maxdif
exceeds the greatest threshold, maxlev, the total-balancing
strategy is used. This choice is justified by the fact that keeping
the capacitor voltages inside the desired range of values, around
, is always the highest priority task for the inner control
loop constituted by the optimal controller for the capacitor
voltages balance. If maxdif is comprised between maxlev and
the smallest minlev, the commutation-saving strategy is used,
because, despite the need of a balancing action, the capacitor
voltages values do not differ so much to require the strongest
intervention. This makes it possible to consider the aspect of
the reduction of the number of commutations. Furthermore, if
the value of maxdif is even below the smallest threshold minlev,
the capacitor voltages in this instant are so acceptably close
to that no balancing action is really required. In this
case, all the attention is devoted to reduce the total sum of the
“jumps” amplitudes by employing the minimum-commutation
strategy (i.e., standard PWM strategy) only.
VIII. FINAL RESULTS
In this section, the behavior and the performance of an
ac/dc/ac MPC conversion system, under the aforementioned
combined action of the proposed control strategies, are pre-
sented. Several simulation results, which have been obtained
considering the two strongly opposite load operating conditions
a) and b) summarized in Table I, are shown and commented
upon. A high-power experimental setup is planned to test the
strategy in practice, but the realization time still precludes the
possibility of including experimental results in this paper.
A. Features of the Chosen Operating Conditions
The load operating condition a) of Table I is typical of an al-
most resistive three-phase star-connected load drawing a great
average power from the converter due to the high value of the
desired phase modulation index . Such operating condition
is typical of a situation where the capacitor voltages balance is
difficult to achieve, because the load is virtually resistive and the
inverter modulation index is close to its upper limit, leaving so
few possible redundant switching states available for the syn-
thesis of the line-to-line voltages [4]. The load condition b) is
typical of an almost purely reactive, three-phase star-connected
load, drawing a small average power from the converter also
due to the low value of This operating condition is typ-
ical of a situation where the capacitor voltages balance is easily
achievable because the load is virtually reactive and addition-
ally, the small modulation index allows a wide choice among
many possible redundant switching states. It is also interesting
to examine the capability of the overall control system about
the steady-state recovery when abrupt step changes, between the
load-side operating conditions a) and b), are imposed. Such ca-
pability is evaluated by observing the time needed to recover the
steady state and the deviations of the capacitor voltages from the
ideal value (2000 V), both in transient and when the steady state
is reached again.
B. Use of the Total-Balancing Strategy Only
The results obtained always using only the total-balancing
strategy are presented here. This decisional behavior of the op-
MARCHESONI AND TENCA: DIODE-CLAMPED MULTILEVEL CONVERTERS 761

(a)

(b)

(c)

(d)
Fig. 10. Total-balancing strategy. (a) Four dc-link capacitor voltages. (b) Four dc-link capacitor voltages on enlarged voltage scale. (c) Cumulative sums of the
jumps amplitudes for a line-side rectifier phase terminal. (d) Cumulative sums of the jumps amplitudes for a load-side inverter phase terminal.

timal controller for the capacitor voltages balance is straight- Fig. 10(a) shows the four bank capacitor voltages with the step
forwardly obtainable by setting . change from operating conditions a) to b) imposed at the time
762 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002

(a)

(b)

(c)

(d)
Fig. 11. Commutation-saving strategy ( minlev = 0% maxlev = 5%
, ). (a) Four dc-link capacitor voltages. (b) Four dc-link capacitor voltages on enlarged
voltage scale. (c) Cumulative sums of the jumps amplitudes for a line-side rectifier phase terminal. (d) Cumulative sums of the jumps amplitudes for a load-side
inverter phase terminal.

instant s. The good potential of the total-balancing ages are very close to the ideal value of 2000 V even when the
strategy emerges by observing that all the four capacitor volt- converter supplies the most critical load for the voltages bal-
MARCHESONI AND TENCA: DIODE-CLAMPED MULTILEVEL CONVERTERS 763

(a)

(b)

(c)

(d)
Fig. 12. Commutation-saving strategy ( minlev = 5% maxlev = 10%
, ). (a) Four dc-link capacitor voltages. (b) Four dc-link capacitor voltages on enlarged
voltage scale. (c) Cumulative sums of the jumps amplitudes for a line-side rectifier phase terminal. (d) Cumulative sums of the jumps amplitudes for a load-side
inverter phase terminal.

ance [operating condition a)]. Fig. 10(a) also shows the over- lease. How fast the steady-state conditions are recovered, can
shoots of the capacitor voltages due to the aforementioned step be better appreciated by observing Fig. 10(b). There, the ca-
change, which has effects similar to those typical of a load re- pacitor voltages magnified around 2000 V outrun the borders
764 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 49, NO. 4, AUGUST 2002
TABLE I
TWO LOAD OPERATING CONDITIONS USED TO TEST THE COMBINED ACTION OF THE STRATEGIES
of the plane strip comprised between 95%–105% of 2000 V
(symmetrical excursion of 5% around the ideal value) only for
a very short time not exceeding 6 ms. It was stated before that
using the total-balancing strategy, only, leads to the strongest
possible balancing action, but without any care to reduce the
total sum of the amplitudes of the phase-terminals jumps. It ap-
pears interesting to compare such total sum, which is necessary
to achieve such an effective voltages balance in this case, with
the total sum that would be otherwise required by employing the
minimum-commutation strategy (i.e., standard PWM strategy).
Fig. 10(c) and (d) shows the cumulative total sums of the afore-
mentioned amplitudes for a rectifier-side phase terminal and for
an inverter-side phase terminal, respectively. In these graphs, the
cumulative total sums are measured in “voltage-level” units, so
that a jump, whose amplitude is one voltage level, possesses
the value 1. The cumulative total sums have been obtained by
adding all the absolute values of the amplitudes of the jumps,
which were computed from zero to the actual time instant. From
the definition and use of these quantities, it follows straight-
forwardly that the slower they increase, the smaller is the total
number of the commutations and, consequently, the higher is
the converter efficiency. Fig. 10(c) and (d) makes evident that,
using the total-balancing strategy, both the rectifier-side and in-
verter-side phase terminals have the sums of the jump ampli-
tudes greater than those arising from the use of the standard
PWM strategy. The slopes of the traces are clearly proportional
to the converter switching losses, which, in some cases, may
have a strong increment.
C. Commutation-Saving Strategy and Use of All the Strategies
Combined Together
This section presents the results obtained using the commu-
tation-saving strategy when it is combined with the other two
strategies following the criteria explained in Section VII. The
plots in Fig. 11 show the same quantities explained before, but
obtained when and . The choice
of this couple of values implies that the inner control loop uses
only the commutation-saving strategy and the total-balancing
strategy; indeed, due to the zero value assigned to the smallest
threshold, the minimum-commutation strategy is never used. In
particular, Fig. 11(a) shows the four capacitor voltages when the
step change, from operating conditions a) to b) of Table I, hap-
pens at s and, subsequently, a further step change,
from operating conditions b) to a), happens at s.
Fig. 11(b) shows the capacitor voltages magnified around to the
ideal value of 2000 V, together with the plane strip whose bor-
ders are constituted by the two lines drawn at 95% and 105%
of 2000 V. Observing both these figures, but mainly Fig. 11(b),
it appears evident that the capacitor voltages are more spread
around the ideal value than in Fig. 10(b); this is because the bal-
ancing action performed by the inner control loop in the whole
time is weaker than the case when the total-balancing strategy
only is used. Anyway, the overall voltage balance is still main-
tained and the introduction of the commutation-saving strategy
has a positive impact on the cumulative total sums of the jump
amplitudes. The plots shown in Fig. 11(c) and (d) prove that set-
ting the greatest threshold to the value 5%, consequently using
the commutation-saving strategy for the most part of the time,
could lead to a great improvement in the converter efficiency.
Finally, the graphs in Fig. 12 show the results obtained using
all the three strategies previously referred to combined together.
The value 5% is assigned to the smallest threshold, minlev, and
the value 10% to the greatest one, maxlev, therefore also al-
lowing the use of the minimum-commutation strategy (i.e., stan-
dard PWM strategy). Fig. 12(a) shows the four capacitor volt-
ages when the step change from operating condition a) to b) has
been imposed at s followed by another step change,
from operating conditions b) to a), at s. The plots in
Fig. 12(b) show the usual magnification of the capacitor volt-
ages around 2000 V, together with the two plane strips extended
from 5 to 5 and from 10 to 10 of 2000 V, re-
spectively. From both Fig. 12(a) and (b), it can be appreciated
how much the capacitor voltages are kept bounded, even if the
balancing action is weaker than in the two previous cases. With
the capacitor voltages balance still maintained, the combined
presence of the commutation-saving strategy and of the min-
imum-commutation strategy greatly improves the converter ef-
ficiency as the graphs in Fig. 12(c) and (d) prove. The effec-
tiveness of the combined use of these three strategies from the
commutations reduction point of view is particularly remark-
able at the inverter side of the converter. Obviously, the choice
of the threshold values must be done considering the desired
right tradeoff between the effectiveness of the balancing action
and the converter efficiency, which are two aspects always char-
acterized by opposite exigencies.
IX. CONCLUSIONS
Can ac/dc/ac MPC converter topologies be used without any
additional hardware devoted to achieving the capacitor voltages
balance? The increase in converter losses and semiconductor
dynamical stresses, due to redundancies exploitation, is partic-
ularly undesired in high-power converters, where efficiency, re-
liability, and prevention against catastrophic faults are of pri-
mary concern. In this paper, the minimization of such undesired
effects has been faced and investigated in the implementation
MARCHESONI AND TENCA: DIODE-CLAMPED MULTILEVEL CONVERTERS
of voltage-balancing strategies, based on redundant switching
configurations. The very general strategy presented here derives
from a minimum-energy principle suitable to be implemented
by a DSP-based optimal controller, aimed at the real-time bal-
ance of the capacitor voltages in an ac/dc/ac MPC converter with
any number of dc-link capacitors. The obtained results show
that the total-balancing strategy leads to the strongest possible
balancing action, but at the expenses of the conversion system
efficiency. The commutation-saving strategy brings great prac-
tical improvements to the operation of the whole system, by
remarkably reducing the overall switching losses, while, at the
same time, still guarantees the capacitor voltages balance. The
combined balancing strategy, obtained introducing also the min-
imum-commutation strategy, has proved to be very robust, de-
spite the unavoidable weakening in the balancing action conse-
quent to the reduction of the number of commutations.
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Mario Marchesoni (M’89) was born in Genoa, Italy,
in 1959. He received the M.S. degree (cum laude) in
electrical engineering and the Ph.D. degree in elec-
trical engineering on power electronics from the Uni-
versity of Genoa, Genoa, Italy, in 1986 and 1990, re-
spectively.
Following graduation, he began his research ac-
tivity in the Department of Electrical Engineering,
University of Genoa, where he was an Assistant Pro-
fessor from 1992 to 1995. From 1995 to 2000, he was
with the Department of Electrical and Electronic Engineering, University of
Cagliari, Cagliari, Italy, where he was a Full Professor of Power Industrial Elec-
tronics. In 2000, he rejoined the University of Genoa. His research interests in-
clude power electronics, rotating machinery, and automatic control, particularly
in high-power converters, robotics, and electric propulsion. He is the author or
coauthor of about 100 papers in these fields.
Dr. Marchesoni is a member of the Italian Association of Electrical and
Electronic Engineers (AEI), Italian College of Railway Engineers (CIFI),
and the IEEE Control Systems, IEEE Industry Applications, IEEE Industrial
Electronics, IEEE Power Electronics, and IEEE Power Engineering Societies.
Pierluigi Tenca (S’94–M’97) was born in Genoa,
Italy, in 1971. He received the degree (cum laude)
in electronic engineering and the Ph.D. degree in
electrical engineering on power electronics topics
(design and prototyping of low power/high-fre-
quency dc/dc converters, study of high-power
multilevel topologies) from the University of Genoa,
Genoa, Italy, in 1996 and 2000, respectively.
He spent a part of his Ph.D. course as Visiting Staff
in the Department of Electronic and Electrical Engi-
neering, University of Bath, Bath, U.K., dealing with
high-power voltage-source multilevel converters, which constitute his actual re-
search interests. Since 2000, he has been working as an R&D Engineer with
Siemens AG Transportation Systems, Erlangen, Germany, dealing with high-
power converters and drives for traction applications.
Dr. Tenca received the “Lucio Mayer” prize issued by the “Collegio Ingegneri
Ferroviari Italiani” for his graduation thesis dealing with analytical modeling
of railways electrification systems by time-varying electrical networks. He is
a member of the IEEE Industrial Electronics and IEEE Circuit and Systems
Societies.