ISSCC 2015 / SESSION 11 / SENSORS AND IMAGERS FOR LIFE SCIENCES / 11.
11.6 A Multi-Channel Neural-Recording Amplifier System
with 90dB CMRR Employing CMOS-Inverter-Based
OTAs with CMFB Through Supply Rails in 65nm
CMOS
Chỗ này nghĩa là: trong vài ứng dụng mình cần cái Zin nhỏ
Kian Ann Ng, Yong Ping Xu
National University of Singapore, Singapore, Singapore
In addition to minimizing input-referred noise and lowering power consumption,
a good multi-channel neural amplifier system should be able to significantly
reject common-mode electrical interference (CMI). The dominant source of CMI
comes from capacitive coupling of electrical mains supply line or EMGs onto
neural tissues and can be as high as 100mVpp [1]. Thus any neural recording
setup needs a total common-mode rejection ratio (TCMRR) of at least 70dB for
a minimum detectable neural signal of 5μVrms [1]. However, multi-channel neural
amplifiers are commonly implemented with a shared reference input whose
input impedance is several times lower than that of corresponding signal inputs
[2]. This results in a large mismatch at the bipolar electrode-amplifier input
interface [1]. As analysed in Fig. 11.6.1, the TCMRR is significantly degraded
below 70dB, independent of an amplifier’s intrinsic CMRR (ICMRR). In this
work, we report a micro-power, low-noise 16-channel neural amplifier that
eliminates this impedance mismatch problem by using single-ended CMOS
inverter-based LNAs for both the reference and signal inputs. Compared to
conventional replica channel works [3], when operating at 1V supply, the LNAs
can accommodate a large input CMI of up to 220mVpp through the use of a
common-mode feedback (CMFB) loop implemented through the supply rails of
the CMOS-inverter-based LNAs, which coincidentally leads to a high amplifier
ICMRR. WHY Zin decrease -> CMRR reduce
Figure 11.6.2 shows the circuit architecture of the multi-channel neural
amplifier. In its most basic form, the amplifier system consists of 16
single-ended, capacitively coupled, CMOS-inverter-based LNAs (CCLNA) that
pre-amplify neural signals (I1-I16) with a gain of 21V/V. A replica CCLNA also
pre-amplifies reference input by the same gain. Since identical CCLNAs are used
for both the reference and signal inputs, input impedance mismatch is
eliminated. The CCLNAs outputs are further amplified with respect to the
reference CCLNA’s output by 22V/V through a differential capacitive-coupled
amplifier, G2, resulting in a total gain of 462V/V. A 3b capacitor bank across the
inputs of G2 corrects for gain mismatch between the signal CCLNA and the
reference CCLNA arising from intra-die process variation. At any time instance,
only 4 of the 16 G2 outputs are connected to a corresponding rail-to-rail pad
driver with a tunable high-pass filter response. Here, the OTA within each CCLNA
is based on a CMOS inverter (Fig. 11.6.3) operating as a linear amplifier. With
an operating voltage of 0.65V and a gain of 21V/V, the CCLNA saturates at a low
input CMI of 33mVpp and is therefore unable to accommodate large CMI
amplitudes. To compensate, a CMFB loop similar to that in [4] is implemented
to extend the input AC common-mode range. Why using CMFB -> extend được
In [4], the CMFB signal is fed back to the non-inverting terminals of differential
OTAs, but the single-ended OTA in this work does not have an obvious
non-inverting terminal. However, when driven concurrently, the supply and
ground rails of each CMOS-inverter-based OTA virtually function as a non-invert-
ing terminal that completes the CMFB loop. Hence, in our current approach, the
CMFB signal generated by the circuit depicted in Fig. 11.6.3 is fed back through
the supply (LNAVDD) and ground (LNAVSS) rails of the OTAs. The outputs of
each CCLNA are averaged by the summing circuit formed by A0, C1-16 and Cfb.
The on-chip generated voltage, VLS, sets the DC level of the summing circuit’s
output at 0.14V. R1 and C1 help stabilize the CMFB loop. The output of the
summing circuit, VCFMB is buffered by a unity gain driver formed by A1 and M1
which in turn drives the LNAVSS terminals of all CCLNAs. A corresponding
voltage, intVDD, is generated by passing a fixed current of 2μA through a master
OTA,(MOTA, same OTA used in CCLNA) and this voltage is buffered by a
unity-gain driver formed by A2 and M2 which in turn drives the LNAVDD
terminals of all CCLNAs. The voltage across LNAVDD and LNAVSS is effectively
Why??? fixed to the voltage across the MOTA at (0.65V) regardless of the concurrent
voltage variation on LNAVDD and LNAVSS. This voltage difference (0.65V)
establishes the bias current of the OTAs in all CCLNAs in the signal and reference
channels and makes them closely match the 2μA current flowing through the
MOTA. VCFMB tracks the averaged AC CMI signals on all inputs of the CCLNAs and
the CMFB loop adjusts the LNAVDD and LNAVSS concurrently. This leads to the
CMI signals being attenuated by approximately 17V/V at the output of all
206 • 2015 IEEE International Solid-State Circuits Conference
CCLNAs. This CFMB loop not only reduces the common-mode gain of the
amplifier, allowing an input AC CMI of up to 220mVpp to be applied without
saturating the CCLNAs, but also improves the ICMRR. Voltages VNB and VPB
provide bulk biasing to the OTA’s transistors (MP and MN) and closely track
variations on LNAVDD and LNAVSS respectively. để làm gì? À là khi LNAVDD change
thì VPB cũng change theo
không làm ảnh hưởng đến MP
In Fig. 11.6.3, the complementary transistors of the CMOS-inverter-based OTA,
MN and MP operate in a weak inversion region and both the transistors contribute
to the OTAs transconductance. Thin-gate transistors M3-M6 configure MN and MP
as active cascoded transconductors for high OTA open-loop gain, allowing a
reliable closed-loop gain to be achieved over the neural signal bandwidth. As the
gate leakage current of the thin-gate transistors are high enough to disturb the
DC feedback path created by the pseudo-resistor, MN and MP are implemented
with 2.5V thick gate oxide transistors that have negligible gate leakage currents.
As mentioned earlier, the bulk of MN and MP are respectively biased by VNB and
VPB voltages lowering their Vt and hence allowing regulated supply voltage
across LNAVDD and LNAVSS to be 0.65V. As shown in Fig. 11.6.2, each signal
CCLNA is buffered by a 0.4μA flipped voltage follower (FVF) which then drives
the Vp inputs of G2. The reference CCLNA also drives a pair of FVFs operating in
guard/active configuration. The active FVF drives the Vm inputs of the four
selected G2 amplifiers that are multiplexed to the inputs of the pad drivers. The
guard FVF drives the Vm inputs of all remaining G2s and provides a guard shield K hiểu???
Guard FVF
in a layout that reduces parasitic capacitances on the active FVF output. Both làm gì???
implementations minimise phase delays between the CCLNAs, therefore
preserving a high overall amplifier ICMRR across a higher frequency range.
The fabricated 16-channel amplifier IC occupies an area of 1.44mm2 and Fig.
11.6.7 shows the chip microphotograph. Figure 11.6.4 shows the AC frequency
response, PSRR and input-referred noise performance from one channel of the
overall amplifier. Each active channel equivalently consumes 2.8μA with
input-referred noise of 4.2μVrms within 1Hz to 8.2kHz. Measurements in Fig.
11.6.5 show in the event of a 220mVpp input CMI disturbance, the CMFB loop
instantly drives LNAVDD and LNAVSS to track the CMI disturbance and
suppresses any CMI residue before reaching the amplifier’s output. Figure
11.6.5 also shows ICMRR frequency response of 1 representative channel and
the CMRR of all channels at 106Hz for 3 different settings. The ICMRR for all
channels is above 90dB (up to 1kHz) when the CMFB loop is active with the
mismatch correction capacitor banks activated at G2.
Using the amplifier IC, neural spikes from chronically implanted tungsten
electrodes in the dorsal medial cortex brain region were successfully recorded in
an awake M. fascicularis (Fig. 11.6.6). The neural amplifier’s electrical
performance depicted in Fig. 11.6.6 is also comparable with similar works [2-3],
[5-6]. The techniques in the current work improve the TCMRR of the neural
recording system, extend a neural amplifier’s input CMI range and increases
ICMRR without compromising other performance parameters.
Acknowledgements:
This work is supported by A*Star Singapore (Project:1021520023) and NRF
Singapore (Project:NRFCRP10201201). We thank MediaTek for fabricating this
chip and SiNAPSE(NUS) for facilitating the animal recordings.
References: ĐÁNG ĐỌC
[1] T. Jochum, T. Denison, and P. Wolf, “Integrated Circuit Amplifiers for Multi-
Electrode Intracortical Recording.,” J. Neural Eng., vol. 6, no. 1, p. 012001, Feb.
2009.
[2] K. Abdelhalim, H. M. Jafari, L. Kokarovtseva, J. L. P. Velazquez, and R.
Genov, “64-Channel UWB Wireless Neural Vector Analyzer SoC with a Closed-
Loop Phase Synchrony-Triggered Neurostimulator,” IEEE J. Solid-State Circuits,
vol. 48, no. 10, pp. 2494–2510, Oct. 2013.
[3] C.M. Lopez, A. Andrei, S. Mitra, et al., “An Implantable 455-Active-Electrode
52-Channel CMOS Neural Probe,” ISSCC Dig.Tech. Papers, pp. 288–289, Feb.
2013.
[4] J. Xu, R.F. Yazicioglu, P. Harpe, K.A.A. Makinwa, and C. Van Hoof, “A 160
μW 8-Channel Active Electrode System for EEG Monitoring,” ISSCC Dig.Tech.
Papers, pp. 300–301, Feb. 2011.
[5] V. Majidzadeh, A. Schmid, and Y. Leblebici, “Energy Efficient Low-Noise
Neural Recording Amplifier With Enhanced Noise Efficiency Factor,” IEEE Trans.
Biomed. Circuits Syst., vol. 5, no. 3, pp. 262–271, June 2011.
[6] R. Muller, S. Gambini, and J. M. Rabaey, “A 0.013mm2 5μW DC-Coupled
Neural Signal Acquisition IC with 0.5V Supply,” ISSCC Dig.Tech. Papers, pp.
302–303, Feb. 2011.
978-1-4799-6224-2/15/$31.00 ©2015 IEEE
 ISSCC 2015 / February 24, 2015 / 11:15 AM

Chứng minh công thức này nào ???

Buffer

Figure 11.6.1: The problem of degraded TCMRR due to input impedance Figure 11.6.2: Schematic representation of the multi-channel neural recording
mismatch even though amplifier’s ICMRR is high. amplifier system.

CCLNA
11

Summing circuit

Stabilize CMFB loop Figure 11.6.4: Measured AC response, PSRR (Left) and input-referred noise
PSD plot (Right) of a neural amplifier channel. The amplifier has measured
Figure 11.6.3: CMOS-inverter-based OTA (Left) and the supply-rail based low-pass cut off frequency at 8.2kHz and its high-pass cutoff frequency is
CMFB generator (Right). tunable from 53mHz to 100Hz.

Figure 11.6.5: Transient response of system to sudden CMI disturbance (Top), Figure 11.6.6: In-vivo neural recordings (Top-Left) and time-aligned signals
CMRR of 1 representative channel across frequency (Bottom-Left) and all (Top-Right) from a M. fascicularis with pad-driver’s gain=3V/V. Comparison
channels at 106Hz (Bottom-Right). with state of the art (Bottom).

DIGEST OF TECHNICAL PAPERS • 207

 ISSCC 2015 PAPER CONTINUATIONS

Figure 11.6.7: Die microphotograph of the 16-channel neural amplifier.

• 2015 IEEE International Solid-State Circuits Conference 978-1-4799-6224-2/15/$31.00 ©2015 IEEE