Beruflich Dokumente
Kultur Dokumente
7
Programming by burning the fuses.
Logic gates
Inputs and Outputs
(logic variables) programmable (logic functions)
Switches
Fuse
Number of variables at input and output doesn’t fall into any relationship
Block Diagram of PLA
Inputs
Outputs
12
Programmable Logic Array (PLA) x1 x2 xn
We may need X1, or X1’ and X2, or X2’
x1 x1 xn xn
P1
f1 fm
Gate Level Diagram of PLA
PLA with 3×2
Example :
Full Adder , having three bits as input out of two bits i.e. “SUM” and “CARRY”
14
Gate Level Diagram of PLA
PLA with 3×2 with 4 product terms.
F0 = A + B' C'
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A
Input Side:
1 = asserted in term
0 = negated in term
- = does not participate
PLA Table
Output Side:
Product Inputs Outputs
1 = term connected to output
term A B C F0 F1 F2 F3 0 = no connection to output
AB 1 1 - 0 1 1 0
BC - 0 1 0 0 0 1
AC 1 - 0 0 1 0 0
BC - 0 0 1 0 1 0
A 1 - - 1 0 0 1
17
Question 1: Implement the following using suitable PLA.
A B C
F0 = A + B' C' AB
F1 = A C' + A B
F2 = B' C' + A B
F3 = B' C + A B’C
AC’
PLA table
B’C’
Product Inputs Outputs
term A B C F0 F1 F2 F3 A
AB 1 1 - 0 1 1 0
BC - 0 1 0 0 0 1
AC 1 - 0 0 1 0 0
BC - 0 0 1 0 1 0
A 1 - - 1 0 0 1 F0 F1 F2 F3
18
Question 2: Implement the following using suitable PLA.
f1 = x1x2 + x1x3‘ + x1'x2'x3 f2 = x1x2 + x1'x2'x3 + x1x3
x1 x2 x3
Programmable
connections
OR plane
P1
P2
P3
P4
AND plane
f1 f2
Question 2: Implement the following using suitable PLA.
f1 = x1x2 + x1x3‘ + x1'x2'x3 f2 = x1x2 + x1'x2'x3 + x1x3
x1 x2 x3 x1 x2 x3
Programmable
connections
OR plane
OR plane
P1 P1
P2 P2
P3 P3
P4
P4
Address n 2n x m m Data
inputs ROM outputs
A(n-1, ... , 0) D(m-1, ... , 0)
n=2 m=4
Example: A1 A0 D3 D2 D1 D0
0 0 0 1 0 1 Stores 4 4-bit words, or
0 1 1 1 1 1 stores 4 functions of 2
1 0 0 0 0 1 input variables
1 1 1 0 0 0
Procedure to Implement CC from ROM
• Give the logic implementation of Boolean function: F1(A1,A0 )=(1,2,3) & F2
(A1,A0 =(0,2) using ROM with (AOI) and without inverter.
00
I/P n = 2 O/P m = 2= No of OR Gates
Example: A1 A0 F1 F2 A1 01
0 0 0 1 2 to 4
0 1 1 0 Decoder 10
A0
1 0 1 1
1 1 1 0 11
R3 R2 R1 R0
Inputs Outputs
A2 A1 A0 D3 D2 D1 D0
8 4ROM
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1 I0 A0 D0 Y0
0 1 1 0 1 1 1 I1 A1 D1 Y1
1 0 0 0 0 0 1 POL A2 D2 Y2
1 0 1 0 0 1 0 D3 Y3
1 1 0 0 1 0 0
1 1 1 1 0 0 0
• Read/Write Memory
(Random Access Memory, RAM):
• Types of RAM:
• Static RAM (SRAM)
• Dynamic RAM (DRAM)
• SRAM Timing
• DRAM Timing