CS302 Collection of Old Papers

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FINALTERM EXAMINATION
Total Marks:70
SEMESTER FALL 2004
CS302-Digital Logic Design (S1) Duration:120 Min
Student ID / Login ID
Name
PVC Name / Code
Date
Maximum Time Allowed: (2 Hours)
Please read the following instructions carefully before attempting any of the
questions:
1. Attempt all questions.
2. Calculators are NOT allowed.
3. Do not ask any questions about the contents of this examination from anyone.
a. If you think that there is something wrong with any of the questions,
attempt it to the best of your understanding.
b. If you believe that some essential piece of information is missing, make an
appropriate assumption and use it to solve the problem.
4. Circuit Diagrams, Equations and Truth Tables should be clear.
Write down all the steps in Subjective Questions. Marks will be deducted for
missing steps.
**WARNING: Please note that Virtual University takes serious note of unfair means.
Anyone found involved in cheating will get an `F` grade in this course.
1
For Teacher’s use only
Question Q1 Q2 Q3 Q4 Q5 Q6 Q7 Total
Marks
Question No: 1 Marks: 8+8

a) Convert each of the following POS expression to minimum SOP expression using a Karnaugh Map.
( A + B )( A + B + C )( B + C + D )( A + B + C + D )
b) Convert the decimal numbers 78 and 34 into Octal. Using octal addition, add the two numbers
and convert the octal result back into decimal and verify the answer.
Question No: 2 Marks: 8
Draw the timing diagram of QA, QA , QB and QB . Assume the Positive edge triggering.
2
Show the complete timing diagram for the 5 stage synchronous binary counter.
HIGH
FF0
LSB J4
J0 J1 J2 J3
Q4
Q0 Q1 Q2 Q3
C C C C C
K0 K1 K2 K4
K3
CLK
3
It is required to construct a memory with 256 words, 16 bits per word. Cores are available in a
matrix of 16 rows and 16 columns.
a) How many matrices are needed?
b) How many flip-flops are in the address and buffer registers?
c) How many cores receive current during a read cycle?
d) How many cores receive at least half-current during a write cycle?

Show the data output waveform for a 4-bit register with the parallel input data and the clock and
SHIFT / LOAD waveform given in the figure. The serial data input (SER) is a 0. The parallel data
inputs are D0=1, D1=0, D2=1, D3=0 as shown. Develop the data-output waveform in relation to the
inputs.
D0 D1 D2 D3
1 0 1 0
SHIFT/LOAD
Data out
SER Q3
CLK C
CLK 1 2 3 4 5 6
SHIFT/LOAD
Data out Q3
Implement a 4-bit Johnson Counter using J-K flip-flops

Briefly answer the following questions:
a) What does sampling mean?
b) Why you must hold a sampled value?
c) If the highest frequency component in an analog signal is 20kHz, what is minimum sample
frequency?
d) What determines the accuracy of quantization process?
4
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MIDTERM EXAMINATION
Total Marks:100
SEMESTER SPRING 2005
Name
PVC Name / Code
Date
Maximum Time Allowed: (2 Hours)
questions:
missing steps.
1
For Teacher’s use only
Question Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Total
Marks
Question No: 1 Marks: 2+2+2+2+2=10

Select the best possible choice.
1) The OR gate performs Boolean ___________.
a) multiplication
b) subtraction
c) division
d) addition
2) How many states does a modulus-4 counter have?
a) 1
b) 2
c) 4
d) 16
3) How will a serial in/serial out shift register accept data serially?
a) one bit at a time

b) 8 bits at a time
c) only after a load pulse
d) only after being cleared
4) The invalid state of an SR latch occurs when
a) S=1,R=0
b) S=0,R=1
c) S=1,R=1
d) S=0,R=0
5) The storage cell in SRAM is
a) a flip –flop
b) a capacitor
c) a fuse
2
d) a magnetic domain
Question No: 2 Marks: 12+2+2=16

a) Simplify the Boolean function using k-map and draw the circuit diagram.
F ( x, y, z ) = ∑ (1,3,5, 6, 7)
b) Define JEDEC file

c) What is 2’s complement of 0011 1001?
Draw the circuit diagram of the 4x1 Multiplexer. Also write down its truth table?
Design a 2-bit count-down counter. This is a sequential circuit with two flip flops and one input x.
when x=0 the state of flip flop doesn’t change. When x=1 the state sequence is 11, 10.01,00,11 and
repeat.
For the data input and clock in figure, determine the states of each flip-flop in the shift register for
the diagram and show the Q waveforms. Assume that the register contains all 1s initially.
FF0 FF1 FF2 FF3

Serial Serial data
D D D D
data input Q0 Q1 Q2 Q3 output
C C C C
Serial data
Q3 output
CLK
3
CLK
Serial
data input
Q0
Q1
Q2
Q3

Draw block diagram of 4-bit Johnson Counter?
Question No: 7 Marks: 6+4
a) Answer the following questions briefly:

a. What is current sourcing?
b. Define noise margin?
b) Name any four performance characteristics of Digital-to-Analog Converters.
Question No: 8 Marks:2+2+1+5=10
a) What does DSP stands for?

b) What does SIMM stands for?
c) Define ROM and list the types of read-only memories?
4
Spring 2009
CS302- Digital Logic Design (Session - 2)
Question No: 1 ( Marks: 1 ) - Please choose one
The diagram given below represents __________
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► Demorgans law
► Associative law
► Product of sum form
► Sum of product form
Question No: 2 ( Marks: 1 ) - Please choose one M

Excess-8 code assigns _______ to “+7” O
► 0000
g .C
► 1001
► 1000
i n
► 1111
.t n
NOR gate is formed by connecting _________ n a
an
► OR Gate and then NOT Gate
► NOT Gate and then OR Gate
u j
► AND Gate and then OR Gate
► OR Gate and then AND Gate
. v
Question No: 4 W
( Marks: 1 ) - Please choose one
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A full-adder has a Cin = 0. What are the sum (<PRIVATE
"TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1?
►
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= 0, Cout = 0
= 0, Cout = 0
► = 0, Cout = 1
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► = 1, Cout = 0
► = 1, Cout = 1

adder has-A particular half
► 2 INPUTS AND 1 OUTPUT
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT
MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT __________ GATE
► AND
► OR
► NAND
► XOR
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THE MANUFACTURER.
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A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY
i n
.t n
► TRUE
► FALSE
n a
FLIP FLOPS ARE ALSO CALLED _____________
► BI-STABLE DUALVIBRATORS
an
► BI-STABLE TRANSFORMER
► BI-STABLE MULTIVIBRATORS u j
.
► Bi-stable singlevibrators
v
Question No: 9
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A POSITIVE EDGE-TRIGGERED FLIP-FLOP CHANGES ITS STATE WHEN ________________
W
► LOW-TO-HIGH TRANSITION OF CLOCK
► HIGH-TO-LOW TRANSITION OF CLOCK
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► ENABLE INPUT (EN) IS SET
► PRESET INPUT (PRE) IS SET

___________ IS ONE OF THE EXAMPLES OF SYNCHRONOUS INPUTS.
► J-K INPUT
► EN INPUT
► Preset input (PRE)
► CLEAR INPUT (CLR)

THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________
► GATED FLIP-FLOPS
► PULSE TRIGGERED FLIP-FLOPS
► POSITIVE-EDGE TRIGGERED FLIP-FLOPS
► NEGATIVE-EDGE TRIGGERED FLIP-FLOPS
THE DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTERS START FROM
_________
► TRUTH TABLE
M
► K-MAP
► STATE TABLE O
► STATE DIAGRAM
g .C
Question No: 13 ( Marks: 1 )
n
- Please choose one
i
.t n
THE HOURS COUNTER IS IMPLEMENTED USING __________
► ONLY A SINGLE MOD-12 COUNTER IS REQUIRED
► MOD-10 AND MOD-6 COUNTERS
► MOD-10 AND MOD-2 COUNTERS
n a
► A SINGLE DECADE COUNTER AND A FLIP-FLOP
an
u j
GIVEN THE STATE DIAGRAM OF AN UP/DOWN COUNTER, WE CAN FIND __________
. v
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► THE NEXT STATE OF A GIVEN PRESENT STATE
► THE PREVIOUS STATE OF A GIVEN PRESENT STATE
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► BOTH THE NEXT AND PREVIOUS STATES OF A GIVEN STATE
► The state diagram shows only the inputs/outputs of a given states
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In ________ outputs depend only on the current state.
► Mealy machine
► MOORE MACHINE
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► STATE REDUCTION TABLE
► STATE ASSIGNMENT TABLE

A SYNCHRONOUS DECADE COUNTER WILL HAVE _______ FLIP-FLOPS
►3
►4
►7
► 10

A MULTIPLEXER WITH A REGISTER CIRCUIT CONVERTS _________
► SERIAL DATA TO PARALLEL

► PARALLEL DATA TO SERIAL
► Serial data to serial
M
► PARALLEL DATA TO PARALLEL
O
g .C
The alternate solution for a multiplexer and a register circuit is _________
i n
► PARALLEL IN / SERIAL OUT SHIFT REGISTER
.t n
a
► SERIAL IN / PARALLEL OUT SHIFT REGISTER
► PARALLEL IN / PARALLEL OUT SHIFT REGISTER
n
► SERIAL IN / SERIAL OUT SHIFT REGISTER
an
u j
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF
. v
REGISTER AFTER THREE CLOCK PULSES?
►2
►4 W
►6
►8 W
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A 8-BIT SERIAL IN / PARALLEL OUT SHIFT REGISTER CONTAINS THE VALUE “8”, _____
CLOCK SIGNAL(S) WILL BE REQUIRED TO SHIFT THE VALUE COMPLETELY OUT OF THE
REGISTER.
►1
►2
►4
►8

5-BIT JOHNSON COUNTER SEQUENCES THROUGH ____ STATES
►7
► 10
► 32
► 25
IN ________ Q OUTPUT OF THE LAST FLIP-FLOP OF THE SHIFT REGISTER IS CONNECTED TO
THE DATA INPUT OF THE FIRST FLIP-FLOP OF THE SHIFT REGISTER.
► MOORE MACHINE
► Meally machine
► Johnson counter
► Ring counter
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DRAM STANDS FOR __________
► DYNAMIC RAM
n g
► Data RAM
i
► Demoduler RAM
► None of given options .t n
n a
- Please choose one
an
IF THE FIFO MEMORY OUTPUT IS ALREADY FILLED WITH DATA THEN ________
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► IT IS LOCKED; NO DATA IS ALLOWED TO ENTER
► IT IS NOT LOCKED; THE NEW DATA OVERWRITES THE PREVIOUS DATA.
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► PREVIOUS DATA IS SWAPPED OUT OF MEMORY AND NEW DATA ENTERS
► NONE OF GIVEN OPTIONS
W
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LUT is acronym for _________
► LOOK UP TABLE
► LOCAL USER TERMINAL
► LEAST UPPER TIME PERIOD
______ OF A D/A CONVERTER IS DETERMINED BY COMPARING THE ACTUAL OUTPUT OF A D/A
CONVERTER WITH THE EXPECTED OUTPUT.
► RESOLUTION
► Accuracy
► Quantization
► Missing Code
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i n
.t n
In the circuit diagram of 3-bit synchronous counterThe red rectangle would ,shown above
be replaced which gate?
n a
► AND
► OR
an
► NAND
► XNOR
u j
. v
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WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO
_________
W
► THE FLOP-FLOP IS TRIGGERED
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► Q=0 AND Q’=1
► Q=1 AND Q’=0
► THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED

A FREQUENCY COUNTER ______________

► Counts pulse width
► COUNTS NO. OF CLOCK PULSES IN 1 SECOND
► Counts high and low range of given clock pulse
Stack is an acronym for _________
► FIFO memory
► LIFO memory
► Flash Memory
► Bust Flash Memory

What is the role of MOS transistor in Mask ROM.
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i n
THE GROUP OF BITS 10110111 IS SERIALLY SHIFTED (RIGHT-MOST BIT FIRST) INTO AN 8-BIT PARALLEL
OUTPUT SHIFT REGISTER WITH AN INITIAL STATE 11110000. WHAT WILL BE THE CONTENTS OF REGISTER
AFTER TWO CLOCK PULSES THE REGISTER CONTAINS?
.t n
n a
an
j
DRAW THE CIRCUIT DIAGRAM OF GATED S-R LATCH.
u
Question No: 34 ( Marks: 2 ) . v
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HOW MANY BYTES WILL BE THERE IN 32 K X 4 MEMORY?
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32 X 1024BYTES X 4 = 131072 BYTES
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THE ________ OF FIRST 74HC163 COUNTER IS CONNECTED TO _______ AND
________ INPUTS OF OTHER 74HC COUNTER TO FORM A SINGLE CASCADED COUNTER

GIVEN THE FOLLOWING STATEMENT USED IN PLD PROGRAMMING:
Y PIN 23 ISTYPE ‘COM’;
Explain what does this statement mean?
VARIABLE Y AT OUTPUT PIN 23 WHICH IS A COMBINATIONAL OUTPUT AVAILABLE DIRECTLY

FROM THE AND-OR GATE ARRAY OUTPUT.
Y = VARIABLE Y
PIN 23 = PIN NUMBER 23
ISTYPE “COM” = OUTPUT TYPE COMBINATIONAL
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WHAT IS MEMORY EXPANSION PROCESS?

CONSIDER THE TABLE GIVEN BELOW, APPLY THE STATE REDUCTION PROCESS ON THE
M
STATES GIVEN IN THE TABLE AND REDUCE THE NUMBER OF STATES AS MUCH AS POSSIBLE.
PRESENT STATE NEXT STATE OUTPUT O

A
X=0
F
X=1
B
X=0
0
g .C X=1
0
B
C
B
A
C
F
i n
1
0
1
1
.t n
D E D 1 0
E A G 0 1
F
G
D
D
E
E
n a 0
0
0
0
an
u j
PERFORMANCE CHARACTERISTICS OF D/A CONVERTERS ARE DETERMINED BY FIVE
PARAMETERS. NAME THEM.
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GIVEN BELOW IS THE CIRCUIT DIAGRAM OF BI-DIRECTIONAL 4-BIT SERIAL IN/SERIAL OUT
SHIFT REGISTER. REGISTER SHIFTS DATA LEFT OR RIGHT DEPENDS ON THE
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RIGHT / LEFT SIGNAL APPLIED. EXPLAIN HOW THIS CIRCUIT SHIFTS DATA LEFT AND
RIGHT.
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BRIEFLY EXPLAIN ADDRESS MULTIPLEXING IN DRAM.
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i n
.t n
n a
an
u j
. v
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MIDTERM EXAMINATION
FALL 2006 Marks: 55
CS302 - DIGITAL LOGIC DESIGN (Session - 3 ) Time: 60min
StudentID/LoginID: ______________________________
Student Name: ______________________________
Center Name/Code: ______________________________
Exam Date: Wednesday, November 22, 2006
Please read the following instructions carefully before attempting any

of the questions:
3. Do not ask any questions about the contents of this examination
from anyone.
a. If you think that there is something wrong with any of the
questions, attempt it to the best of your understanding.
b. If you believe that some essential piece of information is
missing, make an appropriate assumption and use it to solve the
problem.
**WARNING: Please note that Virtual University takes serious note of

unfair means. Anyone found involved in cheating will get an `F` grade
in this course.
For Teacher's use only

Question 1 2 3 4 5 6 7 8 9 Total
Marks
According to rule of Boolean Algebra; A+0

► 0
► A
► 1
► A'
If a three-input AND gate has eight input possibilities, how many of those
possibilities will result in a HIGH output?
► 1
► 2
► 7
► 8
A multiplexer has
► one input and several outputs
► one input and one output
► several inputs and several outputs
► several inputs and one output
8 X 101 + 6 X 100 is equal to
► 8.6
► 86
► 860
► 0.86
OLMC is an acronym for
► Output Logic Main Cell
► Optimum Logic Multiple Channel
► Output Logic Macro Cell
► Odd-parity Logic Master Check
Consider the following Octal number: (5+5)
a) (453) 8
Convert it into Binary number system.
b) Calculate (2394) 16 + (7187) 16
Minimize the following problems using the Karnaugh maps method.
Z = f(A,B,C) = B + B + BC + A
Draw a circuit diagram of 8-to-3 line Binary Encoder.
Given the following Boolean function. (7+8)
F = x yz + wxy + wxy
i) Obtain the truth table of the function.

ii) Draw the logical diagram using the original Boolean expression
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MIDTERM EXAMINATION
Total Marks:50
SEMESTER SPRING 2005
Name
PVC Name / Code
Date
Maximum Time Allowed: (1 Hour)
questions:
missing steps.
For Teacher’s use Only
Question Q1 Q2 Q3 Q4 Q5 Total
Marks
Question No: 1 Marks: : 2+2+2+2+2=10

Select the best possible choice.
a) A NOR’s gate output is HIGH if
I. all inputs are HIGH
II. any input is HIGH
III. any input is LOW
IV. all inputs are LOW
b) A demultiplexer has
I. one input and several outputs

II. one input and one output
III. several inputs and several outputs
IV. several inputs and one output
c) The difference of 111 - 001 equals

I. 100
II. 111
III. 001
IV. 110
d) To implement the expression ABCD + ABCD + ABC D , it takes one OR gate and
I. three AND gates and three inverters
II. three AND gates and four inverters
III. three AND gates
IV. one AND gate
e) Which gate is best used as a basic comparator?
I. NOR
II. OR
III. exclusive-OR
IV. AND
Convert (-7A) 16 into Binary number system and then take 2’s complement of the resultant binary
number. (Show all necessary steps.)

Implement a logic circuit for the truth table given below:
INPUTS OUTPUTS
A B C X
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
Question No: 4 Marks:6+4=10
a) Draw a 4-variable K-map and label each cell according to its binary value.
(Hint) for 2 –variable k-map
A\B 0 1
0 00 01
1 10 11
b) Expand each expression to standard SOP form.
ABCD + AC D + BCD + ABC D

Question No: 5 Marks: 4+6=10
Draw a truth table and circuit diagram of 4 bit parallel adder?
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MIDTERM EXAMINATION
SPRING 2007 Marks: 45
Student Name: ______________________________
Center Name/Code: ______________________________
Exam Date: Friday, April 27, 2007

of the questions:
from anyone.
problem.
Write down all the steps in Subjective Questions. Marks will be
deducted for missing steps.

in this course.

Question 1 2 3 4 5 6 7 Total
Marks
(a) Convert the decimal number 6789.8 to octal correct to 3 decimal places Marks = 4
(b) Draw the truth table for the following expression F = xy + x’z Marks = 6
Use Quine-McCluskey method to find all prime implicants for the given expression
f (a, b, c, d) = Σm(3,7,9,14) +Σd(1,4,6,11
Implement f (A, B, C, D) = AC’D’ + B’D using a 4-to-1 multiplexer. Choose the appropriate
control inputs
2’s complement of hexadecimal number B70A is
► B70B
► B709
► 48F6
► 48F5
The minterm expansion for F(A,B,C) = (A + B + C)(A + B’ + C’)(A’ + B + C’)(A’ + B’ + C) is
► F(A,B,C) = ΠM(0,3,5,6)
► F(A,B,C) = ∑m(0,3,5,6)
► F(A,B,C) = ΠM(1,2,4,7)
► F(A,B,C) = ∑m(1,2,4,7)
The minimum expression of the logic diagram shown below is:
► (A’D + B)
► ((D +(A’B)’)(B + C)’ )’
► (AB’D) +B’ +C’
► B +C
An 8-line to 1-line multiplexer is connected as shown in the following figure

where output Y = F(x, y, z) and z is the least significant input. Which of the following functions
does Y generate?
► F(x, y, z) = z
► F(x, y, z) = y
► F(x, y, z) = z'
► F(x, y, z) = x
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FALL 2006 Marks: 60
Student Name: ______________________________
Center Name/Code: ______________________________
Exam Date: Tuesday, February 13, 2007

of the questions:
from anyone.
problem.

Question 1 2 3 4 5 6 7 8 9 10 Total
Marks
The OR gate performs Boolean ___________.
► multiplication
► subtraction
► division
► addition
How many states does a modulus-4 counter have?
► 1
► 2
► 4
► 16
How will a serial in/serial out shift register accept data serially?
► one bit at a time
► 8 bits at a time
► only after a load pulse
► only after being cleared
If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to
0, the latch will be
► set
► reset
► invalid
► clear
The storage cell in SRAM is
► a flip –flop
► a capacitor
► a fuse
► a magnetic domain
Convert the following POS expression to minimum SOP expression using K-Map
( A + B) ( A + B + C ) ( B + C + D) ( A + B + C + D)
Draw the circuit diagram of the 4x1 Multiplexer.
Design a 2-bit count-down counter. This is a sequential circuit with two flip flops and
one input x. when x=0 the state of flip flop doesn’t change. When x=1 the state
sequence is 11, 10, 01, 00,11 and repeat.
Show a complete timing diagram showing the parallel outputs for the shift register in figure.
Use the waveforms in figure below with the register initially clear.
Data input D D D D
C C C C
CLK
Q0 Q1 Q2 Q3
CLK
Serial
data in
Q0
Q1
Q2
Q3
Draw block diagram of 4-bit Johnson Counter?

W
MIDTERM EXAMINATION
Spring 2009
GAL
can be reprogrammed because instead of fuses _______ logic is used in it
► E2CMOS
► TTL
► CMOS+
► None of the given options

The
device shown here is most likely a
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► Comparator
i n
.t n
► Multiplexer
► Demultiplexer
► Parity generator
n a
n
- Please choose one
a If
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“1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:
u
► 2nd
► 4th
. v
► 14th
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► No output wire will be activated
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Question No: 4
W ( Marks: 1 ) - Please choose one
Half-Adder Logic circuit contains 2 XOR Gates

► True
► False

A

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particular Full Adder has
► 3 inputs and 2 output
Sum = A ⊕ B ⊕ C
CarryOut = C( A ⊕ B) + AB
are the Sum and CarryOut expression of
► Half Adder
► Full Adder
► 3-bit parralel adder
► MSI adder cicuit

A
M
Karnaugh map is similar to a truth table because it presents all the possible values of input
variables and the resulting output of each value.
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► True
► False g .C
i n
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The
a
output A < B is set to 1 when the input combinations is __________
n
► A=10, B=01
an
► A=11, B=01
► A=01, B=01
u j
► A=01, B=10
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Question No: 9
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The
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4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
►4
►8
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► 12
► 16

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Generally, the Power dissipation of _______ devices remains constant throughout their operation.
► TTL
► CMOS 3.5 series
► CMOS 5 Series
► Power dissipation of all circuits increases with time.
The
decimal “8” is represented as _________ using Gray-Code.
► 0011
► 1100
► 1000
► 1010

M
(A+B).(A+C) = ___________
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► B+C
g .C
► AB+C
► A+BC
i n
► AC+B
.t n
a
- Please choose one
n A.(B
n
+ C) = A.B + A.C is the expression of _________________
a
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► Demorgan’s Law
► Commutative Law
► Distributive Law . v
► Associative Law
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Question No: 14
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NOR Gate can be used to perform the operation of AND, OR and NOT Gate
► FALSE
► TRUE

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In
ANSI/IEEE Standard 754 “Mantissa” is represented by ___32-bits______ bits
► 8-bits
► 16-bits
► 32-bits
► 64-bits
Caveman number system is Base _5_____ number system
►2
►5
► 10
► 16
Briefly state the basic principle of Repeated Multiplication-by-2 Method. M

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i n
.t n
na
How
standard Boolean expressions can be converted into truth table format.
an
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Question No: 19 ( Marks: 2 ) . v
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What will be the out put of the diagram given below
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When an Input (source) file is created in ABEL a module is created which has three sections. Name
These three sections.
Explain “AND” Gate and some of its uses
Write down different situations where we need the sequential circuits.
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i n
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MIDTERM EXAMINATION
Spring 2009

In
the binary number “10011” the weight of the most significant digit is ____
► 24 (2 raise to power 4)

An
S-R latch can be implemented by using _________ gates
► AND, OR
► NAND, NOR M
► NAND, XOR
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► NOT, XOR

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latch has _____ stable states
► One
► Two
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► Three
► Four
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Sequential circuits have storage elements
► True
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► False
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Question No: 5W ( Marks: 1 ) - Please choose one
The
ABEL symbol for “XOR” operation is
►$
►#
►!

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►&

A
Demultiplexer is not available commercially.
► True
► False
Using multiplexer as parallel to serial converter requires ___________ connected to the

multiplexer
► A parallel to serial converter circuit

► A counter circuit
► A BCD to Decimal decoder
M
► A 2-to-8 bit decoder
O
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device shown here is most likely a
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► Comparator
► Multiplexer
► Demultiplexer . v
► Parity generator
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Question No: 9
The
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main use of the Multiplexer is to
► Select data from multiple sources and to route it to a single Destination

► Select data from Single source and to route it to a multiple Destinations
► Select data from Single source and to route to single destination
► Select data from multiple sources and to route to multiple destinations

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A
logic circuit with an output consists of ________.
► two AND gates, two OR gates, two inverters

► three AND gates, two OR gates, one inverter
► two AND gates, one OR gate, two inverters
► two AND gates, one OR gate

The
binary value of 1010 is converted to the product term
► True
M
► False O
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ng
The
i
3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms
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►
►
4
8
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►
►
12
16
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Following is standard POS expression
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► True
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► False
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The
output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the
symbol’+’ here represents OR Gate.

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► Undefined
► One
► Zero
► 10 (binary)

The
Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code
► 2-bit
► 7-bit
► 8-bit
► 16-bit

The
diagram given below represents __________
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► Demorgans law .t n
► Associative law
► Product of sum form
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► Sum of product form
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How can a PLD be programmed?
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Question No: 18
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( Marks: 1 )
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How many input and output bits do a Half-Adder contain?
Question No: 19
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Explain the difference between 1-to-4 Demultiplexer 2-to-4 Binary Decoder?

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Name the three declarations that are included in “declaration section” of the
module that is created when an Input (source) file is created in ABEL.
Explain with example how noise affects Operation of a CMOS AND Gate circuit.
explain the SOP based implementation of the Adjacent 1s Detector Circuit
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BEST SITE TO HELP STUDENTS
MIDTERM EXAMINATION
SUMMER 2007 Marks: 50
Student Name: ______________________________
Center Name/Code: ______________________________
Exam Date: Friday, August 17, 2007

of the questions:
from anyone.
problem.
5. Use of cell phone during the examination is strictly prohibited, otherwise
strict disciplinary action will be taken as per university rules

in this course.

Question 1 2 3 4 5 6 7 8 9 Total
Marks

Convert decimal numbers 79 and 83 into binary. Using binary addition, add the two
numbers and convert the binary result back into decimal and verify the answer.
(a) Draw the truth table representing the function defined by the following expression:
( A ( B + C) D )
(b) Implement the circuit for the expression using only NAND gates.
( A ( B + C) D )
Use Karnaugh map to find the minimum SOP form for following expression
F = Σ (3, 5, 7, 8, 10, 12, 13, 14, 15)
Write the Boolean expression and draw the truth table representing the function of a 4x2 Encoder.
Draw the circuit diagram of the Encoder.
Determine the values of A, B, C, and D that make the sum term equal to zero.
► A = 1, B = 0, C = 0, D = 0
► A = 1, B = 0, C = 1, D = 0
► A = 0, B = 1, C = 0, D = 0
► A = 1, B = 0, C = 1, D = 1
A NAND gate's output is LOW if
► all inputs are LOW
► all inputs are HIGH
► any input is LOW

► any input is HIGH
One advantage TTL has over CMOS is that TTL is
► less expensive
► not sensitive to electrostatic discharge
► faster
► more widely available
Fan-out is specified in terms of
► voltage
► current
► watt
► unit loads
The power dissipation, P D , of a logic gate is the product of the
► dc supply voltage and the peak current
► dc supply voltage and the average supply current
► ac supply voltage and the peak current

► ac supply voltage and the average supply current
Connecting VU Students
SPRING 2006 Marks: 100
Student Name: ______________________________
Center Name/Code: ______________________________
Exam Date: Saturday, August 19, 2006

of the questions:
from anyone.
problem.

in this course.

Question 1 2 3 4 5 6 7 8 9 10 Total
Marks
Question 11 12
Marks
What is the decimal value of the terminal count of a 4-bit binary counter?
► 10
► 12
► 15
► 16
The 1's complement of 10110111 is __________.
► 10110111
► 01001011
► 01101011
► 01001000
To serially shift a byte of data into a shift register, there must be?
► One clock pulse
► One load pulse.
► Eight clock pulses.
► One clock pulse for each 1 in the data.
What is the difference between a D latch and a D flip-flop?

► The D latch has a clock input.
► The D flip-flop has an enable input.
► The D latch is used for faster operation.
► The D flip-flop has a clock input.
For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will
______ if the clock goes HIGH.
► toggle
► set
► reset
► not change
Draw the circuit diagram and truth table of the following equation.
F ( x, y, z ) = ∑ (0, 2,3,5, 7)
Draw the truth table of a Half-Adder. Draw the logical circuit diagram of a half-adder.
Write Boolean expressions for all the output signals of half adder circuit.
Design a counter to produce the following sequence using J-K Flip-Flops.

1,4,3,5,7,6,2,1
Draw the circuit diagram of the 2-input 4-bit Multiplexer. Also write down its function
table?

Q Q
a) For a gated D latch, determine the and outputs for the inputs in figure. Show
them in proper relation to the enable input. Assume Q starts LOW.
EN
b) What is the difference between Flip-flop and latches?
a) What is the difference between SRAM and DRAM?

b) What is FIFO?
c) What is LIFO?
a) What does sampling mean?

b) Name any four performance characteristics of Digital-to-Analog Converters.
c) Write name of Analog-to-Digital conversion methods

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PVC Name / Code

Maximum Time Allowed: (2 Hours)

Question No: 1 Marks: 8+8

Question No: 2 Marks: 8

Question No: 4 Marks: 10

Question No: 5 Marks: 8

Question No: 6 Marks: 10

Implement a 4-bit Johnson Counter using J-K flip-flops

Question No: 7 Marks: 8

PVC Name / Code

Maximum Time Allowed: (2 Hours)

Question No: 1 Marks: 2+2+2+2+2=10

2) How many states does a modulus-4 counter have?

a) one bit at a time

4) The invalid state of an SR latch occurs when

5) The storage cell in SRAM is

Question No: 2 Marks: 12+2+2=16

b) Define JEDEC file

Question No: 3 Marks: 10

FF0 FF1 FF2 FF3

Question No: 6 Marks: 12

Question No: 7 Marks: 6+4

a) Answer the following questions briefly:

a) What does DSP stands for?

Question No: 2 ( Marks: 1 ) - Please choose one M

Question No: 5 ( Marks: 1 ) - Please choose one

Question No: 10 ( Marks: 1 ) - Please choose one

Question No: 11 ( Marks: 1 ) - Please choose one

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Question No: 16 ( Marks: 1 ) - Please choose one

Question No: 17 ( Marks: 1 ) - Please choose one

► SERIAL DATA TO PARALLEL

Question No: 21 ( Marks: 1 ) - Please choose one

Question No: 29 ( Marks: 1 ) - Please choose one

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► COUNTS NO. OF CLOCK PULSES IN 1 SECOND

► Counts high and low range of given clock pulse

► NONE OF GIVEN OPTIONS

Question No: 31 ( Marks: 1 )

Question No: 36 ( Marks: 3 )

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VARIABLE Y AT OUTPUT PIN 23 WHICH IS A COMBINATIONAL OUTPUT AVAILABLE DIRECTLY

Question No: 38 ( Marks: 5 )

PRESENT STATE NEXT STATE OUTPUT O

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Student Name: ______________________________

Center Name/Code: ______________________________

Exam Date: Wednesday, November 22, 2006

Please read the following instructions carefully before attempting any

**WARNING: Please note that Virtual University takes serious note of

For Teacher's use only

Question No: 1 ( Marks: 2 ) - Please choose one

According to rule of Boolean Algebra; A+0

Question No: 2 ( Marks: 2 ) - Please choose one

Question No: 3 ( Marks: 2 ) - Please choose one

► one input and several outputs

► one input and one output

► several inputs and several outputs

► several inputs and one output

Question No: 4 ( Marks: 2 ) - Please choose one

8 X 101 + 6 X 100 is equal to

Question No: 5 ( Marks: 2 ) - Please choose one