Chapter 6 PDF

An-Najah National University
Faculty of Engineering
Electrical Engineering Department
Field-Effect Transistors (FETs)

 Introduction
 FETs are unipolar devices.
Only one type of carrier is used per transistor (either holes or electrons).
Two main types:
Junction field-effect transistor (JFET).
Metal oxide field-effect transistor (MOSFET).
While the BJT is a current-controlled device (base current controls the collector current), the
FET is a voltage-controlled device (voltage between two of the terminals controls the current
through the device).
FETs have very high input resistance.

 The Junction Field-Effect Transistor (JFET)
The JFET is a type of FET that operates with a reverse-biased pn junction.
The pn junction controls current in a channel.
the channel may be either of n or p type material.
It has three leads:
Drain
Gate
Source
In the n-channel JFET, the gate is connected to both p regions.
In the p-channel JFET, the gate is connected to both n regions.
Only one gate lead is shown for simplicity.

Let’s look at an n-channel JFET.

VDD provides a drain-to-source voltage, thus supplying a current from the drain to the source.
VGG sets the reverse-bias voltage between the gate and the source.
Note that the gate-source pn junction should ALWAYS be reverse biased.
The reverse biasing of the gate source junction produces
a depletion region along the pn junction.
The depletion formed extends into the n channel.

By increasing the depletion region, the width of the n channel becomes thinner.
Making the channel thinner creates more resistance against current flow.

The symbol for the JFET is:

JFET Characteristics and Parameters
The JFET is a voltage-controlled, constant-current device.
To understand this, consider the case when the gate-to-source voltage is zero (VGS=0).
To get this, we need to short the gate to the source.
As VDD increases, VDS increases as well.
ID, the drain current, will also increase
proportionally to increases in V-DD.
This increase in drain current is linear,
because the depletion region is NOT large
enough to have significant effect.
This is shown between points A and B.

The region between points A and B is called the ohmic region.

At point B, ID becomes essentially constant.
This occurs because the reverse bias voltage from gate to drain (VGD) produces a depletion
region large enough to offset the
increase in VDS.
The offset is enough to keep ID constant.
ID- will remain constant until point C, where
we reach breakdown.

Connecting a bias voltage, VGG, to the gate produces a family of curves as shown next.
Notices that ID decreases as VGS is made more negative.
This occurs because the channel is narrowing.
Also notice that pinch-off occurs at different VP’s for different VGS values.
Thus, the drain current is controlled
by VGS.

The value of VGS that makes I-D approximately zero is called the cutoff voltage, VGS(off).
Note that the value of VGS that sets ID to zero (i.e. widening the depletion region to a point
where the channel is completely closed) is the most negative value VGS can take
The operation of a p-channel is the same as the n-channel, but requires a negative V-DD and a
positive VGS.

Relation between Pinch-Off and Cutoff voltages
VP -is the value of VDS at which the drain current becomes constant.
It is always measured at V-GS = 0.
Pinch-off occurs for VDS values less than VP, when VGS is nonzero.
So, although VP is a constant, the minimum value of VDS at which ID becomes constant varies
with VGS.
VGS(off) and VP are always equal in magnitude, but opposite in sign.Thus, knowing one, we have
the other.
Data sheets will generally list only one of the two.
For example, if VGS(off) = -5 V, then VP = +5 V.

Example
Determine the minimum vale of VDD required to put the JFET below in the constant-current
region of operation.

Solution
Since VGS(off) = –4 V, VP = 4 V. The minimum value of VDS for the JFET to enter the constant current
region is
VDS = VP = 4 V
In the constant current area with VGS = 0 V,

ID = IDSS = 12 mA
The drop across the drain resistor is

VR(D) = I-DRD = (12 mA)(560 Ω) = 6.72 V
Using KVL around the drain circuit

VDD = VDS + VR(D) = 4 V + 6.72 V = 10.72 V
Thus, VDD must be 10.72 V for the device to enter the constant current area, i.e. to make VDS = VP.

Example
A particular p-channel JFET has a VGS(off)- = +4 V. What is ID when VGS = +6 V?
Solution
Recall a p-channel JFET requires a positive gate-to-source voltage. The more positive VGS, the
less the drain current. When VGS = 4 V, ID = 0 (cutoff). Any further increase in VGS keeps the JFET
cut off, so ID remains at 0.

JFET Transfer Characteristic
A range of VGS values between 0 and VGS(off) controls the drain current.
For an n channel JFET, VGS(off) is negative.
For a p channel JFET, VGS(off) is positive.
The relation between VGS and ID is shown below:
The voltage ranges from VGS = VGS(off) to zero.
The current ranges from 0 to IDSS.
The curve shows the operational limits of the transistor.

The equation for the JFET characteristic curve is:

ID = I-DSS(1 – VGS/VGS(off))2
 Thus, if IDSS and VGS(off)- are known,
ID- can be determined for any VGS.
Notice that the characteristic curve
is parabolic.
Because of this, JFET and MOSFET
are often referred to as square-law
devices.

Example
Determine the drain current for VGS = 0 V, -1 V and –4 V for a 2N5459 JFET.


Looking at the data sheet we find that IDSS = 9 mA and VGS(off) = -8 V(maximum).
Thus, we can say that for VGS = 0
ID = IDSS = 9mA
For VGS = –1 V we use the equation shown above:

= (9 mA)(1 – (-1 V/-8 V))2
= 6.89 mA
For VGS = –4 V :
= (9 mA)(1 – (-4 V/-8 V))2
= 2.25 mA

Input Resistance
 Since the JFET operates with the gate-source junction reverse-biased, the input resistance is
very high.
This is one advantage of JFET over BJTs.
The input resistance can be calculated by:
RIN- = |VGS/IGSS|

JFET Biasing
Just as with the BJTs, we need to establish the right dc gate-to-source voltage to get the
desired value of drain current.
We will study to biasing methods:
Self Bias
Voltage-Divider Bias

JFET Biasing
Self Bias
Most common biasing method for JFETs.

We need a negative VGS for an n channel JFET.
We need a positive VGS for a p channel JFET.
We achieve that with the circuit shown below.
The gate resistor, RG, does NOT affect the bias since there is almost no drop across it.
Thus, the gate remains at zero.
RG is used to isolate an ac signal from ground in amplifier applications.

JFET Biasing
Self Bias_ n-channel
Consider the n-channel JFET circuit.

IS produces a voltage drop across RS.
This makes the source positive with respect to ground.
Since IS = ID and VG = 0, then VS = IDRS.
Thus:
VGS = VG – VS = 0 – IDRS = – IDRS

JFET Biasing
Self Bias_ p-channel

For the p-channel JFET, the current through RS produces a negative voltage at the source.
This makes the gate positive with respect to the source.
Thus IS = ID, and VGS = +IDRS
 Consider again the n-channel transistor.
VD = VDD – IDRD
 Since VS = IDRS, the drain-to-source voltage is
VDS = V-D – VS
= VDD – ID(RD + RS)

JFET Biasing
Self Bias-channel
Solution
VS = IDRS = (5 mA)(220 Ω) = 1.1 V
VD = VDD – ID-R-D = 15 V – (5 mA)(1.0 kΩ) = 10 V

Thus,
VDS = VD – VS = 10 V – 1.1 V = 8.9 V

Since VG = 0 V:
VGS = VG – VS = 0 V – 1.1 V = –1.1 V

JFET Biasing
Setting the Q-point of a Self-Biased JFET
Determine ID for a desired value of VGS or viceversa.

Then, calculate the value of RS by using:RS = |VGS/ID|

JFET Biasing
Example
Determine the value of RS (at VGS = -5 V) required to self-bias an n-channel JFET that has the
transfer characteristic curve shown next.

JFET Biasing
From the graph, ID = 6.25 mA at VGS = - 5 V.

Then
RS = |VGS/ID| = 5 V/6.25 mA = 800 Ω

JFET Biasing
Example
Determine the value of RS required to self-bias a p-channel JFET with IDSS=25 mA and VGS(off) = 15
V. VGS is to be 5 V.

JFET Biasing
Solution
Use the square-law equation:
ID = IDSS(1 – VGS/VGS(off))2 = (25 mA)(1–5V/15V)2 = 11.1mA
Now determine R-S:

RS = | VGS/ID| = 5 V/11.1 mA = 450 Ω

JFET Biasing
NOTE
It is generally desirable to bias a JFET near the midpoint of its transfer characteristic, that is,
where ID = IDSS/2.
At this point we allow the maximum amount of drain current swing between IDSS and 0.
It can be shown that we get approximately that value for ID when VGS=VGS(off)/3.4.
To select a drain voltage at midpoint (VD = VDD/2), select a value of RD to produce the desired
voltage drop.

JFET Biasing
Graphical Analysis of a Self Biased JFET
Consider the circuit shown below.

From data sheet, plot the characteristic curve.
To determine the Q-point of the circuit, find VGS at ID = 0.
VGS = -IDRS = (0)(470 Ω) = 0 V
Now, using IDSS, calculate VGS when ID = IDSS:
VGS = -IDRS = -(10 mA)(470 Ω) = -4.7 V

JFET Biasing
Draw a line connecting the two points.

This line is the load line.
Wherever the load line intersects the characteristic curve,
we have the Q-point of the circuit.

JFET Biasing
Draw a line connecting the two points.

This line is the load line.
Wherever the load line intersects the characteristic curve,
we have the Q-point of the circuit.

JFET Biasing
Self Biased JFET
Determine the following for the network shown below

1- IDQ and VGSQ
2- VD
3- VS
4-VDS
5-VDG

JFET Biasing
Voltage-Divider Bias
Voltage at source needs to be more positive than voltage at gate to keep
the gate-source junction reverse biased.
Source voltage is VS = ISRS.
The voltage at the gate is:
VG = VDD(R2/(R2 + R1))
 Thus, VGS = VG - VS
Combining these equations we get:
ID = (VG - VGS)/RS

JFET Biasing
Determine ID and VGS for the FET with voltage-divider bias shown below. For this particular FET,
the internal parameters are such that VD  7 V.
Solution
ID = (VDD – VD)/RD = (12 V – 7 V)/3.3 kΩ = 1.52 mA
VS = IDRS = (1.52 mA)(2.2 kΩ) = 3.34 V
VG = R2/(R1+R2)VDD = (1 MΩ)/(7.8 MΩ) 12 V = 1.54 V
VGS = VG – VS = 1.54 V – 3.34 V =–1.8V

JFET Biasing
Determine ID and VGS for the FET with voltage-divider bias shown below. For this particular FET,
the internal parameters are such that VD  7 V.
Solution
ID = (VDD – VD)/RD = (12 V – 7 V)/3.3 kΩ = 1.52 mA
VS = IDRS = (1.52 mA)(2.2 kΩ) = 3.34 V
VG = R2/(R1+R2)VDD = (1 MΩ)/(7.8 MΩ) 12 V = 1.54 V
VGS = VG – VS = 1.54 V – 3.34 V =–1.8V

JFET Biasing
Determine the following for the network shown below

1- IDQ and VGSQ
2- VD
3- VS
4-VDS
5-VDG

 The Metal Oxide Semiconductor Field-Effect Transistor (MOSFET)
The MOSFET differs from the JFET in that it has no pn junctions.

Instead, the gate of the MOSFET is insulated from the channel by a silicon dioxide (SiO2) layer.
There are two basic types of MOSFETs:
Depletion (D) MOSFETs.
Enhancement (E) MOSFETs.

Depletion MOSFET.
The D MOSFET can operate both in the enhancement and depletion modes.
Since the gate is insulated from the channel, either a positive or a negative gate voltage can be
applied.
An n-channel MOSFET operates in depletion mode when a negative gate-to-source voltage is
applied.
It operates in an enhancement mode when a positive

The symbol for an D-MOSFET is shown next.


Drain and source are diffused into the

substrate material and then connected
by a narrow channel adjacent to the
insulated gate.

When the gate and source are connected to the

Ground and VDD is applied the current will pass
Through the channel from drain to source similar to
The FET operation.

With a negative gate voltage, the negative charges on

the gate repel conduction electrons from the channel,
leaving positive ions in their place.
Thus, the n channel is depleted of some of its conducting
electrons.
Conductivity is decreased.
The greater the negative voltage on the gate, the greater the depletion of n channel
electrons.

At a sufficiently large gate-to-source voltage, VGS(off), the channel is completely depleted and
ID becomes zero.
Just like the n-channel FET, the n-channel D-MOSFET conducts drain current for gate-to-
source voltages between VGS(off) and zero.

Enhancement MOSFET.
Operates ONLY in the enhancement mode. It has no depletion mode.

It has no actual channel.
The substrate extends completely to the SiO-2 layer.

For the n channel device, a positive gate

voltage above a threshold value induces a channel
by creating a thin layer of negative charges in the
substrate region adjacent to the SiO2 layer.
Conductivity is enhanced by increasing the
gate-to-source voltage.
This pulls more electrons into the channel area.

For any voltage below the threshold value,

there is no channel.

The symbol for an E-MOSFET is shown next.

The dashed line indicates the absence of a channel.

Enhanced MOSFET.
There is no drain current when V-GS = 0.

Ideally, there is no drain current until VGS reaches a certain non-zero value called the threshold
voltage, VGS(th).
The square law equation for the drain current, thus, becomes:
ID = K(VGS – VGS(th))2
The constant K depends on the particular MOSFET.

It can be found from the data sheet by looking at the
specified value of ID, called the on-state value or ID(on), at
the given value of VGS-.
Substitute the two parameters into the equation above
and solve for K.


K= ID/(VGS(on) – VGS(th))2=3 mA/(10-3V)2=0.061x10-3 A/V2


Handling precautions!!
ALL MOS DEVICES ARE SUBJECT TO DAMAGE FROM ELECTROSTATIC DISCHARGE (ESD).
Since the gate of a MOSFET is insulated form the channel, the input resistance is very high.
The gate leakage current (IGSS) is in the pA range.
The gate reverse current for a JFET is in the nA range.
The input capacitance results from the insulated gate structure.
Excess static charge can be accumulated because the input capacitance combines with the
very high input resistance.
This can result in damaging the device.

D-MOSFET Biasing
Example :- for n-channel depletion-type MOSFET. Determine

IDQ , VGSQ , VDS
Repeat with Rs=150

D-MOSFET Biasing
Example :- for n-channel depletion-type MOSFET. Determine

IDQ , VGSQ , VDS
Repeat with Rs=150

E-MOSFET Biasing
VGS must be greater than the threshold value VGS(th).
Thus, zero bias cannot be used.
We use either a voltage-divider or a drain-feedback bias arrangement.
The goal is to make the gate voltage more positive than the source by an amount exceeding
VGS(th).
The drain-feedback bias circuit has a negligible gate
current.
Thus, there is no drop across RG.
Thus, VGS = VDS.

E-MOSFET Biasing
Example :- for n-channel enhanced-type MOSFET. Determine

IDQ , VGSQ ,

E-MOSFET Biasing
Example :- for n-channel enhanced-type MOSFET. Determine

IDQ , VGSQ ,

Chapter 6 PDF

Hochgeladen von

Dokumentinformationen

Originalbeschreibung:

Originaltitel

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Chapter 6 PDF

Hochgeladen von

Copyright:

Verfügbare Formate

An-Najah National University

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

Let’s look at an n-channel JFET.

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

The region between points A and B is called the ohmic region.

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

In the constant current area with VGS = 0 V,

The drop across the drain resistor is

Using KVL around the drain circuit

Field-Effect Transistors (FETs)

A particular p-channel JFET has a VGS(off)- = +4 V. What is ID when VGS = +6 V?

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

The equation for the JFET characteristic curve is:

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

For VGS = –1 V we use the equation shown above:

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

Field-Effect Transistors (FETs)

Most common biasing method for JFETs.

Field-Effect Transistors (FETs)

Self Bias_ n-channel

Consider the n-channel JFET circuit.

Field-Effect Transistors (FETs)

Self Bias_ p-channel

Field-Effect Transistors (FETs)

VD = VDD – ID-R-D = 15 V – (5 mA)(1.0 kΩ) = 10 V

VDS = VD – VS = 10 V – 1.1 V = 8.9 V

Field-Effect Transistors (FETs)

Setting the Q-point of a Self-Biased JFET

Determine ID for a desired value of VGS or viceversa.

Field-Effect Transistors (FETs)

Setting the Q-point of a Self-Biased JFET

Field-Effect Transistors (FETs)

Setting the Q-point of a Self-Biased JFET

From the graph, ID = 6.25 mA at VGS = - 5 V.

Field-Effect Transistors (FETs)

Setting the Q-point of a Self-Biased JFET

Field-Effect Transistors (FETs)

Setting the Q-point of a Self-Biased JFET

Now determine R-S:

Field-Effect Transistors (FETs)

Setting the Q-point of a Self-Biased JFET

Field-Effect Transistors (FETs)

Setting the Q-point of a Self-Biased JFET

Graphical Analysis of a Self Biased JFET

Consider the circuit shown below.

Field-Effect Transistors (FETs)

Setting the Q-point of a Self-Biased JFET

Graphical Analysis of a Self Biased JFET

Draw a line connecting the two points.