Clocks, Latches and

Flip-Flops
Sequential Circuits

Engr. Ralph Gerard B. Sangalang Batangas State University

ECE ECE/ICE/MEXE Department
Sequential Circuits
 Sequential Circuits
Synchronous
Asynchronous
 Sequential Circuits
Latch
Flip-Flops
The Clock
 Transistor Clock Circuits
Bistable Multivibrator
Schmitt Trigger
Monostable Multivibrator
Astable Multivibrator
Bistable Multivibrator
Schmitt Trigger
Monostable Multivibrator
Astable Multivibrator
 IC Clock Circuits
74121 (single monostable multivibrator)
74221 (dual monostable multivibrator)
74122 (single retriggerable monostable
multivibrator)
74123 (dual retriggerable monostable multivibrator)
4098B (dual retriggerable monostable multivibrator)
555 Timer IC
74121 Monoshot
74121 Monoshot
74122 Monoshot
74122 Monoshot
555 Timer
555 Timer
555 Timer
555 Timer
555 Timer
555 Timer
 Basic Storage Elements
Latches and Flip-Flops
NOR Latch
NOR Latch
 NOR Latch

𝑆 𝑅 𝑄 𝑡+1
0 0 𝑄 𝑡
0 1 0
1 0 1
1 1 Forbidden
 NOR Latch

𝑄 𝑡 𝑄 𝑡+1 𝑆 𝑅
0 0 0 d
0 1 1 0
1 0 0 1
1 1 d 0
NAND Latch
NAND Latch
 NAND Latch
𝑆 𝑅 𝑄 𝑡+1
0 0 Forbidden
0 1 1
1 0 0
1 1 𝑄 𝑡
 NAND Latch
𝑄 𝑡 𝑄 𝑡+1 𝑆 𝑅
0 0 1 d
0 1 0 1
1 0 1 0
1 1 d 1
Gated SR Latch
Gated SR Latch
 Gated SR Latch
𝐸 𝑆 𝑅 𝑄 𝑡+1
0 d d 𝑄 𝑡
1 0 0 𝑄 𝑡
1 0 1 0
1 1 0 1
1 1 1 Forbidden
Gated D Latch
Gated D Latch
Gated D Latch
𝐸 𝐷 𝑄 𝑡+1
0 d 𝑄 𝑡
1 0 0
1 1 1
 Triggering Mechanisms
Level
Edge
SR Latch with Feedback
Racing Condition
Master Slave Configuration
1’s and 0’s
Catching
Master-Slave SR Flip-Flop
Master Slave D Flip-Flop
Triggering
Mechanism
The Dynamic Input Indicator
Edge Detector
Edge Detector
D Flip-Flop
D Flip-Flop

𝐷 𝑄 𝑡+1
0 0
1 1
 D Flip-Flop
𝑄 𝑡 𝑄 𝑡+1 𝐷
0 0 0
0 1 1
1 0 0
1 1 1
 Positive
edge
Triggered
D Flip-
Flop
SR Flip-Flop
 SR Flip-Flop
𝑆 𝑅 𝑄 𝑡+1
0 0 𝑄 𝑡
0 1 0
1 0 1
1 1 Forbidden
 SR Flip-Flop
𝑄 𝑡 𝑄 𝑡+1 𝑆 𝑅
0 0 0 d
0 1 1 0
1 0 0 1
1 1 d 0
JK Flip-Flop
 JK Flip-Flop
𝐽 𝐾 𝑄 𝑡+1
0 0 𝑄 𝑡
0 1 0
1 0 1
1 1 𝑄 𝑡
 JK Flip-Flop
𝑄 𝑡 𝑄 𝑡+1 𝐽 𝐾
0 0 0 d
0 1 1 d
1 0 d 1
1 1 d 0
JK Flip-Flop
T Flip-Flop
T Flip-Flop

𝑇 𝑄 𝑡+1
0 𝑄 𝑡
1 𝑄 𝑡
 T Flip-Flop

𝑄 𝑡 𝑄 𝑡+1 𝑇
0 0 0
0 1 1
1 0 1
1 1 0
T Flip-Flop
Asynchronous Inputs
JK Flip-Flop with Preset and Clear
Preset and Clear Inputs
𝑃𝑟 𝐶𝑙 Function
0 0 Forbidden
0 1 Preset (1)
1 0 Clear (0)
1 1 Enable
 Characteristic Equations
SR Flip-Flop
𝑄 𝑡+1 =𝑄 𝑡 ⋅𝑅+𝑆
with a restriction that
𝑆⋅𝑅 =0
JK Flip-Flop
𝑄 𝑡+1 =𝑄 𝑡 ⋅𝐽+𝑄 𝑡 ⋅𝐾
D Flip-Flop
𝑄 𝑡+1 =𝐷
T Flip-Flop
𝑄 𝑡+1 =𝑇⊕𝑄 𝑡
State Diagram and State Table
 State Table 1
Present Input Next Output
State 𝑥 State 𝑦
𝑆0 0 𝑆0 0
𝑆0 1 𝑆1 0
𝑆1 0 𝑆0 1
𝑆1 1 𝑆3 0
𝑆2 0 𝑆0 1
𝑆2 1 𝑆2 0
𝑆3 0 𝑆0 1
𝑆3 1 𝑆2 0
 State Table 2
Present Next State Output
State 𝑥=0 𝑥=1 𝑥=1 𝑥 =0
𝑆0 𝑆0 𝑆1 0 0
𝑆1 𝑆0 𝑆3 1 0
𝑆2 𝑆0 𝑆2 1 0
𝑆3 𝑆0 𝑆2 1 0
 State Table 3
Present Next State
State 𝑥=0 𝑥=1
𝑆0 𝑆0 /0 𝑆1 /0
𝑆1 𝑆0 /1 𝑆3 /0
𝑆2 𝑆0 /1 𝑆2 /0
𝑆3 𝑆0 /1 𝑆2 /0
State Diagram
State Diagram
Analysis of Networks with Flip-
Flop
Analysis with SR Flip-Flop
 Analysis with SR Flip-Flop
Present State Input FF B FF A Next State Output
𝑄𝐵 𝑄𝐴 𝑥 𝑆𝐵 𝑅𝐵 𝑆𝐴 𝑅𝐴 𝑄𝐵 𝑄𝐴 𝑦
0 0 0 1 0 1 0 1 1 1
0 0 1 0 0 0 0 0 0 1
0 1 0 1 0 0 1 1 0 0
0 1 1 0 0 0 0 0 1 0
1 0 0 0 0 1 0 1 1 0
1 0 1 0 1 0 0 0 0 0
1 1 0 1 0 0 1 1 0 1
1 1 1 0 0 0 0 1 1 1
Analysis with SR Flip-Flop

FF State Representation
00 𝑆0
01 𝑆1
10 𝑆2
11 𝑆3
Analysis with
JK Flip-Flop
 Analysis with JK Flip-Flop
Present State Input FF B FF A Next State Output
𝑄𝐵 𝑄𝐴 𝑥 𝐽𝐵 𝐾𝐵 𝐽𝐴 𝐾𝐴 𝑄𝐵 𝑄𝐴 𝑦
0 0 0 0 1 1 1 0 1 1
0 0 1 1 0 1 1 1 1 0
0 1 0 1 0 1 1 1 0 0
0 1 1 0 1 1 1 0 0 1
1 0 0 0 1 0 0 0 0 0
1 0 1 1 0 1 0 1 1 0
1 1 0 1 0 0 0 1 1 1
1 1 1 0 1 1 0 0 1 1
Analysis with JK Flip-Flop
Analysis with D Flip-Flop
 Analysis with D Flip-Flop
Present State Input FFB FFA Next State Output
𝑄𝐵 𝑄𝐴 𝑥1 𝑥0 𝐷𝐵 𝐷𝐴 𝑄𝐵 𝑄𝐴 𝑦
0 0 0 0 0 0 0 0 0
0 0 0 1 1 0 1 0 0
0 0 1 0 0 1 0 1 0
0 0 1 1 1 1 1 1 0
0 1 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0
0 1 1 0 0 1 0 1 0
0 1 1 1 0 1 0 1 0
1 0 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0 1
1 0 1 0 0 0 0 0 0
1 0 1 1 1 0 1 0 1
1 1 0 0 0 0 0 0 0
1 1 0 1 0 0 0 0 1
1 1 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1
Analysis with D Flip-Flop
Analysis with T Flip-Flop
 Analysis with T Flip-Flop
Present State Input FF B FF A Next State Output
𝑄𝐵 𝑄𝐴 𝑥1 𝑥0 𝑇𝐵 𝑇𝐴 𝑄𝐵 𝑄𝐴 𝑦1 𝑦0
0 0 0 0 1 0 1 0 0 0
0 0 0 1 1 0 1 0 0 0
0 0 1 0 1 0 1 0 0 1
0 0 1 1 1 0 1 0 0 1
0 1 0 0 1 0 1 1 1 0
0 1 0 1 1 1 1 0 1 0
0 1 1 0 1 0 1 1 1 1
0 1 1 1 1 1 1 0 1 1
1 0 0 0 0 0 1 0 1 0
1 0 0 1 0 0 1 0 1 0
1 0 1 0 1 1 0 1 1 1
1 0 1 1 1 1 0 1 1 1
1 1 0 0 0 0 1 1 0 1
1 1 0 1 0 1 1 0 0 1
1 1 1 0 1 1 0 0 0 0
1 1 1 1 1 1 0 0 0 0
Analysis with T Flip-Flop
 Synthesis using Flip-Flops
Clocked Sequential Circuit Design
 Design Procedure
The procedure for designing clocked sequential circuits can be summarized by the following
steps:
1. Receive the problem specification.
2. Draw the block diagram for the proposed design displaying all the inputs and the required
outputs.
3. Make an attempt to construct a basic state diagram using the information from steps 1 and 2.
4. Using the state diagram construct a state table and check for redundant states.
5. Reconstruct the state diagram if redundancy has occurred.
6. Make a state assignment.
7. Draw a new state table excluding the redundant states and using the assignments from step 6.
8. Select the flip-flop to be used as a memory element.
9. Using the reduced state table derive the logic equations of the next state inputs of the flip-
flops.
10.Develop the output logic circuit with the aid of the reduced state diagram.
 Cont.
1.From a given state diagram derive the state table.
2.Put additional columns to the state table indicating
entries for the chosen flip-flop’s inputs.
3.Based on the entries of the present state and the next
state in the table, derive the entries for the flip-flop
inputs using the flip-flop’s steering table.
4.Using any simplification method, derive the equations
for the inputs of the flip-flop.
Example
 Output Equation
Present State Input Next State Output
𝐵 𝐴 𝑋 𝐵 𝐴 𝑌
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 0
1 1 1 0 0 1
 Design using D Flip-Flop
Present State Input Next State Output Flip-Flop Input
𝐵 𝐴 𝑋 𝐵 𝐴 𝑌 𝐷𝐵 𝐷𝐴
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 0
1 1 1 0 0 1
Design using
D Flip-Flops
 Design using SR Flip-Flops
Present State Input Next State Output Flip-Flop Inputs
𝐵 𝐴 𝑋 𝐵 𝐴 𝑌 𝑆𝐵 𝑅𝐵 𝑆𝐴 𝑅𝐴
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 0
1 1 1 0 0 1
Design using
SR Flip-Flop
 Design using JK Flip-Flop
Present State Input Next State Output Flip-Flop Inputs
𝐵 𝐴 𝑋 𝐵 𝐴 𝑌 𝐽𝐵 𝐾𝐵 𝐽𝐴 𝐾𝐴
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 0
1 1 1 0 0 1
Design using JK
Flip-Flop
 Design using T Flip-Flop
Present State Input Next State Output Flip-Flop Input
𝐵 𝐴 𝑋 𝐵 𝐴 𝑌 𝑇𝐵 𝑇𝐴
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 1 0 0
0 1 1 0 1 0
1 0 0 1 0 0
1 0 1 1 1 0
1 1 0 1 1 0
1 1 1 0 0 1
Design using
T Flip-Flop
Design of Incompletely Specified States
 Mod-6 Counter
Present State Next State
𝐶 𝐵 𝐴 𝐶 𝐵 𝐴
0 0 1 0 1 1
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 1 0 1
1 0 1 0 0 1
1 1 0 1 0 0
Mod-6 Counter
Synthesized Counter
State Diagram
END