March 1996

NDC7002N
Dual N-Channel Enhancement Mode Field Effect Transistor
General Description Features

These dual N-Channel enhancement mode power field
effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process has been designed to minimize
on-state resistance, provide rugged and reliable
performance and fast switching. These devices is
particularly suited for low voltage applications requiring a
low current high side switch.
0.51A, 50V, RDS(ON) = 2Ω @ VGS=10V
High density cell design for low RDS(ON).
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High saturation current.

____________________________________________________________________________________________

4 3

5 2

6 1

SOT-6 (SuperSOTTM-6)

Absolute Maximum Ratings T A = 25°C unless otherwise noted

Symbol Parameter NDC7002N Units
VDSS Drain-Source Voltage 50 V
VGSS Gate-Source Voltage - Continuous 20 V
ID Drain Current - Continuous (Note 1a) 0.51 A
- Pulsed 1.5
PD Maximum Power Dissipation (Note 1a) 0.96 W
(Note 1b)
0.9
(Note 1c) 0.7
TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS

RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 130 °C/W

RθJC Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W

© 1997 Fairchild Semiconductor Corporation

NDC7002N.SAM
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 50 V
IDSS Zero Gate Voltage Drain Current VDS = 40 V, VGS = 0 V 1 µA
TJ = 125°C 500
IGSSF Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -20 V, VDS= 0 V -100 nA
ON CHARACTERISTICS (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.9 2.5 V
TJ = 125°C 0.8 1.5 2.2
RDS(ON) Static Drain-Source On-Resistance VGS = 10 V, ID = 0.51 A 1 2 Ω
TJ = 125°C 1.7 3.5
VGS = 4.5 V, ID = 0.35 A 1.6 4
ID(on) On-State Drain Current VGS = 10 V, VDS = 10 V 1.5 A
gFS Forward Transconductance VDS = 10 V, ID = 0.51 A 400 mS
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = 25 V, VGS = 0 V, 20 pF
f = 1.0 MHz
Coss Output Capacitance 13 pF
Crss Reverse Transfer Capacitance 5 pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on) Turn - On Delay Time VDD = 25 V, ID = 0.25 A, 6 20 nS
Turn - On Rise Time VGS = 10 V, RGEN = 25 Ω 6 20
tr
tD(off) Turn - Off Delay Time 11 20

tf Turn - Off Fall Time 5 20

Qg Total Gate Charge VDS = 25 V, 1 nC

ID = 0.51 A, VGS = 10 V
Qgs Gate-Source Charge 0.19 nC
Qgd Gate-Drain Charge 0.33 nC

NDC7002N.SAM
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
DRAIN-SOURCE DIODE CHARACTERISTICS
IS Maximum Continuous Source Current 0.51 A
ISM Maximum Pulse Source Current (Note 2) 1.5 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.51 A (Note 2) 0.8 1.2 V
Notes:

1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by

design while RθCA is determined by the user's board design.

T J−TA T J−TA
P D (t ) = R θJ A(t )
= R θJ C+RθCA(t )
= I 2D (t ) × RDS(ON ) TJ

Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:

a. 130oC/W when mounted on a 0.125 in2 pad of 2oz cpper.

b. 140oC/W when mounted on a 0.005 in2 pad of 2oz cpper.

c. 180oC/W when mounted on a 0.0015 in2 pad of 2oz cpper.

1a 1b 1c

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

NDC7002N.SAM
Typical Electrical Characteristics

1.5 3
V GS =10V
8.0 7.0 VGS = 3.5V
6.0 4.0

DRAIN-SOURCE ON-RESISTANCE
I D , DRAIN-SOURCE CURRENT (A)

1.2 2.5 4.5

5.5

RDS(on) , NORMALIZED
5.0
5.0 2
0.9 5.5
4.5 6.0
1.5 7.0
0.6
4.0 8.0
10
1
0.3 3.5

3.0 0.5
0 0.3 0.6 0.9 1.2 1.5
0
0 1 2 3 4 5 I D , DRAIN CURRENT (A)

VDS , DRAIN-SOURCE VOLTAGE (V)

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Gate

Voltage and Drain Current.

2 2.5

1.8 I D = 0.51A V GS = 10V

DRAIN-SOURCE ON-RESISTANCE
DRAIN-SOURCE ON-RESISTANCE

V GS = 10V
1.6 2
R DS(ON), NORMALIZED

TJ = 125°C
R DS(on), NORMALIZED

1.4

1.2 1.5

1
25°C
0.8 1

0.6 -55°C

0.4 0.5
-50 -25 0 25 50 75 100 125 150 0 0.3 0.6 0.9 1.2 1.5
TJ , JUNCTION TEMPERATURE (°C) I , DRAIN CURRENT (A)
D

Figure 3. On-Resistance Variation with Figure 4. On-Resistance Variation with Drain

Temperature. Current and Temperature.

1.5 1.2
V DS = 10V T = -55°C V DS = V GS
J
GATE-SOURCE THRESHOLD VOLTAGE

25°C
1.2 125°C 1.1 I D = 250µA
I D , DRAIN CURRENT (A)

V th, NORMALIZED

0.9 1

0.6 0.9

0.3 0.8

0 0.7
1 2 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 150
V GS , GATE TO SOURCE VOLTAGE (V) TJ , JUNCTION TEMPERATURE (°C)

Figure 5. Transfer Characteristics. Figure 6. Gate Threshold Variation with

Temperature.

NDC7002N.SAM
Typical Electrical Characteristics (continued)
DRAIN-SOURCE BREAKDOWN VOLTAGE

1.16 1.5
I D = 250µA 1 V GS = 0V
1.12 0.5

I S , REVERSE DRAIN CURRENT (A)

1.08
BV DSS , NORMALIZED

TJ = 125°C
0.1 25°C
1.04 -55°C

0.96 0.01

0.92

0.88
-50 -25 0 25 50 75 100 125 150 0.001
0.2 0.4 0.6 0.8 1 1.2
TJ , JUNCTION TEMPERATURE (°C)
V SD , BODY DIODE FORWARD VOLTAGE (V)

Figure 7. Breakdown Voltage Variation with Figure 8. Body Diode Forward Voltage Variation
Temperature. with Current and Temperature.

100 10

VDS = 25V
50
V GS , GATE-SOURCE VOLTAGE (V)

8 I D = 0.51A
C iss
CAPACITANCE (pF)

20
6
C oss
10

4
C rss
5

f = 1 MHz 2
2 V GS = 0 V

1 0
0.1 0.2 0.5 1 2 5 10 20 50 0 0.2 0.4 0.6 0.8 1 1.2
V DS , DRAIN TO SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC)

Figure 9. Capacitance Characteristics. Figure 10. Gate Charge Characteristics.

0.7
V DS = 10V
0.6 T = -55°C
J

0.5 25°C
I D , DRAIN CURRENT (A)

0.4

125°C
0.3

0.2

0.1

0
0 0.3 0.6 0.9 1.2 1.5
V , GATE TO SOURCE VOLTAGE (V)
GS

Figure 11. Transconductance Variation with Drain

Current and Temperature.

NDC7002N.SAM
Typical Thermal Characteristics

1.2 0.55
STEADY-STATE POWER DISSIPATION (W)

I D , STEADY-STATE DRAIN CURRENT (A)

1.1 1a

0.5
1 1a

1b

0.9 1b 0.45 1c

0.8
1c
0.4
4.5"x5" FR-4 Board
0.7 4.5"x5" FR-4 Board o
o TA = 2 5 C
TA = 2 5 C
Still Air
Still Air
VG S = 1 0 V
0.6 0.35
0 0.2 0.4 0.6 0.8 1 0 0.025 0.05 0.075 0.1 0.125
2oz COPPER MOUNTING PAD AREA (in 2 ) 2
2oz COPPER MOUNTING PAD AREA (in )

Figure 12. SOT-6 Dual Package Maximum Figure 13. Maximum Steady-State Drain
Steady-State Power Dissipation versus Copper Current versus Copper Mounting Pad
Mounting Pad Area. Area.

3
2
IT 10
LIM 0
N)
1 S(O 1m us
RD s
I D , DRAIN CURRENT (A)

0.5 10
ms

0.2 10
0m
s
0.1
V = 10V 1s
GS DC
0.05 SINGLE PULSE
R θJ A = See Note 1c
0.02 T A = 25°C

0.01
1 2 5 10 20 50 70
V DS , DRAIN-SOURCE VOLTAGE (V)

Figure 14. Maximum Safe Operating Area.

0 .5 D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE

R JA (t) = r(t) * R JA
θ θ
R JA = See Note 1c
0 .2 0.2 θ

0.1
0 .1 P(pk)

0.05
0.05 t1
t2
0.02
0.01 TJ - T = P * R JA (t)
A θ
0.02 Single Pulse
Duty Cycle, D = t 1 / t 2

0.01
0 .0 0 0 1 0 .001 0 .0 1 0 .1 1 10 100 300
t 1, TIME (sec)

Figure 15. Transient Thermal Response Curve.

Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.

NDC7002N.SAM
 SuperSOTTM-6 Tape and Reel Data and Package Dimensions

SSOT-6 Packaging
Configuration: Figur e 1.0
Packaging Description:
Customize Label SSOT-6 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
Anti static Cover Tape 3,000 units per 7" or 177cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (anti-
static coated). Other option comes in 10,000 units per 13"
or 330cm diameter reel. This and some other options are
described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a pizza box (illustrated in figure 1.0) made of
recyclable corrugated brown paper with a Fairchild logo
printing. One pizza box contains three reels maximum.
And these pizza boxes are placed inside a barcode
labeled shipping box which comes in different sizes
depending on the number of parts shipped.

F63TNR Embossed
Label Carrier Tape

631
631 631 631 631
SSOT-6 Packaging Information
Pin 1
Standard
Packaging Option D87Z
(no f l ow c ode )
Packaging type TNR TNR SSOT-6 Unit Orientation
Qty per Reel/Tube/Bag 3,000 10,000
Reel Size 7" Dia 13"
Box Dimension (mm) 184x187x47 343x343x64
Max qty per Box 9,000 30,000
Weight per unit (gm) 0.0158 0.0158 343mm x 342mm x 64mm F63TNR Label
Weight per Reel (kg) 0.1440 0.4700 Intermediate box fo r D87Z Option
Note/Comments

F63TNR
Label

F63TNR Label sa mpl e

F63TNR
184mm x 187mm x 47mm Label LOT: CBVK741B019 QTY: 3000

Pizza Box fo r Standar d Opti on FSID: FDC633N SPEC:

D/C1: D9842 QTY1: SPEC REV:

SSOT-6 Tape Leader and Trailer D/C2: QTY2: CPN:
N/F: F (F63TNR)3
Configuration: Figur e 2.0

Carrier Tape

Cover Tape
Comp onent s
Traile r Tape Lead er Tape
300mm mi nimum or 500mm mi nimum or
75 empty poc kets 125 emp ty poc kets

1998 Fairchild Semiconductor Corporation August 1999, Rev. C

SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued
SSOT-6 Embossed Carrier Tape
Configuration: Figure 3.0 P0 D0
T
E1

K0 W
E2
Wc B0

Tc
A0 P1 D1

User Direction of Feed

Dimensions are in millimeter

Pkg type A0 B0 W D0 D1 E1 E2 F P1 P0 K0 T Wc Tc

SSOT-6 3.23 3.18 8.0 1.55 1.125 1.75 6.25 3.50 4.0 4.0 1.37 0.255 5.2 0.06
(8mm) +/-0.10 +/-0.10 +/-0.3 +/-0.05 +/-0.125 +/-0.10 min +/-0.05 +/-0.1 +/-0.1 +/-0.10 +/-0.150 +/-0.3 +/-0.02

Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C). 0.5mm
20 deg maximum maximum

Typical
component
cavity 0.5mm
B0 center line maximum

20 deg maximum component rotation

Typical
Sketch A (Side or Front Sectional View) component Sketch C (Top View)
A0 center line
Component Rotation Component lateral movement
Sketch B (Top View)
SSOT-6 Reel Configuration: Figure 4.0 Component Rotation

W1 Measured at Hub

Dim A
Max

Dim A See detail AA

max Dim N

7" Diameter Option

B Min

Dim C

See detail AA
Dim D
W3 min

13" Diameter Option W2 max Measured at Hub

DETAIL AA

Dimensions are in inches and millimeters

Reel
Tape Size Dim A Dim B Dim C Dim D Dim N Dim W1 Dim W2 Dim W3 (LSL-USL)
Option
7.00 0.059 512 +0.020/-0.008 0.795 2.165 0.331 +0.059/-0.000 0.567 0.311 – 0.429
8mm 7" Dia
177.8 1.5 13 +0.5/-0.2 20.2 55 8.4 +1.5/0 14.4 7.9 – 10.9

13.00 0.059 512 +0.020/-0.008 0.795 4.00 0.331 +0.059/-0.000 0.567 0.311 – 0.429
8mm 13" Dia
330 1.5 13 +0.5/-0.2 20.2 100 8.4 +1.5/0 14.4 7.9 – 10.9

July 1999, Rev. C

 SuperSOTTM-6 Tape and Reel Data and Package Dimensions, continued

SuperSOT -6 (FS PKG Code 31, 33)

1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0158

1998 Fairchild Semiconductor Corporation September 1998, Rev. A

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.

ACEx™ ISOPLANAR™ SyncFET™

CoolFET™ MICROWIRE™ TinyLogic™
CROSSVOLT™ POP™ UHC™
E2CMOSTM PowerTrench  VCX™
FACT™ QFET™
FACT Quiet Series™ QS™
FAST® Quiet Series™
FASTr™ SuperSOT™-3
GTO™ SuperSOT™-6
HiSeC™ SuperSOT™-8
DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
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As used herein:
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the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. D