AVR ATmega128 Interrupts Cheat-Sheet

Contents
1 Interrupt Vectors and their Descriptions for ATmega128 2

2 External Interrupts 2

3 Ports 3

4 Sleep Mode 4

5 Timers 5
5.1 Intro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.2 Timer 1,3 Operation Control . . . . . . . . . . . . . . . . . . . . 5
5.3 Timer 0 Operation Control . . . . . . . . . . . . . . . . . . . . . 6
5.4 Timer 2 Operation Control . . . . . . . . . . . . . . . . . . . . . 8
5.5 Timer Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.6 Interrupts and Flags . . . . . . . . . . . . . . . . . . . . . . . . . 9

6 AVR A/D Converter 10

7 Analog Comparator 11

8 Code Snippets 12
8.1 Initialization Routines . . . . . . . . . . . . . . . . . . . . . . . . 12
8.2 Timer 0: CTC, Pin toggle, ISR . . . . . . . . . . . . . . . . . . . 13
8.3 Polling for an A/D conversion . . . . . . . . . . . . . . . . . . . . 14

1
 1 Interrupt Vectors and their Descriptions for
ATmega128

Table 1: Interrupt Vectors of ATmega128

Number Vector Name Device Trigger
1 $0000 RESET Many :P
2 $0002 INT0 External Interrupt 0
3 $0004 INT1 External Interrupt 1
4 $0006 INT2 External Interrupt 2
5 $0008 INT3 External Interrupt 3
6 $000A INT4 External Interrupt 4
7 $000C INT5 External Interrupt 5
8 $000E INT6 External Interrupt 6
9 $0010 INT7 External Interrupt 7
10 $0012 Timer2 Compare Timer/Counter2 Compare Match
11 $0014 Timer2 Overflow Timer/Counter2 Overflow
12 $0016 Timer1 Capt Timer/Counter1 ”Capture” Event
13 $0018 Timer1 COMPA Timer/Counter1 Compare Match A
14 $001A Timer1 COMPB Timer/Counter1 Compare Match B
15 $001C Timer1 Overflow Timer/Counter1 Overflow
16 $001E Timer0 COMP Timer/Counter0 Compare Match
17 $0020 Timer0 OVF Timer/Counter0 Overflow
18 $0022 SPI STC SPI Serial Transfer Complete
19 $0024 USART0 Rx USART0 Receive Complete
20 $0026 USART0 DRE USART0 Data Register Empty
21 $0028 USART0 Tx USART0 Transfer Complete
22 $002A ADC A/D Converter Conversion Complete
23 $002C EE READY EEPROM Ready
24 $002E ANALOG COMP Analog Comparator
25 $0030 TIMER1 COMPC Timer/Counter1 Compare Match C
26 $0032 TIMER3 CAPT Timer/Counter3 Capture Event
27 $0034 TIMER3 COMPA Timer/Counter3 Compare Match A
28 $0036 TIMER3 COMPB Timer/Counter3 Compare Match B
29 $0038 TIMER3 COMPC Timer/Counter3 Compare Match C
30 $003A TIMER3 OVF Timer/Counter3 Overflow
31 $003C USART1 Rx USART1 Receive Complete
32 $003E USART1 DRE USART1 Data Register Empty
33 $0040 USART1 Tx USART1 Transfer Complete
34 $0042 TWI Two-Wire Iface
35 $0044 SPM Ready PM St Prog Mem Rdy

2 External Interrupts
Registers: EIMSK, EIFR, EICRA, EICRB, MCUCR

2
 Enabling Interrupts To enable an external interrupt INTn, n=(0-7), enable
(logical 1) bit n in register EIMSK:

EIMSK BIT 7 6 5 4 3 2 1 0
INTn 7 6 5 4 3 2 1 0

Polling and Flags When an interrupt happens, bit n of EIFR is set to 1.

The flag is cleared when the interrupt routine is executed. Alternatively, you
can clear INTFn by writing 1 (not 0!) to it.

EIFR BIT 7 6 5 4 3 2 1 0
INTFn 7 6 5 4 3 2 1 0

Interrupt Settings Finally, to set the trigger of interrupt INTn, choose one
of these functions:
bit ISCn1 bit ISCn0 what triggers an interrupt
0 0 Low level of input causes interrupt
0 1 Reserved (n=0-3), Any change(n=4-7)
1 0 Falling edge causes interrupt
1 1 Rising edge causes interrupt

Interrupt Sense Control Bits 0 and 1 for each of the 8 external interrupts
are arranged into EICRA and EICRB.
EICRA BIT 7 6 5 4 3 2 1 0
ISC ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00
EICRB BIT 7 6 5 4 3 2 1 0
ISC ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40

3 Ports
ATmega128 has 4 external ports, A, B, C, D. Each port has 3 assigned registers.
For these tables, x={A, B, C, D}

PORTx is used for writing data to port x by using out PORTx, Temp.

PINx is used to read data from port x by using in Temp, PINx.

DDRx sets which bits of port x will be used for input and which for output:
ldi Temp, 0b11110000
out DDRB, Temp
lets us use PORTB7 - PORTB4 for output and PINB3 - PINB0 for input. The
full function of ports, as well as pull-up resistors, is summarized in Table 3. The
alternative function of PORTB pins is in Table 3

3
 Table 2: Port Function
DDxn PORTxn PUD (SFIOR Bit) I/O PUR Comment
0 0 X Input No Tri-state (High impendance)
0 1 0 Input Yes Pin will source current if exit is low
0 1 1 Input No Tri-state (High impendance)
1 0 X Output No Output low (Sink)
1 1 X Output No Output high (Source)

Table 3: Alternative PORTB Function

Pin Alternative Function
7 Timer 2 output
6 Timer 1 output compare B
5 Timer 1 output compare A
4 Timer 0 output
3 MISO (SPI Bus Master In Slave Out)
2 MOSI (SPI Bus Master Out Slave In)
1 SCK (SPI Serial Clock)
0 SS (SPI Slave Select)

4 Sleep Mode
AVR can enter a sleep mode to reduce energy consumption and noise (during
A/D Conversions). The sleep functionality is defined by bits 5 - 2 of MCUCR,
and sleep mode starts with the sleep command.
BIT 5 4 3 2
Name SE SM1 SM0 SM2

• SE - This bit has to be set to 1 before a sleep command is executed,

otherwise AVR will not go to sleep. Good practice dictates setting the bit
to 0 when AVR wakes up.

• SM2:0 - Select from the available sleep modes (see Table 4)

Sleep Modes Description

Table 4: ATmega128 Sleep Modes

SM2:0 Mode
000 Idle
001 A/D Converter Noise Reduction
010 Power-down
011 Power-save
100 Reserved
101 Reserved
110 Standby
111 Extended Standby

4
 • Idle: SPI, USART, AnComp, A/DC, TWSI, Timers, Watchdog, Inter-
rupts are on (only CPU clock off)
• ADCNR: ADC, External Interrupts, TWSI, Timer0, Watchdog are on. A
conversion starts automatically (if A/D is turned on)
• Power-Down: External Interrupts, TWSI, Watchdog are on
• Power-Save: Same as Power-Down. If AS0 in ASSR is 1, TCCNT0 will
run and cause a wake-up on overflow or Output Compare
• Standby: If an external crystal is selected, this makes MCU go into
standby for 6 cycles
• Ext. Standby: Same as Standby, but TCCNT0 keeps running

5 Timers
5.1 Intro
ATmega128 has four timers:
1. Timer/Counter 0: 8-bit counter
2. Timer/Counter 1: 16-bit counter
3. Timer/Counter 2: 8-bit counter
4. Timer/Counter 3: 16-bit counter
Each timer comes with its own Timer/Counter Control Register (TCCRn).
In addition, 16-bit timers (n=1,3) also provide an Output Compare Register
(TCCRn) and an Input Capture Register (ICRn).
Timer interrupts are masked by Timer Interrupt Mask Register (TIMSK)
and the corresponding flags are stored in Timer Interrupt Flag Register (TIFR).

TCNTn Register 8-bit timers store their content in TCNT0 and TCNT2,
respectively. 16-bit timers use double-buffered registers TCNTnL and TCNTnH
to store their content. Specific care must be taken to load or store values in these
registers: When TCNTnL is read, hardware copies the content of TCNTnH to
a temporary register. After that, the correct value of TCNTnH can be read:
in r16, TCNT1L ; When this is done, Temp <- TCNT1H
in r17, TCNT1H ; Not the actual content of TCNT1H
This is done so a change in the timer value won’t mess up the values read:
If TCNT1H is 00000000 and TCNT1L is 11111111, reading TCNT1L without
using Temp would result in probably reading TCNT1H value as 00000001.

5.2 Timer 1,3 Operation Control

TCCRnA Register The register is described below
Bit 7 6 5 4 3 2
Name COMnA1 COMnA0 COMnB1 COMnB0 COMnC1 COMnC0
Bit 1 0
Name WGM1 WGM0

5
 • Bits 7-2 set the Compare Output Mode for channels A, B, and C
• Bits 1 and 0 control waveform generation. (see Table 6)

TCCRnB Register The register is described below

Bit 7 6 5 4 3 2 1 0
Name ICNCn ICESn — WGMn3 WGMn2 CSn2 CSn1 CSn0

• Bit 7: Input Capture Noise Canceler

• Bit 6: Input capture: 0 means capture falling edge, 1 means capture rising
edge
• Bit 5: Reserved
• Bits 4-3 control waveform generation. (see Table 6)
• Bits 2-0 are used to select a clock (see Table 5)

Table 5: Clock Options - Timers 1, 2, 3

CSn2 CSn1 CSn0 Clock
0 0 0 No clock. Timer n disabled
0 0 1 prescaling = 1
0 1 0 prescaling = 1/8
0 1 1 prescaling = 1/64
1 0 0 prescaling = 1/256
1 0 1 prescaling = 1/1024
1 1 0 Pin Tn clock source(external), falling edge
1 1 1 Pin Tn clock source(external), rising edge

5.3 Timer 0 Operation Control

Timer0 is the only timer that can be set not to get its clock from the CPU.
This enables Timer0 to function when the AVR main module is in sleep mode
(asynchronous operation). The external oscillator is clocked at 32,768KHz. At
column 5 of Table 7, the real time function of the timer can be seen.

TCCR0 Register The register is described below

BIT 7 6 5 4 3 2 1 0
Function FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00

• FOC0 - Force Output Compare (for non-PWM modes)

• COM0[0:1] - Select a Compare Output Option (See Tables 8, 9 and 10)
• CS0[0:2] - Select a clock source (WARNING: Different from Timer1-3)
(See Table 7)
• WGM2[1:0] - Select a waveform generation mode (See Table 11)

6
 Table 6: Waveform Generation Mode
Mode WGMn3:0 Mode TOP Update of OCRnx TOV Flag Set
0 0000 Normal 0xFFFF Immediate MAX
1 0001 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM
2 0010 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM
3 0011 PWM, Phase Correct,10-bit 0x03FF TOP BOTTOM
4 0100 CTC OCRnA Immediate MAX
5 0101 Fast PWM, 8-bit 0x00FF BOTTOM TOP
6 0110 Fast PWM, 9-bit 0x01FF BOTTOM TOP
7 0111 Fast PWM,10-bit 0x03FF BOTTOM TOP
8 1000 PWM Ph&Freq Correct ICRn BOTTOM TOP
9 1001 PWM Ph&Freq Correct OCRnA BOTTOM BOTTOM
10 1010 PWM, Phase Correct ICRn TOP BOTTOM
11 1011 PWM, Phase Correct OCRnA TOP BOTTOM
12 1100 CTC ICRn IMMEDIATE MAX
13 1101 reserved - - -
14 1110 FAST PWM ICRn BOTTOM TOP
15 1111 FAST PWM OCRnA BOTTOM TOP

Table 7: Clock Options - Timer0

CSn2 CSn1 CSn0 Clock Real Time Tick
0 0 0 No clock. Timer 0 disabled -
0 0 1 prescaling = CK -
0 1 0 prescaling = CK/8 1/8s
0 1 1 prescaling = CK/32 1/4s
1 0 0 prescaling = CK/64 1/2s
1 0 1 prescaling = CK/128 1s
1 1 0 prescaling = CK/256 2s
1 1 1 prescaling = CK/1024 8s

ASSR - Asynchronous Status Register This register controls asynchronous

function
BIT 3 2 1 0
Function AS0 TCN0UB OCR0UB TCR0UB
Bits 7:4 of the ASSR are not used. The function of bits 3:0 is as follows:

• Bit 3 - Asynchronous Timer0: When this bit is set to 0, Timer0 is clocked

from the I/O clock. When it is set to 1, Timer0 is clocked from an oscillator
at TOSC1 pin.
• Bits 2:0 - These indicate that the respective register (TCNT0, OCR0,
TCCR0) has been written sucessfully. They are used because, in asyn-
chronous mode, writing a value to one of these registers does not immedi-
ately update their value, but an intermediary temporary register is used
(a separate temp register is used for each). When the update is complete,
these bits are cleared by hardware.

7
 5.4 Timer 2 Operation Control
TCCR2 Register The register is described below
BIT 7 6 5 4 3 2 1 0
Function FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20

• FOC2 - Force Output Compare (for non-PWM modes)

• COM2[0:1] - Select a Compare Output Option (See Tables 8, 9 and 10)
• CS2[0:2] - Select a clock source (See Table 5 )
• WGM2[1:0] - Select a waveform generation mode (See Table 11)

Table 8: Timer0, Timer2 - Compare Output for non-PWM modes

COMn1 COMn0 Description
0 0 Normal Port Operation
0 1 Toggle OCn on compare match
1 0 Clear OCn on compare match
1 1 Set OCn on compare match

Table 9: Timer0, Timer2 - Compare Output for Fast PWM mode

COMn1 COMn0 Description
0 0 Normal Port Operation
0 1 Reserved
1 0 Clear OCn on compare match, set OCn at TOP
1 1 Set OCn on compare match, clear OCn at TOP

Table 10: Timer0, Timer2 - Compare Output for Phase Correct PWM mode
COMn1 COMn0 Description
0 0 Normal Port Operation
0 1 Reserved
1 0 Clear OCn on compare match when up counting set OCn in inverse
1 1 Set OCn on compare match when up counting, clear OCn in inverse

Table 11: Timer0, Timer2 - Waveform Generation Mode

Mode WGMn1:0 Mode TOP Update of OCR2 TOV flag
0 00 Normal 0xFF Immediate MAX
1 01 PC-PWM 0xFF Top BOTTOM
2 10 CTC OCRn Immediate MAX
3 11 Fast PWM 0xFF TOP MAX

8
 5.5 Timer Output
By setting the proper mode in the COM bits, the timer can automatically (i.e.,
without software intervention) change the logic level of some port bits. Table 3
shows the output pins for each timer. In order for these to be used as output,
a logical 1 must be written in the corresponding DDRB pin.

5.6 Interrupts and Flags

TIFR Register The Timer Interrupt Flag Register is described below:
BIT 7 6 5 4 3 2 1 0
Function OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0
• OCF2 - Timer 2 value == OCR2
• TOV2 - Timer 2 Overflow
• ICF1 - Capture in Input Capture 1 (ICP1). If IC is to be used as TOP,
ICF1=1 means counter reached TOP
• OCF1A - Timer1 Matches OCR1A
• OCF1B - Timer1 Matches OCR1B
• TOV1 - normal/CTC mode: Timer1 Overflow. Otherwise according to
Table 6
• OCF0 - Timer0 == OCR0
• TOV0 - Timer0 overflow

TIMSK Register The Timer Interrupt Mask Register is described below:

BIT 7 6 5 4 3 2 1 0
Function OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0
• OCIE2 - Timer 2 Output Compare Interrupt
• TOIE2 - Timer 2 Overflow Interrupt
• TICIE1 - Timer1 Input Capture Interrupt
• OCIE1A - Timer1 Output Compare A Interrupt

• OCIE1B - Timer1 Output Compare B Interrupt

• TOIE1 - Timer1 Overflow Interrupt
• OCIE0 - Timer0 Output Compare Interrupt

• TOIE0 - Timer0 Overflow Interrupt

9
6 AVR A/D Converter
ATmega128 has an embedded A/D Converter. It converts analog signals present
in some of the PORTF pins to digital values, stored in ADCL and ADCH
V
registers. The input range [0 Vref ] is split in 2n intervals of width Q = 2ref
n .

For Vref =2.56V and n = 10, Q = 2.5mV. The digital output is calculated:
Y = round( VQin ) and is presented in ADCL and ADCH. If a differential input is
used, the output is in two’s complement.
The ADC is controlled by registers ADMUX and ADCSR.

ADMUX Register The Register is described below:

BIT 7 6 5 4 3 2 1 0
Function REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0

• REFS1:0 control the reference signal source (See Table 12)

• ADLAR: if set to 0, the result stored in ADCH/ADCL is right-aligned
(ADC9:8 in ADCH, rest in ADCL). If set to 1, ADC9:2 in ADCH, rest in
ADCL.
• MUX4:0 set an analog channel and a gain from the multiplexer (See table
13)

ADCSRA Register The register is described below:

BIT 7 6 5 4 3 2 1 0
Function ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0

Table 12: ADC Reference Voltage Options

REFS1:0 Voltage Reference
00 External Reference Voltage on pin AREF
01 AVCC with an external capacitor on pin AREF
10 Reserved
11 Internal Vref = 2.56V with external capacitor on pin AREF

• ADEN Enables the ADC

• ADSC Write 1 to start a conversion. In free running mode, the first
conversion will take 25 ADC cycles, and the rest will take 13
• ADFR Write 1 to operate ADC in free running mode (continuously read,
convert and update registers)

• ADIF A/D Converter flag, meaning end of conversion.

• ADIE A/D Converter interrupt enable.
• ADPS2:0 Prescaler Selection (See Table 14)

10
 Table 13: Analog Signal Options
MUX4:0 Input + Input - Gain MUX4:0 Input + Input - Gain
00000 ADC0 1 10000 ADC0 ADC1 1
00001 ADC1 1 10001 ADC1 ADC1 1
00010 ADC2 1 10010 ADC2 ADC1 1
00011 ADC3 1 10011 ADC3 ADC1 1
00100 ADC4 1 10100 ADC4 ADC1 1
00101 ADC5 1 10101 ADC5 ADC1 1
00110 ADC6 1 10110 ADC6 ADC1 1
00111 ADC7 1 10111 ADC7 ADC1 1
01000 ADC0 ADC0 10 11000 ADC0 ADC2 1
01001 ADC1 ADC0 10 11001 ADC1 ADC2 1
01010 ADC0 ADC0 200 11010 ADC2 ADC2 1
01011 ADC1 ADC0 200 11011 ADC3 ADC2 1
01100 ADC2 ADC2 10 11100 ADC4 ADC2 1
01101 ADC3 ADC2 10 11101 ADC5 ADC2 1
01110 ADC2 ADC2 200 11110 1.22 V
01111 ADC3 ADC2 200 11111 0V

Table 14: A/D Converter Prescaler Options

ADPS2:0 Division Factor
000 2
001 2
010 4
011 8
100 16
101 32
110 64
111 128

7 Analog Comparator
The analog comparator of AVR compares two inputs and sets its output to 1
if Ain0 > Ain1 . It can be set to trigger Timer1’s Input Capture. It also has a
dedicated interrupt. AnComp’s inputs are PORTE2 and PORTE3 (Ain0 , Ain1 )

ACSR The Analog Comparator Status Register is described below.

BIT 7 6 5 4 3 2 1 0
Function ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0

• ACD - If set to 1, analog comparator is disabled

• ACBG - Select fixed voltage (1.4V) instead of Ain0
• ACO - Output of analog comparator
• ACI - Interrupt flag according to event selected by ACIS1:0
• ACIE - Analog Comparator Interrupt Enable

11
 • ACIC - Analog Comparator Input Capture Enable: Input Capture of
Timer1 will be triggered by AnComp.
• ACIS1:0 - Interrupt Select (See Table 7)

Table 15: Analog Comparator Interrupt Options

ACIS1:0 Interrupt Mode
00 Interrupt on toggle
01 Reserved
10 Interrupt on falling edge
11 Interrupt on rising edge

Analog Comparator - Multiplexed Input In the Special Function I/O

Register (SFIOR), bit 3 (ACME, Analog Comparator Multiplexer Enable) can
enable the AnComp Multiplexer. If this bit is set to 1, and the A/D converter
is turned off (bit ADEN of ADCSRA is 0), the A/D Converter’s MUX provides
the negative input to the analog comparator. Table 7 describes this function.

Table 16: Analog Comparator Multiplexer

ACME ADEN MUX2:0 AnComp Negative Input is...
0 x xxx AIN1
1 1 xxx AIN1
1 0 000 ADC0
1 0 001 ADC1
1 0 010 ADC2
1 0 011 ADC3
1 0 100 ADC4
1 0 101 ADC5
1 0 110 ADC6
1 0 111 ADC7

8 Code Snippets
8.1 Initialization Routines
. i n c l u d e ” m128def . i n c ” ; alias file
. d e f temp = r 1 6 ; definition
. equ p i = 3 . 1 4 1 5 9 ; constant

. dseg ; data segment

. o r g $0100
a r r a y .BYTE 256

. cseg
. o r g $0

12
jmp r e s e t ; reset interrupt vector
. o r g $xx
jmp ISR ; some ISR v e c t o r

reset :

ldi temp , low ( ramend )

out SPL , temp
ldi temp , h i g h ( ramend )
out SPH, temp ; Stack p o i n t e r t o end o f RAM

; h e r e you s e t up any p e r i p h e r a l s you want t o s t a r t i m m e d i a t e l y . Example :

l d i temp , 0 b10100100
out ADCSRA, temp ; f o r example , t h e A/D c o n v e r t e r

sei ; i f you want i n t e r r u p t s from t h e b e g i n n i n g

main :
...
8.2 Timer 0: CTC, Pin toggle, ISR

. o r g $0
jmp r e s e t
. o r g $20
jmp T0 ISR

reset :
...

; timer 0 setup
l d i temp , 120
out OCR0, temp ; compare t i m e r with v a l u e 120

s b i DDRB, 4 ; t i m e r 0 output on PORTB, 4

s b i ASSR, 3 ; s e l e c t a s y n c h r o n o u s mode −> one t i m e r c i r c l e i s 0 . 2 5 s

l d i temp , 0 b00011011
out TCCR0, temp ; s e t p r e s c a l i n g t o 1 / 3 2 , CTC mode , t o g g l e output .
; timer s t a r t s !
c l r temp

main :
rjmp main

...
T0 ISR :
push temp
i n temp , SREG

13
push temp

; l e t ’ s say we i n c r e a s e t h e output o f PORTD by one on e v e r y t i m e r o v e r f l o w

i n temp , PIND ; read current value
i n c temp
out PORTD, temp ; update output

pop temp
out SREG, temp
pop temp
reti
8.3 Polling for an A/D conversion

. i n c l u d e ” m128def . i n c ” ; alias file

. d e f temp = r 1 6 ; definition
. o r g $0
jmp r e s e t

reset :

ldi temp , low (RAMEND)

out SPL , temp
ldi temp , h i g h (RAMEND)
out SPH, temp ; s t a c k i n i t i a l i z e d

; s e t up ADC c h a n n e l 3 , no a l i g n m e n t avcc v o l t a g e
l d i temp , 0 b010000111
out ADMUX, temp
; now ADCSRA
l d i temp , 0 b10100010
out ADCSRA, temp
s b i ADCSRA, ADSC ; s t a r t c o n v e r s i o n , we have f r e e r u n n i n g mode s o we do i t once
main :
s b i s ADCSRA, ADIF ; s k i p i f end o f c o n v e r s i o n
rjmp main
s b i ADCSRA, ADIF ; c l e a r i t
; do work h e r e
rjmp main

14