6.

ΑΝΑΛΟΓΙΚΟΣ ΣΥΓΚΡΙΤΗΣ

Συγκρίνει δύο αναλογικές εισόδους και θέτει Ο =1 , εάν V1 >V2

 6.1. ANALOG COMPARATOR Mega128

The Analog Comparator compares AIN0 and AIN1. When the voltage on AIN0
is higher than the voltage on AIN1, the Analog Comparator Output, ACO, is
set. The comparator’s output can be set to trigger the Timer/Counter1 Input
Capture function. In addition, the comparator can trigger a separate interrupt,
exclusive to the Analog Comparator.
6.2. Ακροδέκτες αναλογικού συγκριτή
• AIN1/OC3A – Port E, Bit 3
AIN1 – Analog Comparator Negative input. This pin is directly connected to
the negative input of the Analog Comparator.

• AIN0/XCK0 – Port E, Bit 2

AIN0 – Analog Comparator Positive input. This pin is directly connected to the
positive input of the Analog Comparator.
 6.3. Προγραμματισμός αναλογικού συγκριτή

SFIOR
ADCSRA
 6.3.1. Analog comparator Control and Status register - ACSR

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is
switched off. This bit can be set at any time to turn off the Analog Comparator.
This will reduce power consumption in Active and Idle mode. When changing
the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the
ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive
input to the Analog Comparator. When this bit is cleared, AIN0 is applied to
the positive input of the Analog Comparator. ATmega128 features an internal
bandgap reference. This reference is used for Brownout Detection (VCC is
below the Brown-out Reset threshold (VBOT)) and it can be used as an input to
the Analog Comparator or the ADC. The 2.56V reference to the ADC is also
generated from the internal bandgap reference. See “Internal Voltage
Reference” on page 52 (ATmega128 datasheet).
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly
connected to ACO. The synchronization introduces a delay of 1 – 2 clock
cycles. Refer also to pin ACIC.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the
interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator
Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set.
ACI is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
NOTICE, that if another bit in this register is modified using the SBI or CBI
instruction, ACI will not be cleared (atomic operation) if it has become set
before the operation.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is
set, the Analog Comparator interrupt is activated. When written logic zero,
the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the Input Capture function in
Timer/Counter1 to be triggered by the Analog Comparator. The comparator
output is in this case directly connected to the Input Capture front-end logic,
making the comparator utilize the noise canceler and edge select features of
the Timer/Counter1 Input Capture interrupt. When written logic zero, no
connection between the analog comparator and the Input Capture function
exists. To make the comparator trigger the Timer/Counter1 Input Capture
interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must
be set.
Input Capture Unit of Timer 1
The main trigger source for the Input Capture unit is the Input Capture Pin
(ICPn).
Timer/Counter1 can alternatively use the analog comparator output as
trigger source for the Input Capture unit. The Analog Comparator is
selected as trigger source by setting the analog Comparator Input Capture
(ACIC) bit in the Analog Comparator Control and Status Register (ACSR).
Be aware that changing trigger source can trigger a capture.
The Input Capture flag must therefore be cleared after the change.
Both the Input Capture Pin (ICPn) and the Analog Comparator output
(ACO) inputs are sampled using the same technique as for the Tn pin
(Figure 59 on page 142, ATmega128 datasheet). The edge detector is
also identical. However, when the noise canceler is enabled, additional
logic is inserted before the edge detector, which increases the delay by
four system clock cycles. Note that the input of the noise canceler and
edge detector is always enabled unless the Timer/Counter is set in a
Waveform Generation mode that uses ICRn to define TOP.
The noise canceler improves noise immunity by using a simple digital
filtering scheme. The noise canceler input is monitored over four samples,
and all four must be equal for changing the output that in turn is used by
the edge detector.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine the comparator events that trigger the Analog
Comparator interrupt (ACI).
The different settings are shown in Table 93.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt

must be disabled by clearing its Interrupt Enable bit in the ACSR Register.
Otherwise an interrupt can occur when the bits are changed.
6.3.2. Special Function IO Register - SFIOR
6.3.3. ADC Control and Status Register A – ADCSRA

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is
turned off. Turning the ADC off while a conversion is in progress, will
terminate this conversion.

6.3.4 ADC Multiplexer Selection Register – ADMUX

• Bits 2:0 – MUX2:0: Analog Channel Selection Bits

The value of these bits selects which combination of analog inputs are
connected to the Analog Comparator.
6.3.4.1 Analog Comparator Multiplexed Input
 6.4. Προγραμματισμός του Αναλογικού συγκριτή
6.4.1 Xρήση σημαιών (ACO)

This piece of code waits until the output of the

comparator (the ACO-bit in ACSR) goes high.
This way of doing it requires no setup, however,
extremely short pulses can be missed, since the
program runs three clock cycles between each
time the comparator is checked. Another
disadvantage is that the program has to wait for
the output to become negative first, in case the
output is positive when polling starts.
wait_edge1:
sbic ACSR,ACO ;if output is high
rjmp wait_edge1 ; wait
we1_1:sbis ACSR,ACO ;if output is low
rjmp we1_1 ; wait
6.4.2 Χρήση σημαιών (ACI)

wait_edge2:

;***** Initial Hardware setup (assumes ACIE = 0

; from reset)

sbi ACSR,ACIS0
sbi ACSR,ACIS1 ;enable interrupt on
; rising output edge
sbi ACSR,ACI ;write a "1" to the
;ACI flag to clear it
we2_1:;----------------------- user code goes here
sbis ACSR,ACI ;if ACI is low ACI

rjmp we2_1 ; wait more

6.4.3 Interrupt routine (ACI)

This code segment enables Analog Comparator Interrupt on output

toggle.
.org $2E
jmp ana_comp
reset: ………
; ***** Enable Interrupt (assumes ACIE = 0 from reset)*****
ana_Init :
ldi temp,(ACI<<1) ;clear interrupt flag while
;ACIS1/ACIS0=00
out ACSR,temp ;...to select interrupt on toggle
sei ;enable global interrupts
sbi ACSR,ACIE ;enable Analog Comparator
;interrupt
forever: rjmp forever
ana_comp: ….
reti