MOSFET

Dr. Rajan Pandey

Associate Professor, SENSE
 Parasitic Source-Drain Resistance Current in the
I dsat 0 absence of Rs
• If Idsat0  Vg – Vt , I dsat 
I dsat 0 Rs This factor should
1
Short channel MOSFET (Vgs  Vt ) be dimension-less

• Idsat can be reduced by about 15% in a 0.1 µm (100 nm) MOSFET.

Effect is greater in shorter MOSFETs.
• A second effect is an increase in Vdsat :
Vdsat = Vdsat0 + Idsat (Rs + Rd)
where Vdsat0 is the Vdsat in the absence of Rs and Rd.

• What causes the S/D parasitic resistance? The shallow diffusion region under the dielectric spacer is
a contributor to the parasitic resistance. Why shallow diffusion region is needed at first place? The
shallow junction is needed to prevent excessive off-state leakage Ids in short channel transistors.

• The contact resistance is another main source of resistance. The silicide (e.g., TiSi2 or NiSi2) reduces
the sheet resistivity of the N+ (or P+) source–drain regions by a factor of ten. It also reduces the
contact resistance between the silicide and the N+ or P+ Si.
 SALICIDE (Self-Aligned Silicide) Source/Drain

• After the spacer is formed, a Ti or Ni or Mo film is deposited. Annealing causes

the silicide to be formed over the source, drain, and gate. Unreacted metal
(over the spacer) is removed by wet etching.

• If the sheet resistivity of a film is 1 Ω per square, the resistance between

two opposite edges of a square shaped piece of this film will be 1 Ω.
 Definitions of Channel Length
• A circuit designer specifies a channel length in the circuit layout, called
the drawn gate length, Ldrawn. This layout is transferred to a photomask,
then to a photoresist pattern, and finally to the physical gate.

• The final physical gate length, Lg, may not be equal to Ldrawn because
each pattern transfer can introduce some dimensional change.

• Through Optical Proximity Correction (OPC) one can minimize the

difference between Ldrawn and Lg.

• How do we measure Lg? Through scanning electron microscopy (SEM).

• For device analysis and modeling, it is necessary to know the channel

length, L, or effective channel length (Leff) or electrical channel length
(Le) to differentiate it from Ldrawn and Lg.

• The difference between Ldrawn and L is called ∆L.

L  Ldrawn  L
Ldrawn, Lg, and L (also known as Leff or Le) are different in general.
 RX, PC and Well shapes impacting device
a
Design shape
e
RX shape corner rounding Actual shape
c
d

a
PC shape corner rounding C
b
b
L

a
Design shape
Well shape corner RX RX

rounding Actual shape

b
 Extraction of the Series Resistance and the Effective
Channel Length
L  LDrawn  L Measuring ∆L in short transistors is quite difficult.

WCoxe  sVds
I ds  (Vgs  Vt )
Ldrawn  L
I ds ( Ldrawn  L)
Vds 
WCoxe (Vgs  Vt )  s

Include series resistance,

Rds  Rd + Rs ,

Vds Ldrawn  L
 Rds  y = mx + c
I ds WCoxe (Vgs  Vt )  s

= Rds + channel resistance

Method of extracting Rds and ∆L
S/D parasitic resistance
 Interpretation of channel length and its dependence on Vg
The channel length may be interpreted
as the length of the part of the channel The channel is where the conductivity
where the inversion-layer sheet is determined by Vg, not by the
conductivity is larger than the source–drain doping profiles.
source/drain sheet conductivity.

The inversion-layer sheet The channel expands (i.e., L increases

conductivity increases and Rds decreases) with increasing Vg.
with increasing Vg.

Due to increase in the sheet

Any resistance from outside the conductivity
“channel” is attributed to Rds.
 Velocity Overshoot
• This is a clearer data than the room temperature
data, showing that velocity saturates at high field.
This data shows that vsat becomes larger when L is
very small. In the basic velocity-saturation model,
vsat is independent of the channel length.

• When the channel length is sufficiently small,

electrons may pass through the channel in too short
a time for all the energetic carriers to lose energy by
emitting optical phonons.

• As a result, the carriers can attain somewhat higher

• Velocity saturation should not occur in
very short MOSFETs! Why?
• Because velocity overshoot could lift the
limit on Ids.
velocities in very small devices. This phenomenon is
called velocity overshoot. Velocity overshoot frees
the extremely short transistors from the limit of
velocity saturation. But…….  we have something
else that limits…..
 Velocity Overshoot

• The concept of mobility is questionable when the channel length is

comparable to or smaller than the mean free path. The carrier
velocity at the drain end of the channel is limited by the saturation
velocity, which determines Idsat.

• However, when the channel length is reduced much below 100 nm,
the saturation velocity may be greatly raised by velocity overshoot.
In that case, some other limit on Idsat may set in. What is that?
Source Velocity Limit
B is the fraction of carriers
Short channel • Idsat = WBvthxQinv captured by the drain in a real
MOSFET
= WBvthxCoxe(Vgs – Vt) transistor. The rest of the
injected carriers are scattered
• Similar to back toward the source.

I dsat  Wvsat C oxe (Vgs  Vt )

Except that vsat is replaced by vthx, the x-direction component of the

thermal velocity. vthx is about 1.6 x 107 cm/s for electrons and 1 x 107
cm/s for holes in Silicon MOSFETs.

The carrier velocity at the source becomes the limiting factor. There,
the velocity is limited by the thermal velocity, with which the
carriers enter the channel from the source. This is known as the
source injection velocity limit.
 Output Conductance
• Idsat does NOT saturate in the saturation region, especially in short channel devices!
• The slope of the Ids-Vds curve in the saturation region is called the output conductance (gds),
0.4
L = 0.15 m
V gs = 2.5V
Vt = 0.4 V
0.3

I ds (mA/m)
V gs = 2.0V

dI dsat 0.2
g ds  V gs = 1.5V
dVds 0.1 V gs = 1.0V

0.0
0 1 2 2.5
V ds (V)

• A smaller gds is desirable for a large voltage gain, which is beneficial to analog and digital
circuit applications.
• The physical causes of the output conductance are the influence of Vds on Vt and a
phenomenon called channel length modulation.
 Example of an Amplifier
• The transistor operates in the saturation region. A small signal input, vin, is applied.
ids  g msa t  gs  g ds  ds
 g msa t  in  g ds  out Vdd

R
Also, ids   out / R 
out
in
g msat
Eliminating ids  out   in NFET
( g ds  1 / R)

• The voltage gain is vout/vin = gmsat/(gds + 1/R).

• A smaller gds is desirable for large voltage gain. gds must be kept much lower than gmsat.
• The gain can also be increased by using a large R.
• Maximum available gain is gmsat/gds, also called intrinsic voltage gain (for very large R).
Short Channel Effects

Short-channel effects occur in MOSFETs when the channel length is

comparable to the depletion layer widths of the source and drain
junctions. These effects include, in particular, drain-induced barrier
lowering, velocity saturation, and hot carrier degradation.

Drain-induced barrier lowering (DIBL) is a short channel effect in

MOSFETs referring to a reduction of threshold voltage of the transistor
at higher drain voltages.
 Short Channel Effects
Another important short channel effect, is the reduction in effective channel length after pinch-off as the
drain voltage is increased. This effect is not significant in long-channel devices, since the change in L due to
intrusion of the depletion region is a minor fraction of the total channel length. In short channel devices,
however, the effective channel length can be substantially shortened, leading to a slope in the saturated I–V
characteristic.

• Experimental output characteristics of n-channel

and p-channel MOSFETs with 0.1 µm channel
lengths. The curves exhibit almost equal spacing,
indicating a linear dependence of ID on VG, rather
than a quadratic dependence.

• We also see that ID is not constant but increases

somewhat with VD in the saturation region. The p-
channel devices have lower currents because hole
mobilities are lower than electron mobilities.
Short Channel Effects

As MOSFETs are scaled down, potential problems due to short channel effects include hot carrier
generation (electron–hole pair creation) in the pinch-off region, punch-through breakdown
between source and drain, and thin gate oxide breakdown.
 Short Channel Leakage Mechanisms

• Six short-channel leakage mechanisms are illustrated above. I1 is the

reverse-bias pn junction leakage; I2 is the sub-threshold leakage; I3 is
the oxide tunneling current; I4 is the gate current due to hot-carrier
injection; I5 is the GIDL; and I6 is the channel punch-through current.

• Currents I2, I5, and I6 are off-state leakage mechanisms, while I1 and I3
occur in both ON and OFF states. I4 can occur in the off state, but more
typically occurs during the transistor bias states in transition.