ARM Based Development Course Summary-MouliSankaran

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In 40 Hours of Lectures
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ARM Based Development – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com

Outline of ARM Course
 Introduction to ARM architecture family, Condition Flags, Reset, Register set
 ARM Core Dataflow model, ARM 3 stage and 5-stage pipeline organization
 ARM Instruction Set (ARM7TDMI)
 ARM Assembly Language Programming
 Thumb Instructions, Interrupt processing and handling schemes
 ARM coprocessor interface and Instructions, Floating Point Format and VFP
 Memory hierarchy- Cache Memory Organization in ARM
 Memory Protection Units (MPU), Virtual Memory, Memory Mgt (MMU) in
ARM
 ARM programming tools , Architectural support for System Development
 AMBA architecture (AHB, ASB and APB)
 Peripherals (DMA, RTC, ADC, DAC and PWM)
 I2C and SPI protocols , USART and GPIO
 Other ARM Processor cores and Advanced Features
2
References
Note: Manuals and Technical Documents from ARM Inc. have also been referred.
3
Session 1: Focus
 Types of Digital Computer Architectures
◦ von Neumann
◦ Harvard
 Instruction Set Architecture (ISA)
◦ CISC
◦ RISC
 ARM History
 ARM cores as IPs
 ARM Ecosystem
 Market Landscape of ARM
4
Session 2: Focus
 Deviations of ARM from the pure RISC design
 Embedded System Hardware
 Embedded System Software
◦ Various address spaces (code/data/heap/stack)
◦ Sample C program running on ARM based system
 Stack implementation in ARM
 Endianness
 Condition codes (Arithmetic operations)
5
Session 3: Focus
 Processor Core vs CPU Core
 ARM7TDMI Interface signals
 Memory Interface
 Bus Cycle Types
 Register set
 Operational modes
 Exceptions/Interrupts
 Interrupt Vector Table
6
Session 4: Focus
 Instruction format
 ARM Core Dataflow model
 Instruction Pipeline – an Introduction
 ARM 3-stage pipeline organization
 Different stages of the pipeline
 Limitations of 3-stage Pipeline
 ARM family Attribute Comparison
7
Session 5: Focus
 ARM9 5-stage Pipeline
 Various stages of the pipeline
 Pipeline Hazards
 Data Forwarding- a HW solution
 5-stage Pipeline Organization
8
Session 6: Focus
 ARM ISA & Processor Variants
 Different Types of Instructions
 ARM Instruction Set – ARM7TDMI (ARMv4T)
 Conditional Execution
 Data Processing Instructions
9
Session 7: Focus
 Shift operations (on Register Operand-Rm)
◦ Logical Shift Left
◦ Logical Shift Right
◦ Arithmetic Shift Right
◦ Rotate Right
◦ Rotate Right Extended
 Shift operations using Rs lower byte
 Immediate value encoding
◦ For rotate on Immediate value
10
Session 8: Focus
 Data Processing Instructions
◦ Logical Data Processing
◦ Arithmetic Data Processing
◦ Multiword Arithmetic Examples
◦ Using PC (r15) in Data Processing instructions
11
Session 9: Focus
 Addressing Mode 1 (examples)
 Addressing Mode 2
◦ Load/Store Word and Unsigned Byte
◦ Format
◦ Data Path
12
Session 10: Focus
 Addressing Mode 2
◦ 9 Formats
◦ Examples for each
• LDR/STR
◦ R15 usage
◦ Instruction Timing
 Addressing Mode 3 with examples
◦ Load/Store Halfword and Signed Halfword
◦ Load/Store Signed Byte
13
Session 11: Focus
 Instruction Timings Explained
◦ STR
◦ LDR
◦ LDR with PC as Rd
 Addressing Mode 4 with examples
◦ Load/Store Multiple
◦ Stack Implementation using STM/LDM
◦ Different Stack Modes
◦ Stack Limit Checking
14
Session 12: Focus
 Swap Instructions
 Status Register Related Instructions
◦ MRS: Status register to General Register Transfer
◦ MSR: General Register to Status Register Transfer
◦ Restrictions in the usage of MRS/MSR
 Loading Constants
◦ LDR: Load constant Pseudoinstruction
◦ ADR: Load address Pseudoinstruction
15
Session 13: Focus
 Program Control Flow
 Control Flow Instructions
◦ Format
◦ Data Path
◦ Instruction Cycle Timings
 B and BL Instructions
 BX Instruction
16
Session 14: Focus
 Interrupts and Exceptions
• Interrupt Vector Table
• Various types
• Relative Priorities
 Interrupt/Exception Handlers
 Ways to transfer control
 Functions performed
 Reset Handling
 Functions in Reset Handler
17
Session 15: Focus
 Aborts
◦ Prefetch Aborts
◦ Data Abort
 Software Interrupt Instruction (SWI)
◦ Entry
◦ Return
◦ Processing
◦ Example
 Undefined Instruction Exception
18
Session 16: Focus
 Interrupt Latency
◦ FIQ
 Multiply Instructions
◦ MUL and MLA Instructions
◦ UMULL and UMLAL Instruction
◦ SMULL and SMLAL Instructions
 Instruction Set Examples
19
Session 17: Focus
 Thumb state
◦ Design philosophy
◦ Thumb state Entry and Exit
◦ Switching from ARM to Thumb State
 Thumb Programmer’s Model
◦ Registers
◦ ARM & Thumb Similarities and Differences
 Thumb Implementation
◦ Decompressor
◦ Example Thumb to ARM instruction mapping
 Thumb Applications
◦ Thumb Systems
20
Session 18: Focus
 Thumb Instructions
◦ Push and Pop Instructions
◦ Conditional branches
◦ Summary of other instructions
 Interrupt Processing
◦ Exceptions and Associated Modes
◦ Banked Registers & System mode
◦ Setting up Stack for Exception modes
◦ Assigning Interrupts
◦ Handling of Interrupts
21
Session 19: Focus
 Interrupt Handling Schemes
◦ Non-nested Interrupt Handler
◦ Nested Interrupt Handler
◦ Prioritized Simple Interrupt Handler
◦ Other Schemes
 Examples of Interrupt Handlers
◦ Non-nested Handlers
◦ Nested Handlers
22
Session 20: Focus
 Coprocessors
◦ Why coprocessors?
◦ ARM & Coprocessors
◦ Coprocessor Interface
◦ Pipelining in ARM and Coprocessor
◦ Coprocessor Signaling
23
Session 21: Focus
 Coprocessor Instructions
◦ Format
◦ Busy-wait sequences
◦ Cycle times
◦ Example Usages
 Data Processing Instruction (CDP)
 Data Transfers (LDC/STC)
 Register Transfers (MRC/MCR)
24
Session 22: Focus
 Number Representations
◦ Scientific Notation
◦ Normalized numbers
 Floating-point Representation
◦ IEEE 754 Format
◦ Single Precision (32 bits)
 Exponent and Significand
 Biased Exponent
 Range of floating point numbers
 Zero, Infinity and NaN
◦ Quite and Signaling NaNs
◦ Double Precision (64 bits)
25
Session 23: Focus
 Flynn’s Taxonomy
 SIMD and Vector Processors
◦ Philosophy of Vector Processors
◦ Advantages
 Vector Floating Point Processor (VFP)
◦ Architecture Overview
◦ Registers
◦ Features
◦ Exceptions and Support code
◦ Interrupts
 VFP and ARM Interactions
 An Example Vector Operation
26
Session 24: Focus
 Memory Technologies
◦ SRAM
◦ DRAM
◦ CPU vs Memory Gap
 Need for Memory Hierarchy
◦ Locality of reference
 Hierarchical Memory Organization
◦ Relationship between memory levels
◦ Properties of memory levels
◦ Comparison of memory levels
 Virtual Memory
27
Session 25: Focus
 Cache Memory
◦ Organization
◦ Performance
◦ Design Elements
 Mapping Functions
◦ Direct Mapped Cache
◦ Fully Associative Cache
◦ Set-Associative Cache
28
Session 26: Focus
 Cache Design
◦ Block Replacement
◦ Write policies
 Write through
 Write back
 Write buffer
 Unified or Split cache
 Multiple level of caches
 ARM Cache Features
 Coprocessor 15 for system control
◦ Cache configuration commands
29
Session 27: Focus
 Processes
◦ Process context
◦ Context Switch
 Memory Map
 Protected Systems
◦ MPU and MMU
 ARM Systems with MPU
 Memory Protection Unit (MPU)
◦ Rules and Attributes of Regions
◦ ARM System Control Coprocessor (CP15)
◦ An Example System
30
Session 28: Focus
 Physical vs. Virtual Memory
◦ Virtual Memory Management
 Paging
◦ Page Table
◦ Tranlsation Lookaside Buffer (TLB)
◦ Page Size
◦ Example Page Sizes
 Segmentation
◦ Segmentation Tables
◦ Combination of paging and Segmentation
31
Session 29: Focus
 MMU Advantage
◦ MMU and MPU
 Virtual Memory Translation
◦ Translation Lookaside Buffer
◦ Page Tables
 Multitasking with MMU
 MMU Organization
◦ Master Page Table (L1)
◦ L2 Page Table
◦ MMU Control Register
 An Example System
 Tightly Coupled Memory (TCM)
32
Session 30: Focus
 ARM Development Environment
◦ Toolchain
◦ ARM DS-5
◦ ARM DSTREAM
◦ ABI
 Arm Procedure Call Standard (APCS)
◦ Data Types
◦ Core Registers
◦ Returning Result
 Example C program
◦ Interfacing it with Assembly
33
Session 31: Focus
 Embedded Software Development
◦ Semihosting
◦ C Library Structure
 Image Structure
◦ Sections, Regions and Segments
 Linker inputs and outputs
◦ Relocatable and shared object files
◦ Load and Execution Views
◦ Overlays and Overlay Manager
 Memory Map
◦ Default, Type 1 to 3 Images
 Application Startup
34
Session 32: Focus
 AMBA Overview
◦ AMBA High-performance Bus (AHB)
◦ AMBA System Bus (ASB)
◦ AMBA Peripheral Bus (APB)
 Typical AMBA Based Microcontroller
 AHB Bus features
 AHB Bus Transfers
 APB Bus Transfers
 APB Bridge
35
Session 33: Focus
 DMA
 Peripherals
◦ RTC
◦ ADC
◦ DAC
◦ PWM
 Programming Peripherals in ARM
36
Session 34: Focus
 Protocols
◦ I2 C
◦ SPI
 USART
 GPIO
37
Session 35: Focus
 ARM ISAs
 ARMv5
 ARMv6
 ARMv7
◦ Cortex-A family processors
 big.LITTLE technology
 ARMv8
◦ ARMv8-A
◦ ARMv8-R
38
References
Note: Manuals and Technical Documents from ARM Inc. have also been referred.
39

ARM Based Development Course Summary-MouliSankaran

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ARM Based Development Course Summary-MouliSankaran

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Full Course on Scribd

Full Course Link:

Full Course Videos on NPTEL

ARM Based Development – © 2020 Mouli Sankaran Email: mouli.sankaran@yahoo.com

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