Analog Circuits [18EC42]

Module – 5
OP-AMP CIRCUITS

DAC - WEIGHTED RESISTOR AND R-2R LADDER:

i. DAC Converter with binary Weighted resistors:

Fig: D/A converter with binary weighted resistors

 A D/A converter using binary-weighted resistors is shown in the figure
 In the circuit, the op-amp is connected in the inverting mode.
 The op-amp can also be connected in the non-inverting mode.
 Since the number of binary input is four, the convertor is called as 4-bit
(binary digit) converter.
 Because there are 16 (24) combinations of binary inputs for b0 to b3, an
analog output should have 16 possible corresponding values.
Working:
 When switch b0 is closed (connected to +5V):
o The voltage across R is 5V because of V2=V1=0V.
o Therefore the current through R is
I0 = 5V/10KΩ=0.5mA.
o However, input bias current IB is negligible; hence the current (IF) through
feedback resistor RF is also IF = 0.5mA, which in turn produces an output
voltage of

1 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

VO = – (1 KΩ) (0.5mA) = -0.5V.

 When switch b1 is closed and b0 is open:
o This connects R/2 to the positive supply of +5V,
o Therefore current through R/2 is
I1 = 5V/5KΩ = 1mA.
o Hence, the current through feedback resistor RF is also IF = 1mA, which in
turn produces an output voltage of
VO = – (1 KΩ) (1mA) = -1V.
 If both switch b0 and b1 are closed:
o The current through RF will be
IF = I0 + I1 = (0.5mA) + (1mA) = 1.5mA
o Hence, the output voltage
VO = IFRF = (-1.5mA) (1KΩ) = -1.5V
 Hence depending on whether switches b0 to b3 are open or closed, the
binary-weighted currents will be set up in the input resistors.
 The sum of these currents is equal to the current through RF, which in turn is
converted to a proportional output voltage.
 When all the switches are closed, the output will be maximum.
 The output voltage equation is given by
𝑏0 𝑏1 𝑏2 𝑏3
𝑉𝑂 = −𝑅𝐹 + + +
𝑅 𝑅 2 𝑅 4 𝑅 8
Where each of the inputs b3, b2, b1, and b0 may either be high (+5V) or low (0V)
 The below graph shows the analog outputs versus possible combinations of
inputs.
 The output is a negative-going staircase waveform with 15 steps of -0.5V
each.

2 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

 The drawback of weighted resistor DAC is that it requires binary-weighted

resistors, which may not be readily available, especially if the number of
inputs is more than four.

ii. DAC CONVERTER WITH R-2R RESISTORS:

Fig: D/A CONVERTER WITH R/2R RESISTORS

 The figure shows a D/A converter with R and 2R resistors.
 The binary inputs are simulated by switches b0 through b3, and the output is
proportional to the binary inputs.
 Binary inputs can be in either the high (+5V) or low (0V) state.
 Assume that the most significant bit (MSB) switch b3 is connected to +5V
and other switches are connected to ground, as shown in the figure.
 By applying Thevenin's theorem for the R-2R ladder circuit, Equivalent
resistance RTH is calculated as
𝑅𝑇𝐻 = 2𝑅 2𝑅 + 𝑅 2𝑅 + 𝑅 2𝑅 + 𝑅 = 2𝑅 = 20𝑘Ω
 The resultant circuit after applying Thevenin's theorem is as shown below:

Fig: Equivalent circuit when b3 is high and b0, b1, and b2 are low
 In the figure shown above, the negative input is at virtual ground; therefore
the current through RTH is 0A.
 The Current through 2R connected to +5V is 𝐼 = 5𝑉 20𝑘 Ω = 0.25𝑚𝐴

3 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

 The same current I flows through RF and in turn produces the output voltage
of
𝑉𝑂 = − 20𝑘Ω 0.25𝑚𝐴 = −5𝑉
 Using the same analysis, the output voltage when all the switches are
connected to +5V can be calculated as
𝑏3 𝑏2 𝑏1 𝑏0
𝑉𝑂 = −𝑅𝐹 + + +
2𝑅 4𝑅 8𝑅 16𝑅
Where each of the inputs b3, b2, b1, and b0 may be either high (+5V) or low
(0V).
 The below graph shows the analog outputs versus possible combinations of
inputs.

4 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

SUCCESSIVE-APPROXIMATION A/D CONVERTER:

Fig: Successive-approximation type A/D converter

 The figure shows a successive approximation type of A/D converter.

 A successive approximation A/D converter consists of a comparator, a
successive approximation register (SAR), output latches, and a D/A
converter.
 The main part of the circuit is the 8-bit SAR, whose output is given to an 8-
bit D/A converter.
 The analog output Va of the D/A converter is then compared to an analog
signal Vin by the comparator.
 The output of the comparator is the serial data input to the SAR.
 The SAR then adjusts its digital output (8-bits) until it is equivalent to analog
input Vin.
 The 8-bit latch at the end of the conversation holds onto the resultant digital
data output.

Working of successive-approximation A/D converter:

 At the start of a conversion cycle, the SAR is reset by making the start signal
(S) high.
 The MSB of the SAR (Q7) is set as soon as the first transition from LOW to
HIGH is introduced.
 The output is given to the D/A converter which produces an analog
equivalent of the MSB and is compared with the analog input Vin.
 If comparator output is LOW, D/A output will be greater than Vin and the
MSB will be cleared by the SAR.
 If comparator output is HIGH, D/A output will be less than Vin and the MSB
will be set to the next position (Q7 to Q6) by the SAR.

5 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

 According to the comparator output, the SAR will either keep or reset the Q6
bit.
 This process goes on until all the bits are tried.
 After Q0 is tried, the SAR makes the conversion complete (CC) signal
HIGH to show that the parallel output lines contain valid data.
 The CC signal, in turn, enables the latch, and digital data appear at the output
of the latch.
 As the SAR determines each bit, digital data is also available serially.
 As shown in the figure above, the CC signal is connected to the start
conversion input to convert the cycle continuously.

6 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

SMALL-SIGNAL HALF-WAVE RECTIFIERS:

i. Positive small-signal half-wave rectifier circuit:

Fig: Positive small-signal HWR Fig: Input and Output Waveform

 A positive small-signal half-wave rectifier is shown in the figure.

 The resultant circuit can rectify signals with peak values down to a few
millivolts.
 D1 is used in the feedback path and the analysis can be done for input Vin>
0V and Vin< 0 V.
 Case 1 : Vin> 0V:
o Consider the input to be positive going.
o As Vin starts increasing in the positive direction, the VOA also starts
increasing positively until diode D1 is forward biased.
o When D1 is forward biased, it closes a feedback loop and the op-amp
works as a voltage follower.
o Therefore, the output voltage VO follows the input voltage Vin during the
positive half-cycle as shown in the output waveform.
 Case 2: Vin< 0V:
o When Vin starts increasing in a negative direction, VOA, also increases
negatively until it is equal to negative saturation voltage (Vsat≅-VEE).
o This reverse biases diode D1 and opens the feedback loop as shown in the
below figure.

o Therefore, during negative half-cycle of the input signal, VO is 0V

7 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

ii. Negative small-signal half-wave rectifier circuit:

Fig: Negative small-signal HWR Fig: Input and Output Waveform

 A positive small-signal half-wave rectifier is shown in the figure.

 The resultant circuit can rectify signals with peak values down to a few
millivolts.
 D1 is used in the feedback path and the analysis can be done for input Vin>
0V and Vin< 0 V.
Case 1 : Vin> 0V:
o When Vin starts increasing in a positive direction, VOA, also increases
positively until it is equal to positive saturation voltage (Vsat≅VCC).
o This reverse biases diode D1 and opens the feedback loop as shown in the
below figure.

o Therefore, during positive half-cycle of the input signal, VO is 0V

Case 2: Vin< 0V:
o When the input is negative-going.
o As Vin starts increasing in the negative direction, the VOA also starts
increasing negatively until diode D1 is forward biased.
o When D1 is forward biased, it closes a feedback loop and the op-amp
works as a voltage follower.
o Therefore, the output voltage VO follows the input voltage Vin during the
negative half-cycle as shown in the output waveform.

8 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

ACTIVE FILTERS:

An electric filter is often a frequency selective circuit that passes a specified

band of frequencies and blocks or alternates signals and frequencies outside this
band.
Filters may be classified as
1. Analog or digital.
2. Active or passive
3. Audio (AF) or Radio Frequency (RF)

1. Analog or digital filters:

Analog filters are designed to process analog signals, while digital filters
process analog signals using the digital technique.

2. Active or Passive:
Depending on the type of elements used in their construction, a filter may be
classified as passive or active elements used in passive filters are Resistors,
capacitors, inductors. Elements used in active filters are transistor or op-amp.

Active filters offer the following advantages over passive filters:

1. Gain and Frequency adjustment flexibility:
Since the op-amp is capable of providing a gain, the i/p signal is not attenuated
as it is in a passive filter. [Active filter is easier to tune or adjust].
2. No loading problem:
Because of the high input resistance and low o/p resistance of the op-amp, the
active filter does not cause the loading of the source or load.
3. Cost:
Active filters are more economical than the passive filter. This is because of the
variety of cheaper op-amps and the absence of inductors.

The most commonly used filters are these:

1. Low pass Filters
2. High pass Filters
3. Band pass filters
4. Band reject filters
5. All pass filters.

9 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

The frequency response of the active filters:

Fig: Low pass Filter Fig: High pass Filter

Fig: Band Pass Filters Fig: Band Reject

1. Low Pass Filter:

 It has a constant gain from 0 Hz to a high cutoff frequency f1.
 At fH the gain in down by 3db.
 The frequency between 0hz and fH is known as the passband frequencies.
Whereas the range of frequencies beyond fH, that are attenuated includes the
stopband frequencies.
 Butterworth, Chebyshev, and causer filter are some of the most commonly
used practical filters.
 The key characteristic of the butter worth filter is that it has a flat passband
as well as a stop band. For this reason, it is sometimes called flat-flat filters.
 Chebyshev filter -> has a ripple pass band & flat stopband.
 Causer Filter -> has a ripple pass band & ripple stopband. It gives the best
stopband response among the three.

2. High pass filter:

 High pass filter with a stop band 0<f< fL and a passband f> fL
Where fL - low cut off frequency and f -operating frequency.

3. Band pass filter:

 It has a passband between 2 cut off frequencies fH and fL

10 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

where fH > fL and two, stopbands : 0<f< fL and f > fH between the bandpass filter
(equal to fH - fL).

4. Band –reject filter (Band stop or Band elimination):

 It performs exactly opposite to the bandpass.
 It has a band stop between 2 cut-off frequency fL and fH and 2 passbands:
0<f< fL and f> fH fC -> center frequency.

FIRST ORDER LOW-PASS BUTTERWORTH FILTER:

Fig:First order LPF Butterworth filter circuit Fig: LPF Frequecy response

 Figure shows a first-order low-pass Butterworth filter that uses an RC

network for filtering.
 op-amp is used in the non inverting configuration.
 Resistor R1 & Rf determine the gain of the filter.
 According to the voltage –divider rule, the voltage at the non-inverting
terminal (across capacitor) C is:
−𝑗𝑋𝐶 where 𝑗 = −1 and
𝑉1 = 𝑉𝑖𝑛 1
𝑅 − 𝑗𝑋𝐶 −𝑗𝑋𝐶 =
Simplifying the above equation we get 𝑗 2𝜋𝑓𝑐
1
𝑗2𝜋𝑓𝑐
𝑉1 = 𝑉𝑖𝑛
1
𝑅+
𝑗2𝜋𝑓𝑐
𝑣𝑖𝑛
𝑉1 =
1 + 𝑗2𝜋𝑓𝑅𝐶
And the output voltage of the non inverting amplifier circuit is
𝑅𝑓
𝑉𝑂 = 1 + 𝑉
𝑅1 1
𝑅𝑓 𝑣𝑖𝑛
∴ 𝑉𝑂 = 1 +
𝑅1 1 + 𝑗2𝜋𝑓𝑅𝐶

11 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

𝑉𝑂 𝑅𝑓 1
= 1+
𝑉𝑖𝑛 𝑅1 1 + 𝑗2𝜋𝑓𝑅𝐶

𝑉𝑂 1 Where
= 𝐴𝑓 𝑉𝑂
𝑉𝑖𝑛 1 + 𝑗 𝑓 𝑓𝐻 𝑉 𝑖𝑛
= gain of the filter as a function of frequency
𝑅
𝐴𝑓 = 1 + 𝑅𝑓 = passband of the filter
1

1
𝑓𝐻 = = high cutoff frequency of the filter
2𝜋𝑅𝐶

f = frequency of the input signal

The gain magnitude and phase angle equations of the low-pass filter can be
obtained by converting the above equation into its equivalent polar form, we get
𝑉𝑂 𝐴𝑓
=
𝑉𝑖𝑛 1 + 𝑓 𝑓𝐻 2
𝑓 Where
∅ = − tan−1 ∅= is phase angle in degrees
𝑓𝐻

The operation of the low-pass filter can be verified from the gain magnitude
equation:
1. At very low frequencies, that is, 𝑓 < 𝑓𝐻 ,
𝑉𝑂
≅ 𝐴𝑓
𝑉𝑖𝑛
2. At 𝑓 = 𝑓𝐻 ,
𝑉𝑂 𝐴𝑓
= = 0.707𝐴𝑓
𝑉𝑖𝑛 2
3. At 𝑓 > 𝑓𝐻 ,
𝑉𝑂
< 𝐴𝑓
𝑉𝑖𝑛
Thus the low-pass filter has a constant gain 𝐴𝑓 from 0Hz to the high cutoff
frequency fH.
At fH the gain is 0.707Af, and after fH it decreases at a constant rate with an
increase in frequency as shown in the frequency response.

12 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

Filter Design First Order LPF Butterworth Filter:

A low-pass filter can be designed by implementing the following steps:
o Choose a value of high cutoff frequency fH.
o Select a value of C less than or equal to 1µF.
1
o Calculate the value of R using 𝑅 =
2𝜋𝑓𝐻 𝐶
o Finally, select values of R1 and RF dependent on the desired passband gain
𝑅𝑓
Af using 𝐴𝑓 = 1 +
𝑅1

SECOND ORDER LOW-PASS BUTTERWORTH FILTER:

Fig: Second order LPF Butterworth filter circuit Fig: LPF Frequecy response

 Figure shows a Second-order low-pass Butterworth filter that uses an RC

network for filtering.
 A first order low-pass filter can be converted second order type by using an
additional RC network, as shown in figure.
 A stop-band response having a 40-db/decade roll-off is obtained with the
second order low-pass filter.
 The gain of the II order filter is set by R1 and RF, while the high cut off
frequency fH is determined by R2,C2,R3 and C3.
1
That is 𝑓𝐻 =
2𝜋 𝑅2 𝑅3 𝐶2 𝐶3

 The voltage gain magnitude euation for a second order low-pass Butterworth
filter is given by
𝑉𝑂 𝐴𝑓 Where 𝐴𝑓 = 1 +
𝑅𝑓
=passband gain of the filter
= 𝑅1

𝑉𝑖𝑛 1 + 𝑓 𝑓𝐻 4 f=frequency of the input signal (Hz)

1
𝑓𝐻 = =high cutoff frequency (Hz)
2𝜋 𝑅2 𝑅3 𝐶2 𝐶3

13 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

Filter Design:
1. Choose a value for a high cut off freq (fH ).
2. To simplify the design calculations, set R2 = R3 = R and C2 = C3 = C
then choose a value of c<=1μf.
1
3. Calculate the value of R using eqn 𝑅 =
2𝜋𝑓𝐻 𝐶
4. Finally, because of the equal resistor (R2 = R3) and capacitor (C2 = C3)
values, the pass band volt gain AF = (1 + RF / R1) of the second order LPF
has to be equal to 1.586. That is RF = 0.586 R1. Hence choose a value of
R1≤100kΩ and Calculate the value of RF.

FIRST ORDER HIGH-PASS BUTTERWORTH FILTER:

Fig:First order HPF Butterworth filter circuit Fig: HPF Frequecy response

 Figure shows a first-order high-pass Butterworth filter that uses an RC

network for filtering.
 op-amp is used in the non inverting configuration.
 Resistor R1 & Rf determine the gain of the filter.
 According to the voltage –divider rule, the voltage at the non-inverting
terminal (across Resistor) R is:
𝑅 where 𝑗 = −1 and
𝑉1 = 𝑉𝑖𝑛 1
𝑅 − 𝑗𝑋𝐶 −𝑗𝑋𝐶 =
Simplifying the above equation we get 𝑗 2𝜋𝑓𝑐
𝑅
𝑉1 = 𝑉𝑖𝑛
1
𝑅+
𝑗2𝜋𝑓𝑐
𝑗2𝜋𝑓𝑅𝐶𝑣𝑖𝑛
𝑉1 =
1 + 𝑗2𝜋𝑓𝑅𝐶
And the output voltage of the non inverting amplifier circuit is

14 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

𝑅𝑓
𝑉𝑂 = 1 + 𝑉
𝑅1 1
𝑅𝑓 𝑗2𝜋𝑓𝑅𝐶𝑣𝑖𝑛
∴ 𝑉𝑂 = 1 +
𝑅1 1 + 𝑗2𝜋𝑓𝑅𝐶
𝑉𝑂 𝑅𝑓 𝑗2𝜋𝑓𝑅𝐶
= 1+
𝑉𝑖𝑛 𝑅1 1 + 𝑗2𝜋𝑓𝑅𝐶
Where
𝑉𝑂 𝑗 𝑓 𝑓𝐿 𝑉𝑂
= gain of the filter as a function of frequency
= 𝐴𝑓 𝑉 𝑖𝑛
𝑉𝑖𝑛 1 + 𝑗 𝑓 𝑓𝐿 𝑅
𝐴𝑓 = 1 + 𝑅𝑓 = passband of the filter
1

1
𝑓𝐿 = 2𝜋𝑅𝐶
= low cutoff frequency of the filter

f = frequency of the input signal

The gain magnitude equations of the high-pass filter can be obtained by
converting the above equation into its equivalent polar form, we get
𝑉𝑂 𝐴𝑓 𝑓 𝑓𝐿
=
𝑉𝑖𝑛 1 + 𝑓 𝑓𝐿 2

The operation of the high-pass filter can be verified from the gain magnitude
equation:
4. At very low frequencies, that is, 𝑓 < 𝑓𝐿 ,
𝑉𝑂
< 𝐴𝑓
𝑉𝑖𝑛
5. At 𝑓 = 𝑓𝐿 ,
𝑉𝑂 𝐴𝑓
= = 0.707𝐴𝑓
𝑉𝑖𝑛 2
6. At 𝑓 > 𝑓𝐿 ,
𝑉𝑂
≅ 𝐴𝑓
𝑉𝑖𝑛

15 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

Filter Design First Order LPF Butterworth Filter:

A high-pass filter can be designed by implementing the following steps:
o Choose a value of low cutoff frequency fH.
o Select a value of C less than or equal to 1µF.
1
o Calculate the value of R using 𝑅 =
2𝜋𝑓𝐿 𝐶
o Finally, select values of R1 and RF dependent on the desired passband gain
𝑅𝑓
Af using 𝐴𝑓 = 1 +
𝑅1

SECOND ORDER HIGH-PASS BUTTERWORTH FILTER:

Fig: Second order HPF Butterworth filter circuit Fig: HPF Frequecy response

 Figure shows a Second-order high-pass Butterworth filter that uses an RC

network for filtering.
 A first order low-pass filter can be converted second order type by using an
additional RC network, as shown in figure.
 A stop-band response having a 40-db/decade roll-off is obtained with the
second order high-pass filter.
 The gain of the II order filter is set by R1 and RF, while the high cut off
frequency fH is determined by R2,C2,R3 and C3.
1
That is 𝑓𝐿 =
2𝜋 𝑅2 𝑅3 𝐶2 𝐶3

 The voltage gain magnitude euation for a second order low-pass Butterworth
filter is given by
𝑉𝑂 𝐴𝑓 Where 𝐴𝑓 = 1 +
𝑅𝑓
=passband gain of the filter
= 𝑅1

𝑉𝑖𝑛 1 + 𝑓 𝑓𝐿 4 f=frequency of the input signal (Hz)

1
𝑓𝐿 = =low cutoff frequency (Hz)
2𝜋 𝑅2 𝑅3 𝐶2 𝐶3

16 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

BAND-PASS FILTERS:

 A band-pass filter has a passband between two cutoff frequencies f H and fL

such that fH>fL.
 Any input frequency outside this passband is attenuated.

Types of band-pass filters:

 Basically there are two types of band-pass filters:
o Wide band pass filter: A band pass filter if figure of merit or quality factor
Q is less than 10 (Q<10).
o Narrow band pass filter: A band pass filter if figure of merit or quality
factor Q is greater than 10 (Q>10).

 Thus Q is a measure of selectivity, meaning the higher the value of Q the

more selective is the filter, or the narrower is the bandwidth (BW).
 The relationship between Q, the -3db bandwidth, and the centre frequency
fc is given by an equation
𝑓𝐶 𝑓𝐶
𝑄= =
𝐵𝑊 𝑓𝐻 − 𝑓𝐿
 For the wide band-pass filter the center frequency fC can be defined as
𝑓𝐶 = 𝑓𝐻 𝑓𝐿
Where 𝑓𝐻 = high cutoff frequency (Hz)
𝑓𝐿 = low cutoff frequency (Hz)

17 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

WIDE BAND-PASS FILTER:

 A wide band-pass filter can be formed by simply cascading high-pass and
low-pass filter as shown in the circuit diagram.

Fig: ±20dB/decade wide band-pass filter

 Frequency response of wide band-pass filter is shown in the graph.
 The circuit design is as same as low-pass and high-pass filters.

Fig: Frequency response of wide band-pass filter

18 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

NARROW BAND-PASS FILTER:

Fig: Narrow band-pass filter Fig: Frequency response

 The narrow band-pass filter using multiple feedback is shown in the figure.
 The unique features of this circuit are:
o It has two feedback paths, and this is the reason that it is called a
multiple-feedback filter.
o The op-amp is used in the inverting mode.
 The frequency response is as shown in the figure.
 Generally, the narrow band-pass filter is designed for specific values of
centre frequency fC and Q or fC and bandwidth.
 The circuit components are determined from the following relationships,
Let 𝐶1 = 𝐶2 = 𝐶
𝑄
𝑅1 =
2𝜋𝑓𝐶 𝐶𝐴𝑓
𝑄
𝑅2 =
2𝜋𝑓𝐶 𝐶 2𝑄2 − 𝐴𝑓
𝑄
𝑅3 =
𝜋𝑓𝐶 𝐶
Where Af is the gain at fC, given by
𝑅3
𝐴𝑓 =
2𝑅1
The gain Af, however, must satisfy the condition
𝐴𝑓 < 2𝑄2
The advantageof the abovenarrow band-pass filter circuit is that its centre
frequency fC can be changed to new centre frequency 𝑓𝐶′ without changing the
gain or bandwidth. This can be accomplished by changing R2 to 𝑅2′ so that
2
′
𝑓𝐶
𝑅2 = 𝑅2 ′
𝑓𝐶

19 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

THE 555 TIMER:

 The 555 is a monolithic timing circuit that can produce accurate and highly
stable time delays or oscillation.
 The timer basically operates in one of two modes they are:
o Monostable (one-shot) multivibrator.
o Astable (free-running) mulivibrator.
 The IC555 timer device is available as an 8-pin metal can, an 8-pin mini
DIP, or a 14-pin DIP.
 The important fetures of the 555 timer are:
o It operates on +5V TO +18V supply voltage in both astable and
monostable modes.
o It has an adjustable duty cycle.
o Timing is from microseconds through hours.
o It has a high current output.
o The output can drive TTL.
o It has a temperature stability of 50 parts per million (ppm) per degree
Celsius change in temperature.
o The 555 timer is reliable, easy to use and low cost.

20 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

THE 555 TIMER IC CONFIGURATION AND BLOCK DIAGRAM:

 The 555 Timer is a 8-pin IC, The pin configuration is shown in the figure.

PIN DESCRIPTION:
Pin 1: Ground:
o All voltages are measured with respect to this terminal.
Pin 2: Trigger:
o The o/p of the timer depends on the amplitude of the external trigger pulse applied to
this pin.
Pin 3: Output:
o There are 2 ways a load can be connected to the o/p terminal either between pin3 &
ground or between pin 3 & supply voltage
o (Between Pin 3 & Ground- ON load )
o (Between Pin 3 & + Vcc - OFF load )
o When the input is low: The load current flows through the load connected between Pin
3 & +Vcc in to the output terminal & is called the sink current.
o When the output is high: The current through the load connected between Pin 3 &
+Vcc (i.e. ON load) is zero. However the output terminal supplies current to the
normally OFF load. This current is called the source current.
Pin 4: Reset:
o The 555 timer can be reset (disabled) by applying a negative pulse to this pin. When
the reset function is not in use, the reset terminal should be connected to +Vcc to avoid
any false triggering.
Pin 5: Control voltage:
o An external voltage applied to this terminal changes the threshold as well as trigger
voltage. In other words by connecting a potentiometer between this pin & GND, the
pulse width of the output waveform can be varied. When not used, the control pin
should be bypassed to ground with 0.01µF capacitor to prevent any noise problems.
Pin 6: Threshold:
o This is the non inverting input terminal of upper comparator which monitors the
voltage across the external capacitor.
Pin 7: Discharge:
o This pin is connected internally to the collector of transistor Q1.
o When the output is high Q1 is OFF.
o When the output is low Q is (saturated) ON.
Pin 8: +Vcc:
o The supply voltage of +5V to +18V is applied to this pin with respect to ground.

21 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

Block diagram of 555 Timer:

 In the block diagram of 555 timer, three 5k internal resistors act as voltage
divider providing bias voltage of 2/3 Vcc to the upper comparator & 1/3 Vcc
to the lower comparator.
 It is possible to vary time electronically by applying a modulation voltage to
the control voltage input terminal 5.
 In the Stable state:
o The output of the control FF is high. This means that the output is low
because of power amplifier which is basically an inverter. Q = 1; Output =
0
 At the Negative going trigger pulse:
o The trigger passes through (Vcc/3) the output of the lower comparator
goes high & sets the FF. Q = 1; Q = 0
 At the Positive going trigger pulse:
o It passes through 2/3Vcc, the output of the upper comparator goes high
and resets the FF. Q = 0; Q = 1
 The reset input (pin 4) provides a mechanism to reset the FF in a manner
which overrides the effect of any instruction coming to FF from lower
comparator.

22 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

THE 555 TIMER AS A MONOSTABLE MULTIVIBRATOR:

 A monostable multivibrator is also called as one-shot multivibrator.
 It is a pulse generating circuit in which the duration of the pulse is
determined by the RC network connected externally to the 555 timer.
 In a stable state or standby state the output of of the circuit is approximately
zero or at logic-low level.
 When an external trigger pulse is applied, the output is forced to go high
(≅ 𝑉𝐶𝐶 ).
 The time output remains high is determined by the external RC network
connected to the timer.
 At the end of the timing interval, the output automatically reverts back to its
logic-low state.
 The output stays low until the trigger pulse is again applied.
 Then the cycle repeats.
 The monostable circuit has only one stable state (outout low), hence the
name monostable.
 Normally, the output of the monostable multivibrator is low.
 Figure shows the 555 timer configured for monostable multivibrator:

Fig:555 timer connected as a monostable multivibrator

23 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

Monostable Operation:

 Initially when the output is low, that is, the circuit is in a stable state,
transistor Q1 is on and the capacitor C is shorted out to ground.
 When negative trigger pulse is applied to pin 2, the transistor Q1 is turned
off, which releases the short circuit across the external capacitor C and
drives the output high.
 The capacitor C now starts charging up towards VCC through RA.
 When the voltage across the capacitor equals 2/3VCC, comparator 1’s output
switches from low to high, which inturn drives the output to its low state via
the output of the flip-flop.
 At the same time, the output of the flip-flop turns transistor Q1 on, and hence
capacitor C rapidly discharges through the transistor.
 The output of the monostable remains low until trigger pulse is again
applied.
 The the cycle repeats.
 The figure shows the trigger input, output voltage, and the capacitor voltage
waveforms.

24 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

 The voltage across the capacitor as in fig (b) is given by

𝑉𝐶 = 𝑉𝐶𝐶 1 − 𝑒 −𝑡 𝑅𝐴 𝐶

At t=T, VC=2/3 VCC

2
𝑉 = 𝑉𝐶𝐶 1 − 𝑒 −𝑇 𝑅𝐴 𝐶
3 𝐶𝐶
Rearranging the above equation
1
𝑇 = 𝑅𝐴 𝐶 ln
3

𝑇 = 1.1𝑅𝐴 𝐶

Where T –width of the pulse

25 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

THE 555 TIMER AS AN ASTABLE MULTIVIBRATOR:

 An astable multivibrator is also called as free-running multivibrator.
 It is a rectangular wave generating circuit.
 The time during which the output is either high or low is determined by two
resistors and a capacitor, which are externally connected to the 555 timer.
 Figure shows the 555 timer connected as an astable multivibrator.

Fig: The 555 timer as an astable multivibrator.

Astable operation:
 Initially, when the output is high :
o Capacitor C starts charging toward Vcc through RA & RB.
o However, as soon as voltage across the capacitor equals 2/3 Vcc,
Comparator 1 triggers the Flip-Flop & output switches low.
 When the output becomes Low:
o Capacitor C starts discharging through RB and transistor Q1.
o when the voltage across C equals 1/3 Vcc, comparator 2’s output triggers
the Flip-Flop & the output goes High.
 Then cycle repeats.
 The output voltage snd capacitor voltage waveforms are shown in the
figures.

26 By: Mahendra Naik, Department of ECE, PESITM Shivamogga

 Analog Circuits [18EC42]

 As sown in the waveforms, the capacitor is periodically charged and

discharged between 2/3 VCC and 1/3 VCC, respectively.
 The time during which the capacitor charges from 1/3 VCC to 2/3 VCC is
equal to the time the output is high and is given by

𝑡𝑐 = 0.69 𝑅𝐴 + 𝑅𝐵 𝐶
 Similarly, the time during which the capacitor discharges from 2/3 VCC to
1/3 VCC is equal to the time the output is low and is given by

𝑡𝑑 = 0.69 𝑅𝐵 𝐶
 Thus the total period of the output waveform is
𝑇 = 𝑡𝑐 + 𝑡𝑑
𝑇 = 0.69 𝑅𝐴 + 2𝑅𝐵 𝐶
 Thus the frequency of oscillation is s
1 1.45
𝑓𝑜 = =
𝑇 𝑅𝐴 + 2𝑅𝐵 𝐶
 The duty cycle is the ratio of the time tC during which the output is high to
the total time period T.
 It is generally expressed as percentage is expressed as
𝑡𝑐
% 𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 𝐷 = × 100
𝑇
0.69 𝑅𝐴 + 𝑅𝐵 𝐶
% 𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 𝐷 = × 100
0.69 𝑅𝐴 + 2𝑅𝐵 𝐶
𝑅𝐴 + 𝑅𝐵
∴ % 𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒 𝐷 = × 100
𝑅𝐴 + 2𝑅𝐵

27 By: Mahendra Naik, Department of ECE, PESITM Shivamogga