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Compal Confidential
2 2

KBLG0/NBLG0 Schematics Document


AMD Puma (JV40-PU) : Griffin Processor with RS780MN/SB700/M92-M2 XT
Tigris (JV40-TR) : Caspian Processor with RS880M/SB710/M92-M2 XT

3
2009-03-11 3

REV:1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
401679 C

hexainf@hotmail.com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 26, 2009 Sheet 1 of 57
A B C D E
GRATIS - FOR FREE
A B C D E

Tigris
Puma
Compal Confidential AMD S1G3 Processor
uPGA-638 Package
VRAM 512MB Caspian AMD S1G2 Processor
Model Name : KBLG0 Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
64M16 x 4 Fan Control uPGA-638 Package
page 19, 20 Dual Channel BANK 0, 1, 2, 3 page 8,9
PowerXpress (MUX) page 44
Griffin page 4,5,6,7 1.8V DDRII 667/800
1 LCD (LED BL) MUX DDR2 500MHz 1
Hyper Transport Link 5 in 1 socket
page 24 (1:2) ATI M92-M2 XT 16 x 16 page 33
ATI RS880M
uFCBGA-962 PCI-Express 16x uFCBGA-528
CRT MUX Page 14,15,16,17,18,21,22
Gen2 Thermal Sensor Clock Generator
page 26 (1:2) ATI RS780MN Card Reader
ADM1032 SLG8SP626VTR
page 6 page 23 RTS5159
HDMI Conn. uFCBGA-528 page 33
page 25
PCI-Express 1x option1
page 10,11,12,13 page 36,37 page 27 page 37 page 36 page 36
option2
USB CMOS Bluetooth Finger Mini
MINI Card x1 LAN(GbE) Card Reader A link Express2 conn printer card
ATI SB710 Camera Conn
WLAN Atheros AR8131 JMB385 uFCBGA-528 X2 AES1610 (WL)X1
page 36 page 34 page 33 USB port 0,6 USB port 3 USB port 12 USB port 13 USB port 8 USB port 4
port 2 port 3 port 4
2
ATI SB700 3.3V 48MHz USB
2

RJ45 5 in 1 socket 3.3V 24.576MHz/48Mhz HD Audio


page 33
page 35 uFCBGA-528
USB port 1
page 27,28,29,30,31 S-ATA

MDC 1.5 HDA Codec Digital MIC


Conn
page 41
ALC888
page 42 page 42

LED LPC BUS SATA HDD CDROM ESATA


page 40
Conn. page 32 Conn.
page 32
Conn.
page 37
port 0 port 1 port 2 Audio AMP
page 43
RTC CKT.
page 26
ENE KB926
3 page 38 3
Phone Jack x3
page 43
LID SW / MEDIA/B
page 39 Touch Pad Int.KBD
page 39 page 39

Power On/Off CKT. EC I/O Buffer BIOS


page 41
page 38 page 39

DC/DC Interface CKT.


page 45

Power Circuit
4
page 46,47,48,49,50,51 4
52,53,54

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
401679 C

Date: Thursday, March 26, 2009 Sheet 2 of 57


A B C D E
A B C D E

SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON

Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW

VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE_0 Core voltage for CPU (0.7-1.2V) ON OFF OFF
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V)ON OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF Board ID / SKU ID Table for AD channel
+1.2V_HT 1.2V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF 0 0 0 V 0 V 0 V
+1.8VS 1.8V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW 3.3V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VS 3.3V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VALW 5V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Board ID PCB Revision BTO Item BOM Structure
External PCI Devices 0 0.1 Discrete VGA@
Device IDSEL# REQ#/GNT# Interrupts 1 0.2 UMA UMA@
2 0.3 M92-M2 XT M92@
3 0.4 VRAM STRAP VRAM@
4 1.0 LAN 8121 8121@
5 LAN 8131 8131@
6 HDT debug HDT@
7 JMB385 CR JMB385@
RTS5159 CR RTS5159@
FOR PUMA PUMA@
EC SM Bus1 address EC SM Bus2 address FOR TIGRIS TIGRIS@
3 FOR TEST UB@ 3

Device Address HEX Device Address HEX


Smart Battery 0001 011X b 16H ADI ADM1032 (CPU) 1001 100X b 98H SB700 SB700 RS780MN DISPLAY OUTPUT
GMT G781-1 (GPU) 1001 101X b 9AH PX_GPIO0 PX_GPIO1 PX_GPIO2
SB-Temp Sensor 9CH Function Description dGPU_Reset dGPU_PWR_Enable PX Mode Switch
IGP only mode X X X
PowerXpress mode H : Enable H : Enable L : iGPU(DC) / H : dGPU(AC) LVDS / CRT
SB700 SB700
SM Bus 0 address SM Bus 1 address KB926
PX_GPIO1 PX_GPIO2 PX_+3VS PX_+1.8VS PX_+VGA_CORE PX_GPIO2_NB
Device Address HEX Device Address Function Description Enable +1.1VS_PX PX MODE SWITCH Enable +3VS_DELAY Enable +1.8VS_PX Enable +VGA_CORE Trigger from SB
New card IGP only mode X X X X X X
Clock Generator 1101 001Xb D2
(SILEGO SLG8SP626) PowerXpress mode H : Enable Reserved H : Enable H : Enable H : Enable Reserved
DDR DIMM1 1001 000Xb 90
KB926
DDR DIMM2 1001 010Xb 94
PX_GPIO1_SB
Mini card
Function Description Trigger from SB to Enable (PX_GPIO1/PX_+3VS/PX_+1.8VS/PX_+VGA_CORE)
4 4
IGP only mode X
PowerXpress mode H : Enable

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B
401679 C

hexainf@hotmail.com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 26, 2009 Sheet 3 of 57
A B C D E
GRATIS - FOR FREE
A B C D E

1 1

+1.2V_HT
VLDT CAP.
250 mil

1 1 1 1 1 1
C727 C666 C725 C726 C722 C668
H_CADIP[0..15] H_CADOP[0..15] 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
10 H_CADIP[0..15] H_CADOP[0..15] 10
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2
10 H_CADIN[0..15] H_CADON[0..15] 10
PUMA@ PUMA@
Change as 10U Near CPU Socket
Change as 10U for Tigris
+1.2V_HT +1.2V_HT for Tigris
JCPU1A
PUMA@
2 2
D1 VLDT_A0 HT LINK VLDT_B0 AE2 1 2
D2 AE3 C664 4.7U_0805_10V4Z
VLDT=1.5A D3
VLDT_A1 VLDT_B1
AE4
VLDT_A2 VLDT_B2
D4 VLDT_A3 VLDT_B3 AE5

H_CADIP0 E3 AD1 H_CADOP0


H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 L0_CADIN_L4 L0_CADOUT_L4 W3
H_CADIP5 L3 V1 H_CADOP5
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1
H_CADIP6 L1 U2 H_CADOP6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 L0_CADIN_L6 L0_CADOUT_L6 U3
H_CADIP7 N3 T1 H_CADOP7
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1
H_CADIP8 E5 AD4 H_CADOP8
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3
H_CADIP9 F3 AD5 H_CADOP9
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5
H_CADIP10 G5 AB4 H_CADOP10
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5
H_CADIP12 K3 Y5 H_CADOP12
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 L0_CADIN_L12 L0_CADOUT_L12 W5
H_CADIP13 L5 V4 H_CADOP13
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 L0_CADIN_L14 L0_CADOUT_L14 U5
H_CADIP15 N5 T4 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
P5 L0_CADIN_L15 L0_CADOUT_L15 T3

10 H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 10


10 H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 10
10 H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 10
10 H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 10

10 H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 10


10 H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 10
10 H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 10
10 H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 10

6090022100G_B conn@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 4 of 57


A B C D E
A B C D E

PLACE CLOSE TO PROCESSOR


Processor DDR2 Memory Interface
WITHIN 1.5 INCH
JCPU1C
9 DDRB_SDQ[63..0]
MEM:DATA
DDRA_SDQ[63..0] 8
DDRA_CLK0 DDRB_SDQ0 C11 G12 DDRA_SDQ0
1 +1.8V DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1 1
1 A11 MB_DATA1 MA_DATA1 F12
DDRB_SDQ2 A14 H14 DDRA_SDQ2
C379 DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B14 MB_DATA3 MA_DATA3 G14
2

1.5P_0402_50V9C DDRB_SDQ4 G11 H11 DDRA_SDQ4


R78 DDRA_CLK0# 2 DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
E11 MB_DATA5 MA_DATA5 H12
1K_0402_1% DDRB_SDQ6 D12 C13 DDRA_SDQ6
DDRA_CLK1 DDRB_SDQ7 MB_DATA6 MA_DATA6 DDRA_SDQ7
A13 MB_DATA7 MA_DATA7 E13
1 DDRB_SDQ8 A15 H15 DDRA_SDQ8
MB_DATA8 MA_DATA8
1

+MCH_REF DDRB_SDQ9 A16 E15 DDRA_SDQ9


C111 DDRB_SDQ10 MB_DATA9 MA_DATA9 DDRA_SDQ10
1000P_0402_25V8J
0.1U_0402_16V4Z

A19 MB_DATA10 MA_DATA10 E17


2

1 1 1.5P_0402_50V9C DDRB_SDQ11 A20 H17 DDRA_SDQ11


R79 DDRA_CLK1# 2 DDRB_SDQ12 MB_DATA11 MA_DATA11 DDRA_SDQ12
C178

C177

C14 MB_DATA12 MA_DATA12 E14


1K_0402_1% DDRB_SDQ13 D14 F14 DDRA_SDQ13
DDRB_SDQ14 MB_DATA13 MA_DATA13 DDRA_SDQ14
C18 MB_DATA14 MA_DATA14 C17
2 2 DDRB_CLK0 DDRB_SDQ15 DDRA_SDQ15
D18 MB_DATA15 MA_DATA15 G17
1

1 DDRB_SDQ16 D20 G18 DDRA_SDQ16


DDRB_SDQ17 MB_DATA16 MA_DATA16 DDRA_SDQ17
A21 MB_DATA17 MA_DATA17 C19
C380 DDRB_SDQ18 D24 D22 DDRA_SDQ18
1.5P_0402_50V9C DDRB_SDQ19 MB_DATA18 MA_DATA18 DDRA_SDQ19
C25 MB_DATA19 MA_DATA19 E20
DDRB_CLK0# 2 DDRB_SDQ20 DDRA_SDQ20
B20 MB_DATA20 MA_DATA20 E18
DDRB_SDQ21 C20 F18 DDRA_SDQ21
DDRB_CLK1 DDRB_SDQ22 MB_DATA21 MA_DATA21 DDRA_SDQ22
B24 MB_DATA22 MA_DATA22 B22
1 DDRB_SDQ23 C24 C23 DDRA_SDQ23
DDRB_SDQ24 MB_DATA23 MA_DATA23 DDRA_SDQ24
E23 MB_DATA24 MA_DATA24 F20
C112 DDRB_SDQ25 E24 F22 DDRA_SDQ25
1.5P_0402_50V9C DDRB_SDQ26 MB_DATA25 MA_DATA25 DDRA_SDQ26
G25 MB_DATA26 MA_DATA26 H24
DDRB_CLK1# 2 DDRB_SDQ27 DDRA_SDQ27
G26 MB_DATA27 MA_DATA27 J19
DDRB_SDQ28 C26 E21 DDRA_SDQ28
DDRB_SDQ29 MB_DATA28 MA_DATA28 DDRA_SDQ29
D26 MB_DATA29 MA_DATA29 E22
DDRB_SDQ30 G23 H20 DDRA_SDQ30
+0.9V +0.9V DDRB_SDQ31 MB_DATA30 MA_DATA30 DDRA_SDQ31
G24 MB_DATA31 MA_DATA31 H22
JCPU1B DDRB_SDQ32 AA24 Y24 DDRA_SDQ32
2 DDRB_SDQ33 MB_DATA32 MA_DATA32 DDRA_SDQ33 2
VTT=0.75A AA23 MB_DATA33 MA_DATA33 AB24
D10 W10 DDRB_SDQ34 AD24 AB22 DDRA_SDQ34
VTT1 MEM:CMD/CTRL/CLK VTT5 DDRB_SDQ35 MB_DATA34 MA_DATA34 DDRA_SDQ35
Place them close to CPU within 1" C10 VTT2 VTT6 AC10 AE24 MB_DATA35 MA_DATA35 AA21
B10 AB10 DDRB_SDQ36 AA26 W22 DDRA_SDQ36
VTT3 VTT7 DDRB_SDQ37 MB_DATA36 MA_DATA36 DDRA_SDQ37
AD10 VTT4 VTT8 AA10 AA25 MB_DATA37 MA_DATA37 W21
R77 39.2_0402_1% A10 DDRB_SDQ38 AD26 Y22 DDRA_SDQ38
VTT9 DDRB_SDQ39 MB_DATA38 MA_DATA38 DDRA_SDQ39
1 2 AF10 MEMZP AE25 MB_DATA39 MA_DATA39 AA22
+1.8V 1 2 AE10 Y10 VTT_SENSE DDRB_SDQ40 AC22 Y20 DDRA_SDQ40
MEMZN VTT_SENSE PAD T4 MB_DATA40 MA_DATA40
R76 39.2_0402_1% DDRB_SDQ41 AD22 AA20 DDRA_SDQ41
+MCH_REF DDRB_SDQ42 MB_DATA41 MA_DATA41 DDRA_SDQ42
H16 RSVD_M1 MEMVREF W17 AE20 MB_DATA42 MA_DATA42 AA18
DDRB_SDQ43 AF20 AB18 DDRA_SDQ43
DDRA_ODT0 DDRB_SDQ44 MB_DATA43 MA_DATA43 DDRA_SDQ44
8 DDRA_ODT0 T19 MA0_ODT0 RSVD_M2 B18 AF24 MB_DATA44 MA_DATA44 AB21
DDRA_ODT1 V22 DDRB_SDQ45 AF23 AD21 DDRA_SDQ45
8 DDRA_ODT1 MA0_ODT1 MB_DATA45 MA_DATA45
U21 W26 DDRB_ODT0 DDRB_SDQ46 AC20 AD19 DDRA_SDQ46
MA1_ODT0 MB0_ODT0 DDRB_ODT0 9 MB_DATA46 MA_DATA46
V19 W23 DDRB_ODT1 DDRB_SDQ47 AD20 Y18 DDRA_SDQ47
MA1_ODT1 MB0_ODT1 DDRB_ODT1 9 MB_DATA47 MA_DATA47
Y26 DDRB_SDQ48 AD18 AD17 DDRA_SDQ48
DDRA_SCS0# MB1_ODT0 DDRB_SDQ49 MB_DATA48 MA_DATA48 DDRA_SDQ49
8 DDRA_SCS0# T20 MA0_CS_L0 AE18 MB_DATA49 MA_DATA49 W16
DDRA_SCS1# U19 V26 DDRB_SCS0# DDRB_SDQ50 AC14 W14 DDRA_SDQ50
8 DDRA_SCS1# MA0_CS_L1 MB0_CS_L0 DDRB_SCS0# 9 MB_DATA50 MA_DATA50
U20 W25 DDRB_SCS1# DDRB_SDQ51 AD14 Y14 DDRA_SDQ51
MA1_CS_L0 MB0_CS_L1 DDRB_SCS1# 9 MB_DATA51 MA_DATA51
V20 U22 DDRB_SDQ52 AF19 Y17 DDRA_SDQ52
MA1_CS_L1 MB1_CS_L0 DDRB_SDQ53 MB_DATA52 MA_DATA52 DDRA_SDQ53
AC18 MB_DATA53 MA_DATA53 AB17
DDRA_CKE0 J22 J25 DDRB_CKE0 DDRB_SDQ54 AF16 AB15 DDRA_SDQ54
8 DDRA_CKE0 MA_CKE0 MB_CKE0 DDRB_CKE0 9 MB_DATA54 MA_DATA54
DDRA_CKE1 J20 H26 DDRB_CKE1 DDRB_SDQ55 AF15 AD15 DDRA_SDQ55
8 DDRA_CKE1 MA_CKE1 MB_CKE1 DDRB_CKE1 9 MB_DATA55 MA_DATA55
DDRB_SDQ56 AF13 AB13 DDRA_SDQ56
DDRB_SDQ57 MB_DATA56 MA_DATA56 DDRA_SDQ57
N19 MA_CLK_H0 MB_CLK_H0 P22 AC12 MB_DATA57 MA_DATA57 AD13
N20 R22 DDRB_SDQ58 AB11 Y12 DDRA_SDQ58
DDRA_CLK0 MA_CLK_L0 MB_CLK_L0 DDRB_CLK0 DDRB_SDQ59 MB_DATA58 MA_DATA58 DDRA_SDQ59
8 DDRA_CLK0 E16 MA_CLK_H1 MB_CLK_H1 A17 DDRB_CLK0 9 Y11 MB_DATA59 MA_DATA59 W11
DDRA_CLK0# F16 A18 DDRB_CLK0# DDRB_SDQ60 AE14 AB14 DDRA_SDQ60
8 DDRA_CLK0# MA_CLK_L1 MB_CLK_L1 DDRB_CLK0# 9 MB_DATA60 MA_DATA60
DDRA_CLK1 Y16 AF18 DDRB_CLK1 DDRB_SDQ61 AF14 AA14 DDRA_SDQ61
8 DDRA_CLK1 MA_CLK_H2 MB_CLK_H2 DDRB_CLK1 9 MB_DATA61 MA_DATA61
DDRA_CLK1# AA16 AF17 DDRB_CLK1# DDRB_SDQ62 AF11 AB12 DDRA_SDQ62
8 DDRA_CLK1# MA_CLK_L2 MB_CLK_L2 DDRB_CLK1# 9 MB_DATA62 MA_DATA62
P19 R26 DDRB_SDQ63 AD11 AA12 DDRA_SDQ63
MA_CLK_H3 MB_CLK_H3 MB_DATA63 MA_DATA63
P20 MA_CLK_L3 MB_CLK_L3 R25 9 DDRB_SDM[7..0] DDRA_SDM[7..0] 8
3 DDRB_SDM0 DDRA_SDM0 3
8 DDRA_SMA[15..0] DDRB_SMA[15..0] 9 A12 MB_DM0 MA_DM0 E12
DDRA_SMA0 N21 P24 DDRB_SMA0 DDRB_SDM1 B16 C15 DDRA_SDM1
DDRA_SMA1 MA_ADD0 MB_ADD0 DDRB_SMA1 DDRB_SDM2 MB_DM1 MA_DM1 DDRA_SDM2
M20 MA_ADD1 MB_ADD1 N24 A22 MB_DM2 MA_DM2 E19
DDRA_SMA2 N22 P26 DDRB_SMA2 DDRB_SDM3 E25 F24 DDRA_SDM3
DDRA_SMA3 MA_ADD2 MB_ADD2 DDRB_SMA3 DDRB_SDM4 MB_DM3 MA_DM3 DDRA_SDM4
M19 MA_ADD3 MB_ADD3 N23 AB26 MB_DM4 MA_DM4 AC24
DDRA_SMA4 M22 N26 DDRB_SMA4 DDRB_SDM5 AE22 Y19 DDRA_SDM5
DDRA_SMA5 MA_ADD4 MB_ADD4 DDRB_SMA5 DDRB_SDM6 MB_DM5 MA_DM5 DDRA_SDM6
L20 MA_ADD5 MB_ADD5 L23 AC16 MB_DM6 MA_DM6 AB16
DDRA_SMA6 M24 N25 DDRB_SMA6 DDRB_SDM7 AD12 Y13 DDRA_SDM7
DDRA_SMA7 MA_ADD6 MB_ADD6 DDRB_SMA7 MB_DM7 MA_DM7
L21 MA_ADD7 MB_ADD7 L24
DDRA_SMA8 L19 M26 DDRB_SMA8 DDRB_SDQS0 C12 G13 DDRA_SDQS0
MA_ADD8 MB_ADD8 9 DDRB_SDQS0 MB_DQS_H0 MA_DQS_H0 DDRA_SDQS0 8
DDRA_SMA9 K22 K26 DDRB_SMA9 DDRB_SDQS0# B12 H13 DDRA_SDQS0#
MA_ADD9 MB_ADD9 9 DDRB_SDQS0# MB_DQS_L0 MA_DQS_L0 DDRA_SDQS0# 8
DDRA_SMA10 R21 T26 DDRB_SMA10 DDRB_SDQS1 D16 G16 DDRA_SDQS1
MA_ADD10 MB_ADD10 9 DDRB_SDQS1 MB_DQS_H1 MA_DQS_H1 DDRA_SDQS1 8
DDRA_SMA11 L22 L26 DDRB_SMA11 DDRB_SDQS1# C16 G15 DDRA_SDQS1#
MA_ADD11 MB_ADD11 9 DDRB_SDQS1# MB_DQS_L1 MA_DQS_L1 DDRA_SDQS1# 8
DDRA_SMA12 K20 L25 DDRB_SMA12 DDRB_SDQS2 A24 C22 DDRA_SDQS2
MA_ADD12 MB_ADD12 9 DDRB_SDQS2 MB_DQS_H2 MA_DQS_H2 DDRA_SDQS2 8
DDRA_SMA13 V24 W24 DDRB_SMA13 DDRB_SDQS2# A23 C21 DDRA_SDQS2#
MA_ADD13 MB_ADD13 9 DDRB_SDQS2# MB_DQS_L2 MA_DQS_L2 DDRA_SDQS2# 8
DDRA_SMA14 K24 J23 DDRB_SMA14 DDRB_SDQS3 F26 G22 DDRA_SDQS3
MA_ADD14 MB_ADD14 9 DDRB_SDQS3 MB_DQS_H3 MA_DQS_H3 DDRA_SDQS3 8
DDRA_SMA15 K19 J24 DDRB_SMA15 DDRB_SDQS3# E26 G21 DDRA_SDQS3#
MA_ADD15 MB_ADD15 9 DDRB_SDQS3# MB_DQS_L3 MA_DQS_L3 DDRA_SDQS3# 8
DDRB_SDQS4 AC25 AD23 DDRA_SDQS4
9 DDRB_SDQS4 MB_DQS_H4 MA_DQS_H4 DDRA_SDQS4 8
DDRA_SBS0# R20 R24 DDRB_SBS0# DDRB_SDQS4# AC26 AC23 DDRA_SDQS4#
8 DDRA_SBS0# MA_BANK0 MB_BANK0 DDRB_SBS0# 9 9 DDRB_SDQS4# MB_DQS_L4 MA_DQS_L4 DDRA_SDQS4# 8
DDRA_SBS1# R23 U26 DDRB_SBS1# DDRB_SDQS5 AF21 AB19 DDRA_SDQS5
8 DDRA_SBS1# MA_BANK1 MB_BANK1 DDRB_SBS1# 9 9 DDRB_SDQS5 MB_DQS_H5 MA_DQS_H5 DDRA_SDQS5 8
DDRA_SBS2# J21 J26 DDRB_SBS2# DDRB_SDQS5# AF22 AB20 DDRA_SDQS5#
8 DDRA_SBS2# MA_BANK2 MB_BANK2 DDRB_SBS2# 9 9 DDRB_SDQS5# MB_DQS_L5 MA_DQS_L5 DDRA_SDQS5# 8
DDRB_SDQS6 AE16 Y15 DDRA_SDQS6
9 DDRB_SDQS6 MB_DQS_H6 MA_DQS_H6 DDRA_SDQS6 8
DDRA_SRAS# R19 U25 DDRB_SRAS# DDRB_SDQS6# AD16 W15 DDRA_SDQS6#
8 DDRA_SRAS# MA_RAS_L MB_RAS_L DDRB_SRAS# 9 9 DDRB_SDQS6# MB_DQS_L6 MA_DQS_L6 DDRA_SDQS6# 8
DDRA_SCAS# T22 U24 DDRB_SCAS# DDRB_SDQS7 AF12 W12 DDRA_SDQS7
8 DDRA_SCAS# MA_CAS_L MB_CAS_L DDRB_SCAS# 9 9 DDRB_SDQS7 MB_DQS_H7 MA_DQS_H7 DDRA_SDQS7 8
DDRA_SWE# T24 U23 DDRB_SWE# DDRB_SDQS7# AE12 W13 DDRA_SDQS7#
8 DDRA_SWE# MA_WE_L MB_WE_L DDRB_SWE# 9 9 DDRB_SDQS7# MB_DQS_L7 MA_DQS_L7 DDRA_SDQS7# 8

6090022100G_B 6090022100G_B
conn@ conn@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
401679 C

hexainf@hotmail.com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 26, 2009 Sheet 5 of 57
A B C D E
GRATIS - FOR FREE
A B C D E

+2.5VDDA
L35 VDDA=0.25A
+2.5VS 1 2 3300P_0402_50V7K
FBM_L11_201209_300L_0805
1 1 1 1 +1.8V 1 2
R66 10K_0402_5%
+ C391 4.7U_0805_10V4Z C385 C319 C384 1 2
150U_B2_6.3VM 0.22U_0603_16V4Z R67 300_0402_5%
2 2 2
2

2
B
Q9
1 JCPU1D CPU_THERMTRIP#_R R65 1

E
3 1 1 2 H_THERMTRIP# 28
0_0402_5%

C
F8 M11 MMBT3904_NL_SOT23-3
VDDA1 KEY1
F9 VDDA2 KEY2 W18

1 2 3900P_0402_50V7K CPU_CLKIN_SC_P A9 A6 CPU_SVC


23 CLK_CPU_BCLK CLKIN_H SVC CPU_SVC 53
C723 CPU_CLKIN_SC_N A8 A4 CPU_SVD
CLKIN_L SVD CPU_SVD 53

1
+1.8V 1 2
LDT_RST# B7 R69 300_0402_5%
R325 H_PWRGD RESET_L
A7 PWROK
169_0402_1% LDT_STOP# F10 AF6 CPU_THERMTRIP#_R
LDTSTOP_L THERMTRIP_L H_PROCHOT#
11 CPU_LDT_REQ# C6 LDTREQ_L PROCHOT_L AC7

2
1 2 AA8 H_PROCHOT# 1 R68 2
23 CLK_CPU_BCLK# MEMHOT_L H_PROCHOT_R# 27
C724 3900P_0402_50V7K +1.8V R70 2 1 2.2K_0402_5% CPU_SIC AF4 0_0402_5%
CPU_SID SIC
+1.8V 2 1 AF5 SID
+1.8VS R71 2.2K_0402_5% AE6 W7 THERMDC_CPU
ALERT_L THERMDC THERMDA_CPU
THERMDA W8
R82 1 2 44.2_0402_1% CPU_HTREF0 R6 HT_REF0
2

+1.2V_HT R89 1 2 44.2_0402_1% CPU_HTREF1 P6


R339 HT_REF1
300_0402_5% 53 CPU_VDD0_FB_H CPU_VDD0_FB_H F6 W9
VDD0_FB_H VDDIO_FB_H PAD T6
53 CPU_VDD0_FB_L CPU_VDD0_FB_L E6 Y9
VDD0_FB_L VDDIO_FB_L PAD T5
1

LDT_RST# 53 CPU_VDD1_FB_H CPU_VDD1_FB_H Y6 H6 CPU_VDDNB_FB_H


27 LDT_RST# VDD1_FB_H VDDNB_FB_H CPU_VDDNB_FB_H 53
53 CPU_VDD1_FB_L CPU_VDD1_FB_L AB6 G6 CPU_VDDNB_FB_L
VDD1_FB_L VDDNB_FB_L CPU_VDDNB_FB_L 53
1
C721 CPU_DBRDY G10
0.01U_0402_25V4Z CPU_TMS DBRDY CPU_DBREQ#
AA9 TMS DBREQ_L E10
@ CPU_TCK AC9
2 CPU_TRST# TCK CPU_TDO
AD9 TRST_L TDO AE9
CPU_TDI AF9 TDI
2 T44 PAD CPU_TEST23 CPU_TEST28_H_PLLCHRZ_P 2
AD7 TEST23 TEST28_H J7 PAD T24
H8 CPU_TEST28_L_PLLCHRZ_N
+1.8VS TEST28_L PAD T21
T25 PAD CPU_TEST18 H10
T26 PAD CPU_TEST19 TEST18 CPU_TEST17
G9 TEST19 TEST17 D7 PAD T34
E7 CPU_TEST16
TEST16 PAD T36
2

T37 PAD CPU_TEST25H E9 F7 CPU_TEST15 +1.8V


TEST25_H TEST15 PAD T32
R338 T33 PAD CPU_TEST25L E8 C7 CPU_TEST14
TEST25_L TEST14 PAD T38
300_0402_5%
CPU_TEST21 AB8 C3 CPU_TEST7 CPU_SVC 1 2
TEST21 TEST7 PAD T31
T43 PAD CPU_TEST20 AF7 K8 CPU_TEST10 CPU_SVD R328 1 1K_0402_5%
2
TEST20 TEST10 PAD T18
1

H_PWRGD CPU_TEST24 AE7 R329 1K_0402_5%


27 H_PWRGD TEST24
T42 PAD CPU_TEST22 AE8 C4 CPU_TEST8
TEST22 TEST8 PAD T67
1 T3 PAD CPU_TEST12 AC8
C720 T41 PAD CPU_TEST27 TEST12
AF8 TEST27
0.01U_0402_25V4Z C9 CPU_TEST29_H_FBCLKOUT_P
TEST29_H PAD T39
@ 1 R330 2 0_0402_5% C2 C8 CPU_TEST29_L_FBCLKOUT_N
2 TEST9 TEST29_L PAD T35
T2 PAD CPU_TEST6 AA6 TEST6
A3 RSVD1 RSVD10 H18
A5 RSVD2 RSVD9 H19
B3 RSVD3 RSVD8 AA7
+1.8VS B5 D5 +1.8V
RSVD4 RSVD7 TIGRIS@
C1 RSVD5 RSVD6 C5
DVT2 CPU internal thermal sensor For Tigris CPU_TEST25H 1 2
2

R144 300_0402_5%
R337 6090022100G_B CPU_TEST25L 1 2
300_0402_5% 1 2 R143 300_0402_5%
conn@ CPU_DBREQ# 1 2
C92 @ 0.1U_0402_16V4Z R327 300_0402_5%
1

LDT_STOP# CPU_TEST21 1 2
11,27 LDT_STOP# R52
R53 FDV301N, the Vgs is: R75 300_0402_5%
1 +3VS 2 1 2 1 CPU_TEST24 1 2
3 C719
min = 0.65V R74 300_0402_5% 3
0.01U_0402_25V4Z 20K_0402_5% 34.8K_0402_1% Typ = 0.85V CPU_TEST20 1 2
@ @ @ Max = 1.5V R73 300_0402_5%
2 CPU_TEST23 1 2
2.09V for Gate R72 300_0402_5%
2

CPU_TEST25H
G

1 2
@ R136 300_0402_5%
CPU_SID 3 1 EC_SMB_DA 1 2 EC_SMB_DA2 CPU_TEST25L 1 2
R479 0_0402_5% R135 300_0402_5%
S

@ EC_SMB_DA1
For Tigris TIGRIS@
1 2 EC_SMB_DA1 38,47
Q7 @ FDV301N_NL_SOT23-3 R484 0_0402_5%
+1.8V
DVT
+1.8V
2
G

220_0402_5%R117

220_0402_5%R118

220_0402_5%R119

220_0402_5%R120
@

1
CPU_SIC 3 1 EC_SMB_CK 1 2 EC_SMB_CK2
R480 0_0402_5%
S

1 @ 2 EC_SMB_CK1 EC_SMB_CK1 38,47 JP1


Q8 @ FDV301N_NL_SOT23-3 R485 0_0402_5%
1 2
3 4

2
CPU_DBREQ# HDT@ HDT@ 5 6 R140 2
7 8 1
+3VS CPU_DBRDY HDT@ HDT@ @ 0_0402_5%
CPU_TCK
9 10
CPU_TMS 11 12 +3VS
CPU_TDI 13 14
CPU_TRST# 15 16 MP(Remove)
0.1U_0402_16V4Z

1 17 18

5
CPU_TDO U15
C206 19 20 LDT_RST#
2

P
21 22 HDT_RST# B
MP(Remove) 23 24 4 Y
2 U11
26 A 1 SB_PWRGD 11,28,41 4

G
4 EC_SMB_CK2
1 VDD SCLK 8 EC_SMB_CK2 22,38
NC7SZ08P5X_NL_SC70-5

3
THERMDA_CPU 2 7 EC_SMB_DA2 CONN@ SAMTEC_ASP-68200-07 HDT@
D+ SDATA EC_SMB_DA2 22,38
C194 THERMDC_CPU 3 6 MP(mask)
D- ALERT#
1 2
2200P_0402_50V7K 4 5
THERM# GND
PUMA@
Change as 3300pF
Security Classification Compal Secret Data Compal Electronics, Inc.
ADM1032ARMZ_MSOP8
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
For Tigris
Address 1001 100X b THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 6 of 57


A B C D E
A B C D E

VDD0 = 18A VDD1 =18A JCPU1F

VDD(+CPU_CORE) decoupling. +CPU_CORE_0 JCPU1E +CPU_CORE_1


AA4
AA11
VSS1
VSS2
VSS66
VSS67
J6
J8
AA13 VSS3 VSS68 J10
G4 VDD0_1 VDD1_1 P8 AA15 VSS4 VSS69 J12
H2 VDD0_2 VDD1_2 P10 AA17 VSS5 VSS70 J14
+CPU_CORE_0 +CPU_CORE_1 J9 R4 AA19 J16
VDD0_3 VDD1_3 VSS6 VSS71
J11 VDD0_4 VDD1_4 R7 AB2 VSS7 VSS72 J18
J13 VDD0_5 VDD1_5 R9 AB7 VSS8 VSS73 K2
J15 VDD0_6 VDD1_6 R11 AB9 VSS9 VSS74 K7
1 1 1 1 K6 VDD0_7 VDD1_7 T2 AB23 VSS10 VSS75 K9
K10 VDD0_8 VDD1_8 T6 AB25 VSS11 VSS76 K11
+ C106 + C661 + C96 + C643 K12 T8 AC11 K13
1 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M VDD0_9 VDD1_9 VSS12 VSS77 1
K14 VDD0_10 VDD1_10 T10 AC13 VSS13 VSS78 K15
L4 VDD0_11 VDD1_11 T12 AC15 VSS14 VSS79 K17
2 2 2 2
L7 VDD0_12 VDD1_12 T14 AC17 VSS15 VSS80 L6
L9 VDD0_13 VDD1_13 U7 AC19 VSS16 VSS81 L8
L11 U9 AC21 L10
Near CPU Socket L13
VDD0_14
VDD0_15
VDD1_14
VDD1_15 U11 AD6
VSS17
VSS18
VSS82
VSS83 L12
VDDNB=4A L15 VDD0_16 VDD1_16 U13 AD8 VSS19 VSS84 L14
M2 VDD0_17 VDD1_17 U15 AD25 VSS20 VSS85 L16
(For Tigris) M6 V6 AE11 L18
VDD0_18 VDD1_18 VSS21 VSS86
M8 VDD0_19 VDD1_19 V8 AE13 VSS22 VSS87 M7
+CPU_CORE_0 VDDNB=3A M10 V10 AE15 M9
+CPU_CORE_1 VDD0_20 VDD1_20 VSS23 VSS88
N7 VDD0_21 VDD1_21 V12 AE17 VSS24 VSS89 AC6
N9 VDD0_22 VDD1_22 V14 AE19 VSS25 VSS90 M17
+CPU_CORE_NB N11 W4 AE21 N4
VDD0_23 VDD1_23 VSS26 VSS91
1 1 1 1 VDD1_24 Y2 AE23 VSS27 VSS92 N8
C280 C281 C273 C257 1 1 1 1 K16 AC4 B4 N10
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M C214 C238 C227 C215 VDDNB_1 VDD1_25 +1.8V VSS28 VSS93
M16 VDDNB_2 VDD1_26 AD2 B6 VSS29 VSS94 N16
22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M P16 B8 N18
2 2 2 2 VDDNB_3 VSS30 VSS95
T16 VDDNB_4 VDDIO27 Y25 B9 VSS31 VSS96 P2
2 2 2 2 +1.8V V16 VDDNB_5 VDDIO26 V25 B11 VSS32 VSS97 P7
VDDIO25 V23 B13 VSS33 VSS98 P9
+CPU_CORE_0 H25 V21 B15 P11
+CPU_CORE_1 VDDIO1 VDDIO24 VSS34 VSS99
J17 VDDIO2 VDDIO23 V18 B17 VSS35 VSS100 P17
VDDIO=3A K18 VDDIO3 VDDIO22 U17 B19 VSS36 VSS101 R8
K21 VDDIO4 VDDIO21 T25 B21 VSS37 VSS102 R10
1 1 1 1 1 1 K23 VDDIO5 VDDIO20 T23 B23 VSS38 VSS103 R16
C253 C276 C290 C244 C184 C230 K25 T21 B25 R18
0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 0.22U_0603_16V4Z 0.01U_0402_25V4Z 180P_0402_50V8J VDDIO6 VDDIO19 VSS39 VSS104
L17 VDDIO7 VDDIO18 T18 D6 VSS40 VSS105 T7
M18 VDDIO8 VDDIO17 R17 D8 VSS41 VSS106 T9
2 2 2 2 2 2
M21 VDDIO9 VDDIO16 P25 D9 VSS42 VSS107 T11
M23 P23 D11 T13
Under CPU Socket M25
VDDIO10
VDDIO11
VDDIO15
VDDIO14 P21 D13
VSS43
VSS44
VSS108
VSS109 T15
2 2
N17 VDDIO12 VDDIO13 P18 D15 VSS45 VSS110 T17
D17 VSS46 VSS111 U4
D19 VSS47 VSS112 U6
6090022100G_B D21 U8
Athlon 64 S1 VSS48 VSS113
D23 VSS49 VSS114 U10
VDDIO decoupling. Processor Socket
conn@
D25
E4
VSS50
VSS51
VSS115
VSS116
U12
U14
F2 VSS52 VSS117 U16

+1.8V
+CPU_CORE_NB decoupling. F11
F13
VSS53
VSS54
VSS118
VSS119
U18
V2
F15 VSS55 VSS120 V7
F17 VSS56 VSS121 V9
+CPU_CORE_NB F19 V11
VSS57 VSS122
F21 VSS58 VSS123 V13
1 1 1 1 1 1 F23 VSS59 VSS124 V15
C195 C228 C222 C294 C295 C274 1 1 1 F25 V17
22U_0805_6.3V6M 22U_0805_6.3V6M C207 C186 C249 VSS60 VSS125
H7 VSS61 VSS126 W6
0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M H9 Y21
2 2 2 2 2 2 VSS62 VSS127
H21 VSS63 VSS128 Y23
2 2 2
H23 VSS64 VSS129 N6
J4 VSS65
6090022100G_B
Under CPU Socket Athlon 64 S1
Processor Socket
conn@

Between CPU Socket and DIMM


+1.8V +0.9V
3 3
Near Power Supply
1
C301
1
C302
1
C303
1
C300
VTT decoupling. C107
1
+
C: Change to NBO CAP
1
C113
0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 220U_D2_4VM_R15 22U_0805_6.3V6M
2 2 2 2 2 2

180PF Qt'y follow the distance between


+1.8V +1.8V CPU socket and DIMM0. <2.5inch> +0.9V

1 1 1 1 1 1
C309 C307 C218 C308 C310 C219 1 1 1 1 1 1 1 1
0.01U_0402_25V4Z 0.01U_0402_25V4Z 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J 180P_0402_50V8J C163 C164 C109 C110 C190 C191 C189 C173
4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2
A: Add C165 and C176 2 2 2 2 2 2 2 2
to follow AMD Layout
+1.8V
review recommand for
EMI Near CPU Socket Right side.
+0.9V
1
1 1 1 1 C: Change to NBO CAP
+ C226
C211 C209 C208 C210 330U_X_2VM_R6M 1 1 1 1 1 1 1 1
4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z 4.7U_0805_10V4Z C387 C386 C383 C382 C718 C717 C716 C715
2 2 2 2 2 4.7U_0805_10V4Z 4.7U_0805_10V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 1000P_0402_25V8J 1000P_0402_25V8J 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2 2 2
4 4

Near CPU Socket Left side.

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
401679 C

hexainf@hotmail.com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 26, 2009 Sheet 7 of 57
A B C D E
GRATIS - FOR FREE
A B C D E

+1.8V +1.8V

JDIMM1
+V_DDR_MCH_REF 1 VREF VSS 2
3 4 DDRA_SDQ4
DDRA_SDQ0 VSS DQ4 DDRA_SDQ5
5 DQ0 DQ5 6
DDRA_SDQ1 7 8 DDRA_SDQ[0..63]
DQ1 VSS DDRA_SDM0 DDRA_SDQ[0..63] 5
9 VSS DM0 10
DDRA_SDQS0# 11 12 DDRA_SDM[0..7]
5 DDRA_SDQS0# DQS0# VSS DDRA_SDM[0..7] 5
DDRA_SDQS0 13 14 DDRA_SDQ6
1 5 DDRA_SDQS0 DQS0 DQ6 DDRA_SDQ7 1
15 VSS DQ7 16
DDRA_SDQ2 17 18
DDRA_SDQ3 DQ2 VSS DDRA_SDQ12 DDRA_SMA[0..15]
19 DQ3 DQ12 20 DDRA_SMA[0..15] 5
21 22 DDRA_SDQ13
DDRA_SDQ8 VSS DQ13
23 DQ8 VSS 24
DDRA_SDQ9 25 26 DDRA_SDM1
DQ9 DM1 +0.9V +1.8V
27 VSS VSS 28
DDRA_SDQS1# 29 30 RP10
5 DDRA_SDQS1# DQS1# CK0 DDRA_CLK0 5
DDRA_SDQS1 31 32 DDRA_SMA6 1 8 1 2
5 DDRA_SDQS1 DQS1 CK0# DDRA_CLK0# 5
33 34 DDRA_SMA7 2 7 C182 0.1U_0402_16V4Z
DDRA_SDQ10 VSS VSS DDRA_SDQ14 DDRA_SMA11
35 DQ10 DQ14 36 3 6 1 2
DDRA_SDQ11 37 38 DDRA_SDQ15 DDRA_SMA15 4 5 C198 0.1U_0402_16V4Z
DQ11 DQ15
39 VSS VSS 40
+1.8V 47_0804_8P4R_5%
RP13
41 42 DDRA_CKE0 8 1 1 2
VSS VSS

2
DDRA_SDQ16 43 44 DDRA_SDQ20 DDRA_SBS2# 7 2 C225 0.1U_0402_16V4Z
DDRA_SDQ17 DQ16 DQ20 DDRA_SDQ21 R147 DDRA_SMA14
45 DQ17 DQ21 46 6 3 1 2
47 48 1K_0402_1% DDRA_CKE1 5 4 C223 0.1U_0402_16V4Z
DDRA_SDQS2# VSS VSS
5 DDRA_SDQS2# 49 DQS2# NC 50
DDRA_SDQS2 51 52 DDRA_SDM2 47_0804_8P4R_5%
5 DDRA_SDQS2 DQS2 DM2

1
53 54 +V_DDR_MCH_REF +V_DDR_MCH_REF RP8
DDRA_SDQ18 VSS VSS DDRA_SDQ22 DDRA_SBS1#
55 DQ18 DQ22 56 1 8 1 2
DDRA_SDQ19 DDRA_SDQ23 DDRA_SMA0 C159 0.1U_0402_16V4Z

1000P_0402_25V8J

1U_0402_6.3V4Z
57 DQ19 DQ23 58 1 1 2 7

2
59 60 DDRA_SMA2 3 6 1 2
DDRA_SDQ24 VSS VSS DDRA_SDQ28 R148 DDRA_SMA4 C167 0.1U_0402_16V4Z

C392

C394
61 DQ24 DQ28 62 4 5
DDRA_SDQ25 63 64 DDRA_SDQ29 1K_0402_1%
DQ25 DQ29 2 2 47_0804_8P4R_5%
65 VSS VSS 66
DDRA_SDM3 67 68 DDRA_SDQS3# RP9
DM3 DQS3# DDRA_SDQS3# 5

1
69 70 DDRA_SDQS3 DDRA_SMA5 8 1 1 2
NC DQS3 DDRA_SDQS3 5 DDRA_SMA8 C179 0.1U_0402_16V4Z
71 VSS VSS 72 7 2
DDRA_SDQ26 73 74 DDRA_SDQ30 DDRA_SMA9 6 3 1 2
2 DDRA_SDQ27 DQ26 DQ30 DDRA_SDQ31 DDRA_SMA12 C185 0.1U_0402_16V4Z 2
75 DQ27 DQ31 76 5 4
77 VSS VSS 78
DDRA_CKE0 79 80 DDRA_CKE1 47_0804_8P4R_5%
5 DDRA_CKE0 CKE0 NC/CKE1 DDRA_CKE1 5
81 82 RP7
VDD VDD DDRA_SMA15 DDRA_SBS0#
83 NC NC/A15 84 8 1 1 2
DDRA_SBS2# 85 86 DDRA_SMA14 DDRA_SMA10 7 2 C169 0.1U_0402_16V4Z
5 DDRA_SBS2# BA2 NC/A14
87 88 DDRA_SMA1 6 3 1 2
DDRA_SMA12 VDD VDD DDRA_SMA11 DDRA_SMA3 C161 0.1U_0402_16V4Z
89 A12 A11 90 5 4
DDRA_SMA9 91 92 DDRA_SMA7
DDRA_SMA8 A9 A7 DDRA_SMA6 47_0804_8P4R_5%
93 A8 A6 94
95 96 RP4
DDRA_SMA5 VDD VDD DDRA_SMA4 DDRA_SCS1#
97 A5 A4 98 8 1 1 2
DDRA_SMA3 99 100 DDRA_SMA2 DDRA_ODT1 7 2 C157 0.1U_0402_16V4Z
DDRA_SMA1 A3 A2 DDRA_SMA0 DDRA_SWE#
101 A1 A0 102 6 3 1 2
103 104 DDRA_SCAS# 5 4 C142 0.1U_0402_16V4Z
DDRA_SMA10 VDD VDD DDRA_SBS1#
105 A10/AP BA1 106 DDRA_SBS1# 5
DDRA_SBS0# 107 108 DDRA_SRAS# 47_0804_8P4R_5%
5 DDRA_SBS0# BA0 RAS# DDRA_SRAS# 5
DDRA_SWE# 109 110 DDRA_SCS0# RP3
5 DDRA_SWE# WE# S0# DDRA_SCS0# 5
111 112 DDRA_SMA13 1 8 1 2
DDRA_SCAS# VDD VDD DDRA_ODT0 DDRA_ODT0 C145 0.1U_0402_16V4Z
5 DDRA_SCAS# 113 CAS# ODT0 114 DDRA_ODT0 5 2 7
DDRA_SCS1# 115 116 DDRA_SMA13 DDRA_SCS0# 3 6 1 2
5 DDRA_SCS1# NC/S1# NC/A13
117 118 DDRA_SRAS# 4 5 C135 0.1U_0402_16V4Z
DDRA_ODT1 VDD VDD
5 DDRA_ODT1 119 NC/ODT1 NC 120
121 122 47_0804_8P4R_5%
DDRA_SDQ32 VSS VSS DDRA_SDQ36
123 DQ32 DQ36 124
DDRA_SDQ33 125 126 DDRA_SDQ37
DQ33 DQ37
127 VSS VSS 128
DDRA_SDQS4# 129 130 DDRA_SDM4
5 DDRA_SDQS4# DDRA_SDQS4 DQS4# DM4
5 DDRA_SDQS4 131 DQS4 VSS 132
133 134 DDRA_SDQ38
DDRA_SDQ34 VSS DQ38 DDRA_SDQ39
135 DQ34 DQ39 136
DDRA_SDQ35 137 138
3 DQ35 VSS DDRA_SDQ44 3
139 VSS DQ44 140
DDRA_SDQ40 141 142 DDRA_SDQ45
DDRA_SDQ41 DQ40 DQ45
143 DQ41 VSS 144
145 146 DDRA_SDQS5#
DDRA_SDM5 VSS DQS5# DDRA_SDQS5 DDRA_SDQS5# 5
147 DM5 DQS5 148 DDRA_SDQS5 5
149 VSS VSS 150
DDRA_SDQ42 151 152 DDRA_SDQ46
DDRA_SDQ43 DQ42 DQ46 DDRA_SDQ47
153 DQ43 DQ47 154
155 VSS VSS 156
DDRA_SDQ48 157 158 DDRA_SDQ52
DDRA_SDQ49 DQ48 DQ52 DDRA_SDQ53
159 DQ49 DQ53 160 DVT(EMI)
161 VSS VSS 162
163 164 +1.8V
NC,TEST CK1 DDRA_CLK1 5
165 VSS CK1# 166 DDRA_CLK1# 5
DDRA_SDQS6# 167 168
5 DDRA_SDQS6# DDRA_SDQS6 DQS6# VSS DDRA_SDM6
5 DDRA_SDQS6 169 DQS6 DM6 170 1 2
171 172 C174 0.1U_0402_16V4Z
DDRA_SDQ50 VSS VSS DDRA_SDQ54
173 DQ50 DQ54 174
DDRA_SDQ51 175 176 DDRA_SDQ55 1 2
DQ51 DQ55 C175 0.1U_0402_16V4Z
177 VSS VSS 178
DDRA_SDQ56 179 180 DDRA_SDQ60
DDRA_SDQ57 DQ56 DQ60 DDRA_SDQ61
181 DQ57 DQ61 182 1 2
183 184 C176 0.1U_0402_16V4Z
DDRA_SDM7 VSS VSS DDRA_SDQS7#
185 DM7 DQS7# 186 DDRA_SDQS7# 5
187 188 DDRA_SDQS7
DDRA_SDQ58 VSS DQS7 DDRA_SDQS7 5
189 DQ58 VSS 190
DDRA_SDQ59 191 192 DDRA_SDQ62
DQ59 DQ62 DDRA_SDQ63
193 VSS DQ63 194
ICH_SMBDATA0 195 196
9,23,28,36 ICH_SMBDATA0 SDA VSS
ICH_SMBCLK0 197 198 R39 1 2 10K_0402_5%
9,23,28,36 ICH_SMBCLK0 SCL SAO
+3VS 199 200 R36 1 2 10K_0402_5%
VDDSPD SA1
203 GND GND 204
4 4
FOX_AS0A426-M2RN-7F
+3VS CONN@

1 1
C67 C63 DIMM1 REV H:5.2mm (BOT) Security Classification Compal Secret Data Compal Electronics, Inc.
2
0.1U_0402_16V4Z
2 Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
2.2U_0805_10V6K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 8 of 57


A B C D E
A B C D E

+V_DDR_MCH_REF +1.8V

+1.8V

2.2U_0603_6.3V4Z
1
C390 JDIMM2 DDRB_SDQ[0..63]
DDRB_SDQ[0..63] 5
1 VREF VSS 2
2 DDRB_SDQ4 DDRB_SDM[0..7]
3 VSS DQ4 4 DDRB_SDM[0..7] 5
DDRB_SDQ0 5 6 DDRB_SDQ5
DDRB_SDQ1 DQ0 DQ5
7 DQ1 VSS 8
9 10 DDRB_SDM0
DDRB_SDQS0# VSS DM0 DDRB_SMA[0..15]
5 DDRB_SDQS0# 11 DQS0# VSS 12 DDRB_SMA[0..15] 5
1 DDRB_SDQS0 DDRB_SDQ6 1
5 DDRB_SDQS0 13 DQS0 DQ6 14
15 16 DDRB_SDQ7
DDRB_SDQ2 VSS DQ7
17 DQ2 VSS 18
DDRB_SDQ3 19 20 DDRB_SDQ12
DQ3 DQ12 DDRB_SDQ13
21 VSS DQ13 22
DDRB_SDQ8 23 24
DDRB_SDQ9 DQ8 VSS DDRB_SDM1
25 DQ9 DM1 26
27 VSS VSS 28
DDRB_SDQS1# 29 30
5 DDRB_SDQS1# DQS1# CK0 DDRB_CLK0 5
DDRB_SDQS1 31 32
5 DDRB_SDQS1 DQS1 CK0# DDRB_CLK0# 5 +1.8V
33 34 +0.9V
DDRB_SDQ10 VSS VSS DDRB_SDQ14 RP6
35 DQ10 DQ14 36
DDRB_SDQ11 37 38 DDRB_SDQ15 DDRB_SRAS# 1 8 2 1
DQ11 DQ15 DDRB_SMA0 C171 0.1U_0402_16V4Z
39 VSS VSS 40 2 7
DDRB_SMA2 3 6 1 2
DDRB_SMA4 4 5 C201 0.1U_0402_16V4Z
41 VSS VSS 42
DDRB_SDQ16 43 44 DDRB_SDQ20 47_0804_8P4R_5%
DDRB_SDQ17 DQ16 DQ20 DDRB_SDQ21
45 DQ17 DQ21 46
47 48 RP12
DDRB_SDQS2# VSS VSS DDRB_SMA6
5 DDRB_SDQS2# 49 DQS2# NC 50 1 8 2 1
DDRB_SDQS2 51 52 DDRB_SDM2 DDRB_SMA7 2 7 C180 0.1U_0402_16V4Z
5 DDRB_SDQS2 DQS2 DM2 DDRB_SMA11
53 VSS VSS 54 3 6 1 2
DDRB_SDQ18 55 56 DDRB_SDQ22 DDRB_SMA14 4 5 C224 0.1U_0402_16V4Z
DDRB_SDQ19 DQ18 DQ22 DDRB_SDQ23
57 DQ19 DQ23 58
59 60 47_0804_8P4R_5%
DDRB_SDQ24 VSS VSS DDRB_SDQ28
61 DQ24 DQ28 62
DDRB_SDQ25 63 64 DDRB_SDQ29 RP14
DQ25 DQ29 DDRB_CKE0
65 VSS VSS 66 8 1 2 1
DDRB_SDM3 67 68 DDRB_SDQS3# DDRB_SBS2# 7 2 C200 0.1U_0402_16V4Z
DM3 DQS3# DDRB_SDQS3 DDRB_SDQS3# 5 DDRB_SMA15
69 NC DQS3 70 DDRB_SDQS3 5 6 3 1 2
71 72 DDRB_CKE1 5 4 C231 0.1U_0402_16V4Z
2 DDRB_SDQ26 VSS VSS DDRB_SDQ30 2
73 DQ26 DQ30 74
DDRB_SDQ27 75 76 DDRB_SDQ31 47_0804_8P4R_5%
DQ27 DQ31
77 VSS VSS 78
DDRB_CKE0 79 80 DDRB_CKE1 RP11
5 DDRB_CKE0 CKE0 NC/CKE1 DDRB_CKE1 5
81 82 DDRB_SMA8 8 1 2 1
VDD VDD DDRB_SMA15 DDRB_SMA5 C183 0.1U_0402_16V4Z
83 NC NC/A15 84 7 2
DDRB_SBS2# 85 86 DDRB_SMA14 DDRB_SMA12 6 3 1 2
5 DDRB_SBS2# BA2 NC/A14
87 88 DDRB_SMA9 5 4 C197 0.1U_0402_16V4Z
DDRB_SMA12 VDD VDD DDRB_SMA11
89 A12 A11 90
DDRB_SMA9 91 92 DDRB_SMA7 47_0804_8P4R_5%
DDRB_SMA8 A9 A7 DDRB_SMA6
93 A8 A6 94
95 96 RP5
DDRB_SMA5 VDD VDD DDRB_SMA4 DDRB_SBS0#
97 A5 A4 98 8 1 2 1
DDRB_SMA3 99 100 DDRB_SMA2 DDRB_SMA10 7 2 C146 0.1U_0402_16V4Z
DDRB_SMA1 A3 A2 DDRB_SMA0 DDRB_SMA3
101 A1 A0 102 6 3 1 2
103 104 DDRB_SMA1 5 4 C170 0.1U_0402_16V4Z
DDRB_SMA10 VDD VDD DDRB_SBS1#
105 A10/AP BA1 106 DDRB_SBS1# 5
DDRB_SBS0# 107 108 DDRB_SRAS# 47_0804_8P4R_5%
5 DDRB_SBS0# BA0 RAS# DDRB_SRAS# 5
DDRB_SWE# 109 110 DDRB_SCS0#
5 DDRB_SWE# WE# S0# DDRB_SCS0# 5
111 112 RP1
DDRB_SCAS# VDD VDD DDRB_ODT0 DDRB_ODT1
5 DDRB_SCAS# 113 CAS# ODT0 114 DDRB_ODT0 5 8 1 2 1
DDRB_SCS1# 115 116 DDRB_SMA13 DDRB_SCS1# 7 2 C122 0.1U_0402_16V4Z
5 DDRB_SCS1# NC/S1# NC/A13
117 118 DDRB_SWE# 6 3 1 2
DDRB_ODT1 VDD VDD DDRB_SCAS# C117 0.1U_0402_16V4Z
5 DDRB_ODT1 119 NC/ODT1 NC 120 5 4
121 VSS VSS 122
DDRB_SDQ32 123 124 DDRB_SDQ36 47_0804_8P4R_5%
DDRB_SDQ33 DQ32 DQ36 DDRB_SDQ37
125 DQ33 DQ37 126
127 128 RP2
DDRB_SDQS4# VSS VSS DDRB_SDM4 DDRB_SMA13
5 DDRB_SDQS4# 129 DQS4# DM4 130 1 8 2 1
DDRB_SDQS4 131 132 DDRB_ODT0 2 7 C147 0.1U_0402_16V4Z
5 DDRB_SDQS4 DQS4 VSS DDRB_SDQ38 DDRB_SCS0#
133 VSS DQ38 134 3 6 1 2
DDRB_SDQ34 135 136 DDRB_SDQ39 DDRB_SBS1# 4 5 C118 0.1U_0402_16V4Z
3 DDRB_SDQ35 DQ34 DQ39 3
137 DQ35 VSS 138
139 140 DDRB_SDQ44 47_0804_8P4R_5%
DDRB_SDQ40 VSS DQ44 DDRB_SDQ45
141 DQ40 DQ45 142
DDRB_SDQ41 143 144
DQ41 VSS DDRB_SDQS5#
145 VSS DQS5# 146 DDRB_SDQS5# 5
DDRB_SDM5 147 148 DDRB_SDQS5
DM5 DQS5 DDRB_SDQS5 5
149 VSS VSS 150
DDRB_SDQ42 151 152 DDRB_SDQ46
DDRB_SDQ43 DQ42 DQ46 DDRB_SDQ47
153 DQ43 DQ47 154
155 VSS VSS 156
DDRB_SDQ48 157 158 DDRB_SDQ52
DDRB_SDQ49 DQ48 DQ52 DDRB_SDQ53
159 DQ49 DQ53 160
161 VSS VSS 162
163 NC,TEST CK1 164 DDRB_CLK1 5
165 VSS CK1# 166 DDRB_CLK1# 5
DDRB_SDQS6# 167 168
5 DDRB_SDQS6# DDRB_SDQS6 DQS6# VSS DDRB_SDM6
5 DDRB_SDQS6 169 DQS6 DM6 170
171 VSS VSS 172
DDRB_SDQ50 173 174 DDRB_SDQ54
DDRB_SDQ51 DQ50 DQ54 DDRB_SDQ55
175 DQ51 DQ55 176
177 VSS VSS 178
DDRB_SDQ56 179 180 DDRB_SDQ60
DDRB_SDQ57 DQ56 DQ60 DDRB_SDQ61
181 DQ57 DQ61 182
183 VSS VSS 184
DDRB_SDM7 185 186 DDRB_SDQS7#
DM7 DQS7# DDRB_SDQS7 DDRB_SDQS7# 5
187 VSS DQS7 188 DDRB_SDQS7 5
DDRB_SDQ58 189 190
DDRB_SDQ59 DQ58 VSS DDRB_SDQ62
191 DQ59 DQ62 192
193 194 DDRB_SDQ63
ICH_SMBDATA0 VSS DQ63
8,23,28,36 ICH_SMBDATA0 195 SDA VSS 196
ICH_SMBCLK0 197 198 R37 1 2 10K_0402_5% +3VS
8,23,28,36 ICH_SMBCLK0 SCL SAO
+3VS 199 200 R35 1 2 10K_0402_5%
4 VDDSPD SA1 4
201 GND GND 202

FOX_AS0A426-MARG-7F
CONN@

DIMM2 REV H:9.2mm (BOT)


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
401679 C

hexainf@hotmail.com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 26, 2009 Sheet 9 of 57
A B C D E
GRATIS - FOR FREE
A B C D E

PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] PCIE_MTX_GRX_N[0..3]


14 PCIE_GTX_C_MRX_P[0..15] PCIE_MTX_C_GRX_P[0..15] 14 PCIE_MTX_GRX_N[0..3] 25
PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] PCIE_MTX_GRX_P[0..3]
14 PCIE_GTX_C_MRX_N[0..15] PCIE_MTX_C_GRX_N[0..15] 14 PCIE_MTX_GRX_P[0..3] 25

U3B DVT
PCIE_GTX_C_MRX_P0 D4 A5 PCIE_MTX_GRX_P0 C647 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P0
PCIE_GTX_C_MRX_N0 GFX_RX0P GFX_TX0P PCIE_MTX_GRX_N0 C646 1 PCIE_MTX_C_GRX_N0
C4 GFX_RX0N PART 2 OF 6 GFX_TX0N B5 2 VGA@ 0.1U_0402_16V7K
PCIE_GTX_C_MRX_N1 A3 A4 PCIE_MTX_GRX_P1 C649 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P1
PCIE_GTX_C_MRX_P1 GFX_RX1P GFX_TX1P PCIE_MTX_GRX_N1 C648 1
B3 GFX_RX1N GFX_TX1N B4 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N1
1 PCIE_GTX_C_MRX_P2 PCIE_MTX_GRX_P2
C2 GFX_RX2P GFX_TX2P C3 C651 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P2 1
PCIE_GTX_C_MRX_N2 C1 B2 PCIE_MTX_GRX_N2 C650 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N2
PCIE_GTX_C_MRX_P3 GFX_RX2N GFX_TX2N PCIE_MTX_GRX_P3
E5 GFX_RX3P GFX_TX3P D1 C653 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P3
PCIE_GTX_C_MRX_N3 F5 D2 PCIE_MTX_GRX_N3 C652 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N3
PCIE_GTX_C_MRX_P4 GFX_RX3N GFX_TX3N PCIE_MTX_GRX_P4 C654 1
G5 GFX_RX4P GFX_TX4P E2 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P4
PCIE_GTX_C_MRX_N4 G6 E1 PCIE_MTX_GRX_N4 C655 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N4
PCIE_GTX_C_MRX_P5 GFX_RX4N GFX_TX4N PCIE_MTX_GRX_P5 C656 1
H5 GFX_RX5P GFX_TX5P F4 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P5
PCIE_GTX_C_MRX_N5 H6 F3 PCIE_MTX_GRX_N5 C657 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N5
PCIE_GTX_C_MRX_N6 GFX_RX5N GFX_TX5N PCIE_MTX_GRX_P6 C658 1
J6 GFX_RX6P GFX_TX6P F1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P6
PCIE_GTX_C_MRX_P6 J5 F2 PCIE_MTX_GRX_N6 C659 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N6
PCIE_GTX_C_MRX_P7 GFX_RX6N GFX_TX6N PCIE_MTX_GRX_P7
J7 GFX_RX7P GFX_TX7P H4 C642 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P7
PCIE_GTX_C_MRX_N7 J8 H3 PCIE_MTX_GRX_N7 C641 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N7
PCIE_GTX_C_MRX_P8 GFX_RX7N GFX_TX7N PCIE_MTX_GRX_P8 C638 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P8
L5 GFX_RX8P GFX_TX8P H1 2
PCIE_GTX_C_MRX_N8 L6 H2 PCIE_MTX_GRX_N8 C636 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N8
PCIE_GTX_C_MRX_P9 GFX_RX8N GFX_TX8N PCIE_MTX_GRX_P9 C637 1
M8 GFX_RX9P GFX_TX9P J2 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P9
PCIE_GTX_C_MRX_N9 L8 J1 PCIE_MTX_GRX_N9 C635 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N9
PCIE_GTX_C_MRX_P10 GFX_RX9N GFX_TX9N PCIE_MTX_GRX_P10 C634 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P10

PCIE I/F GFX


P7 GFX_RX10P GFX_TX10P K4
PCIE_GTX_C_MRX_N10 M7 K3 PCIE_MTX_GRX_N10 C632 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N10
PCIE_GTX_C_MRX_P11 GFX_RX10N GFX_TX10N PCIE_MTX_GRX_P11 C631 1
P5 GFX_RX11P GFX_TX11P K1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P11
PCIE_GTX_C_MRX_N11 M5 K2 PCIE_MTX_GRX_N11 C630 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N11
PCIE_GTX_C_MRX_P12 GFX_RX11N GFX_TX11N PCIE_MTX_GRX_P12 C629 1 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P12
R8 GFX_RX12P GFX_TX12P M4 2
PCIE_GTX_C_MRX_N12 P8 M3 PCIE_MTX_GRX_N12 C627 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N12
PCIE_GTX_C_MRX_P13 GFX_RX12N GFX_TX12N PCIE_MTX_GRX_P13
R6 GFX_RX13P GFX_TX13P M1 C625 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P13
PCIE_GTX_C_MRX_N13 R5 M2 PCIE_MTX_GRX_N13 C623 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N13
PCIE_GTX_C_MRX_P14 GFX_RX13N GFX_TX13N PCIE_MTX_GRX_P14 C620 1
P4 GFX_RX14P GFX_TX14P N2 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P14
PCIE_GTX_C_MRX_N14 P3 N1 PCIE_MTX_GRX_N14 C624 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N14
PCIE_GTX_C_MRX_P15 GFX_RX14N GFX_TX14N PCIE_MTX_GRX_P15 C621 1
T4 GFX_RX15P GFX_TX15P P1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_P15
PCIE_GTX_C_MRX_N15 T3 P2 PCIE_MTX_GRX_N15 C619 1 2 VGA@ 0.1U_0402_16V7K PCIE_MTX_C_GRX_N15
GFX_RX15N GFX_TX15N
AE3 GPP_RX0P GPP_TX0P AC1
AD4 GPP_RX0N GPP_TX0N AC2 New Card
AE2 GPP_RX1P GPP_TX1P AB4
2 2
AD3 GPP_RX1N GPP_TX1N AB3
AD1 AA2 PCIE_ITX_PRX_P2 C617 1 2 0.1U_0402_16V7K
36 PCIE_PTX_C_IRX_P2 GPP_RX2P GPP_TX2P PCIE_ITX_C_PRX_P2 36
AD2 PCIE I/F GPP AA1 PCIE_ITX_PRX_N2 C618 1 2 0.1U_0402_16V7K WLAN
36 PCIE_PTX_C_IRX_N2 GPP_RX2N GPP_TX2N PCIE_ITX_C_PRX_N2 36
V5 Y1 PCIE_ITX_PRX_P3 C614 1 2 0.1U_0402_16V7K
34 PCIE_PTX_C_IRX_P3 GPP_RX3P GPP_TX3P PCIE_ITX_C_PRX_P3 34
W6 Y2 PCIE_ITX_PRX_N3 C613 1 2 0.1U_0402_16V7K GLAN
34 PCIE_PTX_C_IRX_N3 GPP_RX3N GPP_TX3N PCIE_ITX_C_PRX_N3 34
U5 Y4 PCIE_ITX_PRX_P4 C46 1 2 0.1U_0402_16V7K
33 PCIE_PTX_C_IRX_P4 GPP_RX4P GPP_TX4P PCIE_ITX_C_PRX_P4 33 H_CADOP[0..15] H_CADIP[0..15]
U6 Y3 PCIE_ITX_PRX_N4 C42 1 2 0.1U_0402_16V7K Card Reader
33 PCIE_PTX_C_IRX_N4 GPP_RX4N GPP_TX4N PCIE_ITX_C_PRX_N4 33 4 H_CADOP[0..15] H_CADIP[0..15] 4
U8 GPP_RX5P GPP_TX5P V1 @
U7 V2 @ H_CADON[0..15] H_CADIN[0..15]
GPP_RX5N GPP_TX5N MP 4 H_CADON[0..15] H_CADIN[0..15] 4

27 SB_RX0P AA8 AD7 SB_TX0P_C C615 1 2 0.1U_0402_16V7K


SB_RX0P SB_TX0P SB_TX0P 27
27 SB_RX0N Y8 AE7 SB_TX0N_C C609 1 2 0.1U_0402_16V7K
SB_RX0N SB_TX0N SB_TX0N 27
27 SB_RX1P AA7 AE6 SB_TX1P_C C38 1 2 0.1U_0402_16V7K
SB_RX1P SB_TX1P SB_TX1P 27
27 SB_RX1N Y7 AD6 SB_TX1N_C C33 1 2 0.1U_0402_16V7K U3A
SB_RX1N SB_TX1N SB_TX1N 27
27 SB_RX2P AA5 PCIE I/F SB AB6 SB_TX2P_C C37 1 2 0.1U_0402_16V7K H_CADOP0 Y25 D24 H_CADIP0
SB_RX2P SB_TX2P SB_TX2P 27 HT_RXCAD0P HT_TXCAD0P
27 SB_RX2N AA6 AC6 SB_TX2N_C C32 1 2 0.1U_0402_16V7K H_CADON0 Y24 PART 1 OF 6 D25 H_CADIN0
SB_RX2N SB_TX2N SB_TX2N 27 HT_RXCAD0N HT_TXCAD0N
27 SB_RX3P W5 AD5 SB_TX3P_C C610 1 2 0.1U_0402_16V7K H_CADOP1 V22 E24 H_CADIP1
SB_RX3P SB_TX3P SB_TX3P 27 HT_RXCAD1P HT_TXCAD1P
27 SB_RX3N Y5 AE5 SB_TX3N_C C616 1 2 0.1U_0402_16V7K H_CADON1 V23 E25 H_CADIN1
SB_RX3N SB_TX3N SB_TX3N 27 HT_RXCAD1N HT_TXCAD1N
H_CADOP2 V25 F24 H_CADIP2
R32 1 1.27K_0402_1% H_CADON2 HT_RXCAD2P HT_TXCAD2P H_CADIN2
PCE_CALRP(PCE_BCALRP) AC8 2 V24 HT_RXCAD2N HT_TXCAD2N F25
AB8 R267 1 2 2K_0402_1% +1.1VS H_CADOP3 U24 F23 H_CADIP3
PCE_CALRN(PCE_BCALRN) H_CADON3 HT_RXCAD3P HT_TXCAD3P H_CADIN3
U25 HT_RXCAD3N HT_TXCAD3N F22
RS780M_FCBGA528 H_CADOP4
H_CADON4
T25 HT_RXCAD4P HT_TXCAD4P H23 H_CADIP4
H_CADIN4
T24 HT_RXCAD4N HT_TXCAD4N H22

HYPER TRANSPORT CPU I/F


RS780M Display Port Support (muxed on GFX) H_CADOP5 P22 J25 H_CADIP5
H_CADON5 HT_RXCAD5P HT_TXCAD5P H_CADIN5
P23 HT_RXCAD5N HT_TXCAD5N J24
H_CADOP6 P25 K24 H_CADIP6
GFX_TX0,TX1,TX2 and TX3 H_CADON6 HT_RXCAD6P HT_TXCAD6P H_CADIN6
P24 HT_RXCAD6N HT_TXCAD6N K25
DP0 H_CADOP7 N24 K23 H_CADIP7
AUX0 and HPD0 H_CADON7 HT_RXCAD7P HT_TXCAD7P H_CADIN7
N25 HT_RXCAD7N HT_TXCAD7N K22

H_CADOP8 AC24 F21 H_CADIP8


3 GFX_TX4,TX5,TX6 and TX7 H_CADON8 HT_RXCAD8P HT_TXCAD8P H_CADIN8 3
AC25 HT_RXCAD8N HT_TXCAD8N G21
DP1 H_CADOP9 AB25 G20 H_CADIP9
AUX1 and HPD1 H_CADON9 HT_RXCAD9P HT_TXCAD9P H_CADIN9
AB24 HT_RXCAD9N HT_TXCAD9N H21
H_CADOP10 AA24 J20 H_CADIP10
H_CADON10 HT_RXCAD10P HT_TXCAD10P H_CADIN10
AA25 HT_RXCAD10N HT_TXCAD10N J21
H_CADOP11 Y22 J18 H_CADIP11
H_CADON11 HT_RXCAD11P HT_TXCAD11P H_CADIN11
Y23 HT_RXCAD11N HT_TXCAD11N K17
H_CADOP12 W21 L19 H_CADIP12
H_CADON12 HT_RXCAD12P HT_TXCAD12P H_CADIN12
W20 HT_RXCAD12N HT_TXCAD12N J19
H_CADOP13 V21 M19 H_CADIP13
H_CADON13 HT_RXCAD13P HT_TXCAD13P H_CADIN13
V20 HT_RXCAD13N HT_TXCAD13N L18
H_CADOP14 U20 M21 H_CADIP14
H_CADON14 HT_RXCAD14P HT_TXCAD14P H_CADIN14
U21 HT_RXCAD14N HT_TXCAD14N P21
H_CADOP15 U19 P18 H_CADIP15
H_CADON15 HT_RXCAD15P HT_TXCAD15P H_CADIN15
U18 HT_RXCAD15N HT_TXCAD15N M18

4 H_CLKOP0 T22 HT_RXCLK0P HT_TXCLK0P H24 H_CLKIP0 4


4 H_CLKON0 T23 HT_RXCLK0N HT_TXCLK0N H25 H_CLKIN0 4
4 H_CLKOP1 AB23 HT_RXCLK1P HT_TXCLK1P L21 H_CLKIP1 4
4 H_CLKON1 AA22 HT_RXCLK1N HT_TXCLK1N L20 H_CLKIN1 4
H_CTLOP0 M22 M24 H_CTLIP0
4 H_CTLOP0 HT_RXCTL0P HT_TXCTL0P H_CTLIP0 4
H_CTLON0 M23 M25 H_CTLIN0
4 H_CTLON0 HT_RXCTL0N HT_TXCTL0N H_CTLIN0 4
H_CTLOP1 R21 P19 H_CTLIP1
4 H_CTLOP1 HT_RXCTL1P HT_TXCTL1P H_CTLIP1 4
H_CTLON1 R20 R18 H_CTLIN1
4 H_CTLON1 HT_RXCTL1N HT_TXCTL1N H_CTLIN1 4
1 R56 2 C23 B24 1 R51 2
HT_RXCALP HT_TXCALP
A24 HT_RXCALN HT_TXCALN B25
301_0402_1%~D 301_0402_1%~D
0718 Place within 1" RS780M_FCBGA528 0718 Place within 1"
layout 1:2 layout 1:2
4 4
SA00002DR30 S IC 216-0674026 A13 RS780MN FCBGA 0FA

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 10 of 57


A B C D E
A B C D E

For RS780M A13


RED: Connected to GND through two separate 140ohm 1% resistor

UMA@ 1 2 GMCH_CRT_R
R45 140_0402_1%
UMA@ 1 2 GMCH_CRT_G
R49 150_0402_1%
UMA@ 1 2 GMCH_CRT_B
R50 150_0402_1%

1 1

+3VS AVDD=0.11A
PLLVDD=65mA L15
PVT
+1.1VS +NB_PLLVDD 1 2 +AVDD1
L59 FBM-L11-201209-300LMA30T_0805 1 1
1 2 AVDDDI=20mA C94
MBK2012221YZF 0805 1 +1.8VS C874 2.2U_0603_6.3V4Z
1
L10 1U_0402_6.3V4Z
C645 C663 +AVDD2 2 2
1 2
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z FBM-L11-201209-300LMA30T_0805 1
2 2 U3C
C74 F12 A22 GMCH_TXOUT0+ 24
+1.8VS 0.1U_0402_16V4Z AVDD1(NC) TXOUT_L0P(NC)
PLLVDD18=20mA E12 AVDD2(NC) PART 3 OF 6 TXOUT_L0N(NC) B22 GMCH_TXOUT0- 24
2
AVDDQ=4mA F14 AVDDDI(NC) TXOUT_L1P(NC) A21 GMCH_TXOUT1+ 24
+1.8VS +NB_HTPVDD L8 G15 B21
AVSSDI(NC) TXOUT_L1N(NC) GMCH_TXOUT1- 24
L13 1 2 +AVDDQ H15 B20 GMCH_TXOUT2+ 24
FBM-L11-201209-300LMA30T_0805 AVDDQ(NC) TXOUT_L2P(NC)
1 2 1 1 PVT H14 AVSSQ(NC) TXOUT_L2N(DBG_GPIO0) A20 GMCH_TXOUT2- 24
MBK2012221YZF 0805 1 1 A19
C61 C875 TXOUT_L3P(NC)
E17 C_Pr(DFT_GPIO5) TXOUT_L3N(DBG_GPIO2) B19
C93 C84 2.2U_0603_6.3V4Z 1U_0402_6.3V4Z F17

CRT/TVOUT
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z 2 2 Y(DFT_GPIO2)
F15 COMP_Pb(DFT_GPIO4) TXOUT_U0P(NC) B18
2 2
TXOUT_U0N(NC) A18
GMCH_CRT_R G18 A17
26 GMCH_CRT_R RED(DFT_GPIO0) TXOUT_U1P(PCIE_RESET_GPIO3)
G17 REDb(NC) TXOUT_U1N(PCIE_RESET_GPIO2) B17
VDDA18HTPLL=20mA GMCH_CRT_G E18 D20
26 GMCH_CRT_G GREEN(DFT_GPIO1) TXOUT_U2P(NC)
F18 GREENb(NC) TXOUT_U2N(NC) D21
+1.8VS +VDDA18HTPLL GMCH_CRT_B E19 D18
26 GMCH_CRT_B BLUE(DFT_GPIO3) TXOUT_U3P(PCIE_RESET_GPIO5)
L9 F19 D19
BLUEb(NC) TXOUT_U3N(NC)
1 2 VDDLTP18=15mA
MBK2012221YZF 0805 1 1 GMCH_CRT_HSYNC A11 B16 GMCH_TXCLK+ 24 L56
2 13,26 GMCH_CRT_HSYNC DAC_HSYNC(PWM_GPIO4) TXCLK_LP(DBG_GPIO1)
GMCH_CRT_VSYNC B11 A16 GMCH_TXCLK- 24 +VDDLTP18 1 2 +1.8VS
2
13,26 GMCH_CRT_VSYNC DAC_VSYNC(PWM_GPIO6) TXCLK_LN(DBG_GPIO3)
C66 C72 GMCH_CRT_CLK F8 D16 1 1 MBC1608121YZF_0603
26 GMCH_CRT_CLK DAC_SCL(PCE_RCALRN) TXCLK_UP(PCIE_RESET_GPIO4)
2.2U_0603_6.3V4Z 1U_0402_6.3V4Z GMCH_CRT_DATA E8 D17
2 2 26 GMCH_CRT_DATA DAC_SDA(PCE_TCALRN) TXCLK_UN(PCIE_RESET_GPIO1) C665 C644
R42 1 2 715_0402_1% G14 1U_0402_6.3V4Z 2.2U_0603_6.3V4Z
+1.8VS DAC_RSET(PWM_GPIO1) +VDDLTP18 2 2
VDDA18PCIEPLL=0.12A PVT VDDLTP18(NC) A13
U50 +NB_PLLVDD +NB_PLLVDD A12 B13
+1.8VS +VDDA18PCIEPLL PLLVDD(NC) VSSLTP18(NC)
5

NC7SZ08P5X_NL_SC70-5 +NB_HTPVDD +NB_HTPVDD D14


L14 PLLVDD18(NC) +VDDLT18
2 B12 A15

LVTM
28 NB_PWRGD
P

B PLLVSS(NC) VDDLT18_1(NC)
1 2 Y 4 VDDLT18_2(NC) B15 VDDLT18=0.3A

PLL PWR
MBK2012221YZF 0805 1 1 1 +VDDA18HTPLL H17 A14 L12
6,28,41 SB_PWRGD A VDDA18HTPLL VDDLT33_1(NC)
G

B14 +VDDLT18 1 2 +1.8VS


C87 C86 VDDLT33_2(NC) MBC1608121YZF_0603
+VDDA18PCIEPLL D7 VDDA18PCIEPLL1 1 1
3

2.2U_0603_6.3V4Z 1U_0402_6.3V4Z E7 C14


2 2 R296 0_0402_5% VDDA18PCIEPLL2 VSSLT1(VSS) C90 C95
VSSLT2(VSS) D15
1 2 NB_RESET# D8 C16 0.1U_0402_16V4Z 4.7U_0805_10V4Z
13,14,24,27,33,34,36,38 PLT_RST# SYSRESETb VSSLT3(VSS) 2 2
1 2 NB_PWRGD_R A10 C18
28 NB_PWRGD POWERGOOD VSSLT4(VSS)
R511 @ 0_0402_5% NB_LDTSTOP# C10 C20
NB_ALLOW_LDTSTOP LDTSTOPb VSSLT5(VSS)
+1.8VS 2 1 PVT C12 E20

PM
R283 300_0402_5% ALLOW_LDTSTOP VSSLT6(VSS)
VSSLT7(VSS) C22
23 CLK_NBHT C25 HT_REFCLKP
23 CLK_NBHT# C24 HT_REFCLKN
CLK_NB_14.318M
CLK_NB_14.318M E11
23 CLK_NB_14.318M REFCLK_P/OSCIN(OSCIN)

CLOCKs
F11 REFCLK_N(PWM_GPIO3) LVDS_DIGON(PCE_TCALRP) E9 UMA_ENVDD
LVDS_BLON(PCE_RCALRP) F7 UMA_ENBKL 38
1

+1.1VS 1 2 1 2 23 CLK_NBGFX T2 GFX_REFCLKP LVDS_ENA_BL(PWM_GPIO2) G12 UMA_DPST 24


R477 R293 R290

1.27K_0402_1%

1.27K_0402_1%
23 CLK_NBGFX# T1 GFX_REFCLKN

2
100_0402_5% 4.7K_0402_5% 4.7K_0402_5%
@ U1 R469
GPP_REFCLKP 1.27K_0402_1% UMA@ UMA@

1 R294

1 R29
U2 GPP_REFCLKN
2

@
3 +3VS V4 3
1 23 CLK_SBLINK_BCLK GPPSB_REFCLKP(SB_REFCLKP)

2
23 CLK_SBLINK_BCLK# V3 GPPSB_REFCLKN(SB_REFCLKN)
1

C854 DVT
100P_0402_25V8K R483 GMCH_LCD_CLK B9
2 24 GMCH_LCD_CLK I2C_CLK
1.5K_0402_5% GMCH_LCD_DATA A9 D9
@
@
24 GMCH_LCD_DATA
GMCH_HDMI_DATA_R2 B8
I2C_DATA MIS. TMDS_HPD(NC)
D10
HDMI_DET 15,25
@ GMCH_HDMI_CLK_R2 DDC_DATA0/AUX0N(NC) HPD(NC)
A8 DDC_CLK0/AUX0P(NC)
2

1 2 GMCH_HDMI_CLK_R1 B7 D12 1 2 SUS_STAT# 28


24,26,38 PX_GPIO2 DDC_CLK1/AUX1P(NC) SUS_STAT#(PWM_GPIO5)
R486 0_0402_5% DVT GMCH_HDMI_DATA_R1 A7 DDC_DATA1/AUX1N(NC)
R297 0_0402_5% SUS_STAT_R# 13 Strap pin
38 PX_GPIO2_NB 1 2 THERMALDIODE_P AE8
DVT R490 0_0402_5% +3VS 2 @ 1 B10 AD8
@ R288 10K_0402_5% STRP_DATA THERMALDIODE_N
POWER_SEL G11 D13 1 2 UMA@
50 POWER_SEL RSVD TESTMODE R279 R744 0_0402_5% DVT2
C8 1.8K_0402_5% 1 2
13 AUX_CAL AUX_CAL(NC)
+3VS
+3VS
Strap pin RS780M_FCBGA528
C857 0.1U_0402_16V4Z
UMA@ POWER_SEL @
R295 1 2 4.7K_0402_5% GMCH_LCD_CLK DVT R491 @ 0_0402_5%

5
R289 1 2 4.7K_0402_5% GMCH_LCD_DATA 1 2GMCH_HDMI_CLK_R2 PVT
HIGH 1.0V UMA_ENVDD 2

P
B
UMA@ Y 4 UMA_ENVDD_R 24
R488 UMA@ 0_0402_5% 1 A

G
LOW 1.1V 25 GMCH_HDMI_CLK GMCH_HDMI_CLK 1 2 GMCH_HDMI_CLK_R1 U48
GMCH_HDMI_DATA 1 2 GMCH_HDMI_DATA_R1 NC7SZ08P5X_NL_SC70-5
25 GMCH_HDMI_DATA

3
R489 UMA@ 0_0402_5% @
NB_PWRGD
+1.8VS 1 2GMCH_HDMI_DATA_R2
R492 @ 0_0402_5%

5
PVT
2

P
4 B 4
Y 4 ENBKL 38
2

Un-stuff for Tigris Change as 1K_5% ohm 0_0402_5% UMA_ENBKL 1 A

G
1 2 NB_LDTSTOP# U49
for Tigris 6,27 LDT_STOP#
R61 0_0402_5% R60 R280 @ NC7SZ08P5X_NL_SC70-5

3
1 2 300_0402_5%
6 CPU_LDT_REQ#
PUMA@
1

PUMA@

27 ALLOW_LDTSTOP
R59
1
0_0402_5%
2 NB_ALLOW_LDTSTOP Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
401679 C

hexainf@hotmail.com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 26, 2009 Sheet 11 of 57
A B C D E
GRATIS - FOR FREE
A B C D E

U3F
A25 VSSAHT1 VSSAPCIE1 A2
D23 VSSAHT2 PART 6/6 VSSAPCIE2 B1
E22 VSSAHT3 VSSAPCIE3 D3
G22 VSSAHT4 VSSAPCIE4 D5
VDDHTRX+VDDHT=0.68A G24 VSSAHT5 VSSAPCIE5 E4
G25 VSSAHT6 VSSAPCIE6 G1
1 L49 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1
H19 VSSAHT7 VSSAPCIE7 G2
+1.1VS 2 1 +VDDHT J22 G4
VSSAHT8 VSSAPCIE8
L17 VSSAHT9 VSSAPCIE9 H7
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 L22 J4
L3 VSSAHT10 VSSAPCIE10
L24 VSSAHT11 VSSAPCIE11 R7
C612 C75 C71 C62 1 2 +1.1VS L25 L1
FBMA-L11-201209-221LMA30T_0805 VSSAHT12 VSSAPCIE12
U3E VDDPCIE=1.1A M20 VSSAHT13 VSSAPCIE13 L2
2 2 2 2
N22 VSSAHT14 VSSAPCIE14 L4
4.7U_0805_10V4Z 0.1U_0402_16V4Z J17 A6 +VDDA11PCIE C30 1 2 10U_0805_10V4Z P20 L7
VDDHT_1 VDDPCIE_1 C28 VSSAHT15 VSSAPCIE15
K16 VDDHT_2 PART 5/6 VDDPCIE_2 B6 1 2 10U_0805_10V4Z R19 VSSAHT16 VSSAPCIE16 M6
L16 VDDHT_3 VDDPCIE_3 C6 R22 VSSAHT17 VSSAPCIE17 N4
L11 1U_0402_6.3V4Z M16 D6 R24 P6
0.1U_0402_16V4Z +VDDHTRX VDDHT_4 VDDPCIE_4 C29 VSSAHT18 VSSAPCIE18
2 1 P16 VDDHT_5 VDDPCIE_5 E6 1 2 4.7U_0805_10V4Z R25 VSSAHT19 VSSAPCIE19 R1
R16 VDDHT_6 VDDPCIE_6 F6 H20 VSSAHT20 VSSAPCIE20 R2
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 T16 G7 C53 1 2 1U_0402_6.3V4Z U22 R4
VDDHT_7 VDDPCIE_7 C79 VSSAHT21 VSSAPCIE21
VDDPCIE_8 H8 1 2 1U_0402_6.3V4Z V19 VSSAHT22 VSSAPCIE22 V7
C83 C82 C85 C91 H18 J9 W22 U4

GROUND
VDDHTRX_1 VDDPCIE_9 VSSAHT23 VSSAPCIE23
G19 VDDHTRX_2 VDDPCIE_10 K9 1 2 W24 VSSAHT24 VSSAPCIE24 V8
2 2 2 2 C88
F20 VDDHTRX_3 VDDPCIE_11 M9 1 2 0.1U_0402_16V4Z W25 VSSAHT25 VSSAPCIE25 V6
4.7U_0805_10V4Z 0.1U_0402_16V4Z E21 L9 C57 0.1U_0402_16V4Z Y21 W1
VDDHTRX_4 VDDPCIE_12 VSSAHT26 VSSAPCIE26
D22 VDDHTRX_5 VDDPCIE_13 P9 AD25 VSSAHT27 VSSAPCIE27 W2
B23 VDDHTRX_6 VDDPCIE_14 R9 VSSAPCIE28 W4
VDDHTTX=0.68A A23 VDDHTRX_7 VDDPCIE_15 T9 L12 VSS11 VSSAPCIE29 W7
L4 V9 M14 W8
0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDHTTX VDDPCIE_16 VSS12 VSSAPCIE30
+1.2V_HT 2 1 AE25 VDDHTTX_1 VDDPCIE_17 U9 VDDC=7.6A N13 VSS13 VSSAPCIE31 Y6
AD24 VGA@ P12 AA4
FBMA-L11-201209-221LMA30T_0805 VDDHTTX_2 VSS14 VSSAPCIE32
1 1 1 1 1 AC23 VDDHTTX_3 VDDC_1 K12 +1.1VS 1 2 +NB_CORE P15 VSS15 VSSAPCIE33 AB5
AB22 J14 L6 0_1206_5% R11 AB1
C31 C49 C50 C54 C52 VDDHTTX_4 VDDC_2 VSS16 VSSAPCIE34
AA21 VDDHTTX_5 VDDC_3 U16 1 2 R14 VSS17 VSSAPCIE35 AB7
Y20 J11 DVT L7 0_1206_5% T12 AC3
2 2 2 2 2 VDDHTTX_6 VDDC_4 VGA@ VSS18 VSSAPCIE36
W19 VDDHTTX_7 VDDC_5 K15 U14 VSS19 VSSAPCIE37 AC4

POWER
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z V18 M12 U11 AE1
2 VDDHTTX_8 VDDC_6 VSS20 VSSAPCIE38 2
U17 VDDHTTX_9 VDDC_7 L14 U15 VSS21 VSSAPCIE39 AE4
FOR Version A11 pop 1.35VS A12 T17 VDDHTTX_10 VDDC_8 L11 V12 VSS22 VSSAPCIE40 AB2
use 1.2V_HT R17 VDDHTTX_11 VDDC_9 M13 W11 VSS23
P17 VDDHTTX_12 VDDC_10 M15 W15 VSS24
VDDA18PCIE=0.7A M17 VDDHTTX_13 VDDC_11 N12 AC12 VSS25 VSS1 AE14
L5

C27
C35

C60

C34

C69

C43

C76

C64

C81

C68

C36

C44
VDDC_12 N14 1 AA14 VSS26 VSS2 D11
+1.8VS 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z +VDDA18PCIE J10 P11 1 1 1 1 1 1 1 1 1 1 1 Y18 G8
FBMA-L11-201209-221LMA30T_0805 VDDA18PCIE_1 VDDC_13 + VSS27 VSS3
P10 VDDA18PCIE_2 VDDC_14 P13 AB11 VSS28 VSS4 E14
1 1 1 1 1 1 K10 VDDA18PCIE_3 VDDC_15 P14 AB15 VSS29 VSS5 E15

330U_D2E_2.5VM
10U_0805_10V4Z

10U_0805_10V4Z
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
M10 VDDA18PCIE_4 VDDC_16 R12 AB17 VSS30 VSS6 J15
C45 C47 C40 C51 C48 C73 2 2 2 2 2 2 2 2 2 2 2 2
L10 VDDA18PCIE_5 VDDC_17 R15 AB19 VSS31 VSS7 J12
4.7U_0805_10V4Z W9 T11 AE20 K14
2 2 2 2 2 2 VDDA18PCIE_6 VDDC_18 VSS32 VSS8
H9 VDDA18PCIE_7 VDDC_19 T15 AB21 VSS33 VSS9 M11
4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z T10 U12 K11 L15
VDDA18PCIE_8 VDDC_20 VSS34 VSS10
R10 VDDA18PCIE_9 VDDC_21 T14
Y9 J16 RS780M_FCBGA528
VDDA18PCIE_10 VDDC_22
AA9 VDDA18PCIE_11
AB9 VDDA18PCIE_12 VDD_MEM1(NC) AE10
AD9 VDDA18PCIE_13 VDD_MEM2(NC) AA11
AE9 VDDA18PCIE_14 VDD_MEM3(NC) Y11
U10 VDDA18PCIE_15 VDD_MEM4(NC) AD10
VDD18=10mA VDD_MEM5(NC) AB10
+1.8VS F9 VDD18_1 VDD_MEM6(NC) AC10
G9 VDD18_2 VDD33=60mA
AE11 VDD18_MEM1(NC) VDD33_1(NC) H11 +3VS
AD11 VDD18_MEM2(NC) VDD33_2(NC) H12
1 1
1 RS780M_FCBGA528
C89 C80 C78
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z U3D
2 2
2
PAR 4 OF 6
AB12 MEM_A0(NC) MEM_DQ0/DVO_VSYNC(NC) AA18
3 3
AE16 MEM_A1(NC) MEM_DQ1/DVO_HSYNC(NC) AA20
V11 MEM_A2(NC) MEM_DQ2/DVO_DE(NC) AA19
AE15 MEM_A3(NC) MEM_DQ3/DVO_D0(NC) Y19
AA12 MEM_A4(NC) MEM_DQ4(NC) V17
AB16 MEM_A5(NC) MEM_DQ5/DVO_D1(NC) AA17
AB14 MEM_A6(NC) MEM_DQ6/DVO_D2(NC) AA15
AD14 MEM_A7(NC) MEM_DQ7/DVO_D4(NC) Y15
AD13 MEM_A8(NC) MEM_DQ8/DVO_D3(NC) AC20
AD15 MEM_A9(NC) MEM_DQ9/DVO_D5(NC) AD19

SBD_MEM/DVO_I/F
AC16 MEM_A10(NC) MEM_DQ10/DVO_D6(NC) AE22
AE13 MEM_A11(NC) MEM_DQ11/DVO_D7(NC) AC18
AC14 MEM_A12(NC) MEM_DQ12(NC) AB20
Y14 MEM_A13(NC) MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22
AD16 MEM_BA0(NC) MEM_DQ15/DVO_D11(NC) AD21
AE17 MEM_BA1(NC)
AD17 MEM_BA2(NC) MEM_DQS0P/DVO_IDCKP(NC) Y17
MEM_DQS0N/DVO_IDCKN(NC) W18
W12 MEM_RASb(NC) MEM_DQS1P(NC) AD20
Y12 MEM_CASb(NC) MEM_DQS1N(NC) AE21
AD18 MEM_WEb(NC)
AB13 MEM_CSb(NC) MEM_DM0(NC) W17
AB18 MEM_CKE(NC) MEM_DM1/DVO_D8(NC) AE19 15mA
V14 MEM_ODT(NC)
IOPLLVDD18(NC) AE23 +1.8VS
V15 MEM_CKP(NC) IOPLLVDD(NC) AE24 +1.1VS
W14 MEM_CKN(NC)
IOPLLVSS(NC) AD23 26mA
AE12 MEM_COMPP(NC)
AD12 MEM_COMPN(NC) MEM_VREF(NC) AE18

RS780M_FCBGA528
4 +1.8VS=W/S=20/10mil For Memory PLL power 4
+1.1VS=W/S=20/10mil For Memory PLL power

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 12 of 57


A B C D E
A B C D E

DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb

11,26 GMCH_CRT_VSYNC 2 1 +3VS Enables the Test Debug Bus using GPIO. (VSYNC)
R286 3K_0402_5%
1 : Disable (RS780)
2 1
1 R287 @ 3K_0402_5% 0 : Enable (Rs780) 1

DFT_GPIO1: LOAD_EEPROM_STRAPS

11 AUX_CAL 1 2 Selects Loading of STRAPS from EPROM


@R284
@ R284 150_0402_1%
D29
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
@ CH751H-40_SC76 0 : I2C Master can load strap values from EEPROM if connected, or use
RS780 DFT_GPIO1 11 SUS_STAT_R# 2 1 PLT_RST# 11,14,24,27,33,34,36,38
default values if not connected
RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

2 2

RS780 use HSYNC to enable SIDE PORT

RS780 use HSYNC to enable SIDE PORT RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)
0. Enable (RS780)
2 1 1 : Disable(RS780)
11,26 GMCH_CRT_HSYNC +3VS
R281 3K_0402_5%
2 @ 1
R282 3K_0402_5%

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
401679 C

hexainf@hotmail.com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 26, 2009 Sheet 13 of 57
A B C D E
GRATIS - FOR FREE
5 4 3 2 1

PCIE_GTX_C_MRX_P[0..15]
10 PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]
10 PCIE_GTX_C_MRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
10 PCIE_MTX_C_GRX_P[0..15]
PCIE_MTX_C_GRX_N[0..15]
10 PCIE_MTX_C_GRX_N[0..15]

D D

PCIE LANE REVERSAL U4A


PCIE LANE REVERSAL

PCIE_MTX_C_GRX_P15 AA38 Y33 PCIE_GTX_MRX_P15 C172 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P15


PCIE_MTX_C_GRX_N15 PCIE_RX0P PCIE_TX0P PCIE_GTX_MRX_N15 C181 0.1U_0402_16V7K PCIE_GTX_C_MRX_N15
Y37 PCIE_RX0N PCIE_TX0N Y32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P14 Y35 W33 PCIE_GTX_MRX_P14 C160 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P14
PCIE_MTX_C_GRX_N14 PCIE_RX1P PCIE_TX1P PCIE_GTX_MRX_N14 C162 0.1U_0402_16V7K PCIE_GTX_C_MRX_N14
W36 PCIE_RX1N PCIE_TX1N W32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P13 W38 U33 PCIE_GTX_MRX_P13 C139 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P13
PCIE_MTX_C_GRX_N13 PCIE_RX2P PCIE_TX2P PCIE_GTX_MRX_N13 C143 0.1U_0402_16V7K PCIE_GTX_C_MRX_N13
V37 PCIE_RX2N PCIE_TX2N U32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P12 V35 U30 PCIE_GTX_MRX_P12 C141 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P12
PCIE_MTX_C_GRX_N12 PCIE_RX3P PCIE_TX3P PCIE_GTX_MRX_N12 C148 0.1U_0402_16V7K PCIE_GTX_C_MRX_N12
U36 PCIE_RX3N PCIE_TX3N U29 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P11 U38 T33 PCIE_GTX_MRX_P11 C134 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P11
PCIE_MTX_C_GRX_N11 PCIE_RX4P PCIE_TX4P PCIE_GTX_MRX_N11 C138 0.1U_0402_16V7K PCIE_GTX_C_MRX_N11
T37 PCIE_RX4N PCIE_TX4N T32 1 2

PCI EXPRESS INTERFACE


VGA@
VGA@
C PCIE_MTX_C_GRX_P10 T35 T30 PCIE_GTX_MRX_P10 C128 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P10 C
PCIE_MTX_C_GRX_N10 PCIE_RX5P PCIE_TX5P PCIE_GTX_MRX_N10 C137 0.1U_0402_16V7K PCIE_GTX_C_MRX_N10
R36 PCIE_RX5N PCIE_TX5N T29 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P9 R38 P33 PCIE_GTX_MRX_P9 C126 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P9
PCIE_MTX_C_GRX_N9 PCIE_RX6P PCIE_TX6P PCIE_GTX_MRX_N9 C133 0.1U_0402_16V7K PCIE_GTX_C_MRX_N9
P37 PCIE_RX6N PCIE_TX6N P32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P8 P35 P30 PCIE_GTX_MRX_P8 C156 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P8
PCIE_MTX_C_GRX_N8 PCIE_RX7P PCIE_TX7P PCIE_GTX_MRX_N8 C158 0.1U_0402_16V7K PCIE_GTX_C_MRX_N8
N36 PCIE_RX7N PCIE_TX7N P29 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P7 N38 N33 PCIE_GTX_MRX_P7 C136 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P7
PCIE_MTX_C_GRX_N7 PCIE_RX8P PCIE_TX8P PCIE_GTX_MRX_N7 C127 0.1U_0402_16V7K PCIE_GTX_C_MRX_N7
M37 PCIE_RX8N PCIE_TX8N N32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P6 M35 N30 PCIE_GTX_MRX_P6 C144 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P6
PCIE_MTX_C_GRX_N6 PCIE_RX9P PCIE_TX9P PCIE_GTX_MRX_N6 C140 0.1U_0402_16V7K PCIE_GTX_C_MRX_N6
L36 PCIE_RX9N PCIE_TX9N N29 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P5 L38 L33 PCIE_GTX_MRX_P5 C116 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P5
PCIE_MTX_C_GRX_N5 PCIE_RX10P PCIE_TX10P PCIE_GTX_MRX_N5 C114 0.1U_0402_16V7K PCIE_GTX_C_MRX_N5
K37 PCIE_RX10N PCIE_TX10N L32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P4 K35 L30 PCIE_GTX_MRX_P4 C154 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P4
PCIE_MTX_C_GRX_N4 PCIE_RX11P PCIE_TX11P PCIE_GTX_MRX_N4 C155 0.1U_0402_16V7K PCIE_GTX_C_MRX_N4
J36 PCIE_RX11N PCIE_TX11N L29 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P3 J38 K33 PCIE_GTX_MRX_P3 C129 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P3
B PCIE_MTX_C_GRX_N3 PCIE_RX12P PCIE_TX12P PCIE_GTX_MRX_N3 C130 0.1U_0402_16V7K PCIE_GTX_C_MRX_N3 B
H37 PCIE_RX12N PCIE_TX12N K32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P2 H35 J33 PCIE_GTX_MRX_P2 C120 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P2
PCIE_MTX_C_GRX_N2 PCIE_RX13P PCIE_TX13P PCIE_GTX_MRX_N2 C115 0.1U_0402_16V7K PCIE_GTX_C_MRX_N2
G36 PCIE_RX13N PCIE_TX13N J32 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P1 G38 K30 PCIE_GTX_MRX_P1 C152 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P1
PCIE_MTX_C_GRX_N1 PCIE_RX14P PCIE_TX14P PCIE_GTX_MRX_N1 C153 0.1U_0402_16V7K PCIE_GTX_C_MRX_N1
F37 PCIE_RX14N PCIE_TX14N K29 1 2
VGA@
VGA@
PCIE_MTX_C_GRX_P0 F35 H33 PCIE_GTX_MRX_P0 C131 1 2 0.1U_0402_16V7K PCIE_GTX_C_MRX_P0
PCIE_MTX_C_GRX_N0 PCIE_RX15P PCIE_TX15P PCIE_GTX_MRX_N0 C132 0.1U_0402_16V7K PCIE_GTX_C_MRX_N0
E37 PCIE_RX15N PCIE_TX15N H32 1 2
VGA@
VGA@
CLOCK
CLK_PCIE_VGA AB35
23 CLK_PCIE_VGA PCIE_REFCLKP
CLK_PCIE_VGA# AA36
23 CLK_PCIE_VGA# PCIE_REFCLKN

CALIBRATION VGA@
AJ21 Y30 R83 1 2 1.27K_0402_1%
NC#1 PCIE_CALRP
AK21 NC#2
+3VS_DELAY AH16 Y29 R90 1 2 2K_0402_1% +1.1VS_PX
NC_PWRGOOD PCIE_CALRN
VGA@
GPU_RST# AA30 PERSTB
1

A A
R474
10K_0402_5% M92@
VGA@ 216-0729002 A12 M96_BGA962
D4
2

11,13,24,27,33,34,36,38 PLT_RST# 2
GPU_RST#
27 PX_GPIO0 3
1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

2 1
CHP202UPT_SOT323-3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
VGA@ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
R481 @ 2.2K_0402_5% DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 14 of 57


5 4 3 2 1
5 4 3 2 1

U4B

TXCAP_DPA3P AU24 HDMI_CLK+_VGA 25


TXCAM_DPA3N AV23 HDMI_CLK-_VGA 25
U4G
TX0P_DPA2P AT25 HDMI_TX0+_VGA 25
MUTI GFX AR24
DPA TX0M_DPA2N HDMI_TX0-_VGA 25
AU26 LVDS CONTROL AK27 T11 PAD
TX1P_DPA1P HDMI_TX1+_VGA 25 VARY_BL
TX1M_DPA1N AV25 HDMI_TX1-_VGA 25 DIGON AJ27 VGA_ENVDD 24
T64 PAD AR8 AT27
DVPCNTL_MVP_0 TX2P_DPA0P HDMI_TX2+_VGA 25
T45 PAD AU8 AR26
DVPCNTL_MVP_1 TX2M_DPA0N HDMI_TX2-_VGA 25
T27 PAD AP8
T51 PAD DVPCNTL_0
D
AW8 DVPCNTL_1 TXCBP_DPB3P AR30 TXCLK_UP_DPF3P AK35 D
T55 PAD AR3 AT29 AL36
T65 PAD DVPCNTL_2 TXCBM_DPB3N TXCLK_UN_DPF3N
AR1 DVPCLK
T66 PAD AU1 AV31 AJ38
T30 PAD DVPDATA_0 TX3P_DPB2P TXOUT_U0P_DPF2P
AU3 DVPDATA_1 TX3M_DPB2N AU30 TXOUT_U0N_DPF2N AK37
T60 PAD AW3 DPB
T29 PAD DVPDATA_2
AP6 DVPDATA_3 TX4P_DPB1P AR32 TXOUT_U1P_DPF1P AH35
T61 PAD AW5 AT31 AJ36
T56 PAD DVPDATA_4 TX4M_DPB1N TXOUT_U1N_DPF1N
AU5 DVPDATA_5
T63 PAD AR6 AT33 AG38
+3VS_DELAY T57 PAD DVPDATA_6 TX5P_DPB0P TXOUT_U2P_DPF0P
AW6 DVPDATA_7 TX5M_DPB0N AU32 TXOUT_U2N_DPF0N AH37
T62 PAD AU6
T58 PAD DVPDATA_8
AT7 DVPDATA_9 TXCCP_DPC3P AU14 TXOUT_U3P AF35
T50 PAD AV7 AV13 AG36
T28 PAD DVPDATA_10 TXCCM_DPC3N TXOUT_U3N
AN7 DVPDATA_11
1 2 VGA_LCD_CLK T46 PAD AV9 AT15
R92 4.7K_0402_5% T59 PAD DVPDATA_12 TX0P_DPC2P LVTMDP
AT9 DVPDATA_13 TX0M_DPC2N AR14
VGA@ T52 PAD AR10
VGA_LCD_DATA T53 PAD DVPDATA_14 DPC
1 2 AW10 DVPDATA_15 TX1P_DPC1P AU16 TXCLK_LP_DPE3P AP34 VGA_TXCLK+ 24
R88 4.7K_0402_5% T47 PAD AU10 AV15 AR34 VGA_TXCLK- 24
T48 PAD DVPDATA_16 TX1M_DPC1N TXCLK_LN_DPE3N
VGA@ AP10 DVPDATA_17
T49 PAD AV11 AT17 AW37 VGA_TXOUT0+ 24
R97 VGA_PWRSEL T54 PAD DVPDATA_18 TX2P_DPC0P TXOUT_L0P_DPE2P
2 1 AT11 DVPDATA_19 TX2M_DPC0N AR16 TXOUT_L0N_DPE2N AU35 VGA_TXOUT0- 24
@ 10K_0402_5% AR12
22 VRAM_ID0 DVPDATA_20
22 VRAM_ID1 AW12 DVPDATA_21 TXCDP_DPD3P AU20 TXOUT_L1P_DPE1P AR37 VGA_TXOUT1+ 24
AU12 AT19 VGA_CRT_R 1 VGA@ 2 AU39 VGA_TXOUT1- 24
22 VRAM_ID2 DVPDATA_22 TXCDM_DPD3N TXOUT_L1N_DPE1N
AP12 R303 150_0402_1%
22 VRAM_ID3 DVPDATA_23
AT21 VGA_CRT_G 1 VGA@ 2 AP35 VGA_TXOUT2+ 24
TX3P_DPD2P R302 150_0402_1% TXOUT_L2P_DPE0P
TX3M_DPD2N AR20 TXOUT_L2N_DPE0N AR35 VGA_TXOUT2- 24
VGA_CRT_B 1 VGA@ 2
DPD AU22 R301 150_0402_1% AN36
TX4P_DPD1P TXOUT_L3P
TX4M_DPD1N AV21 TXOUT_L3N AP37
I2C AT23
TX5P_DPD0P
TX5M_DPD0N AR22
24 VGA_LCD_CLK AK26 SCL
24 VGA_LCD_DATA AJ26 SDA 216-0729002 A12 M96_BGA962
C GPIO_5_AC_BATT R AD39 VGA_CRT_R 26 C
GENERAL PURPOSE I/O AD37
AC (Performance mode) = 3.3 V RB M92@
GPU_GPIO0 AH20
Battery saving mode = 0.0 V 22
GPU_GPIO0 GPIO_0
GPU_GPIO1 AH18 AE36 VGA_CRT_G 26
22
GPU_GPIO1 GPIO_1 G
GPU_GPIO2 AN16 AD35
22
GPU_GPIO2 GPIO_2 GB
+3VS_DELAY 1 2 AH23 GPIO_3_SMBDATA
R99 VGA@ 100K_0402_5% AJ23 AF37
GPIO_4_SMBCLK B VGA_CRT_B 26
1 2 GPIO_5_AC_BATT# AH17 AE38
29,38,40,46,49 ACIN GPIO_5_AC_BATT BB
D13 VGA@ RB751V_SOD323 R101 1 2 10K_0402_5% AJ17 DAC1
VGA@ GPIO_6
38 VGA_ENBKL AK17 GPIO_7_BLON HSYNC AC36 VGA_CRT_HSYNC 22,26
GPU_GPIO8 AJ13 AC38
22 GPU_GPIO8 GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC 22,26
GPU_GPIO9 AH15
+3VS_DELAY
VGA_PWRSEL 22 GPU_GPIO9
AJ16
GPIO_9_ROMSI VGA@
GPU_GPIO11 GPIO_10_ROMSCK
High:VGA_CORE 0.95V 22 GPU_GPIO11 AK16 GPIO_11 RSET AB34 1 R80 2
GPU_GPIO12 AL16 499_0402_1% +1.8VS_PX AVDD=70mA +AVDD
22 GPU_GPIO12 GPIO_12
Low :VGA_CORE 1.2V 22 GPU_GPIO13
GPU_GPIO13 AM16 GPIO_13 AVDD AD34 +AVDD L61
1

AM14 AE34 2 1 1U_0402_6.3V4Z


R104 VGA_PWRSEL GPIO_14_HPD2 AVSSQ BLM18PG121SN1D_0603
54 VGA_PWRSEL AM13 GPIO_15_PWRCNTL_0 1 1 1
10K_0402_5% 27M_SSC 1 2 27M_SSC_M92 AK14 AC33 +VDD1DI C680 C684 C671
23 27M_SSC GPIO_16_SSIN VDD1DI
@ @ R334 0_0402_5% AG30 AC34 10U_0805_10V4Z
22 THM_ALERT# GPIO_17_THERMAL_INT VSS1DI
27M_SSC_R 1 2 AN14 VGA@ VGA@ VGA@ VGA@
19 27M_SSC_R GPIO_18_HPD3
2

GPIO23_CLKREQB 2 2 2
@ R335 0_0402_5% @ 1 R100 2 10K_0402_5% GPU_CTF AM17 GPIO_19_CTF
AL13 AC30 0.1U_0402_16V7K
BB_EN GPIO_20_PWRCNTL_1 R2
R334 & R335 be place close AJ14 GPIO_21_BB_EN R2B AC31
+3VS_DELAY AK13 +VDD1DI
CTF (High active) GPIO23_CLKREQB GPIO_22_ROMCSB L62
VDD1DI=45mA
AN13 GPIO_23_CLKREQB G2 AD30
GPIO24_TRSTB AM23 AD31 2 1 1U_0402_6.3V4Z
JTAG_TRSTB G2B
1

T16 PAD AN23 BLM18PG121SN1D_0603 1 1 1


R98 T17 PAD JTAG_TDI C676 C681 C673
AK23 JTAG_TCK B2 AF30
10K_0402_5% T14 PAD AL24 AF31 VGA@ 10U_0805_10V4Z
@ T12 PAD JTAG_TMS B2B VGA@ VGA@ VGA@
AM24 JTAG_TDO
T23 PAD 2 2 2
AJ19 GENERICA
2

T22 PAD AK19 AC32 0.1U_0402_16V7K


BB_EN T20 PAD GENERICB C
AJ20 GENERICC Y AD32
T19 PAD AK20 AF32
GENERICD COMP +A2VDDQ
Back bias (BB) control AJ24 GENERICE_HPD4 A2VDDQ=1mA
Back Bias Disabled : T13 PAD AH26 DAC2 L63
T15 PAD GENERICF 1U_0402_6.3V4Z
B GPIO_21_BB_EN = 0V AH24 GENERICG H2SYNC AD29 HSYNC_DAC2 22 2 1 B
+1.8VS_PX AC29 BLM18PG121SN1D_0603 1 1 1
BBP connect directly to VDDC V2SYNC VSYNC_DAC2 22
C682 C677 C672
AK24 VGA@ 10U_0805_10V4Z
11,25 HDMI_DET HPD1
AG31 +VDD1DI VGA@ VGA@ VGA@
VDD2DI 2 2 2
1

+3VS_DELAY AG32
R110 VSS2DI +3VS_DELAY 0.1U_0402_16V7K
499_0402_1%
VGA@ AG33
A2VDD
2
1

AD33 +A2VDDQ
R95 +VGA_VREF A2VDDQ
AH13 VREFG
10K_0402_5% A2VSSQ AF33
@
1

1
2

R107 C354 AA29 1 R86 2


GPIO24_TRSTB 249_0402_1% 0.1U_0402_16V7K R2SET
VGA@ VGA@ 715_0402_1%
2
VGA@
2
1

@ DDC/AUX AM26
DDC1CLK VGA_CRT_CLK 26
R96 PLL/CLOCK AN26
DDC1DATA VGA_CRT_DATA 26
1K_0402_5% +DPLL_PVDD AM32 DPLL_PVDD
AN32 DPLL_PVSS AUX1P AM27
Internal 2% downspread (disable) AUX1N AL27
2

61.9 ohm +DPLL_VDDC AN31 AM19 VGA_HDMI_SCLK 25


DPLL_VDDC DDC2CLK
DDC2DATA AL19 VGA_HDMI_SDATA 25
R306 75_0402_1%
1 2 27MCLK AV33 AN20
19,23 27M_NSSC XTALIN AUX2P
+1.8VS_PX Voltage Swing: 1.8 V AU34 AM20
XTALOUT AUX2N
2

DPLL_PVDD=0.12A VGA@
L66
R305 AL30
1U_0402_6.3V4Z +DPLL_PVDD VGA@ DDCCLK_AUX3P
1 2 DDCDATA_AUX3N AM30
75 ohm 100_0402_5%
MCK1608471YZF 0603 1 1 1 AL29
DDCCLK_AUX4P
1

VGA@ C688 C689 C690 AF29 AM29


22 GPU_THERMAL_D+ DPLUS DDCDATA_AUX4N
10U_0603_6.3V6M 0.1U_0402_16V7K AG29 THERMAL
22 GPU_THERMAL_D- DMINUS
VGA@ VGA@ VGA@ AN21
2 2 2 DDCCLK_AUX5P
A TSVDD=20mA DDCDATA_AUX5N AM21 A
L65 T7 PAD AK32
1U_0402_6.3V4Z +TSVDD TS_FDO
+1.8VS_PX 2 1 AJ32 TSVDD DDC6CLK AJ30
AJ33 TSVSS DDC6DATA AJ31
+1.1VS_PX BLM18PG121SN1D_0603 1 1 1
DPLL_VDDC=0.3A VGA@ C685 C687 C686 AK30
L24 NC_DDCCLK_AUX7P
VGA@ VGA@ VGA@ AK29
1U_0402_6.3V4Z +DPLL_VDDC NC_DDCDATA_AUX7N
1 2
2 2 2
MCK1608471YZF 0603 1 1 1 10U_0805_10V4Z 0.1U_0402_16V7K
VGA@
10U_0603_6.3V6M
C254 C256 C255
0.1U_0402_16V7K 216-0729002 A12 M96_BGA962 M92@ Security Classification Compal Secret Data Compal Electronics, Inc.
2
VGA@
2
VGA@
2
VGA@
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
401679 C

Date: Thursday, March 26, 2009 Sheet 15 of 57

GRATIS - FOR FREE 5 4 3 2 1


5 4 3 2 1

U4D U4C

MDA0 C5 P8 MAA0 C37 G24


MDA1 DQB_0 MAB_0 MAA1 DQA_0 MAA_0
C3 DQB_1 MAB_1 T9 C35 DQA_1 MAA_1 J23

MEMORY INTERFACE B

MEMORY INTERFACE A
MDA2 E3 P9 MAA2 A35 H24
MDA3 DQB_2 MAB_2 MAA3 DQA_2 MAA_2
E1 DQB_3 MAB_3 N7 E34 DQA_3 MAA_3 J24
MDA4 F1 N8 MAA4 G32 H26
MDA5 DQB_4 MAB_4 MAA5 DQA_4 MAA_4
F3 DQB_5 MAB_5 N9 D33 DQA_5 MAA_5 J26
MDA6 F5 U9 MAA6 F32 H21
MDA7 DQB_6 MAB_6 MAA7 DQA_6 MAA_6
G4 DQB_7 MAB_7 U8 E32 DQA_7 MAA_7 G21
MDA8 H5 Y9 MAA8 D31 H19
MDA9 DQB_8 MAB_8 MAA9 DQA_8 MAA_8
D H6 DQB_9 MAB_9 W9 F30 DQA_9 MAA_9 H20 D
MDA10 J4 AC8 MAA10 C30 L13
MDA11 DQB_10 MAB_10 MAA11 DQA_10 MAA_10
K6 DQB_11 MAB_11 AC9 A30 DQA_11 MAA_11 G16
MDA12 K5 AA7 MAA12 F28 J16
MDA13 DQB_12 MAB_12 BA2 DQA_12 MAA_12
L4 DQB_13 MAB_13/BA2 AA8 C28 DQA_13 MAA_13/BA2 H16
MDA14 M6 Y8 BA0 A28 J17
MDA15 DQB_14 MAB_14/BA0 BA1 DQA_14 MAA_14/BA0
M1 DQB_15 MAB_15/BA1 AA9 E28 DQA_15 MAA_15/BA1 H17
MDA16 M3 D27
DQB_16 DQMA#[7..0] 20,21 DQA_16
MDA17 M5 H3 DQMA#0 F26 A32
MDA18 DQB_17 DQMB_0 DQMA#1 DQA_17 DQMA_0
N4 DQB_18 DQMB_1 H1 C26 DQA_18 DQMA_1 C32
MDA19 P6 T3 DQMA#2 A26 D23
MDA20 DQB_19 DQMB_2 DQMA#3 DQA_19 DQMA_2
P5 DQB_20 DQMB_3 T5 F24 DQA_20 DQMA_3 E22
MDA21 R4 AE4 DQMA#4 C24 C14
MDA22 DQB_21 DQMB_4 DQMA#5 DQA_21 DQMA_4
T6 DQB_22 DQMB_5 AF5 A24 DQA_22 DQMA_5 A14
MDA23 T1 AK6 DQMA#6 E24 E10
MDA24 DQB_23 DQMB_6 DQMA#7 DQA_23 DQMA_6
U4 DQB_24 DQMB_7 AK5 C22 DQA_24 DQMA_7 D9
MAA[12..0] MDA25 V6 A22
MAA[12..0] 20,21 DQB_25 QSA[7..0] 20,21 DQA_25
MDA26 V1 F6 QSA0 F22 C34
BA[2..0] MDA27 DQB_26 QSB_0/RDQSB_0 QSA1 DQA_26 QSA_0/RDQSA_0
BA[2..0] 20,21 V3 DQB_27 QSB_1/RDQSB_1 K3 D21 DQA_27 QSA_1/RDQSA_1 D29
MDA28 Y6 P3 QSA2 A20 D25
MDA29 DQB_28 QSB_2/RDQSB_2 QSA3 DQA_28 QSA_2/RDQSA_2
Y1 DQB_29 QSB_3/RDQSB_3 V5 F20 DQA_29 QSA_3/RDQSA_3 E20
MDA30 Y3 AB5 QSA4 D19 E16
MDA31 DQB_30 QSB_4/RDQSB_4 QSA5 DQA_30 QSA_4/RDQSA_4
Y5 DQB_31 QSB_5/RDQSB_5 AH1 E18 DQA_31 QSA_5/RDQSA_5 E12
MDA32 AA4 AJ9 QSA6 C18 J10
MDA[63..32] MDA33 DQB_32 QSB_6/RDQSB_6 QSA7 DQA_32 QSA_6/RDQSA_6
21 MDA[63..32] AB6 DQB_33 QSB_7/RDQSB_7 AM5 QSA#[7..0] 20,21 A18 DQA_33 QSA_7/RDQSA_7 D7
MDA34 AB1 F18
MDA[31..0] MDA35 DQB_34 QSA#0 DQA_34
20 MDA[31..0] AB3 DQB_35 QSB_0B/WDQSB_0 G7 D17 DQA_35 QSA_0B/WDQSA_0 A34
MDA36 AD6 K1 QSA#1 A16 E30
MDA37 DQB_36 QSB_1B/WDQSB_1 QSA#2 DQA_36 QSA_1B/WDQSA_1
AD1 DQB_37 QSB_2B/WDQSB_2 P1 F16 DQA_37 QSA_2B/WDQSA_2 E26
C MDA38 AD3 W4 QSA#3 D15 C20 C
MDA39 DQB_38 QSB_3B/WDQSB_3 QSA#4 DQA_38 QSA_3B/WDQSA_3
AD5 DQB_39 QSB_4B/WDQSB_4 AC4 E14 DQA_39 QSA_4B/WDQSA_4 C16
MDA40 AF1 AH3 QSA#5 F14 C12
MDA41 DQB_40 QSB_5B/WDQSB_5 QSA#6 DQA_40 QSA_5B/WDQSA_5
AF3 DQB_41 QSB_6B/WDQSB_6 AJ8 D13 DQA_41 QSA_6B/WDQSA_6 J11
MDA42 AF6 AM3 QSA#7 F12 F8
MDA43 DQB_42 QSB_7B/WDQSB_7 DQA_42 QSA_7B/WDQSA_7
AG4 DQB_43 A12 DQA_43
MDA44 AH5 T7 ODTA0 D11 J21
DQB_44 ODTB0 ODTA0 20 DQA_44 ODTA0
MDA45 AH6 W7 ODTA1 F10 G19
DQB_45 ODTB1 ODTA1 21 DQA_45 ODTA1
MDA46 AJ4 A10
MDA47 DQB_46 CLKA0 DQA_46
AK3 DQB_47 CLKB0 L9 CLKA0 20 C10 DQA_47 CLKA0 H27
MDA48 AF8 L8 CLKA0# G13 G27
DQB_48 CLKB0B CLKA0# 20 DQA_48 CLKA0B
MDA49 AF9 H13
MDA50 DQB_49 CLKA1 DQA_49
AG8 DQB_50 CLKB1 AD8 CLKA1 21 J13 DQA_50 CLKA1 J14
MDA51 AG7 AD7 CLKA1# H11 H14
DQB_51 CLKB1B CLKA1# 21 DQA_51 CLKA1B
MDA52 AK9 G10
MDA53 DQB_52 RASA#0 DQA_52
AL7 DQB_53 RASB0B T10 RASA#0 20 G8 DQA_53 RASA0B K23
MDA54 AM8 Y10 RASA#1 K9 K19
DQB_54 RASB1B RASA#1 21 DQA_54 RASA1B
MDA55 AM7 K10
MDA56 DQB_55 CASA#0 DQA_55
AK1 DQB_56 CASB0B W10 CASA#0 20 G9 DQA_56 CASA0B K20
MDA57 AL4 AA10 CASA#1 A8 K17
DQB_57 CASB1B CASA#1 21 DQA_57 CASA1B
MDA58 AM6 C8
MDA59 DQB_58 CSA0# DQA_58
AM1 DQB_59 CSB0B_0 P10 CSA0# 20 E8 DQA_59 CSA0B_0 K24
MDA60 AN4 L10 A6 K27
MDA61 DQB_60 CSB0B_1 DQA_60 CSA0B_1
AP3 DQB_61 C6 DQA_61
MDA62 AP1 AD10 CSA1# E6 M13
DQB_62 CSB1B_0 CSA1# 21 +1.8VS_PX DQA_62 CSA1B_0
MDA63 AP5 AC10 A5 K16
+3VS_DELAY DQB_63 CSB1B_1 DQA_63 CSA1B_1
U10 CKEA0 L18 K21
CKEB0 CKEA0 20 MVREFDA CKEA0
+VDD_MEM18_REFD Y12 AA11 CKEA1 L20 J20
MVREFDB CKEB1 CKEA1 21 MVREFSA CKEA1
1

B +VDD_MEM18_REFS AA12 B
R87 MVREFSB WEA#0 243_0402_1% 1 R94
WEB0B N10 WEA#0 20 2 @ L27 NC_MEM_CALRN0 WEA0B K26
5.11K_0402_1% AB11 WEA#1 243_0402_1% 1 R105 2 @ N12 L15
WEB1B WEA#1 21 NC_MEM_CALRN1 WEA1B
@ 243_0402_1% 1 R108 2 @ AG12 NC_MEM_CALRN2
RSVD#1 AF28
2

TESTEN AD28 243_0402_1% 1 R106 2 M12 AG28 PAD T10


TESTEN 243_0402_1% 1 R93 MEM_CALRP1 RSVD#2
2 @ M27 NC_MEM_CALRP0 RSVD#3 AL31 PAD T9
1

AK10 243_0402_1% 1 R122 2 @ AH12 PAD T8


CLKTESTA NC_MEM_CALRP2
MP AL10 CLKTESTB DRAM_RST AH11 RSVD#5 H23
R91 J19
RSVD#6
1

1K_0402_1%
VGA@ T8
RSVD#9
2

R111 R109 W8
4.7K_0402_5% 4.7K_0402_5% RSVD#11
VGA@ VGA@
2

216-0729002 A12 M96_BGA962


216-0729002 A12 M96_BGA962
M92@ M92@

+1.8VS_PX +1.8VS_PX

Close to pin Y12 Close to pin AA12 M92-S2 and M92-M use memory group A only
1

R139 R138 while M92-M2 uses memory group B only.


100_0402_1% 100_0402_1%

VGA@ VGA@
2

A A
+VDD_MEM18_REFD +VDD_MEM18_REFS

1 1
1

C388 C381
R131 0.1U_0402_16V4Z R127 0.1U_0402_16V4Z
100_0402_1%
2 VGA@
100_0402_1%
2 VGA@ Security Classification Compal Secret Data Compal Electronics, Inc.
VGA@ VGA@
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 16 of 57


5 4 3 2 1
5 4 3 2 1

U4H

DP C/D POWER DP A/B POWER

AP20 NC_DPC_VDD18#1 NC_DPA_VDD18#1 AN24 DPA_VDD10: Transmitter Power 1.1V +/-3%


AP21 NC_DPC_VDD18#2 NC_DPA_VDD18#2 AP24
+1.1VS_PX +1.1VS_PX
D DPA_VDD10=0.2A L23
D

AP13 AP31 +DPA_VDD10 1U_0402_6.3V4Z 2 1


DPC_VDD10#1 DPA_VDD10#1
AT13 DPC_VDD10#2 DPA_VDD10#2 AP32
1 1 1 BLM18PG121SN1D_0603
10U_0603_6.3V6M C241 C235 C234 VGA@
AN17 DPC_VSSR#1 DPA_VSSR#1 AN27
AP16 AP27 0.1U_0402_16V7K
DPC_VSSR#2 DPA_VSSR#2 2 2 2
AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
AW16 DPC_VSSR#5 DPA_VSSR#5 AW26
VGA@ VGA@ VGA@

AP22 NC_DPD_VDD18#1 NC_DPB_VDD18#1 AP25


AP23 NC_DPD_VDD18#2 NC_DPB_VDD18#2 AP26
+1.1VS_PX
+1.1VS_PX

AP14 DPD_VDD10#1 DPB_VDD10#1 AN33


AP15 DPD_VDD10#2 DPB_VDD10#2 AP33

AN19 DPD_VSSR#1 DPB_VSSR#1 AN29


AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
AP19 DPD_VSSR#3 DPB_VSSR#3 AP30
AW20 DPD_VSSR#4 DPB_VSSR#4 AW30
AW22 DPD_VSSR#5 DPB_VSSR#5 AW32

R316 R308
C 150_0402_1% 150_0402_1% C
1 2 AW18 DPCD_CALR DPAB_CALR AW28 1 2

VGA@ VGA@
DP E/F POWER DP PLL POWER
+DPE_VDD18 AH34 AU28 +DPA_PVDD
DPE_VDD18#1 DPA_PVDD
DPE_VDD18: Output Driver Analog Power Supply. AJ34 DPE_VDD18#2 DPA_PVSS AV27
DPA_PVDD: DP PLL Power 1.8V +/-3%
+1.8VS_PX DPE_VDD18=0.31A +1.8VS_PX
L17 DPA_PVDD=20mA +1.8VS_PX
2 1 1U_0402_6.3V4Z +DPE_VDD18 +DPE_VDD10 AL33 AV29 L68
BLM18PG121SN1D_0603 DPE_VDD10#1 DPB_PVDD +DPA_PVDD 1U_0402_6.3V4Z
AM33 DPE_VDD10#2 DPB_PVSS AR28 2 1
VGA@ 1 1 1 1 1 1 BLM18PG121SN1D_0603
C149 C151 C150 VGA@
C696 C695 C694
10U_0805_10V4Z VGA@ VGA@ AN34 AU18 10U_0603_6.3V6M 0.1U_0402_16V7K
2 2 2 VGA@ DPE_VSSR#1 DPC_PVDD 2 2 2
AP39 DPE_VSSR#2 DPC_PVSS AV17
0.1U_0402_16V7K AR39 VGA@ VGA@ VGA@
DPE_VSSR#3
AU37 DPE_VSSR#4
AW35 DPE_VSSR#5
DPD_PVDD AV19
DPD_PVSS AR18

+DPE_VDD18 AF34 DPF_VDD18#1


AG34 DPF_VDD18#2
DPE_VDD10: Output Driver Analog Power Supply. AM37 +DPE_PVDD
DPE_PVDD
DPE_PVSS AN38 DPE_PVDD: DP PLL Power 1.8V +/-3%
+1.1VS_PX DPE_VDD10=0.27A
L20 +DPE_VDD10 AK33 DPE_PVDD=20mA +1.8VS_PX
1U_0402_6.3V4Z +DPE_VDD10 DPF_VDD10#1 L18
2 1 AK34 DPF_VDD10#2
BLM18PG121SN1D_0603 AL38 +DPE_PVDD +DPE_PVDD 1U_0402_6.3V4Z 2 1
B VGA@ NC_DPF_PVDD BLM18PG121SN1D_0603 B
1 1 1 NC_DPF_PVSS AM35 1 1 1
C192 C188 C187 VGA@
AF39 C165 C168 C166
10U_0805_10V4Z VGA@ VGA@ VGA@ DPF_VSSR#1 10U_0603_6.3V6M 0.1U_0402_16V7K
AH39 DPF_VSSR#2
2 2 2 0.1U_0402_16V7K 2 2 2
AK39 DPF_VSSR#3
AL34 VGA@ VGA@ VGA@
DPF_VSSR#4
AM34 DPF_VSSR#5
R304
150_0402_1%
1 2 AM39 DPEF_CALR
VGA@
216-0729002 A12 M96_BGA962

M92@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev

hexainf@hotmail.com DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 17 of 57


GRATIS - FOR FREE 5 4 3 2 1
5 4 3 2 1

U4E
+1.8VS_PX +PCIE_VDDR_M92 +1.8VS_PX
MEM I/O
VDDR1+VDDRHA+VDDRHB=TBD(2.9A/M96) PCIE
PCIE_VDDR=0.5A VGA@
AC7 VDDR1#1 PCIE_VDDR#1 AA31 2 1
AD11 AA32 L22 BLM18PG121SN1D_0603
VDDR1#2 PCIE_VDDR#2
1 1 2 1 2 1 2 AF7 VDDR1#3 PCIE_VDDR#3 AA33 PCIE_VDDR:PCI-E I/O power. 1 2
C331 10U_0603_6.3V6M VGA@ C339 1U_0402_6.3V4Z VGA@ C378 1U_0402_6.3V4Z VGA@ AG10 AA34 C221 10U_0603_6.3V6M VGA@
+ VDDR1#4 PCIE_VDDR#4
1 2 1 2 1 2 AJ7 VDDR1#5 PCIE_VDDR#5 V28 1 2
C355 330U_V_2.5VM_R9M C239 10U_0603_6.3V6M VGA@ C373 1U_0402_6.3V4Z VGA@ C363 1U_0402_6.3V4Z VGA@ AK8 W29 C237 1U_0402_6.3V4Z VGA@
VGA@ VDDR1#6 PCIE_VDDR#6
1 2 1 2 1 2 AL9 VDDR1#7 PCIE_VDDR#7 W30 1 2
2 C314 10U_0603_6.3V6M VGA@ C370 1U_0402_6.3V4Z VGA@ C362 1U_0402_6.3V4Z VGA@ C193 1U_0402_6.3V4Z VGA@
G11 VDDR1#8 PCIE_VDDR#8 Y31 PCIE_VDDC: PCI-E Digital Power Supply
1 2 1 2 1 2 G14 VDDR1#9 1 2
D C376 10U_0603_6.3V6M VGA@ C357 1U_0402_6.3V4Z VGA@ C369 1U_0402_6.3V4Z VGA@ G17 +1.1VS_PX C199 1U_0402_6.3V4Z VGA@ D
VDDR1#10
1 2 1 2 1 2 G20 VDDR1#11 PCIE_VDDC#1 G30 1 2
C389 10U_0603_6.3V6M VGA@ C361 1U_0402_6.3V4Z VGA@ C426 1U_0402_6.3V4Z VGA@ G23 G31 PCIE_VDDC=2A C236 1U_0402_6.3V4Z VGA@
VDDR1#12 PCIE_VDDC#2
1 2 1 2 G26 VDDR1#13 PCIE_VDDC#3 H29 1 2
C371 1U_0402_6.3V4Z VGA@ C372 1U_0402_6.3V4Z VGA@ G29 H30 C213 1U_0402_6.3V4Z VGA@
VDDR1#14 PCIE_VDDC#4
1 2 1 2 H10 VDDR1#15 PCIE_VDDC#5 J29 1 2 1 2
C326 1U_0402_6.3V4Z VGA@ C293 1U_0402_6.3V4Z VGA@ J7 J30 C196 10U_0603_6.3V6M VGA@ C212 0.1U_0402_16V7K VGA@
VDDR1#16 PCIE_VDDC#6
1 2 1 2 J9 VDDR1#17 PCIE_VDDC#7 L28 1 2 1 2
C283 1U_0402_6.3V4Z VGA@ C282 1U_0402_6.3V4Z VGA@ K11 M28 C233 1U_0402_6.3V4Z VGA@ C232 0.1U_0402_16V7K VGA@
VDDR1#18 PCIE_VDDC#8
1 2 1 2 K13 VDDR1#19 PCIE_VDDC#9 N28 1 2
C338 1U_0402_6.3V4Z VGA@ C292 1U_0402_6.3V4Z VGA@ K8 R28 C229 1U_0402_6.3V4Z VGA@ +VGA_CORE
VDDR1#20 PCIE_VDDC#10
1 2 1 2 L12 VDDR1#21 PCIE_VDDC#11 T28 1 2
C342 1U_0402_6.3V4Z VGA@ C350 1U_0402_6.3V4Z VGA@ L16 U28 C242 1U_0402_6.3V4Z VGA@
VDDR1#22 PCIE_VDDC#12
L21 VDDR1#23 1 2
L23 C220 1U_0402_6.3V4Z VGA@ 1 1
VDDR1#24
L26 VDDR1#25 VDDC#1 AA15 1 2
L7 CORE AA17 C216 1U_0402_6.3V4Z VGA@ + C243 + C333
VDDR1#26 VDDC#2 330U_V_2.5VM_R9M 330U_V_2.5VM_R9M
VDD_CT:Level translation between core and I/O M11 VDDR1#27 VDDC#3 AA20 1 2
N11 AA22 C217 1U_0402_6.3V4Z VGA@ VGA@ VGA@
+1.8VS_PX VDDR1#28 VDDC#4 2 2
VDD_CT=0.11A P7 VDDR1#29 VDDC#5 AA24 1 2
VGA@ R11 AA27 C202 1U_0402_6.3V4Z VGA@
+VDD_CT VDDR1#30 VDDC#6
2 1 U11 VDDR1#31 VDDC#7 AB13
L69 BLM18PG121SN1D_0603 U7 AB16
VDDR1#32 VDDC#8
1 2 Y11 VDDR1#33 VDDC#9 AB18 1 2 1 2 1 2
C706 10U_0603_6.3V6M VGA@ Y7 AB21 C311 10U_0603_6.3V6M VGA@ C352 1U_0402_6.3V4Z VGA@ C337 1U_0402_6.3V4Z VGA@
VDDR1#34 VDDC#10
1 2 VDDC#11 AB23 1 2 1 2 1 2
C271 1U_0402_6.3V4Z VGA@ AB26 C312 10U_0603_6.3V6M VGA@ C343 1U_0402_6.3V4Z VGA@ C329 1U_0402_6.3V4Z VGA@
VDDC#12
1 2 VDDC#13 AB28 1 2 1 2 1 2
C703 1U_0402_6.3V4Z VGA@ AC12 C313 10U_0603_6.3V6M VGA@ C279 1U_0402_6.3V4Z VGA@ C353 1U_0402_6.3V4Z VGA@
LEVEL VDDC#14
1 2 VDDC#15 AC15 1 2 1 2 1 2
C702 1U_0402_6.3V4Z VGA@ TRANSLATION AC17 C263 10U_0603_6.3V6M VGA@ C291 1U_0402_6.3V4Z VGA@ C240 1U_0402_6.3V4Z VGA@
+VDD_CT VDDC#16

POWER
C 1 2 AF26 AC20 1 2 1 2 1 2 C
C245 0.1U_0402_16V7K VGA@ VDD_CT#1 VDDC#17 C264 10U_0603_6.3V6M VGA@ C299 1U_0402_6.3V4Z VGA@ C322 1U_0402_6.3V4Z VGA@
AF27 VDD_CT#2 VDDC#18 AC22
AG26 VDD_CT#3 VDDC#19 AC24 1 2 1 2 1 2
AG27 AC27 C265 10U_0603_6.3V6M VGA@ C336 1U_0402_6.3V4Z VGA@ C285 1U_0402_6.3V4Z VGA@
VDD_CT#4 VDDC#20
VDDR3:ROM+Sync+DDC VDDC#21 AD13 1 2 1 2 1 2
+3VS_DELAY AD16 C262 10U_0603_6.3V6M VGA@ C298 1U_0402_6.3V4Z VGA@ C321 1U_0402_6.3V4Z VGA@
I/O VDDC#22
VDDR5 for DVPDATA[0..11] VDDR3=50mA VDDC#23 AD18 1 2 1 2 1 2
AF23 AD21 C252 1U_0402_6.3V4Z VGA@ C328 1U_0402_6.3V4Z VGA@ C316 1U_0402_6.3V4Z VGA@
+1.8VS_PX VDDR3#1 VDDC#24
VDDR5=0.17A 1 2 AF24 VDDR3#2 VDDC#25 AD23 1 2 1 2 1 2
L32 BLM18PG121SN1D_0603 C266 10U_0603_6.3V6M VGA@ AG23 AD26 C289 1U_0402_6.3V4Z VGA@ C270 1U_0402_6.3V4Z VGA@ C251 1U_0402_6.3V4Z VGA@
1U_0402_6.3V4Z +VDDR5 VDDR3#3 VDDC#26
2 1 1 2 AG24 VDDR3#4 VDDC#27 AF17 1 2 1 2 1 2
VGA@ 2 2 2 C259 1U_0402_6.3V4Z VGA@ AF20 C351 1U_0402_6.3V4Z VGA@ C269 1U_0402_6.3V4Z VGA@ C248 1U_0402_6.3V4Z VGA@
VDDC#28
1 2 VDDC#29 AF22 1 2 1 2
C364 C366 C365 C258 1U_0402_6.3V4Z VGA@ AF13 AG16 C284 1U_0402_6.3V4Z VGA@ C296 1U_0402_6.3V4Z VGA@
VGA@ VGA@ VGA@ VDDR5#1 VDDC#30
1 2 AF15 VDDR5#2 VDDC#31 AG18 1 2 1 2
1 1 1 C260 1U_0402_6.3V4Z VGA@ C335 1U_0402_6.3V4Z VGA@ C334 1U_0402_6.3V4Z VGA@
AG13 VDDR5#3 VDDC#32 AG21
10U_0603_6.3V6M 0.1U_0402_16V7K +VDDR5 AG15 AH22 1 2 1 2
VDDR5#4 VDDC#33 C320 1U_0402_6.3V4Z VGA@ C297 1U_0402_6.3V4Z VGA@
VDDC#34 M16
+1.8VS_PX VDDRHA:MCLK PAD Power M18 1 2 1 2
L34 BLM18PG121SN1D_0603
VDDR4=0.17A VDDC#35 C286 1U_0402_6.3V4Z VGA@ C267 1U_0402_6.3V4Z VGA@
AD12 VDDR4#1 VDDC#36 M23
2 1 1U_0402_6.3V4Z +VDDR4 VDDRHA=20mA +VDDR4 AF11 M26 1 2 1 2
VGA@ +1.8VS_PX VDDR4#2 VDDC#37 C247 1U_0402_6.3V4Z VGA@ C268 1U_0402_6.3V4Z VGA@
2 2 2 AF12 VDDR4#3 VDDC#38 N15
VDDRHA for M96 ONLY AG11 VDDR4#4 VDDC#39 N17 1 2 1 2
C377 C374 C375 L26 @ BLM18PG121SN1D_0603 N20 VDDC+VDDCI=16A C287 1U_0402_6.3V4Z VGA@ C250 1U_0402_6.3V4Z VGA@
VGA@ VGA@ VGA@ +VDDARHA VDDC#40
2 1 VDDC#41 N22 1 2 1 2
1 1 1 C275 1U_0402_6.3V4Z VGA@ C261 1U_0402_6.3V4Z VGA@
1 2 VDDC#42 N24
10U_0603_6.3V6M 0.1U_0402_16V7K C304 @ 1U_0402_6.3V4Z MEM CLK N27 1 2 1 2
VDDC#43 C332 1U_0402_6.3V4Z VGA@ C323 1U_0402_6.3V4Z VGA@
VDDRHB=20mA M20 VDDRHA VDDC#44 R13
+1.8VS_PX M21 R16 1 2 1 2
VGA@ VSSRHA VDDC#45 C288 1U_0402_6.3V4Z VGA@ C315 1U_0402_6.3V4Z VGA@
VDDR4 for DVPDATA[12..23] VDDC#46 R18
L33 BLM18PG121SN1D_0603 R21 1 2 1 2
B +VDDARHB VDDC#47 C330 1U_0402_6.3V4Z VGA@ C346 1U_0402_6.3V4Z B
VGA@
2 1 V12 VDDRHB VDDC#48 R23
1 2 U12 VSSRHB VDDC#49 R26
C349 1U_0402_6.3V4Z T15
VGA@ VDDC#50
VDDC#51 T17
VDDRHB:MCLK PAD Power VDDC#52 T20
+1.8VS_PX T22
L60 BLM18PG121SN1D_0603 PLL VDDC#53
PCIE_PVDD=40mA VDDC#54 T24
2 1 1U_0402_6.3V4Z +PCIE_PVDD AB37 T27
VGA@ PCIE_PVDD VDDC#55
2 2 2 PCIE_PVDD:PCI-E PLL power. VDDC#56 U16
H7 NC_MPV18#1 VDDC#57 U18
C669 C679 C675 H8 U21
VGA@ VGA@ VGA@ NC_MPV18#2 VDDC#58
VDDC#59 U23
1 1 1
VDDC#60 U26
+VGA_CORE 10U_0603_6.3V6M 0.1U_0402_16V7K AM10 V15
SPV10=414mA NC_SPV18 VDDC#61
VDDC#62 V17
2 1 1U_0402_6.3V4Z +SPV10 AN9 V20
L30 BLM18PG121SN1D_0603 2 SPV10 VDDC#63
2 2 VDDC#64 V22
VGA@ AN10 V24
C348 C360 C359 SPVSS VDDC#65
VDDC#66 V27
VGA@ VGA@ VGA@ Y16
1 1 1 VDDC#67
VDDC#68 Y18
10U_0603_6.3V6M 0.1U_0402_16V7K Y21
BACK BIAS VDDC#69
VDDC#70 Y23
SPV10: Dedicated power pin for memory +VGA_CORE Y26
BBP=0.12A VDDC#71
and engine PLLs. AA13 BBP#1 VDDC#72 Y28 VDDCI: Isolated (clean) core power for the l/O logic
Y13 AH27 +VGA_CORE
BBP#2 VDDC#73
2 2 VDDC#74 AH28
VGA@
C327 C318 M15 +VDDCI 1U_0402_6.3V4Z 1U_0402_6.3V4Z 2 1
VGA@ VGA@ ISOLATED VDDCI#1 N13 2 2 2 2 L31 BLM18PG121SN1D_0603
1 1 CORE I/O VDDCI#2 R12
A
1U_0402_6.3V4Z 0.1U_0402_16V7K VDDCI#3 C347 C356 C344 C358
A
VDDCI#4 T12
1 1 1 1
VGA@ VGA@ VGA@ VGA@
216-0729002 A12 M96_BGA962 M92@ 1U_0402_6.3V4Z 10U_0603_6.3V6M

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 18 of 57


5 4 3 2 1
5 4 3 2 1

U4F

AB39 PCIE_VSS#1 GND#1 A3


E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
H34 PCIE_VSS#8 GND#8 AA26
H39 PCIE_VSS#9 GND#9 AA28
J31 PCIE_VSS#10 GND#10 AA6
D D
J34 PCIE_VSS#11 GND#11 AB12
K31 PCIE_VSS#12 GND#12 AB15
K34 PCIE_VSS#13 GND#13 AB17
K39 PCIE_VSS#14 GND#14 AB20
L31 PCIE_VSS#15 GND#15 AB22
L34 PCIE_VSS#16 GND#16 AB24
M34 PCIE_VSS#17 GND#17 AB27
M39 PCIE_VSS#18 GND#18 AC11
N31 PCIE_VSS#19 GND#19 AC13
N34 PCIE_VSS#20 GND#20 AC16
P31 PCIE_VSS#21 GND#21 AC18
P34 PCIE_VSS#22 GND#22 AC2
P39 PCIE_VSS#23 GND#23 AC21
R34 PCIE_VSS#24 GND#24 AC23
T31 PCIE_VSS#25 GND#25 AC26
T34 AC28
T39
PCIE_VSS#26 GND#26
AC6
Spread spectrum
PCIE_VSS#27 GND#27
U31 PCIE_VSS#28 GND#28 AD15
U34 PCIE_VSS#29 GND#29 AD17
V34 AD20 +3VS_DELAY
PCIE_VSS#30 GND#30
V39 PCIE_VSS#31 GND#31 AD22
W31 AD24 C742 1 2 0.1U_0402_16V4Z
PCIE_VSS#32 GND#32 @
W34 PCIE_VSS#33 GND#33 AD27
Y34 AD9 U27
PCIE_VSS#34 GND#34
Y39 PCIE_VSS#35 GND#35 AE2 7 VDD REF 5
AE6 @
GND#36 27M_NSSC 27M_SSC_R
GND#37 AF10 15,23 27M_NSSC 1 2 1 XIN MODOUT 4 1 2 27M_SSC_R 15
AF16 R331 0_0402_5% R336 22_0402_5%
GND#38 @
GND#39 AF18 8 XOUT NC 3
AF21 Place close to R306
F15 GND#101
GND GND#40
GND#41
GND#42
AG17
AG2
2 VSS PD# 6
C ASM3P1819N-SR_SO8 C
F17 GND#102 GND#43 AG20
F19 GND#103 GND#44 AG22 @
F21 GND#104 GND#45 AG6
F23 GND#105 GND#46 AG9
F25 GND#106 GND#47 AH21
F27 GND#107 GND#48 AH29
F29 GND#108 GND#49 AJ10
F31 GND#109 GND#50 AJ11
F33 GND#110 GND#51 AJ2
F7 GND#111 GND#52 AJ28
F9 GND#112 GND#53 AJ6
G2 GND#113 GND#54 AK11
G6 GND#114 GND#55 AK31
H9 GND#115 GND#56 AK7
J2 GND#116 GND#57 AL11
J27 GND#117 GND#58 AL14
J6 GND#118 GND#59 AL17
J8 GND#119 GND#60 AL2
K14 GND#120 GND#61 AL20
K7 AL21 +3VS_DELAY Q15
GND#121 GND#62
L11 GND#122 GND#63 AL23
L17 AL26 1 3

S
+3VS

D
GND#123 GND#64
L2 GND#124 GND#65 AL32
L22 AL6 SI2301BDS_SOT23
GND#125 GND#66

2
L24 AL8 VGA@ R142

G
GND#126 GND#67

2
L6 AM11 100K_0402_5%
GND#127 GND#68 VGA@
M17 GND#128 GND#69 AM31
M22 GND#129 GND#70 AM9
M24 GND#130 GND#71 AN11

1
N16 GND#131 GND#72 AN2
N18 GND#132 GND#73 AN30 38 PX_+3VS 1 @ 2 PX_+3VS_R
N2 AN6 R467 0_0402_5%
B GND#133 GND#74 B
N21 GND#134 GND#75 AN8

1
D
N23 GND#135 GND#76 AP11
N26 AP7 +3VS 1 2 2 Q16
GND#136 GND#77 R151 4.7K_0402_5% 2N7002_SOT23
N6 GND#137 GND#78 AP9 G
R15 AR5 VGA@ S VGA@
GND#138 GND#79

3
R17 GND#139 GND#80 AW34
R2 GND#140 GND#81 B11 1
R20 GND#141 GND#82 B13
R22 B15 @ C405
GND#142 GND#83 0.01U_0402_25V7K
R24 GND#143 GND#84 B17
2
R27 GND#144 GND#85 B19
R6 GND#145 GND#86 B21
T11 GND#146 GND#87 B23
T13 GND#147 GND#88 B25
T16 GND#148 GND#89 B27
T18 GND#149 GND#90 B29 Use Delay 3.3V BUS (VDDR3) for GPIO/DDC Pull up to reduce Leakage to VDDR3 Bus.
T21 GND#150 GND#91 B31
T23 GND#151 GND#92 B33
T26 GND#152 GND#93 B7
U15 GND#153 GND#94 B9
U17 GND#154 GND#95 C1
U2 GND#155 GND#96 C39
U20 GND#156 GND#97 E35
U22 GND#157 GND#98 E5
U24 GND#158 GND#99 F11
U27 GND#159 GND#100 F13
U6 GND#160
V11 GND#161
V16 GND#162
V18 GND#163
V21 GND#164
V23 GND#165
A A
V26 GND#166
W2 GND#167
W6 GND#168
Y15 GND#169
Y17 GND#170
Y20 GND#171
Y22 GND#172 VSS_MECH#1 A39
Y24
Y27
GND#173
GND#174
VSS_MECH#2
VSS_MECH#3
AW1
AW39
Security Classification Compal Secret Data Compal Electronics, Inc.
U13 GND#175 Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
V13 GND#176
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
216-0729002 A12 M96_BGA962
M92@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
401679 C

hexainf@hotmail.com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 26, 2009 Sheet 19 of 57
5 4 3 2 1
GRATIS - FOR FREE
5 4 3 2 1

U6 U5
BA0 L2 B9 MDA21 BA0 L2 B9 MDA3 BA[2..0]
BA0 DQ15 BA0 DQ15 16,21 BA[2..0]
BA1 L3 B1 MDA19 BA1 L3 B1 MDA5
D BA1 DQ14 MDA20 BA1 DQ14 MDA1 QSA[7..0] D
DQ13 D9 DQ13 D9 16,21 QSA[7..0]
MAA12 R2 D1 MDA16 MAA12 R2 D1 MDA6
MAA11 A12 DQ12 MDA17 MAA11 A12 DQ12 MDA4 QSA#[7..0]
P7 A11 DQ11 D3 Group2 P7 A11 DQ11 D3 Group0 16,21 QSA#[7..0]
MAA10 M2 D7 MDA22 MAA10 M2 D7 MDA0
MAA9 A10/AP DQ10 MDA18 MAA9 A10/AP DQ10 MDA7 DQMA#[7..0]
P3 A9 DQ9 C2 P3 A9 DQ9 C2 16,21 DQMA#[7..0]
MAA8 P8 C8 MDA23 MAA8 P8 C8 MDA2
MAA7 A8 DQ8 MDA12 MAA7 A8 DQ8 MDA27 MAA[12..0]
P2 A7 DQ7 F9 P2 A7 DQ7 F9 16,21 MAA[12..0]
MAA6 N7 F1 MDA10 MAA6 N7 F1 MDA31
MAA5 A6 DQ6 MDA15 MAA5 A6 DQ6 MDA24 MDA[63..0]
N3 A5 DQ5 H9 N3 A5 DQ5 H9 16,21 MDA[63..0]
MAA4 N8 H1 MDA8 MAA4 N8 H1 MDA28
MAA3 A4 DQ4 MDA11 MAA3 A4 DQ4 MDA29
N2 A3 DQ3 H3 Group1 N2 A3 DQ3 H3 Group3
MAA2 M7 H7 MDA14 MAA2 M7 H7 MDA25 ODTA0
A2 DQ2 A2 DQ2 16 ODTA0
MAA1 M3 G2 MDA9 MAA1 M3 G2 MDA30
MAA0 A1 DQ1 MDA13 MAA0 A1 DQ1 MDA26 CKEA0
M8 A0 DQ0 G8 M8 A0 DQ0 G8 16 CKEA0
RASA#0
16 RASA#0
CLKA0# K8 A9 +1.8VS_PX CLKA0# K8 A9 +1.8VS_PX
CLKA0 CK VDDQ1 CLKA0 CK VDDQ1 CASA#0
J8 CK VDDQ2 C1 J8 CK VDDQ2 C1 16 CASA#0
VDDQ3 C3 VDDQ3 C3
CKEA0 K2 C7 CKEA0 K2 C7 WEA#0
CKE VDDQ4 CKE VDDQ4 16 WEA#0
VDDQ5 C9 VDDQ5 C9
E9 E9 CSA0#
VDDQ6 VDDQ6 16 CSA0#
VDDQ7 G1 VDDQ7 G1
CSA0# L8 G3 CSA0# L8 G3
CS VDDQ8 CS VDDQ8
VDDQ9 G7 VDDQ9 G7
WEA#0 K3 G9 WEA#0 K3 G9
WE VDDQ10 WE VDDQ10
RASA#0 K7 A1 RASA#0 K7 A1
RAS VDD1 RAS VDD1
VDD2 E1 VDD2 E1
CASA#0 L7 J9 CASA#0 L7 J9
CAS VDD3 CAS VDD3
VDD4 M9 VDD4 M9
DQMA#1 F3 R1 DQMA#3 F3 R1
C DQMA#2 LDM VDD5 DQMA#0 LDM VDD5 C
B3 UDM B3 UDM
J1 0.1U_0402_16V4Z +1.8VS_PX J1 0.1U_0402_16V4Z +1.8VS_PX
VDDL VDDL
VSSDL J7 1 1 VSSDL J7 1 1
ODTA0 K9 ODTA0 K9
ODT C745 C734 ODT C412 C399
VGA@ VGA@ VGA@ VGA@
+1.8VS_PX QSA1 2 2 1U_0402_6.3V4Z QSA3 2 2 1U_0402_6.3V4Z
F7 LDQS F7 LDQS
QSA#1 E8 A7 +1.8VS_PX QSA#3 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
VSSQ3 B8 VSSQ3 B8
1

1
VSSQ4 D2 VSSQ4 D2
R349 QSA2 B7 D8 R160 QSA0 B7 D8
4.99K_0402_1% VGA@ QSA#2 UDQS VSSQ5 4.99K_0402_1% VGA@ QSA#0 UDQS VSSQ5
A8 UDQS VSSQ6 E7 A8 UDQS VSSQ6 E7
F2 F2 CLKA0
VSSQ7 VSSQ7 16 CLKA0
VSSQ8 F8 VSSQ8 F8
2

2
+VRAM_REF1 J2 H2 +VRAM_REF2 J2 H2 CLKA0#
VREF VSSQ9 VREF VSSQ9 16 CLKA0#
VSSQ10 H8 VSSQ10 H8
1

1
1 A2 NC#A2 1 A2 NC#A2
R353 E2 A3 R162 E2 A3 R164 R161
4.99K_0402_1% BA2 NC#E2 VSS1 4.99K_0402_1% BA2 NC#E2 VSS1 56_0402_5% 56_0402_5%
L1 NC#L1 VSS2 E3 L1 NC#L1 VSS2 E3
C748 R3 J3 C418 R3 J3
VGA@ 2 0.1U_0402_16V4Z NC#R3 VSS3 VGA@ 2 0.1U_0402_16V4Z NC#R3 VSS3 VGA@ VGA@
R7 NC#R7 VSS4 N1 R7 NC#R7 VSS4 N1
2

2
VGA@ R8 P9 VGA@ R8 P9
NC#R8 VSS5 NC#R8 VSS5

HYB18T256161BF-25 HYB18T256161BF-25 1
VRAM@ VRAM@ C419
470P_0402_50V7K

SA00002UH00 HYNIX S IC D2 64M16/500 H5PS1G63EFR-20L FBGA84 2 VGA@

SA00002MF00 Qimonda S IC D2 64M16/500 HYB18T1G161C2F-20


B B
SA00002MD00 Samsung S IC D2 64M16/500 K4N1G164QQ-HC20 FBGA84
SA000031O00 Samsung S IC D2 64M16/500 K4N1G164QE-HC20 FBGA 84P
+1.8VS_PX
+1.8VS_PX
10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
C753 C752 C730 C741 C740 C736 C732 C728
C424 C423 C415 C409 C396 C416 C410 C400
2 2 2 2 2 2 2 2
10U_0603_6.3V6M 2 2 2 2 2 2 2 2
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0603_6.3V6M
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 20 of 57


5 4 3 2 1
5 4 3 2 1

D U7 U8 D
BA0 L2 B9 MDA48 BA0 L2 B9 MDA45
BA1 BA0 DQ15 MDA52 BA1 BA0 DQ15 MDA43
L3 BA1 DQ14 B1 L3 BA1 DQ14 B1
D9 MDA49 D9 MDA47
MAA12 DQ13 MDA54 MAA12 DQ13 MDA41
R2 A12 DQ12 D1 R2 A12 DQ12 D1
MAA11 P7 D3 MDA53 Group6 MAA11 P7 D3 MDA42 Group5 BA[2..0]
A11 DQ11 A11 DQ11 16,20 BA[2..0]
MAA10 M2 D7 MDA50 MAA10 M2 D7 MDA46
MAA9 A10/AP DQ10 MDA55 MAA9 A10/AP DQ10 MDA40 DQMA#[7..0]
P3 A9 DQ9 C2 P3 A9 DQ9 C2 16,20 DQMA#[7..0]
MAA8 P8 C8 MDA51 MAA8 P8 C8 MDA44
MAA7 A8 DQ8 MDA34 MAA7 A8 DQ8 MDA60 MAA[12..0]
P2 A7 DQ7 F9 P2 A7 DQ7 F9 16,20 MAA[12..0]
MAA6 N7 F1 MDA37 MAA6 N7 F1 MDA58
MAA5 A6 DQ6 MDA33 MAA5 A6 DQ6 MDA63 QSA#[7..0]
N3 A5 DQ5 H9 N3 A5 DQ5 H9 16,20 QSA#[7..0]
MAA4 N8 H1 MDA35 MAA4 N8 H1 MDA56
MAA3 A4 DQ4 MDA39 MAA3 A4 DQ4 MDA59 QSA[7..0]
N2 A3 DQ3 H3 Group4 N2 A3 DQ3 H3 Group7 16,20 QSA[7..0]
MAA2 M7 H7 MDA32 MAA2 M7 H7 MDA61
MAA1 A2 DQ2 MDA38 MAA1 A2 DQ2 MDA57 MDA[63..0]
M3 A1 DQ1 G2 M3 A1 DQ1 G2 16,20 MDA[63..0]
MAA0 M8 G8 MDA36 MAA0 M8 G8 MDA62
A0 DQ0 A0 DQ0 ODTA1
16 ODTA1
CLKA1# K8 A9 +1.8VS_PX CLKA1# K8 A9 +1.8VS_PX CKEA1
CK VDDQ1 CK VDDQ1 16 CKEA1
CLKA1 J8 C1 CLKA1 J8 C1
CK VDDQ2 CK VDDQ2 RASA#1
VDDQ3 C3 VDDQ3 C3 16 RASA#1
CKEA1 K2 C7 CKEA1 K2 C7
CKE VDDQ4 CKE VDDQ4 CASA#1
VDDQ5 C9 VDDQ5 C9 16 CASA#1
VDDQ6 E9 VDDQ6 E9
G1 G1 WEA#1
VDDQ7 VDDQ7 16 WEA#1
CSA1# L8 G3 CSA1# L8 G3
CS VDDQ8 CS VDDQ8 CSA1#
VDDQ9 G7 VDDQ9 G7 16 CSA1#
WEA#1 K3 G9 WEA#1 K3 G9
WE VDDQ10 WE VDDQ10
RASA#1 K7 A1 RASA#1 K7 A1
RAS VDD1 RAS VDD1
VDD2 E1 VDD2 E1
C CASA#1 CASA#1 C
L7 CAS VDD3 J9 L7 CAS VDD3 J9
VDD4 M9 VDD4 M9
DQMA#4 F3 R1 DQMA#7 F3 R1
DQMA#6 LDM VDD5 DQMA#5 LDM VDD5
B3 UDM B3 UDM
J1 0.1U_0402_16V4Z +1.8VS_PX J1 0.1U_0402_16V4Z +1.8VS_PX
VDDL VDDL
VSSDL J7 1 1 VSSDL J7 1 1
ODTA1 K9 ODTA1 K9
ODT VGA@ C744 VGA@ ODT C414 C417
+1.8VS_PX C739 VGA@ VGA@
QSA4 2 2 1U_0402_6.3V4Z +1.8VS_PX QSA7 2 2 1U_0402_6.3V4Z
F7 LDQS F7 LDQS
QSA#4 E8 A7 QSA#7 E8 A7
LDQS VSSQ1 LDQS VSSQ1
VSSQ2 B2 VSSQ2 B2
1

VSSQ3 B8 VSSQ3 B8

1
R347 D2 D2
4.99K_0402_1% QSA6 VSSQ4 R163 QSA5 VSSQ4
B7 UDQS VSSQ5 D8 B7 UDQS VSSQ5 D8
VGA@ QSA#6 A8 E7 4.99K_0402_1% VGA@ QSA#5 A8 E7
UDQS VSSQ6 UDQS VSSQ6
VSSQ7 F2 VSSQ7 F2
2

VSSQ8 F8 VSSQ8 F8

2
+VRAM_REF3 J2 H2 +VRAM_REF4 J2 H2
VREF VSSQ9 VREF VSSQ9
VSSQ10 H8 VSSQ10 H8
1

1
1 A2 NC#A2 1 A2 NC#A2
R348 E2 A3 R165 E2 A3
4.99K_0402_1% BA2 NC#E2 VSS1 4.99K_0402_1% BA2 NC#E2 VSS1
L1 NC#L1 VSS2 E3 L1 NC#L1 VSS2 E3
C747 R3 J3 C420 R3 J3 CLKA1
2 NC#R3 VSS3 2 NC#R3 VSS3 16 CLKA1
VGA@ 0.1U_0402_16V4Z R7 N1 VGA@ 0.1U_0402_16V4Z R7 N1
NC#R7 VSS4 NC#R7 VSS4
2

2
VGA@ R8 P9 VGA@ R8 P9 CLKA1#
NC#R8 VSS5 NC#R8 VSS5 16 CLKA1#

1
HYB18T256161BF-25 HYB18T256161BF-25 R351 R350
VRAM@ VRAM@ 56_0402_5% 56_0402_5%

VGA@ VGA@

2
B B

1
C746
470P_0402_50V7K
2
VGA@
+1.8VS_PX +1.8VS_PX

10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 10U_0603_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
C750 C754 C735 C731 C729 C738 C737 C733 C425 C422 C408 C413 C411 C401 C395 C398
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M 10U_0603_6.3V6M
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
401679 C

hexainf@hotmail.com MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 26, 2009 Sheet 21 of 57
5 4 3 2 1
GRATIS - FOR FREE
5 4 3 2 1

CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
STRAPS +3VS_DELAY THEY MUST NOT CONFLICT DURING RESET

STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS RECOMMENDED SETTINGS

15 GPU_GPIO0 GPU_GPIO0 VGA@ R123 2 1 10K_0402_5% 1 : PCIe bus Full Tx output swing
15 GPU_GPIO1 GPU_GPIO1 VGA@ R133 2 1 10K_0402_5% TX_PWRS_ENB GPIO0 Transmitter Power Savings Enable
D GPU_GPIO2 VGA@ R125 D
15 GPU_GPIO2 2 1 10K_0402_5% 0 : PCIe bus 50% Tx output swing
1 : Tx de-emphasis enabled
TX_DEEMPH_EN GPIO1 PCI Express Transmitter De-emphasis Enable
15 GPU_GPIO8 GPU_GPIO8 @ R463 2 1 10K_0402_5% 0 : Tx de-emphasis disabled
15 GPU_GPIO9 GPU_GPIO9 @ R134 2 1 10K_0402_5% PCIE GNE2 ENABLED
15 GPU_GPIO11 GPU_GPIO11 VGA@ R130 2 1 10K_0402_5% BIF_GEN2_EN_A GPIO2 0 = Advertises the PCIe device as 2.5 GT/s capable at power-on.
15 GPU_GPIO12 GPU_GPIO12 @ R129 2 1 10K_0402_5% 1 = Advertises the PCIe device as 5.0 GT/s capable at power-on. 0 (5.0 GT/s capability will be controlled by software)
15 GPU_GPIO13 GPU_GPIO13 @ R126 2 1 10K_0402_5%
0 : VGA Controller capacity enabled
VGA Disable determines whether or not the card will
VSYNC_DAC1 and HSYNC_DAC1 VGA_DIS GPIO9 be recognized as the system's VGA controller 1 : The device will not be recognized as the system’s
15,26 VGA_CRT_VSYNC VGA@ R300 2 1 10K_0402_5% VGA controller
VGA@ R299 2 1 10K_0402_5% pull up for HDMI & DISPLAYPORT
15,26 VGA_CRT_HSYNC
15 VSYNC_DAC2 @ R81 2 1 10K_0402_5% Audio codec enable
15 HSYNC_DAC2 @ R84 2 1 10K_0402_5% CONFIG(2:0) GPIO[13:11] Size of the primary memory apertures 0 0 1

VIP_DEVICE_STRAP_EN V2SYNC 0

+3VS_DELAY RESERVED H2SYNC 0

AUD[1] AUD[0]
AUD[1] HSYNC 0 0 No audio function

1
0 1 Audio for DisplayPort and HDMI if dongle is detected 11
R150 AUD[0] VSYNC 1 0 Audio for DisplayPort only
10K_0402_5% 1 1 Audio for both DisplayPort and HDMI
VGA@

2
+3VS

1
RESERVED GPIO21 0
R146
10K_0402_5% 0: Disable external BIOS ROM device
C VGA@ BIOS_ROM_EN GPIO_22_ROMCSB C
1: Enable external BIOS ROM device

2
CCBYPASS GENERICC IGNORE VIP DEVICE STRAPS 0
EC_SMB_CK2_PX 6 1 EC_SMB_CK2 6,38
External VGA Thermal Sensor

5
Q48A BIF_CLK_PM_EN GPIO8 BIF_CLK_PM_EN 0
2N7002DW-T/R7_SOT363-6
EC_SMB_DA2_PX VGA@ 3 4 EC_SMB_DA2 6,38
+3VS_DELAY Q48B
2N7002DW-T/R7_SOT363-6 AMD RESERVED CONFIGURATION STRAPS
VGA@

VGA@ C305
2 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
0.1U_0402_16V4Z
1
U12 H2SYNC GENERICC
1 8 EC_SMB_CK2_PX
VCC SMBCLK
15 GPU_THERMAL_D+ 2 7 EC_SMB_DA2_PX PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
C306 VGA@ DXP SMBDATA
1 2 3 6 THM_ALERT# 15
THEY MUST NOT CONFLICT DURING RESET
DXN ALERT
2200P_0402_50V7K 4 5 +3VS_DELAY
15 GPU_THERMAL_D- THERM GND VGA@ GPIO_28_TDO GPIO21_BB_EN
1 2
G781-1_SOP8 R85 4.7K_0402_5%
VGA@

B
Address 1001 101X b B

VRAM@ VRAM@ STRAPS PIN GPU Project VRAM size Vendor Part Number# Compal Part Number# VRAM_ID 3,2,1,0
R323 10K_0402_5% R319 10K_0402_5%
2 1 +1.8VS_PX 2 1 +1.8VS_PX JV40-PU_KBLG0 512M(x4) Samsung 64Mx16 1.8V (Q-die) SA00002MD00 0000

VRAM_ID0 15 VRAM_ID1 15 JV40-PU_KBLG0 512M(x4) Hynix 64Mx16 1.8V SA00002UH20 0001


1 2 1 2 M92-M2 XT JV40-PU_KBLG0 512M(x4) Qimonda 64Mx16 1.8V SA00002MF00PVT 0010
R324 10K_0402_5% R320 10K_0402_5%
VRAM@ VRAM@ JV40-PU_KBLG0 512M(x4) Samsung 64Mx16 1.8V (E-die) SA000031O10 0100
DVPDATA
VRAM_ID[3:0] (23,22,21,20)

VRAM@ VRAM@
R321 10K_0402_5% R317 10K_0402_5%
2 1 +1.8VS_PX 2 1 +1.8VS_PX

VRAM_ID2 15 VRAM_ID3 15
1 2 1 2
R322 10K_0402_5% R318 10K_0402_5%
VRAM@ VRAM@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A4921P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
401679 C

Date: Thursday, March 26, 2009 Sheet 22 of 57


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