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DATA SHEET

MOS FIELD EFFECT TRANSISTOR


2SK3324
SWITCHING
N-CHANNEL POWER MOS FET
INDUSTRIAL USE

DESCRIPTION ORDERING INFORMATION


The 2SK3324 is N-Channel MOS FET device that features a PART NUMBER PACKAGE
Low gate charge and excellent switching characteristics, and
2SK3324 TO-3P
Designed for high voltage applications such as switching
power supply, AC adapter.

FEATURES
• Low gate charge : (TO-3P)
QG = 32 nC TYP. (VDD = 450 V, VGS = 10 V, ID = 6.0 A)
• Gate voltage rating : ±30 V
• Low on-state resistance :
RDS(on) = 2.8 Ω MAX. (VGS = 10 V, ID = 3.0 A)
• Avalanche capability ratings

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)


Drain to Source Voltage VDSS 900 V
Gate to Source Voltage VGSS(AC) ±30 V
Drain Current (DC) ID(DC) ±6 A
Note1
Drain Current (Pulse) ID(pulse) ±18 A
Total Power Dissipation (TC = 25°C) PT 120 W
Total Power Dissipation (TA = 25°C) PT 3.0 W
Storage Temperature Tstg –55 to + 150 °C
Note2
Single Avalanche Current IAS 6.0 A
Note2
Single Avalanche Energy EAS 21.6 mJ

Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1 %


2. Starting Tch = 25 °C, VDD = 150 V, RG = 25 Ω, VGS = 20 V → 0 V

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Document No. D14203EJ2V0DS00 (2nd edition) The mark • shows major revised points. © 1999
Date Published January 2000 NS CP(K)
Printed in Japan

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2SK3324

ELECTRICAL CHARACTERISTICS (TA = 25 °C)


CHARACTERISTICS SYMBOL MIN. TYP. MAX. UNIT TEST CONDITIONS

Drain Leakage Current IDSS 100 µA VDS = 900 V, VGS = 0 V

Gate to Source Leakage Current IGSS ±100 nA VGS = ±30 V, VDS = 0 V

Gate to Source Cut-off Voltage VGS(off) 2.5 3.5 V VDS = 10 V, ID = 1.0 mA

• Forward Transfer Admittance | yfs | 2.5 3.3 S VDS = 20 V, ID = 3.0 A

• Drain to Source On-state Resistance RDS(on) 2.5 2.8 Ω VGS = 10 V, ID = 3.0 A

Input Capacitance Ciss 1000 pF VDS = 10 V,

Output Capacitance Coss 200 pF VGS = 0 V,


f = 1 MHz
Reverse Transfer Capacitance Crss 42 pF

Turn-on Delay Time td(on) 17 ns VDD = 150 V,

Rise Time tr 38 ns ID = 3.0 A,


VGS(on) = 10 V,
Turn-off Delay Time td(off) 57 ns
RG = 10 Ω, RL = 10 Ω
Fall Time tf 33 ns

Total Gate Charge QG 32 nC VDD = 450 V,

Gate to Source Charge QGS 5 nC VGS = 10 V,


ID = 6.0 A
Gate to Drain Charge QGD 20 nC
Body Diode Forward Voltage VF(S-D) 0.9 V IF = 6.0 A, VGS = 0 V

Reverse Recovery Time trr 1.9 µs IF = 6.0 A, VGS = 0 V,

Reverse Recovery Charge Qrr 9.0 µC di/dt = 50 A/µs

TEST CIRCUIT 1 AVALANCHE CAPABILITY TEST CIRCUIT 2 SWITCHING TIME

D.U.T.
D.U.T.
RG = 25 Ω L
RL VGS
PG VGS 90 %
50 Ω VDD 10 % VGS(on)
Wave Form 0
RG
VGS = 20 → 0 V PG. VDD
ID 90 %
90 %
IAS BVDSS ID
VGS 10 %
VDS ID 0 10 %
ID 0 Wave Form

VDD τ td(on) tr td(off) tf

τ = 1 µs ton toff
Starting Tch Duty Cycle ≤ 1 %

TEST CIRCUIT 3 GATE CHARGE

D.U.T.
IG = 2 mA RL

PG. 50 Ω VDD

2 Data Sheet D14203EJ2V0DS00

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2SK3324

TYPICAL CHARACTERISTICS (TA = 25 °C)

DERATING FACTOR OF FORWARD BIAS TOTAL POWER DISSIPATION vs.


SAFE OPERATING AREA CASE TEMPERATURE
140
dT - Percentage of Rated Power - %

PT - Total Power Dissipation - W


100 120

100
80
80
60
60
40
40

20 20

0 20 40 60 80 100 120 140 160 0 20 40 60 80 100 120 140 160


TC - Case Temperature - °C TC - Case Temperature - °C

FORWARD BIAS SAFE OPERATING AREA DRAIN CURRENT vs.


DRAIN TO SOURCE VOLTAGE
100 10
Pulsed

ID(pulse) P 8
ID - Drain Current - A
ID - Drain Current - A

W
=1
10 00
d µs
ite 1m
6
Lim s VGS = 10 V
n)
S(
o Po
we 10
RD m
r Di s 4
ss
1 ip
at
io
n
Li
m
ite 2
d
TC = 25˚C
Single Pulse
0.1
1 10 100 1000 0 4 8 12 16 20

VDS - Drain to Source Voltage - V VDS - Drain to Source Voltage - V

FORWARD TRANSFER CHARACTERISTICS


100

TA = 125˚C
75˚C
ID - Drain Current - A

10 25˚C
−25˚C

0.1

Pulsed
0.01
0 5 10 15
VGS - Gate to Source Voltage - V

Data Sheet D14203EJ2V0DS00 3

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2SK3324

TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH


1 000

rth(t) - Transient Thermal Resistance - ˚C/W


100
Rth(ch-A)= 41.7 ˚C

10

Rth(ch-C)= 1.04 ˚C
1

0.1

0.01
TC = 25˚C
Single Pulse
0.001
0.0001 0.001 0.01 0.1 1 10 100 1000

PW - Pulse Width - s

FORWARD TRANSFER ADMITTANCE vs. RDS(on) - Drain to Source On-state Resistance - Ω DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT GATE TO SOURCE VOLTAGE
100 8
Pulsed
| yfs | - Forward Transfer Admittance - S

6
10
TA = −25˚C
25˚C
75˚C 4
125˚C
ID = 6.0 A
1
2 3.0 A

VDS = 20 V
Pulsed
0.1
0.01 0.1 1.0 10 0 4 8 12
ID - Drain Current - A VGS - Gate to Source Voltage - V

DRAIN TO SOURCE ON-STATE GATE TO SOURCE CUT-OFF VOLTAGE vs.


RDS(on) - Drain to Source On-state Resistance - Ω

RESISTANCE vs. DRAIN CURRENT CHANNEL TEMPERATURE


VGS(off) - Gate to Source Cut-off Voltage - V

8 5
Pulsed
VGS = 10 V VDS = 10 V
ID = 1.0 mA
4
6

3
4
2

2
1

0 0
0.01 0.1 1 10 100 −50 0 50 100 150
ID - Drain Current - A Tch - Channel Temperature - ˚C

4 Data Sheet D14203EJ2V0DS00

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2SK3324

DRAIN TO SOURCE ON-STATE RESISTANCE vs. SOURCE TO DRAIN DIODE


RDS(on) - Drain to Source On-state Resistance - Ω
CHANNEL TEMPERATURE FORWARD VOLTAGE
6 100
Pulsed

ISD - Diode Forward Current - A


5

4 10

3
VGS = 10 V
2 1
0V
1
VGS = 10 V
ID = 3.0 A
0 0.1
−50 0 50 100 150 0 0.5 1 1.5
Tch - Channel Temperature - ˚C VSD - Source to Drain Voltage - V

CAPACITANCE vs. DRAIN TO


SOURCE VOLTAGE SWITCHING CHARACTERISTICS
10000 1000
VGS = 0 V
Ciss, Coss, Crss - Capacitance - pF

td(on), tr, td(off), tf - Switching Time - ns


f = 1 MHz

tr
Ciss
1000 100 tf
td(off)
td(on)
Coss
100 10

Crss VDD = 150 V


VGS = 10 V
RG = 10 Ω
10 1
0.1 1 10 100 0.1 1 10 100
VDS - Drain to Source Voltage - V ID - Drain Current - A

REVERSE RECOVERY TIME vs.


DRAIN CURRENT DYNAMIC INPUT/OUTPUT CHARACTERISTICS
10000 16
di/dt = 50 A / µ s ID = 6.0 A
VGS = 0 V
VDS - Drain to Source Voltage - V
trr - Reverse Recovery Time - ns

12
1000
VDD = 450 V
300 V
8 150 V

100
4

10
0.1 1 10 100 0 10 20 30 40
IF - Drain Current - A QG - Gate Charge - nC

Data Sheet D14203EJ2V0DS00 5

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2SK3324

SINGLE AVALANCHE ENERGY vs. SINGLE AVALANCHE ENERGY


INDUCTIVE LOAD DERATING FACTOR
100.0 100
VDD = 150 V
RG = 25 Ω
IAS - Single Avalanche Energy - A

VGS = 20 V → 0 V

Energy Derating Factor - %


80 IAS ≤ 6.0 A

10.0
IAS = 6.0 A 60
EAS
=2
1.6
mJ
40
1.0

20
VDD = 150 V
VGS = 20 V → 0 V
0.1 RG = 25 Ω 0
1.00E-04 1.00E-03 1.00E-02 1.00E-01 25 50 75 100 125 150
L - Inductive Load - H Starting Tch - Starting Channel Temperature - ˚C

6 Data Sheet D14203EJ2V0DS00

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2SK3324

PACKAGE DRAWING (Unit : mm)

TO-3P (MP-88) EQUIVALENT CIRCUIT

3.2±0.2 Drain
4.7 MAX.
15.7 MAX.
1.0 TYP.

4.5±0.2
1.5 TYP.
Body
Gate Diode

7.0 TYP.
4
20.5 MAX.

5.0 TYP.

18.7±0.4

1 2 3 Source
3.4 MAX.
19 MIN.

2.2±0.2 1.0±0.2 0.6±0.1 2.8±0.1

5.45 TYP. 5.45 TYP.


1: Gate
2: Drain
3: Source
4: Fin (Drain)

Remark Strong electric field, when exposed to this device, cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as
possible, and quickly dissipate it once, when it has occurred.

Data Sheet D14203EJ2V0DS00 7

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2SK3324

• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
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The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8

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