Reg. No.

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY CYCLE TEST – I Feb-2019
CYCLE TEST – I Feb-2019 VI Semester – Electronics& Communication Engineering
VI Semester – Electronics& Communication Engineering 15EC327E – ASIC Design
15EC327E – ASIC Design Duration: 45 Mins Max. Marks: 25
Duration: 45 Mins Max. Marks: 25 PART – A (5 X 1 = 5 Marks)
PART – A (5 X 1 = 5 Marks) Answer ALL Questions
Answer ALL Questions
1. Design cost comes under which category
1. Design cost comes under which category a.Variable cost b. Fixed cost c. Low cost d. High cost
a.Variable cost b. Fixed cost c. Low cost d. High cost 2. AOI221 CMOS logic cell has how many transistor
2. AOI221 CMOS logic cell has how many transistor a. 10 b.12 c.14 d.8
a. 10 b.12 c.14 d.8 3. Which design style has the shortest manufacturing lead time
3. Which design style has the shortest manufacturing lead time a.Full custom b. Standard Cell c. Gate array d. FPGA
a.Full custom b. Standard Cell c. Gate array d. FPGA 4. Advantage of PT when compared to TG
4. Advantage of PT when compared to TG a)less no. of Transistor b)Faster c)Easy to design d)passes
a)less no. of Transistor b)Faster c)Easy to design d)passes good 0 & 1
good 0 & 1 5. PMOS acts as ………….device
5. PMOS acts as ………….device a)Pull up b)pull down c)pull back d)pull side
a)Pull up b)pull down c)pull back d)pull side
PART – B (2 X 4 = 8 Marks)
PART – B (2 X 4 = 8 Marks) Answer ANY TWO questions
Answer ANY TWO questions
6. Sketch the schematic of a OAI321 and AOI22 gate.
6. Sketch the schematic of a OAI321 and AOI22 gate. 7. Realize 2:1 MUX and 2 i/p NOR using transmission gate.
7. Realize 2:1 MUX and 2 i/p NOR using transmission gate. 8. Write the steps involved in CMOS fabrication process.
8. Write the steps involved in CMOS fabrication process.
PART – C (1 X 12 = 12 Marks)
PART – C (1 X 12 = 12 Marks) Answer ALL questions
Answer ALL questions
9. a. Explain the various steps involved in ASIC design flow
9. a. Explain the various steps involved in ASIC design flow OR
OR b. Implement sequential logic cells using Transmission gates
b. Implement sequential logic cells using Transmission gates

Reg. No.