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The document contains questions matching various computer architecture concepts with their definitions or examples. It covers topics like CPU registers, addressing modes, instruction types, assembly directives, stack operations and more. The questions are multiple choice with one right answer out of the given options for each question.
The document contains questions matching various computer architecture concepts with their definitions or examples. It covers topics like CPU registers, addressing modes, instruction types, assembly directives, stack operations and more. The questions are multiple choice with one right answer out of the given options for each question.
The document contains questions matching various computer architecture concepts with their definitions or examples. It covers topics like CPU registers, addressing modes, instruction types, assembly directives, stack operations and more. The questions are multiple choice with one right answer out of the given options for each question.
2. Immediate of the operand b. Register specifies the address 3. Register c. Specified in the register 4. Register Indirect definition of instruction d. Specified implicitly in the 5. Processing unit e Timing and Control 6. Instruction unit f. General purpose Register 7. Storage and Interface unit g. ALU 8. TCON h. contains status information 9. SBUF i. timer / counter control register. 10. TMOD j. idle bit, power down bit 11. PSW k. serial data buffer for Tx and Rx. 12. PCON l. timer/ counter modes of operation.
Ans. 1. D , 2. C , 3. A , 4. B, 5. G , 6. E , 7. F , 8. I , 9. k , 10. L , 11. H , 12. J
13. Register file, a. 232 byte
14. I/O Ports b. five 8bit 15. architecture c. register to register 16. INTR d. Non-maskable 17. RST 5.5 e. Maskable 18. TRAP f. Software 19. RST 1 g. Non-vectored
Ans. 12. J,13. A, 14. B, 15. C, 16 G, 17. E,18. F ,19. G
20. MOvSB/SW a.loads AL/AX register by content of a string
21. CMPS b. moves a string of bytes stored in source to destination 22. SCAS c. compares two strings of bytes or words whose length is stored in CX register 23. LODS d. scans a string of bytes or words 24. Hardware triggered strobe e. Mode 3 25. Software triggered strobe f. Mode 5 26. Square wave mode g. Mode 4
Ans. 20.B,21. C, 22. D,23. A,24. F,25. G, 26. E
27. Decoder a. 1 line to 2n lines
28. Multiplexer b. n lines to 2n lines 29. De multiplexer c. 2n lines to 1 line
30. Interrupts which can be delayed when a much highest a. Exception
31. Unplanned interrupts which occur while executing b. Synchronous a program 32. Source of interrupt is in phase with the system clock c. Maskable
33. Operation code field a.1 byte
34. one-byte instruction b. machine language instruction 35. register to register’ has a length c. another memory location 36. R/M field in a machine instruction d. 2 bytes
37. S-bit a. Z-bit
38. ‘REP’ b. sign extension bit 39. JUMP” belongs c. immediate 40. MOV AX, 0005H d. control transfer & branch instructions
41. MOV AX, 1234H a. direct addressing mode
42. MOV AX, [2500H] b. immediate addressing mode 43. MOV AX,[BX] c. register indirect addressing mode 44. MOV AX, 0005H d. control transfer & branch instructions
45. machine language instruction a. Operation code field
46. 1 byte b. one-byte instruction 47. 2 bytes c. register to register’ has a length 48. another memory location d. R/M field in a machine instruction
49. sign extension bit a. S-bit
50. Z-bit b. ‘REP’ 51. control transfer & branch instructions c. JUMP” 52. immediate d. MOV AX, 0005H
53. immediate addressing mode a. MOV AX, 1234H
54. direct addressing mode b. MOV AX, [2500H] 55. register indirect addressing mode c. MOV AX,[BX]
56. unconditional branch instructions a. intersegment direct mode
57. JMP 5000H:2000H b.intrasegment indirect addressing mode 58. data copy/transfer instruction c.The translate 59. XLAT d. PUSH
60. loads the AH register a. PUSHF
61. pushes the flag register b. LAHF 62. loads the flag register c. ADC 63. addition d. PUSH 64. The translate a. XLAT 65. PUSH b. data copy/transfer instruction 66. intersegment direct mode c. JMP 5000H:2000H 67. unconditional branch instructions d. intrasegment indirect addressing mode
68. PUSHF a. pushes the flag register
69. POPF b. ‘loads the flag register 70. ADC c. addition 71. immediate d. MOV AX, 0005H
72. INC a. DEC
73. subtracts 1 b. SBB 74. subtraction with borrow c. carry flag 75. Borrow flag d. adds 1
76. AAM a. mnemonic
77. AAA b. decimal adjust accumulator 78. DAA c. Rotate Right without carry 79. ROR d. unpacked decimal digits
80. adds 1 a. INC
81. subtracts 1 b. DEC 82. subtraction with borrow c. SBB 83. carry flag d. Borrow flag
84. unpacked decimal digits a. AAM
85. mnemonic b. AAA 86. decimal adjust accumulator c. DAA 87. ROR instruction d. Rotate Right without carry
88. MOvSB/SW a. loads AL/AX register by content of a string
89. CMPS b. moves a string of bytes stored in source to destination 90. SCAS c. compares two strings of bytes or words whose length is stored in CX register 91. LODS d. scans a string of bytes or words
92. out of ‘halt’ state a. Delay
93. NOP b. Clear Carry Flag. 94. CLC c. Rotate Right without carry 95. ROR d. Hold
96. DB a. used to direct the assembler to reserve only 10-bytes
97. DT b. used to direct the assembler to reserve only 4 words 98. DW c. used to direct the assembler to reserve byte or bytes 99. DQ d. used to direct the assembler to reserve words
100. end of an assembly language a. ENDS
101. end of a logical segment b.start the memory allotment for a particular segment. 102. ORG c. SEGMENT 103. starting of the logical segment d. END
104. Delay a. NOP
105. Hold b. out of ‘halt’ state 106. Clear Carry Flag. c. CAA 107. carry flag d. Borrow flag
108. END a. end of an assembly language
109. ENDS b. end of a logical segment 110. start the memory allotment for a particular segment c.ORG 111. SEGMENT d. Rotate Right without carry
112. immediate addressing mode a. MOV AX, 1234H
113. direct addressing mode b. MOV AX, [2500H] 114. register indirect addressing mode c. MOV AX,[BX]
115. coded object modules a. .ASM
116. extension for assembly level program b. debugging and trouble shooting 117. DEBUG.COM c. last-in-first-out 118. Stack d. .OBJ file
119. stack pointer register a. base address of the stack segment
120. stack segment register b. decrements SP 121. PUSH operation c. increments SP 122. POP operation d. offset of address of stack segment
123. offset of address of stack segment a. stack pointer register
124. stack segment register b. base address of the stack segment 125. decrements SP c. PUSH operation 126. increments SP d. POP operation
127. .ASM a. extension for assembly level program
128. .OBJ file b. coded object modules 129. debugging and trouble shooting c. DEBUG.COM 130. Stack d. last-in-first-out 131. Register file, a.232 byte, 132. I/O Ports b. five 8bit 133. architecture c. register to register
134. INTR a. Non-maskable
135. RST 5.5 b. Maskable 136. TRAP c. Software 137. RST 1 d. Non-vectored
138. MOvSB/SW a.loads AL/AX register by content of a string
139. CMPS b. moves a string of bytes stored in source to destination 140. SCAS c. compares two strings of bytes or words whose length is stored in CX register 141. LODS d. scans a string of bytes or words
142. Hardware triggered strobe a. Mode 3
143. Software triggered strobe b. Mode 5 144. Square wave mode c. Mode 4
145. Decoder a. 1 line to 2n lines
146. Multiplexer b. n lines to 2n lines 147. De multiplexer c. 2n lines to 1 line
148. machine language instruction a. Operation code field
149. 1 byte b. one-byte instruction 150. 2 bytes c. register to register’ has a length 151. another memory location d. R/M field in a machine instruction
152. sign extension bit a. S-bit
153. Z-bit b. ‘REP’ 154. control transfer & branch instructions c. JUMP” 155. immediate d. MOV AX, 0005H
156. immediate addressing mode a. MOV AX, 1234H
157. direct addressing mode b. MOV AX, [2500H] 158. register indirect addressing mode c. MOV AX,[BX]
159. unconditional branch instructions a. intersegment direct mode
160. JMP 5000H:2000H b. intrasegment indirect addressing mode 161. data copy/transfer instruction c. The translate 162. XLAT d. PUSH 163. loads the AH register a. PUSHF 164. pushes the flag register b. LAHF 165. loads the flag register c. ADC 166. addition d. PUSH
167. The translate a. XLAT
168. PUSH b. data copy/transfer instruction 169. intersegment direct mode c. JMP 5000H:2000H 170. unconditional branch instructions d. intrasegment indirect addressing mode
171. PUSHF a. pushes the flag register
172. POPF b. ‘loads the flag register 173. ADC c. addition 174. immediate d. MOV AX, 0005H
175. INC a. DEC
176. subtracts 1 b. SBB 177. subtraction with borrow c. carry flag 178. Borrow flag d. adds 1
179. AAM a. mnemonic
180. AAA b. decimal adjust accumulator 181. DAA c. Rotate Right without carry 182. ROR d. unpacked decimal digits
183. adds 1 a. INC
184. subtracts 1 b. DEC 185. subtraction with borrow c. SBB 186. carry flag d. Borrow flag
187. NMI a. external interrupt
188. INTR interrupt b. nonmaskable interrupt 189. Programmable interrupt controller c. handle one or more interrupt requests at a time 190. outside the processor d. maskable
191. execution of an interrupt instruction a. TRAP
192. external interrupt b. internal interrupt 193. internal interrupt c. divide by zero interrupt 194. independent of IF flag d. keyboard interrupt 195. highest priority interrupt a.defining a macro 196. INTR signal can be masked b. NMI 197. Procedures c. subroutines 198. The process of assigning a label d. INTERRUPT flag
199. nonmaskable interrupt a. NMI
200. maskable b. INTR interrupt 201. handle one or more interrupt requests at a time c. Programmable interrupt controller 202. external interrupt d. outside the processor
203. internal interrupt a. execution of an interrupt instruction
204. keyboard interrupt b. external interrupt 205. divide by zero interrupt c. internal interrupt 206. TRAP d. independent of IF flag
207. NMI a. highest priority interrupt
208. INTERRUPT flag b. INTR signal can be masked 209. subroutines c. Procedures 210. defining a macro d. The process of assigning a label
211. A macro within a macro a. MACRO
212. A macro can be used b. nested macro 213. end of a macro c. ENDM 214. beginning of the macro d. to represent directives
215. Memory refresh activity a. 8-bit input port
216. output device b. initialised by refresh mechanism 217. IOWR c. write operation on output data 218. The chip 74LS245 d. CRT display
219. Port C of 8255 a. digitally controlled gains
220. I/O mode, the 8255 ports b. either input or output ports 221. BSR mode c. set and reset individual ports 222. DAC d. programmable I/O ports
223. to represent directives a. A macro can be used
224. nested macro b. A macro within a macro 225. ENDM c. end of a macro 226. MACRO d. Beginning of the macro
227. CRT display a. output device
228. MACRO b. Memory refresh activity 229. write operation on output data c. IOWR 230. TRAP d. independent of IF flag
231. loads the AH register a. PUSHF
232. pushes the flag register b. LAHF 233. loads the flag register c. ADC 234. addition d. PUSH
235. The translate a. XLAT
236. PUSH b. data copy/transfer instruction 237. intersegment direct mode c. JMP 5000H:2000H 238. unconditional branch instructions d. intrasegment indirect addressing mode
239. PUSHF a. pushes the flag register
240. POPF b. ‘loads the flag register 241. ADC c. addition 242. immediate d. MOV AX, 0005H
243. INC a. DEC
244. subtracts 1 b. SBB 245. subtraction with borrow c. carry flag 246. Borrow flag d. adds 1
247. AAM a. mnemonic
248. AAA b. decimal adjust accumulator 249. DAA c. Rotate Right without carry 250. ROR d. unpacked decimal digits Answers 1. D 41. b 81. b 121. b 2. C 42. a 82. c 122. c 3. A 43. d 83. d 123. a 4. B 44. c 84. a 124. b 5. C 45. a 85. b 125. c 6. A 46. b 86. c 126. d 7. B 47. c 87. d 127. a 8. B 48. d 88. b 128. b 9. D 49. a 89. c 129. c 10. E 50. b 90. d 130. d 11. A 51. c 91. a 131. A 12. C 52. d 92. d 132. B 13. A 53. a 93. a 133. C 14. B 54. b 94. b 134. D 15. C 55. c 95. c 135. B 16. D 56. b 96. c 136. A 17. B 57. a 97. a 137. C 18. A 58. d 98. d 138. B 19. C 59. c 99. b 139. C 20. B 60. b 100. d 140. D 21. C 61. a 101. a 141. A 22. D 62. d 102. b 142. B 23. A 63. c 103. c 143. C 24. B 64. a 104. a 144. A 25. C 65. b 105. b 145. B 26. A 66. c 106. c 146. C 27. B 67. d 107. d 147. A 28. C 68. a 108. a 148. a 29. A 69. b 109. b 149. b 30. C 70. c 110. c 150. c 31. A 71. d 111. d 151. d 32. B 72. d 112. a 152. a 33. b 73. a 113. b 153. b 34. a 74. b 114. c 154. c 35. d 75. c 115. d 155. d 36. c 76. d 116. a 156. a 37. b 77. a 117. b 157. b 38. a 78. b 118. c 158. c 39. d 79. c 119. d 159. b 40. c 80. a 120. a 160. a 161. d 184. b 207. a 230. d 162. c 185. c 208. b 231. b 163. b 186. d 209. c 232. a 164. a 187. b 210. d 233. d 165. d 188. d 211. b 234. c 166. c 189. c 212. d 235. a 167. a 190. a 213. c 236. b 168. b 191. b 214. a 237. c 169. c 192. d 215. b 238. d 170. d 193. c 216. d 239. a 171. a 194. a 217. c 240. b 172. b 195. b 218. a 241. c 173. c 196. d 219. b 242. d 174. d 197. c 220. d 243. d 175. d 198. a 221. c 244. a 176. a 199. a 222. a 245. b 177. b 200. b 223. a 246. c 178. c 201. c 224. b 247. d 179. d 202. d 225. c 248. a 180. a 203. a 226. d 249. b 181. b 204. b 227. a 250. c 182. c 205. c 228. b 183. a 206. d 229. c