Microelectronic Engineering 83 (2006) 1023–1029

www.elsevier.com/locate/mee

q,qq
The limits of CD metrology
a,*
Bryan J. Rice , Heidi Cao a, Michael Grumski b, Jeanette Roberts a

a
Intel Corporation, Hillsboro, OR 97124, USA
b
Intel Corporation, Chandler, AZ 85226, USA

Available online 3 March 2006

Abstract

One of the many technology decisions facing the semiconductor industry for the 32 nm node (and beyond) is the selection of the best
critical dimension (CD) metrology equipment to meet the needs of process equipment suppliers and semiconductor manufacturers. Over
the past three years Intel has fabricated a variety of test structures and performed a number of technology evaluations aimed at deter-
mining the limits of today’s CD metrology. In this paper, we discuss the capability of those technologies to measure structures having
dimensions representative of the 45, 32, and 22 nm node.
 2006 Elsevier B.V. All rights reserved.

Keywords: CD SEM; Scatterometry; AFM; Dual beam; HV SEM

1. Introduction words, Intel needs CD metro solutions for the 32 nm node

With the semiconductor industry hard at work on devel-
oping 45 nm process technology, metrologists have begun
to worry about the readiness of critical dimension (CD)
metrology manufacturing solutions for the 32 nm node
and beyond.
From Intel’s point of view, the timing for 32 nm node
CD metrology is a simple matter. Our semiconductor road-
map is two years per technology generation and we have
strictly adhered to it for many process technologies. Since
we are selling parts from the 65 nm generation for the first
time in 2005, we expect to sell parts from the 45 nm in 2007
and similarly 32 nm parts will be sold in 2009. One critical
observation, however, is that Intel begins research for any
given technology generation four years in advance. In other
q
Reprinted with permission from ‘‘The limits of CD metrology’’ by
Bryan J. Rice, Heidi Cao, Michael Grumski, and Jeanette Roberts, pp.
379–385, from the AIP Conference Proceedings 788 Characterization and
Metrology for ULSI Technology, 2005.
qq
Portions of this work have previously appeared in Proceedings of
SPIE 5375 (2004), Refs. [2, 3].
*
Corresponding author.
E-mail address: bryan.j.rice@intel.com (B.J. Rice).
in 2005 and 22 nm node solutions in 2007.
On the technology capability side, the first question is
whether the top down or ‘‘CD’’ scanning electron micro-
scope (SEM) will continue to be capable of producing the
reliable and repeatable metrology information that the
semiconductor industry has used as a workhorse for more
than a decade. If the answer to this question is anything but
‘‘yes’’ then there are natural follow-up questions about
what CD SEM suppliers are doing to close the gaps and
what alternative technologies are available or being devel-
oped to replace CD SEM.
The difficulty with any discussion of scalability and gap
identification is going from the whiteboard to the lab.
When we first asked this question in 2002, the 90 nm tech-
nology process was still being developed and we were strug-
gling with how to create features that could probe 32 nm
node capability. We quickly determined that the farthest
we could push our patterning capabilities at that time
was to create features that fell between the 65 and 45 nm
nodes. We proceeded to evaluate CD metrology technolo-
gies using these features sizes, but rather than ‘‘wait’’ for
Intel’s process technology to become capable of hitting
32 nm node targets, we explored alternative solutions for
obtaining very small features.

0167-9317/$ - see front matter  2006 Elsevier B.V. All rights reserved.
doi:10.1016/j.mee.2006.01.267
1024 B.J. Rice et al. / Microelectronic Engineering 83 (2006) 1023–1029
One technology that was capable of producing 32 nm
node features sizes in late 2002 was e-beam lithography.
Intel Corporation contracted with Lawrence Berkeley
National Laboratory’s Center for X-ray Optics (CXRO)
to create a variety of very small and/or dense line/space
structures as well as very small contact holes using their
e-beam writer. After creating these wafers we offered them
to several metrology suppliers to perform evaluations.
Technologies that were evaluated include CD SEM, scatte-
rometry, atomic force microscopy (AFM), dual beam
(DIB), and high voltage CD SEM (HVSEM). These studies
were not product evaluations in the traditional sense, but
were instead aimed at determining if the technologies in
question were either capable at or scalable to the 32 nm
node and beyond. As such, much of the work in the
remainder of this paper is qualitative in nature.
2. Experimental design and methodology
Since our study was aimed ultimately at determining
technology capability for the 32 nm node, we attempted
to pattern features at or beyond the ITRS roadmap targets
for the 32 nm node. These targets are isolated lines in the
range of 10–15 nm, nested line/space features as small as
35 nm 1:1, and contact holes as small as 35 nm.
We collaborated with Berkeley’s CXRO lab to fabricate
features approaching these limits using the Nanowriter, a
100 keV e-beam writer. We were able to achieve isolated
lines of 16 nm, nested lines with 36 nm 1:1, and contacts
as small as 45 nm. Feature targets sizes and the achieved
values are listed in Table 1. The achieved CD’s were
obtained using analytical CD SEM. These measurements
are meant to indicate (qualitatively) the CD’s obtained
with the CDRO process. Both resist and etched features
were produced. In the case of lines, the ‘‘resist’’ used was
hydrogen silsesquioxane (HSQ), a spin-on-glass e-beam
resist. The substrate used for the line/space wafers was sil-
icon. For the contact wafers, ZEP resist, a high resolution
positive tone e-beam resist, was used on an HSQ substrate.
The various stacks are shown in Fig. 1. Note that due to
various processing limitations, 4 in. wafers were used.
For a variety of reasons, some of the technologies that we
evaluated were not able to make measurements of the CXRO
wafers. Specifically, for the AFM and DIB technologies we
utilized a set of wafers fabricated with 193 nm lithography
to pattern 45 nm node feature sizes. These wafers consisted
of 12 in. silicon nitride, polycrystalline silicon, and silicon
dioxide substrates and included patterning done both in
resist on these substrates and patterns etched into the sub-
Table 1
Table of achieved feature sizes using the LBNL CXRO process
Feature type Target (nm) Achieved (nm)
Nested lines 35 36
Isolated lines 10–15 16
Contact holes 35 45
Line/Space
110 HSQ
Silicon (4” 110 Si
wafer) Silicon (4”
Resist Lines (HSQ used Etched Silicon
as ebeam-resist)
Contact hole
110 ZEP
100 nm HSQ 100 HSQ
Silicon (4” Silicon (4”
Resist Lines (ZEP Etched
ebeam-resist)
Fig. 1. The process used to create the CXRO wafers.
strates themselves. The feature sizes included 180 nm L/S
pitch, 45 nm isolated lines, and 90 nm contact holes.
In the case of the HVSEM evaluation we were forced to
perform a very specialized experiment. The details are
described in Ref. [2] and in the next section, but briefly
our study of HVSEM involved irradiating fully integrated
(transistor plus full interconnect metallization) Intel Pen-
tium four die fabricated using Intel’s 130 nm node process.
3. Technology evaluations
The CXRO wafers were distributed to a number of
metrology suppliers across a variety of technologies. In
some cases, the wafer size (4 in. substrates) either precluded
collection of data, or resulted in collecting data that was
not representative of the capability of the technology in
question. For those technologies that were unable to pro-
vide any results on the CXRO wafers we include results
from other evaluation wafers generated with 45 nm node
features (dual beam, AFM) or 130 nm node features
(HVSEM).
3.1. Evaluation of CD SEM technology
The first results we show are from top down CD SEM’s.
Figs. 2–5 show images obtained from various CD SEM
suppliers for line/space and contact/hole features, both
patterned in resist and etched into substrates. The line/
space images show a spectrum of capability, but demon-
strate the clear ability of CD SEM to resolve the edges of
the smallest lines we made. It is worth mentioning that
issues such as resist shrinkage/swelling, charging, and
image bias that are present in today’s SEM’s remain when
imaging 32 nm node features.
Despite the indications of CD SEM capability for imag-
Pitch ing at the 32 nm node, continuous improvement will be
1:1, 1:3 required to meet all of the manufacturing requirements.
1:10 However, today’s CD SEM’s are currently being used in
1:1, 1:2
32 nm node research.
 B.J. Rice et al. / Microelectronic Engineering 83 (2006) 1023–1029 1025

Fig. 5. Etched contact holes, nominally 45 nm on a 1:1 pitch. The quality

of these images is quite good.

3.2. Evaluation of scatterometry technology

The next technology that we investigated was scatterom-

Fig. 2. Resist line/space features. Nominal 16 nm lines on a 176 nm pitch
are shown. Measured values were typically in the range of 25–30 nm,
highlighting a significant bias issue. Note that both edges are clearly
defined in some of the images, indicating the inherent capability of CD
SEM at this technology node.
etry. One of the biggest difficulties in reporting results from
this portion of our study is how to demonstrate the fidelity
of the measurements made by the scatterometry tools. In
general, the line/space patterns were modeled by all suppli-
ers using a rectangular shape. Scatterometry was able to
produce repeatable measurements of CD’s all the way
down to the very smallest features we printed (see Fig. 6).
The correlation of the scatterometry values to analogous
CD SEM measurements is shown in Fig. 7. The R2 of the
fit shows that the scatterometry values are well correlated
with CD SEM results all the way down to 20 nm. The
microstructure of the curves in Fig. 7 results from using a
number of different chrome sizes and doses to cover a large

Resist Bottom CD
OC D R e s is t B C D (nm)

60.0
50.0 Supplier A
40.0 Supplier B
30.0
20.0
Fig. 3. Etched line/space features. Nominal 16 nm on a 176 pitch are 10.0
shown.
0.0
0 10 20 30 40 50
Drawn CD (nm)

Etched Si Bottom CD
OC D Etc he d Si B C D (nm)

60.0
50.0 Supplier X
40.0 Supplier Y
30.0
20.0
10.0
0.0
Fig. 4. Resist contact holes, nominally 45 nm on a 1:1 pitch. The CD 0 10 20 30 40 50
SEM results demonstrate processing issues for the contact lithography Drawn CD (nm)
process employed in this study. While this is not surprising given the
laboratory nature of the process, the key result is that the quality of the Fig. 6. Scatterometry CD results down to 20 nm. Measurements shown
images is sufficient to identify processing issues. are for the bottom CD.
1026 B.J. Rice et al. / Microelectronic Engineering 83 (2006) 1023–1029
Fig. 7. CD SEM vs. scatterometry correlation.
range of CD’s. Process bias accounts for some of the local
non-linearity in this curve.
Another interesting result is the sensitivity of the spec-
tral data to small variations in CD and sidewall angle.
The sensitivity to CD is shown in Fig. 8. Although there
is clearly some sensitivity even to CD changes of 2 nm
down to CD’s as small as 19 nm, the observed sensitivity
is decreasing with CD. The extensibility of scatterometry
beyond the 32 nm node will require improvement in this
sensitivity to small CD changes for CD < 20 nm.
Fig. 9 shows the results of a simulation of sidewall angle
variation from 68 to 78. While this plot shows some sen-
sitivity to sidewall angle variation in simulation, this was
not demonstrated when attempting to extract profiles from
Fig. 8. The figure shows spectral coefficients (actual data) from measure-
ments of small isolated lines. Sensitivity to small variations in CD is
diminishing as the CD shrinks.
Fig. 9. Spectral coefficients (simulated) for various sidewall angles (from
68 to 78).
the smallest etched features. For those suppliers who
allowed the sidewall angle to vary, the best fits were vertical
sidewalls. In the case of the resist samples, the determina-
tion of straight sidewall profiles is accurate. For the etched
features, however, cross-sections indicate that the sidewall
angle is NOT vertical. It is useful to note that although
the nominal height of the etched silicon features was
100 nm, for the smallest isolated features the silicon height
was closer to 30 nm. One possibility is that the reduction in
feature volume causes a reduction in signal to noise, mak-
ing it difficult for the scatterometry models to distinguish
between profiles with differing sidewall angle. It is clear
that improvement in profile determination will be necessary
for this technology to be successful at the 32 nm node.
These improvements are currently being investigated at
Intel where we are employing scatterometry in 32 nm node
research.
3.3. Evaluation of AFM technology
Another technology that has garnered interest for CD
metrology in recent years is atomic force microscopy. We
evaluated AFM using 45 nm node samples described above
and had mixed results. While this technology is highly
accurate and capable of providing true 3D information
about isolated, non-reentrant lines of any size, it is limited
in its applicability for space and hole measurements. One
key requirement for many applications, however, is the
ability to measure a reentrant or ‘‘undercut’’ profile. In this
case a shaped tip is required to accurately determine the
profile. The main issue, in this case, is the size of the tip.
Current tip technology employs etched silicon tips
whose size is limited to 50 nm. During the approach of
the tip to a feature being measured, the tip interacts with
the surface. In the case of narrow space structures (tight
pitch trenches and small holes), the tip can sometimes
‘‘stick’’ to the sidewall. When the tip is retracted it flexes.
If there is insufficient room for this extra flexing, the tip
can touch the opposite side of the trench or hole before
detaching from the surface (see Fig. 10). This creates a
requirement for an extra tip retraction distance of 15–
30 nm above and beyond the actual tip size. The resulting
tip size plus retraction distance determines the ultimate
space and hole resolution of today’s AFM’s. Since the
trench sizes for the 45 nm node are around 50 nm, AFM’s
using traditional tips are not capable for the 45 and 32 nm
nodes.
Carbon nanotube (CNT) probes offer the promise of pro-
viding extremely small (10 nm or smaller) tip sizes for
AFM manufacturers. A major challenge for implementing
CNT probes is determining how to compensate for the inher-
ent flexibility of the tip. One solution [4] is to alter the method
of approach when using CNT’s to follow a ‘‘step-in’’
method. Step-in involves approaching the sample, retracting
from the sample, translating, then repeating. In this mode the
lateral interaction forces are significantly reduced as the tip
translation occurs with the probe is far from the sample.
 B.J. Rice et al. / Microelectronic Engineering 83 (2006) 1023–1029
Fig. 10. Examples of traces showing an AFM tip unable to measure a small trench.
For isolated structures and for non-reentrant space
structures, AFM offers a highly accurate 3D profiling capa-
bility. However, AFM is not capable of measuring reen-
trant structures with features sizes at the 45 nm node and
beyond at this time.
3.4. Evaluation of dual incident beam technology
The concept of using a focused ion beam (FIB) to obtain
profile information of semiconductor features is not new.
The combination of FIB technology and CD SEM, known
as dual beam, is a somewhat newer offering, but has been
in use in laboratory settings for a few years. Using a dual
beam tool in a fab environment has been much less prevalent.
Dual beam technology offers an opportunity to obtain
CD SEM quality images of cross-sectioned features. The
term ‘‘dual beam’’ refers to combining a focused ion beam
with a traditional SEM inside the same platform. Typi-
cally, samples are prepared with a metallic coating in a
small area surrounding the target feature. Fig. 11 shows
a resist feature (left) and etched polysilicon feature (right)
that have been coated with metal, sliced with a Ga ion
beam, and imaged at a 45 angle with an SEM.
As process technologies advance, the need for reliable
and rapid 3D information has increased. An ‘‘in-fab’’
cross-section tool that operates on full wafers, provides
Fig. 11. Resist and etched features imaged with a dual beam tool. The
features have been coated with a metallic layer. The left image shows a
resist feature whose edges appear indistinct. The right image shows a well-
resolved etched poly line.
1027
cross-section data without the need for time-consuming
sample preparation, and which can perform additional dec-
oration operations in situ, is therefore highly desirable.
Unfortunately, the dual beam technology is not without
its downsides: the technique is destructive; the ion beam
of choice is gallium which can cause transistor damage;
the imaging generally takes place at an angle, so CD’s must
be angle corrected; and the technique has particular trouble
imaging resist features (see Fig. 11). At the present time the
dual beam technology is not well suited for CD metrology.
It does offer interesting prospects for rapid cross-sectioning
in the fab environment, however. These possibilities are
currently being studied at Intel where we are employing
dual beam technology in our 32 nm node research.
3.5. Evaluation of high voltage SEM technology
Finally, we turn to a ‘‘new’’ technology possibility.
Today’s top down CD SEM’s use secondary electrons
(SE’s) to image features. It has been suggested [1] that
using a high voltage column (>30 keV) and imaging with
backscattered electrons instead of secondaries could both
improve resolution and decrease surface damage relative
to lower energy SE SEM’s. One concern is that the high
energy electrons may cause damage to transistors if the
technique is employed in active areas. Intel has performed
a study of this [2] and the results are quite interesting.
Our experiment was performed in collaboration with
Hitachi High Technologies (HHT) who provided access
to a high voltage SEM with 200 keV column potentials
and 200 mm stage capability. Since the tool in question
was not in a sufficiently clean facility to allow irradiated
wafers back into the fabrication line, the decision was made
to test only fully functional devices that had been com-
pletely fabricated. We took several fully processed wafers
(made using our 130 nm technology) with fully functional
PentiumTM four processors and performed a suite of electri-
cal tests on a large number of devices. We then irradiated
these devices with a variety of electron beam currents, land-
ing energies, and doses, and repeated the electrical testing
to enable before–after comparisons.
1028 B.J. Rice et al. / Microelectronic Engineering 83 (2006) 1023–1029

“On” “Drive”
1.5
NMOS Drain "On" Current (% Change)

NMOS Drain "Drive" Current (% Change)

.01 .05 .10 .25 .50 .75 .90 .95 .99 .01 .05 .10 .25 .50 .75 .90 .95 Irradiated
.99
Irradiated
1
1

0.5
NMOS

0.5

Control Control
0
0

-0.5 -0.5

Control Irradiated -3 -2 -1 0 1 2 3 Control Irradiated -3 -2 -1 0 1 2 3

Normal Quantile Normal Quantile

Treatment Treatment

1 1

PMOS Drain "Drive" Current (% Change)

PMOS Drain "On" Current (% Change)

.01 .05 .10 .25 .50 .75 .90 .95 Control

.99 .01 .05 .10 .25 .50 .75 .90 .95 .99
0 Control
Irradiated 0
-1 Irradiated

-2 -1
-3 -2
PMOS

-4
-5 -3

-6 -4
-7
-5
-8
-9 -6
Control Irradiated -3 -2 -1 0 1 2 3 Control Irradiated -3 -2 -1 0 1 2 3

Normal Quantile Normal Quantile

Treatment Treatment

Fig. 12. Drain current normal quantile plots. The control data (h) show a tight distribution around 0% deviation, while in all cases the irradiated set (+,
·, and *) shows a huge variation. PMOS drain currents are significantly degraded, sometimes by as much as 9%. Even the lowest doses show at least a 1%
change in drain current, indicating that every irradiated device has been altered.

The quantity of data analyzed is too large to discuss in sion we are forced to draw is that, in its present form, the
detail in the present work. The results of drive and ‘‘on’’ HV SEM is not attractive as a CD metrology technology.
state current measurements are indicative of the entire data
set, however, and are shown in Fig. 12. The ‘‘on’’ current 4. Summary and conclusions
corresponds to measurements of the drain current with
the drain voltage near zero and the gate voltage at nominal. In this work we have attempted to identify CD metrology
The ‘‘drive’’ current corresponds to measurement of the gaps for the 32 nm node (and beyond) by fabricating for-
drain current with the gate and drain held at the nominal ward-looking samples and making them available to metrol-
voltage. The data in the plot correspond to the difference ogy suppliers. We evaluated five separate technologies: CD
between measurements ‘‘after’’ irradiation minus ‘‘before’’ SEM, scatterometry, AFM, dual beam, and HV SEM.
irradiation divided by the ‘‘before’’ values (with the final Our findings indicate that both CD SEM and scatterometry
quantity specified in %). The control set corresponds to are technologies that are capable of measuring CD’s at the
die that saw no high voltage irradiations, while the ‘‘irradi- 32 nm node, although both technologies will require contin-
ated’’ set saw a variety of currents (5, 10, and 20 lA) and uous improvement in the coming years to meet all of the
landing energies (50, 100, and 200 keV). Note that all of manufacturing requirements imposed by that technology
the irradiated data are presented in a single distribution. generation. AFM technology offers excellent 3D informa-
For a more detailed breakdown by parameter please see tion about isolated line structures, but is currently not capa-
Ref. [2]. ble of measuring trench or hole structures for the 45 nm
The stark difference between the control and irradiated node. A breakthrough in tip technology is required for this
distributions for the data sets presented in Fig. 12 show technology to become a viable option for CD metrology at
clearly that transistors subjected to HV irradiation are these nodes. The dual beam technology is attractive as a
being altered. The fact that the device is changing is suffi- high-throughput, in-fab alternative to traditional analytical
cient to cause deep concern to the silicon integrator. Any cross-section SEM, but is not presently suitable as an in-fab
noticeable change in performance is an indication that the CD metrology solution. Finally, HV SEM employing back-
device is no longer working properly, and even though the scattered or primary electrons to image wafer features
device is still functional this information leads to the inevi- causes damage to transistor devices if it is used in active
table conclusion that the part is at risk for a catastrophic areas. This precludes the use of HV SEM in its present form.
failure at some point in the future. This type of reliability
failure mode is difficult to predict, but it is a serious concern Acknowledgments
to the silicon integrator and is to be avoided if at all possi-
ble. Given the choice of using a metrology tool that might The authors would like to thank all of the metrology
cause a reliability failure mode and one that will not, the suppliers who worked to evaluate their products for this
answer is clear: avoid any chance of damage. The conclu- study. We would also like to acknowledge the support of
 B.J. Rice et al. / Microelectronic Engineering 83 (2006) 1023–1029 1029

the CXRO Lab at LBNL, especially Deirdre Olynick and Control for Microlithography XVII, Proceedings of SPIE, vol. 5375,
Alex Liddle, Rex Frost, Brian Coombs, Jose Maiz, and 2004, pp. 1247–1253.
[3] B.J. Rice et al., CD metrology for the 45 and 32 nm nodes, in:
Gary Crays. D.J. Herr (Ed.), Metrology, Inspection, and Process Control for
Microlithography XVII, Proceedings of SPIE, vol. 5375, 2004, pp.
References 1247–1253.
[4] T. Morimoto, T. Shinaki, Y. Kembo, S. Hosaka, New atomic force
[1] D. Joy, SPIE microlithography presentation, 2002. microscope method for critical dimension metrology, in: D.J. Herr
[2] B.J. Rice et al., Prospects for using primary electron-based CD (Ed.), Metrology, Inspection, and Process Control for Microlithogra-
metrology, in: D.J. Herr (Ed.), Metrology, Inspection, and Process phy XVII, Proceedings of SPIE, vol. 5038, 2003, pp. 636–643.