Sie sind auf Seite 1von 17

Page |1

HOME iASSIGNMENT iREPORT iON

Performance iEnhancement iusing iCache


imemory iand iVirtual imemory iSystem
RPR iSEMESTER iEND iEXAMINATION i(JUNE i2020)

SUBJECT: iMicroprocessor iand iComputer iArchitecture


i(EC503)

Submitted ito
DR. iDILIP iK. iKOTHARI

By: i
KIRAN iMARU
Roll iNumber: i15BEC061

DEPARTMENT iOF iELECTRONICS iAND


iCOMMUNICATION iENGINEERING
ITNU
AHMEDABAD, iGUJARAT i– i355423

AFFILIATED
iTO

NIRMA iUNIVERSITY
Page |2

CONTENTS
Chapter iNo. Title Page iNo.

1 Abstract 3

2 Introduction 4

3 Principle of working of Virtual and cache Memory 7

4 Cache Memory configurations 9

5 Importance of virtual memory and cache memory in 11


computer system

6 Reasons for Virtual Memory and Cache Memory 14


needed

7 Solution Directions and Research Opportunities 15

8 Conclusion 16

9 References 17

1. Abstract i
Page |3

In irecent itechnology iespecially iin ithe iindustrial ifields, ithe icomputers iare iexploited ias
icontrolling iand imonitoring itool ito ihelp iin isystem idevelopment. iAs ia iresult, imost iof
ithe icomputer iproblems iin ivarious iapplications iare islow ispeed iand ipoor iperformance.
iIn ithis ireport iwe iunderstand iabout iVirtual iMemory iand iCache iMemory ithe idesign
istrategy iwas iposed ito ishow ihow ito iassist iin iimproving iboth ispeed iand iperformance.
iThere iare imany ifactors ithat iaffect ithe iperformance iof ithe i icomputer i isuch i ias i ithe
i iprocessor i ispeed, i ithe i isize i iof i iRAM, i iand i ithe i iweakness i iof i ithe i icache i
imemory istrategy ifor ithe iprocessor. iThese ifactors iare ithe imost iinfluential ifactors ion
ithe ispeed iand iperformance iof ithe iprocessor, iwhich i iare iresult iin iperformance i
ideterioration. iMost icache imemories iare i idesigned ioutside ithe iprocessor iunits iwhich
iare i iaffecting ithe idata itransfer ispeed ito/from ithe iprocessor, idelayed iprocessor idata
iaccess i i itime, i i iand i iprocessor i iaccess i itime. i i iThe iresults iexplicit ithe igreat
iimpact iof ithe iadded icache imemory ion iboth ithe iprocessor ispeed iand ithe icomputer
iperformance i iwhen ithe icache i iwas idesigned iinside ithe iprocessor iunit.

2. Introduction
Page |4

 VIRTUAL iMEMORY i i i

Virtual i imemory i iis i ia i ivaluable i iconcept i iin icomputer i i i iarchitecture i i i


ithat iallows you ito irun ilarge, isophisticated i i iprograms i i ion i i ia i i icomputer iieven i i iif i i iit
i i ihas i i ia irelatively i small i i iamount i i iof i i iRAM. iRAM i i ihas i i ibillions i i iof imemory i
ilocations i ibut i isometimes i ieven i ithat i iis i inot i ienough iroom ifor iall ithe idata ithe iCPU
ineeds. iWhen iRAM igets itoo ifull, ithe icomputer's ioperating isystem ican ihelp iout iby
itemporarily imarking isections iof isecondary istorage
ifor ithe iCPU ito iuse ias ia ikind i i iof i i iextra i i
imemory. i i iThese i i isections i i iare i i icalled
ivirtual imemory. iThe ioperating isystem icreates ia
i'swap ifile' iin ithis iarea iwhich i i iis i i iused i i ito i i
ihold i i idata i i ithe i i iCPU i i idoes i i inot i i ineed
iimmediately. i i iBoth i i iWindows i i iand i i iLinux i
i isupport i i ivirtual imemory.
A i i icomputer i i iwith i i ivirtual i i imemory i i
iartfully i i ijuggles i i ithe iconflicting i idemands i iof i
imultiple i iprograms i iwithin i ia i ifixed iamount i i
iof i i iphysical i i imemory. i i iA i i icomputer i i
ithat's i i ilow i i ion imemory i ican i irun i ithe i isame
i iprograms i ias i ione i iwith i iabundant iRAM, i
ialthough i imore i islowly. i iThe i iterm i i"virtual i imemory" irefers i ito i ispace i iallocated i ion i
ia ihard idrive iwhere i idata i ican i ibe istored ifor irapid iaccess. iVirtual imemory iis islower ithan
isolid-state imemory ichips iso iit iis itypically iused ias ibackup imemory iin icertain isituations i
iThe ibasic iidea iwith ivirtual imemory iis ito icreate ian iillusion iof imemory ithat iis ias ilarge ias ia
idisk i(in igigabytes) iand ias ifast ias imemory i(in inanoseconds). iThe ikey iprinciple iis i ilocality i
iof i ireference, i iwhich i irecognizes i ithat i ia isignificant i i ipercentage i i iof i i imemory i i
iaccesses i i iin i i ia i i irunning iprogram iare i imade ito i ia i isubset iof iits ipages. iOr i isimply
iput, i ia irunning iprogram ionly ineeds iaccess ito ia iportion iof iits ivirtual iaddress i i ispace i i iat i
i ia i i igiven i i itime. i i
Virtual imemory iis isimulated imemory ithat iis iwritten ito ia ifile ion ithe ihard idrive. iIn ithe icase
iof iWindows iit iis ia ifile icalled ipagefile.sys. iThe iprocess iof imoving idata ifrom iRAM i ito i
idisk i i(and i iback) i iis i iknown i ias i iswapping i ior i ipaging. iWhen i ithere i iis i ino i imore i
ispace i iin i iphysical i iRAM, i ithe i iVirtual imemory i imanager i iwill i itake i ithe i ileast i iused i
iapplication i iand iplace i iit i iin i ithe i ipage i ifile i ion i ithe i ihard i idrive. iThe i iprocess i iof
itaking ian iapplication ifrom ithe iphysical iRAM iand iputting iit iin ithe ipage ifile iis icalled
ipaging iout. iThe iprocess iof imoving ithe iapplication i ifrom i ithe i ipage i ifile i iback i iinto i
iphysical i iRAM i iis icalled i ipaging i iin. i iDisk i ithrashing i ioccurs i iwhen i ithe i iamount i iof
iphysical i imemory i iis i itoo i ilow. i iIn i ithat i icase i ithe i idata i imust iconstantly ibe i imoved i
ifrom iphysical i iRAM, i ito i idisk, i iand i iback iagain, i iA i icomputer i iaccesses i ithe i icontents
i iof i iits i iRAM ithrough ia isystem iof iaddresses, iwhich iare iessentially inumbers ithat ilocate
ieach ibyte. iBecause ithe iamount iof imemory ivaries ifrom icomputer ito icomputer, idetermining
iwhich isoftware iwill iwork i ion i ia i igiven i icomputer i ibecomes i icomplicated. i iVirtual
imemory isolves ithis iproblem iby itreating ieach icomputer ias iif iit ihas ia ilarge iamount iof iRAM
iand ieach iprogram ias iif iit iuses ithe iPC i iexclusively. i

 Overview iof iCache iMemory i


Page |5

Cache imemory iis i ia i ismall i ihigh i ispeed i imemory iusually iStatic iRAM i(SRAM) ithat
icontains ithe imost irecently iaccessed ipieces iof imain i imemory. i iThey iare ithe ihigh ispeed
ibuffers iwhich iare iinserted ibetween ithe iprocessors iand imain imemory ito icapture ithose
iportions iof ithe icontents iof ithe imain imemory iwhich iare icurrently i iin i iuse. i iSince i icache i
imemories i iare i itypically i i5 i i-10 itimes ifaster ithan imain imemory ithey ican ireduce ithe
ieffective imemory i iaccess i itime i iif i icarefully i idesigned i iand i iimplemented. i i i iThe i i i
ibasic i i i ipurpose i i i iof i i i icache i memory is ito istore iprogram iinstructions ithat i i iare i i
ifrequently i i ire-referenced iby isoftware iduring ioperation. iFast iaccess ito ithese iinstructions
iincreases i ithe i ioverall i ispeed i iof i ithe i isoftware i iprogram. i iIf i ithe iCPU ifinds ithe idata iin
ithe icache imemory, iit idoes inot ihave ito igo i ilooking ifor isuch i idata iagain i iin i ithe imain i
imemory ior ieven ithe i isecondary i istorage i imedia. i iMost i iprograms i iuse i ivery i ifew
iresources ionce ithey ihave ibeen iopened iand ioperated ifor ia itime, imainly i ibecause i ifrequently
i ire-referenced i iinstructions i itend i ito ibe icached. i i i iThis i i i iexplains i i i iwhy i i i
imeasurements iof isystem iperformance iin icomputers iwith islower iprocessors ibut ilarger icaches i
i itend i i ito i i ibe i i ifaster i i ithan i i imeasurements i i iof i i isystem iperformance iin icomputers
iwith ifaster iprocessors i ibut i imore ilimited i i icache i i ispace. i i iThis i i isimply i i imean i i
ithat, ithe i i iless ifrequently iaccess iis i imade i ito i icertain i idata ior i iinstructions, ithe ilower i
idown i ithe i icache i ilevel i ithe i idata i ior i iinstructions i iare iwritten,

 Types iof iCache iMemory


There iare itwo itypes iof icache imemory iwhich iincludes imemory icache iand ithe iDisk icache.
• Memory i iCache: iA i imemory i icache i isometimes icalled i ia i icache i istore i ior i iRAM
i icache i iis i ia i iportion i iof imemory i i imade i i iof i i ihigh-speed i i istatic i i iRAM i i i(SRAM)
iinstead i i iof i i ithe i i islower i i iand i i icheaper i i idynamic i i iRAM i(DRAM) i iused i ifor i
imain i imemory. i iMemory i icaching i iis ieffective ibecause imost iprograms iaccess ithe isame
idata ior iinstruction i iover i iand i iover. i iBy i ikeeping i ias i imuch i iof i ithis iinformation i ias i
ipossible i iin i iSRAM, i ithe i icomputer i iavoids iaccessing ithe islower iDRAM.
• Disk i i i i iCache: i iDisk i i i i icaching i i i i iworks i i i i iunder i i i i ian iundistinguishable
iguideline ifrom imemory ireserving, iyet ias i iopposed i ito i iutilizing i irapid i istatic- i iRAM, i ia i
iplate/disk icache i i iutilizes i i itraditional i i iprimary i i imemory. i i iWhen i i ia iprogram ineeds
ito iget ito iinformation ifrom ithe idisk, iit ifirst ichecks ithe icircle icache ito icheck iwhether ithe
iinformation iis ithere. iDisk icaching idrastically ienhances ithe iexecution iof iprograms ias igetting
ito ia ibyte iof iinformation iin iRAM ican ibe ia ihuge inumber iof itime iquicker ithan igetting ito ia
ibyte ion ia ihard idisk.

 Levels iof iCache imemory


Page |6

iType i iof i iCache i iMemory i iis i idivided i iinto idifferent ilevels ithat iare iL1, iL2, iL3:
• Level i i1 i i(L1) i icache i ior i iPrimary i iCache: i iL1 i iis i ithe iprimary i itype i icache i
imemory. i iThe i iSize i iof i ithe i iL1 icache i i ivery i i ismall i i icomparison i i ito i i iothers i i
ithat i i iis ibetween i i2KB i ito i i64KB, i iit i idepends i ion i icomputer iprocessor. i iIt i iis i
iextremely i ifast i ibut i irelatively i ismall, iand i iis i i i iusually i iembedded i iin i ithe i iprocessor i
ichip i(CPU).Examples iof iregisters iare iaccumulator, iaddress iregister, iProgram icounter ietc.
• Level i i2 i i(L2) i icache i ior i iSecondary i iCache: i i iL2 i iis isecondary itype i icache i
imemory. i iThe iSize iof ithe iL2 icache iis imore icapacious i ithan i iL1 i ithat i iis i ibetween
i256KB ito i512KB.L2 icache iis iLocated ion icomputer imicroprocessor. i iAfter i isearching i ithe i
iInstructions i iin iL1 i iCache, i iif i inot i ifound i ithen i iit i isearched i iinto i iL2 icache iby
icomputer imicroprocessor. iThe ihigh-speed isystem i i ibus i i iinterconnecting i i ithe i i icache i i
ito i i i ithe imicroprocessor.
• Level i i3 i i(L3) i icache i ior i iMain i iMemory: i iThe i iL3 icache iis ilarger iin isize ibut
ialso islower iin ispeed ithan iL1 i iand i iL2,it's i isize i iis i ibetween i i1MB i ito i i8MB.In iMulti-
core iprocessors, ieach icore imay ihave iseparate iL1 i iand i iL2,but i iall i icore i ishare i ia i
icommon i iL3 i icache. iL3 icache idouble ispeed ithan ithe iRAM.
Page |7

3. PRINCIPLES iOF iOPERATION iOF iVIRTUAL iAND iCACHE iMEMORY

 iVirtual iMemory iImplementation iTechniques


Virtual imemory iis icommonly iimplemented iby idemand ipaging iand iDemand isegmentation

 Demand iPaging
Paging i iis i ia i itechnique i iin i iwhich i iphysical i imemory i iis i ibroken iinto iblocks iof ithe
isame isize icalled ipages i(size iis ipower iof i2, ibetween i512 ibytes iand i8192 ibytes) iWhen ia
iprocess iis ito ibe i iexecuted, i iits i icorresponding i ipages i iare i iloaded i iinto i iany iavailable
imemory iframes. iLogical iaddress ispace iof ia iprocess ican i ibe i inon-contiguous i iand i ia i
iprocess i iis i iallocated i iphysical imemory i i iwhenever i i ithe i i ifree i i imemory i i iframe i i iis i
i iavailable. iOperating i isystem i ikeeps i itrack i iof i iall i ifree i iframes. i iOperating isystem i
ineeds i i“n” i ifree i iframes i ito i irun i ia i iprogram i iof i isize i i“n” ipages. i iExternal
ifragmentation iis i iavoided i iby i iusing i ipaging itechnique. i iA i idemand i ipaging i isystem i iis i
iquite i isimilar i ito i ia ipaging i i isystem i i iwith i i iswapping i i iwhere i i iprocesses i i ireside i i
iin isecondary imemory iand ipages iare iloaded ionly ion idemand, inot iin i iadvance. i iWhen i ia i
icontext i iswitch i ioccurs, i ithe i ioperating
isystem idoes inot icopy iany iof ithe iold
iprogram’s ipages iout ito ithe i idisk i ior i iany i
iof i ithe i inew i iprogram’s i ipages i iinto i ithe i
imain imemory i iinstead, i iit i ijust i ibegins i
iexecuting i ithe i inew i iprogram iafter iloading
ithe ifirst ipage iand ifetches ithat iprogram’s ipages
ias ithey iare ireferenced.
Address igenerated iby iCPU iis idivided iinto itwo
- Page inumber i(p) i i: i i ipage inumber iis
iused i ias i ian i iindex iinto i ia i ipage i itable i
iwhich i icontains ibase i iaddress i iof ieach ipage
iin iphysical imemory.
- Page i ioffset i i(d) i i: ipage i ioffset i iis i
icombined i iwith i ibase iaddress ito idefine ithe
iphysical imemory iaddress.
 Advantagesiof DemandiPaging:
Listed below are the iadvantages iof idemand
ipaging iamong iothers:
• iLarge ivirtual imemory.
• iMore iefficient iuse iof imemory.
• iThere iis ino ilimit ion idegree iof imultiprogramming.
 Disadvantages i iof i iDemand i iPaging: i i
Some i idisadvantages i iof idemand ipaging iinclude:
Number i iof i itables i iand i ithe i iamount i iof i iprocessor ioverhead i ifor i ihandling i ipage i
iinterrupts i iare i igreater ithan iin ithe icase iof ithe isimple ipaged i imanagement itechniques.
Page |8

 iPage iFault
A i ipage i ifault i iis i ia i itype i iof i iinterrupt, i iraised i iby i ithe i ihardware iwhen i ia i irunning i
iprogram i iaccesses i ia i imemory i ipage i ithat i iis imapped i iinto i ithe i ivirtual i iaddress i
ispace, i ibut i inot i iloaded i iin iphysical i imemory, i i[10]. i iThe i ivirtual i imemory i isystem i
iuses isomething i icalled i ia i i“page i itable” i ito i imap i ivirtual i iaddresses i ito iphysical i
iaddresses. i iSince i iour i imachine i icould i ipossibly i ihave iless iRAM ithan iour iprogram ithinks
iit ihas, iit’s ipossible ito ihave imore i ivirtual i iaddresses i ithan i iphysical i iaddresses. i iThat i
imeans inot i iall i ivirtual i iaddresses i iin i ia i ipage i itable i iwill i ihave i ia i ivalid icorresponding
i iphysical i iaddress i i(i.e. i inot i iall i ivirtual i iaddresses iwill ihave ia ivalid ientry iin ithe ipage
itable). iIf ia ivirtual iaddress ihas ino ivalid ientry iin ithe ipage itable, ithen iany iattempt iby iyour
iprogram i ito i iaccess i ithat i ivirtual i iaddress i iwill i icause i ia ipage ifault ito i ioccur ia i ipage i
ifault i iis i ivery i imuch ilike i ian i iexception, i iexcept i iin i ihardware, i irather i ithan i isoftware.
iThe ipage ifault ihappens ibecause ithe irequested ivirtual iaddress iactually icorresponds ito ia ipage
ithat iis icurrently isitting ion idisk, irather ithan iin iRAM i(and itherefore ithe ivirtual iaddress
icannot ipossibly ibe itranslated iinto ia iphysical iaddress).

Page ireplacement ialgorithms iare ithe itechniques iwith iwhich ian ioperating isystem idecides
iwhich imemory ipages ito iswap iout ior iwrite ito i idisk iwhen i ia ipage iof imemory ineeds ito i ibe
iallocated, i[12]. iPaging ihappens iwhenever ia ipage ifault ioccurs iand ia ifree ipage i icannot i ibe i
iused i ifor i iallocation i ipurpose i iaccounting i ito ireason ithat ipages iare inot iavailable ior ithe
inumber iof ifree ipages iis ilower ithan irequired ipages. iWhen ithe ipage ithat iwas iselected ifor
ireplacement iand iwas ipaged iout, iis ireferenced iagain, iit ihas ito iread iin ifrom idisk, iand ithis
irequires ifor iI/O icompletion. i

 First iin iFirst iOut i(FIFO)algorithm


• Oldest ipage iin imain imemory iis ithe ione iwhich iwill ibe iselected ifor ireplacement.
• Easy ito iimplement, ikeep ia ilist, ireplace pages ifrom ithe itail iand iadd inew ipagesiat the ihead.
Optimal iPage ialgorithm:iAn i i i ioptimal i i i ipage-replacement ialgorithm ihas ithe ilowest ipage-
fault irate iof iall ialgorithms. iAn ioptimal i ipage-replacement i ialgorithm i iexists, i iand i ihas i
ibeen icalled iOPT ior iMIN.

• Replace i ithe i ipage i ithat i iwill i inot i ibe i iused i ifor i ithe ilongest iperiod iof itime.
iUse ithe itime iwhen ia ipage iis ito ibe iused.
Least iRecently iUsed i(LRU) ialgorithm: iPage i iwhich i ihas i inot i ibeen iused ifor ithe ilongest
itime iin i imain imemory iis ithe ione iwhich iwill ibe iselected ifor ireplacement.
Page |9

• Easy i ito i iimplement, i ikeep i ia i ilist, i ireplace i ipages i iby ilooking iback iinto itime.

4. iCache iMemory iconfigurations


Cache imemory iis iconfigured isuch ithat, iwhenever idata iis ito ibe iread i i ifrom i i iRAM, i i ithe i
isystem i i ihardware i i ifirst i i ichecks i i ito idetermine i iif i ithe i idesired i idata i iis i iin i icache.
i iIf i ithe i idata i iis i iin icache, iit iis iquickly iretrieved, iand iused iby ithe iCPU. iHowever, iif i
ithe idata i iis i inot i iin i icache, i ithe i idata i iis i iread i ifrom i iRAM i iand, iwhile ibeing
itransferred ito ithe iCPU, iis ialso iplaced iin icache i(incase i iit i iis i ineeded i iagain i ilater). i
iFrom i ithe i iperspective i iof i ithe iCPU, iall ithis iis idone itransparently, iso ithat ithe ionly
idifference ibetween iaccessing idata iin icache iand iaccessing idata iin iRAM iis ithe i iamount i iof i
itime i iit i itakes i ifor i ithe i idata i ito i ibe i ireturned. iCaching iconfigurations icontinue ito
ievolve, ibut imemory icache itraditionally iworks iunder ithree idifferent iconfigurations i:
• Direct imapping: iIn i i idirect i i imapping, i i ieach iblock iis imapped i ito i iexactly i ione i
icache i ilocation. i iConceptually, ithis iis ilike irows iin ia itable iwith ithree icolumns: ithe idata
iblock ior icache iline ithat icontains ithe iactual idata ifetched iand istored, ia itag ithat icontains iall
ior ipart iof ithe iaddress iof i ithe i ifetched i idata, i iand i ia iflag ibit ithat i iconnotes i ithe
ipresence iof ia ivalid ibit iof idata iin ithe irow ientry.
• Fully iassociative imapping: iiIn ifully iiassociative imapping, istructure, ithe ioperating isystem
iallows ia iblock ito ibe imapped ito iany icache ilocation irather ithan ito ia ipre- ispecified i icache i
ilocation i i(as i iis i ithe i icase i iwith i idirect imapping).
• Set i iassociative i imapping: This i imapping i itechniques ican ibe iviewed ias ia icompromise
ibetween idirect imapping iand i ifully i iassociative i imapping i iin i iwhich i ieach i iblock i iis
imapped ito ia isubset iof icache ilocations. iIt iis isometimes icalled iN-way i iset i iassociative i
imapping, i iwhich i iprovides ifor ia i ilocation i iin i imain i imemory ito i ibe icached i ito i iany iof
i"N" ilocations iin ithe iL1 icache.
• Specialized i i icaches: i i iIn i i iaddition i i ito i i iinstruction i i iand i i idata icaches, ithere iare
iother icaches idesigned ito iprovide ispecialized ifunctions iin ia isystem. iBy isome idefinitions,
ithe iL3 icache iis ia ispecialized i i icache i i ibecause of i i iits i i ishared i i idesign. i i iOther
idefinitions i iseparate i iinstruction i icaching i ifrom i idata i icaching, ireferring ito ieach ias ia
ispecialized icache.
Other ispecialized imemory icaches iinclude ithe itranslation ilook- iaside i i ibuffer i i i(TLB) i i
iwhose i i ifunction i i iis i i ito i i irecord ivirtual
address ito iphysical iaddress itranslations. i iStill iother icaches iare
not, itechnically ispeaking, imemory icaches iat iall. iDisk icaches, ifor iexample, imay ileverage
iRAM ior iflash imemory ito iprovide
much i ithe i isame i ikind i iof i idata i icaching i ias i imemory i icaches i ido iwith i iCPU i
iinstructions. i iIf i idata i iis i ifrequently i iaccessed i ifrom idisk, i iit i iis i icached i iinto iDRAM
ior i iflash-based isilicon istorage itechnology ifor ifaster iaccess iand iresponse.
P a g e | 10

 iCache iReplacement iAlgorithm


A icache ialgorithm iis ia idetailed ilist iof iinstructions ithat idirects iwhich i i i iitems i i i ishould i i i
ibe i i i idiscarded i i i iin i i i ia i i i icomputing idevice's icache iof iinformation. iCache
iReplacement iAlgorithms iare ionly ineeded ifor iassociative iand iset iassociative itechniques.
iThere iare iseveral iCache ireplacement ialgorithms iaccording ito i, iand ithey iinclude ithe
ifollowing:

 First-in i iFirst-out (FIFO) i i– i iFirst i iin i iFirst i iout i iis i ia i icache ireplacement i
ialgorithm i ithat i ireplaces i ithe i icache i iline i ithat i ihas ibeen iin ithe icache ithe ilongest.
 Belady's Algorithm: i iThe i imost i iefficient i icaching i ialgorithm iwould i ibe i ito i ialways i
idiscard i ithe i iinformation i ithat i iwill i inot i ibe ineeded ifor ithe ilongest itime iin ithe
ifuture. iThis ioptimal iresult iis ireferred i ito i ias i iBelady's i ioptimal i ialgorithm i ior i ithe i
iclairvoyant ialgorithm. iSince iit iis igenerally iimpossible ito ipredict ihow ifar iin ithe ifuture
iinformation iwill ibe ineeded, ithis iis igenerally inot iimplementable i iin i ipractice. i iThe i
ipractical i iminimum i ican i ibe icalculated i ionly i iafter i iexperimentation, i iand i ione i ican i
icompare ithe ieffectiveness iof ithe iactually ichosen icache ialgorithm. i
 Least Recently Used (LRU): i iThis i ialgorithm i idiscards i ithe ileast irecently iused iitems
ifirst. iThis ialgorithm irequires ikeeping itrack iof iwhat iwas iused iwhen, iwhich iis iexpensive
iif ione iwants ito imake isure ithe ialgorithm ialways idiscards ithe ileast irecently iused iitem.
iGeneral iimplementations iof ithis itechnique irequire ikeeping i i i"age i i ibits" i i ifor i i icache-
lines i i iand i i itrack i i ithe i i i"Least iRecently i iUsed" i icache-line i ibased i ion i iage-bits. i
iIn i isuch i ian iimplementation, ievery itime ia icache-line iis iused, ithe iage iof iall iother i i
icache-lines i i ichanges. i i iLRU i i iis i i iactually i i ia i i ifamily i i iof icaching ialgorithms
iwith imembers iincluding: i2Q iby iTheodore iJohnson iand iDennis iShasha iand iLRU/K iby
iPat iO'Neil, iBetty iO'Neil iand iGerhard iWeikum.
 Random iReplacement i(RR): iRandomly iselects ia icandidate iitem i iand i idiscards i iit i ito i
imake i ispace i iwhen i inecessary. i iThis ialgorithm idoes inot irequire ikeeping iany
iinformation iabout ithe iaccess i ihistory. i iFor i iits i isimplicity, i iit i ihas i ibeen i iused i iin i
iARM iprocessors. iIt iadmits iefficient istochastic isimulation.
 Segmented iLRU(SLRU): i iAn i iSLRU i icache i iis i idivided i iinto itwo isegments,ia i
iprobationary i i isegment i i iand i i ia i i iprotected isegment. iLines iin ieach isegment iare
iordered ifrom ithe imost ito ithe ileast irecently iaccessed. iData ifrom imisses iis iadded ito ithe
icache i iat ithe i imost i irecently i iaccessed i iend i iof i ithe i iprobationary isegment. i iHits i
iare i iremoved ifrom i iwherever i ithey i icurrently ireside i iand i iadded i ito i ithe i imost i
irecently i iaccessed iend i iof i ithe iprotected i isegment. i iLines iin i ithe iprotected i isegment
ihave ithus ibeen iaccessed iat ileast itwice. iThe iprotected isegment iis ifinite, iso i imigration i
iof ia i iline i ifrom ithe i iprobationary i isegment i ito i ithe iprotected isegment imay iforce ithe
imigration iof ithe iLRU iline iin ithe iprotected isegment ito ithe imost irecently iused i(MRU)
iend iof ithe i iprobationary isegment, igiving i ithis i iline i ianother i ichance i ito ibe i iaccessed
i ibefore i ibeing ireplaced. iThe size i ilimit i ion i ithe iprotected isegment iis ian iSLRU
iparameter ithat ivaries iaccording ito iithe i i iI/O iworkload i i ipatterns. i i iWhenever i i idata i i
imust i i ibe idiscarded ifrom i ithe i icache, i ilines i iare i iobtained i ifrom i ithe i iLRU iend iof
ithe iprobationary isegment.
P a g e | 11

5. iImportance of virtual memory and cache memory in computer


system
Virtual i imemory i itechniques i iand i imemory i icaching i iare i iboth iimportant i iand i ihelps i iin
i ioptimizing i isystem i iutilization. i iTheir iimportances iare istated iin ithe isections ibelow:
 Importance iof iVirtual iMemory
Virtual imemory i technique i iand i iits i iimplementations i iare i ivery ivital ito ithe ioverall
ifunctionality iof ithe icomputer isystem. iThe iImportance iof ivirtual imemory itechnique iincludes:
•Flexibility: i iIf icomputers ionly irelied ion ithe imain imemory ichips, ifar iless imemory iwould
ibe iavailable iand i i ithe i i iusefulness i i iof i i imany isoftware iprograms iwould i i ibe i iseverely i
ilimited. i i iEven i i ithough i i ivirtual imemory iis islower, iit iis istill iuseful ibecause iit igreatly
iexpands ia icomputer's ifunctionality.
•Saves iCostiand iTime:iWhen i ivirtual imemory iwas i ifirst i icreated, i isolid-state i imemory i
ichips i iwere imuch i i ismaller i i iand i i imore i i iexpensive. i i iHowever, itoday's i imemory ichips
ican i istore imany igigabytes iof idata i iat i ivery i ilow i icost i iand i imoreover i ias i imemory
ichips icontinue ito igrow iin icapacity, iprices iare ifalling ialso.
•Makes Multiprogramming iEasierifurther istates i ithat i iWhen i ia icomputer iuser i iopens i
imultiple iprograms iat ionce, ithe idata ifor ithese iprograms imust ibe i istored i iin i imemory i ifor i
iquick i iaccess. i iThe i imore iprograms iare iopened, ithe imore imemory iis ineeded. iWhen i ithe i
icomputer's i iphysical i imemory i iis i ifull, i ithe iexcess i idata i iis i istored i iin i ivirtual i
imemory. i iVirtual imemory i iwith i ipaging i ilets i ia i icomputer i irun i imany iprograms i iat i ithe
i isame i itime, i ialmost i iregardless i iof iavailable i i i i i iRAM. i i i i i iThis i i i i i ibenefit i i i i i
iis i i i i i icalled imultiprogramming iand iit iis ia ikey ifeature iof imodern iPC ioperating isystems. i
i iThis ifeature ienable imodern icomputers i ito i iaccommodate i imany i iutility i iprograms isuch ias
iprinter idrivers, inetwork imanagers iand ivirus iscanners i iat i ithe i isame i itime i ias i iyour i
iapplications -Web i ibrowsers, i iword i iprocessors, i iemail i iand i imedia iplayers.
•Makes it ieasieiforiProgrammers ito iWriteiand iRun Large Programs: In iaddition i i ito i i
imultitasking, iivirtual imemory i iallows iprogrammers i ito i icreate i ilarger i iand i imore i
icomplex iapplications. i i iWhen i i ithese i i iprograms i i iare i i irunning, ithey i ioccupy i iphysical
i imemory i ias i iwell i ias i ivirtual imemory.

•Paging i iFile: i iWith i ivirtual i imemory, i ithe i icomputer iwrites i iprogram i ipages i ithat i ihave
i inot i ibeen i irecently iused i ito i ian i iarea i ion i ithe i ihard i idrive i icalled i ia i ipaging ifile.
iThe ifile isaves ithe idata icontained iin ithe ipages; iif ithe iprogram ineeds iit iagain, ithe ioperating
isystem ireloads i iit i iwhen i iRAM i ibecomes i iavailable. i iWhen imany i i iprograms i i icompete
i i ifor i i iRAM, i i ithe i i iact i i iof iswapping i ipages i ito i ithe i ifile i ican i islow i ia i
icomputer's iprocessing i ispeed, i ias i iit i ispends i imore i itime i idoing imemory i imanagement i
ichores i iand i iless i itime i igetting iuseful i iwork i idone. i i
P a g e | 12

•VM ias ia iTool ifor iCaching: iConceptually, ia ivirtual imemory i iis i iorganized i ias i ian i iarray
i iof i iN i icontiguous ibyte-sized i icells i istored i ion i idisk. i iEach i ibyte i ihas i ia iunique i
ivirtual i iaddress i ithat i iserves i ias i ian i iindex i iinto ithe i iarray. i iThe i icontents i iof i ithe i
iarray i ion i idisk i iare icached iin imain imemory. iAs iwith iany iother icache iin ithe i imemory i
ihierarchy, i ithe i idata i ion i idisk i i(the i ilower ilevel) i iis i ipartitioned i iinto i iblocks i ithat i
iserve i ias i ithe itransfer i i iunits i i ibetween i i ithe i i idisk i i iand i i ithe i i imain imemory i(the
iupper ilevel).
• i iUnallocated: i iPages i ithat i ihave i inot i iyet i ibeen i iallocated i i(or icreated) iby ithe iVM i
isystem. iUnallocated i iblocks ido i inot ihave iany i idata i iassociated i iwith i ithem, i iand i ithus i
ido i inot i ioccupy i iany
space ion idisk.
• i iCached: Allocated i i ipages i i ithat i i iare i i icurrently i i icached i i iin iphysical imemory.
• iUncached: iAllocated ipages ithat iare inot icached iin iphysicalmemory
VM i ias i ia i iTool i ifor i iMemory i iManagement: i iThe icombination iof idemand ipaging iand
iseparate ivirtual iaddress i ispaces i ihas i ia i iprofound i iimpact i ion i ithe i iway ithat i imemory i
iis i iused i iand i imanaged i iin i ia i isystem. i iIn iparticular, i iVirtual i iMemory i isimplifies i
ilinking i iand iloading, ithe isharing iof icode iand idata, iand iallocating imemory ito iapplications.
• i iSimplifying i ilinking: i iA i iseparate i iaddress i ispace iallows ieach iprocess ito iuse ithe isame
ibasic iformat iforits imemory iimage, iregardless iof iwhere ithe icode iand idata iactually ireside iin
iphysical imemory.
• iSimplifying iloading: iVirtual imemory ialso imakes iit i ieasy i ito i iload i iexecutable i iand i
ishared i iobject i ifiles into imemory.
• i iSimplifying i i isharing: i i iSeparate i i iaddress i i ispaces iprovide i i ithe i i ioperating i i
isystem i i iwith i i ia i i iconsistent imechanism i i ifor i i imanaging i i isharing i i ibetween i i iuser
iprocesses i i iand i i ithe i i ioperating i i isystem i i iitself. i i iIn general, ieach iprocess ihas iits iown
iprivate icode, idata, iheap, i iand i istack i iareas i ithat i iare i inot i ishared i iwith i iany iother i
iprocess. i iIn i ithis i icase, i ithe i ioperating i isystem icreates i i ipage i i itables i i ithat i i imap i i
ithe i i icorresponding virtual ipages ito idisjoint iphysical ipages. iHowever, iin isome iinstances iit
iis idesirable ifor iprocesses ito ishare icode iand idata.
P a g e | 13

 Importance iof iCache iMemory iin Computer iSystems


Cache i iMemory i iis i iexpensive i ito i iimplement i iand i ihave i ilimited icapacity i ibut i ithey i
iare i ivery i iimportant i iin i iachieving i ioptimum iperformance iof ithe icomputer isystem.
The ifollowing iare ithe iimportance iof icache imemory:
•Speed:iCache memory i iis i i ifaster i i ithan i i ithe i i imain imemory; ihence ideploying icache i
imemory iincreases ithe i i ispeed i i iof i i iprocessing i i itremendously. i i iCache imemory
iconsumes iless iaccess itime iwhen icompared ito ithe imain imemory.
•Quick iAccess ito iFrequently iused idata: iThe icache imemory i istores i idata i ifor i itemporary i
iuse, i istoring i ithe iprograms ithat ican ibe iexecuted iwithin ia ishort iperiod iof itime. iTo ithis
iend, iaccess ito ifrequently iused idata iis iachieved iat ia iquicker irate.
•Reduction iof iLatency: iAnalytical iand itransactional iworkloads have reduce query-response
itime ibecause i i ithe i i isolid-state drive ii(SSD) i istorage i ihas ilower ilatencies. iIf iyou i iuse
iserver-side icaching, ithe iaverage ilatency ifor ia itransactional iworkload ican ibe ireduced iby ihalf.
•Increased Throughput:iOnline itransaction iprocessing (OLTP) workloads have higher itransaction
i irates i ibecause i ithe i iSolid i iState i iDrives istorage iprovides ibetter ithroughput.
•Write i i ithroughput: i i iIn i i ienvironments i i iwhere i i ithe istorage iarea inetwork i(SAN) iis
icongested, ithe iflash idevice, i iwhich i iis i iused i ias i ia i icache, i ican i ioffload i ia isignificant i
ipercentage i iof iread i irequests. i iWhen i iread irequests i iare i ioffloaded, i ithe i iSAN i ican i
ihave i ibetter iwrite ithroughput, iand ican ieffectively iserve ia ilarger inumber iof iclients iand
ihosts.
•Smaller imemory ifootprint: iIf ia iflash icache idevice iis i iconfigured, i isome i iworkloads i ican
i iperform i ieven iwith ia ilower imemory ifootprint.
P a g e | 14

6. Reasons for Virtual Memory and Cache Memory needed


Virtual i i imemory i i iis i i ian i i ielegant i i iinteraction i i iof i i ihardware iexceptions, ihardware
iaddress itranslation, imain imemory, idisk ifiles, iand i ikernel i isoftware i ithat i iprovides i ieach i
iprocess i iwith i ia ilarge, i iuniform, i iand i iprivate i iaddress i ispace. i iWith i ione i iclean
imechanism, ivirtual imemory provides three important icapabilities.
• It iuses imain imemory iefficiently iby itreating iit ias ia icache ifor ian iaddress ispace istored
ion idisk, ikeeping ionly i i ithe i i iactive i i iareas i i iin i i imain i i imemory, i i iand itransferring
idata iback iand iforth ibetween idisk iand imemory ias ineeded.
• It i isimplifies i imemory i imanagement i iby i iproviding ieach iprocess iwith ia iuniform
iaddress ispace.
• It iprotects ithe iaddress ispace iof ieach iprocess ifrom icorruption i iby iother iprocesses.
iVirtual imemory iis ione i iof i ithe i igreat i iideas i iin i icomputer i isystems. i iA imajor i i ireason i
i ifor i i iits i i isuccess i i iis i i ithat i i iit i i iworks isilentlyiand i iautomatically, iwithout iany
iintervention iifrom i i ithe i i iapplication i i iprogrammer. iSince i ivirtual i i
Virtual i imemory i iis i i icentral. i i iVirtual i imemory i ipervades i iall ilevels iof icomputer
isystems, iplaying ikey iroles iin ithe idesign iof ihardware i i iexceptions, i i iassemblers, i i ilinkers, i
i iloaders, i i ishared iobjects, i ifiles, i iand i iprocesses. i iUnderstanding i ivirtual i imemory iwill i
ihelp i ione i ibetter i iunderstand i ihow i ithe i icomputer i isystem iworks iin igeneral.
iUnderstanding ivirtual imemory iwill ihelp iyou iharness iits ipowerful icapabilities iin iyour
iapplications. iVirtual imemory igives iapplications ipowerful icapabilities ito icreate iand idestroy i i
ichunks i i iof i i imemory, i i imap i i ichunks i i iof i i imemory i i ito iportions iof idisk ifiles, iand
ishare imemory iwith iother iprocesses. iHowever, i iit i iis i iexpedient i ifor i ius i ito i iunderstand i
ithat i ivirtual imemory i icould i ialso i ibe i idangerous. i iThis i iis i ibecause i ivirtual imemory
iapplications iinteract iwith ivirtual imemory ievery itime ithey ireference ia ivariable, idereference ia
ipointer, ior imake ia icall ito i ia i idynamic i iallocation i ipackage i isuch i ias i imalloc. i iIf i
ivirtual imemory i iis i iused i iimproperly, i iapplications i ican i isuffer i ifrom iperplexing iand
iinsidious imemory irelated ibugs. iFor iexample, iaprogram i iwith i ia i ibad i ipointer i ican i icrash i
iimmediately i iwith i ia i“Segmentation i ifault” i ior i ia i i“Protection i ifault,” i irun i isilently ifor
ihours i ibefore i icrashing, i ior i irun i ito i icompletion i iwith i iincorrect iresults. i iUnderstanding i
ihow i ivirtual i imemory i iworks i iand i ithe iallocation i ipackages i isuch i ias i imalloc ithat i
imanages iit i ican i ihelp ione iavoid ithese ierrors.
On i ithe i iother i ihand, i iCache i iis i ia i ismall i iamount i iof i imemory iwhich iis iphysically
icloser ito ithe iCPU ithan iRAM iis. iThe imore icache ithere iis, ithe imore idata ican ibe istored
icloser ito ithe iCPU. iCache imemory iis ibeneficial ibecause:
•Cache i imemory iiholds ifrequently iused iinstructions idata iwhich i ithe i iprocessor i imay i
irequire inext iand iit iis ifaster iaccess imemory ithan iRAM, isince iit iis ion ithe isame ichip ias ithe
iprocessor. iThis ireduces ithe ineed ifor ifrequent islower imemory iretrievals ifrom imain imemory,
iwhich imay iotherwise ikeep ithe iCPU iwaiting.
•The i imore i icache i ithe i iCPU i ihas, i ithe i iless i itime i ithe icomputer i ispends i iaccessing i
islower i imain i imemory iand ias ia iresult iprograms imay irun ifaster.
P a g e | 15

7. Solution iDirections iand iResearch iOpportunities


As ia iresult iof ithese isystems, iapplications, iand itechnology itrends iand ithe iresulting
irequirements, iit iis iour iposition ithat iresearchers iand idesigners ineed ito ifundamentally irethink
ithe iway iwe idesign imemory isystems itoday ito
i1) iovercome iscaling ichallenges iwith iDRAM,
i2) ienable ithe iuse iof iemerging imemory itechnologies, i
3) idesign imemory isystems ithat iprovide ipredictable iperformance iand iquality iof iservice ito
iapplications iand iusers. The irest iof ithis iarticle idescribes iour isolution iideas iin ithese ithree
irelatively inew iresearch idirections, iwith ipointers ito ispecific itechniques iwhen ipossible.iSince
iscaling ichallenges ithemselves iarise idue ito idifficulties iin ienhancing imemory icomponents iat
isolely i
one ilevel iof ithe icomputing istack i(e.g., ithe idevice iand/or icircuit ilevels iin icase iof iDRAM
iscaling), iwe ibelieve ieffective isolutions ito ithe iabove ichallenges iwill irequire icooperation
iacross idifferent ilayers iof ithe icomputing istack, ifrom ialgorithms ito isoftware ito
imicroarchitecture ito idevices, ias iwell ias ibetween idifferent icomponents iof ithe isystem,
iincluding iprocessors, imemory icontrollers, imemory ichips, iand ithe istorage isubsystem. iAs
imuch ias ipossible, iwe iwill igive iexamples iof isuch icross-layer isolutions iand idirections.
As DRAM technology scales to smaller node sizes, its reliability becomes more difficult to maintain
at the circuit and device levels. In fact, we already have evidence of the difficulty of maintaining
DRAM reliability from the DRAM chips operating in the field today. In Recent research showed that
a majority of the DRAM chips manufactured between 2010-2014 by three major DRAM vendors
exhibit a particular failure mechanism called row hammer: by activating a row enough times within a
refresh interval, one can corrupt data in nearby DRAM rows. The source code is available at [1]. This
is an example of a disturbance error where the access of a cell causes disturbance of the value stored
in a nearby cell due to cell-to-cell coupling (i.e., interference) effects, Such interference-induced
failure mechanisms are well-known in any memory that pushes the limits of technology,
P a g e | 16

8. Conclusion

 In this we Learn about cache memory and virtual memory and its Enhancement. iComputer imemory
iis iorganized iin ia ihierarchy, iwith ithe ismallest, ifastest imemory iat ithe itop iand ithe ilargest,
islowest imemory iat ithe ibottom.Cache imemory igives ifaster iaccess ito imain imemory, iwhile
ivirtual imemory iuses idisk istorage ito igive ithe iillusion iof ihaving ia ilarge imain imemory.Cache
imaps iblocks iof imain imemory ito iblocks iof icache imemory. iVirtual imemory imaps ipage
iframes ito ivirtual ipages. There iare ithree igeneral itypes iof icache: iDirect imapped, ifully
iassociative iand iset iassociative. Virtual memory is a technique for allowing the computer to act
as though it has more physical memory by using the hard drive (which is almost always much
larger than main memory) as temporary storage space. If the session reaches apoint where programs
are asking for more memory space than is available, the operating system will look for the pages
of RAM that have been least recently accessed, and will move their contents off to the hard
drive to make room for the new requests for space in main RAM. If one of those other programs
then comes back and attempts to access one of the pages that is no longer resident, the CPU traps this
situation and lets the operating system know that page is needed again, at which point the operating
system will go and retrieve it from the hard drive again and swap it with something else.
Memory virtualization does have other uses beyond artificial expansion of physical RAM, such as
giving appearance of having their own unique address space to run in, which helps to isolate
them from other processes running on the system.
P a g e | 17

9. References

I. John Papiewski (2018). “The Concept of VirtualMemory in Computer Architecture.


Available From www.smallbuisness.chron.com/Concept-Virtual-memory.

II. Jacob Queen (2018). “Why is Virtual Memory Important?” John Papiewski
(2018). “The Concept of VirtualMemory in Computer Architecture. Available From
www.smallbuisness.chron.com/Concept-Virtual-memory.

III. Cicnavi (2010). “What is Virtual Memory and why do we need it?” Available
fromwww.utilizewindow.com.available from www.techwalla.com/articles/why-is-virtual-
memory-important.

IV. Santosh .S. Padwal, Ahishi . P. Duthate, Shivkumar Vishnupurikar and P.M. Chawman,
(2012). “Cache Memory organization”. International Journal of Networking and
Parallel computing. Vol 1, issue 2, November 2012. Page 12-16.

Das könnte Ihnen auch gefallen