Beruflich Dokumente
Kultur Dokumente
Submitted ito
DR. iDILIP iK. iKOTHARI
By: i
KIRAN iMARU
Roll iNumber: i15BEC061
AFFILIATED
iTO
NIRMA iUNIVERSITY
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CONTENTS
Chapter iNo. Title Page iNo.
1 Abstract 3
2 Introduction 4
8 Conclusion 16
9 References 17
1. Abstract i
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In irecent itechnology iespecially iin ithe iindustrial ifields, ithe icomputers iare iexploited ias
icontrolling iand imonitoring itool ito ihelp iin isystem idevelopment. iAs ia iresult, imost iof
ithe icomputer iproblems iin ivarious iapplications iare islow ispeed iand ipoor iperformance.
iIn ithis ireport iwe iunderstand iabout iVirtual iMemory iand iCache iMemory ithe idesign
istrategy iwas iposed ito ishow ihow ito iassist iin iimproving iboth ispeed iand iperformance.
iThere iare imany ifactors ithat iaffect ithe iperformance iof ithe i icomputer i isuch i ias i ithe
i iprocessor i ispeed, i ithe i isize i iof i iRAM, i iand i ithe i iweakness i iof i ithe i icache i
imemory istrategy ifor ithe iprocessor. iThese ifactors iare ithe imost iinfluential ifactors ion
ithe ispeed iand iperformance iof ithe iprocessor, iwhich i iare iresult iin iperformance i
ideterioration. iMost icache imemories iare i idesigned ioutside ithe iprocessor iunits iwhich
iare i iaffecting ithe idata itransfer ispeed ito/from ithe iprocessor, idelayed iprocessor idata
iaccess i i itime, i i iand i iprocessor i iaccess i itime. i i iThe iresults iexplicit ithe igreat
iimpact iof ithe iadded icache imemory ion iboth ithe iprocessor ispeed iand ithe icomputer
iperformance i iwhen ithe icache i iwas idesigned iinside ithe iprocessor iunit.
2. Introduction
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VIRTUAL iMEMORY i i i
Cache imemory iis i ia i ismall i ihigh i ispeed i imemory iusually iStatic iRAM i(SRAM) ithat
icontains ithe imost irecently iaccessed ipieces iof imain i imemory. i iThey iare ithe ihigh ispeed
ibuffers iwhich iare iinserted ibetween ithe iprocessors iand imain imemory ito icapture ithose
iportions iof ithe icontents iof ithe imain imemory iwhich iare icurrently i iin i iuse. i iSince i icache i
imemories i iare i itypically i i5 i i-10 itimes ifaster ithan imain imemory ithey ican ireduce ithe
ieffective imemory i iaccess i itime i iif i icarefully i idesigned i iand i iimplemented. i i i iThe i i i
ibasic i i i ipurpose i i i iof i i i icache i memory is ito istore iprogram iinstructions ithat i i iare i i
ifrequently i i ire-referenced iby isoftware iduring ioperation. iFast iaccess ito ithese iinstructions
iincreases i ithe i ioverall i ispeed i iof i ithe i isoftware i iprogram. i iIf i ithe iCPU ifinds ithe idata iin
ithe icache imemory, iit idoes inot ihave ito igo i ilooking ifor isuch i idata iagain i iin i ithe imain i
imemory ior ieven ithe i isecondary i istorage i imedia. i iMost i iprograms i iuse i ivery i ifew
iresources ionce ithey ihave ibeen iopened iand ioperated ifor ia itime, imainly i ibecause i ifrequently
i ire-referenced i iinstructions i itend i ito ibe icached. i i i iThis i i i iexplains i i i iwhy i i i
imeasurements iof isystem iperformance iin icomputers iwith islower iprocessors ibut ilarger icaches i
i itend i i ito i i ibe i i ifaster i i ithan i i imeasurements i i iof i i isystem iperformance iin icomputers
iwith ifaster iprocessors i ibut i imore ilimited i i icache i i ispace. i i iThis i i isimply i i imean i i
ithat, ithe i i iless ifrequently iaccess iis i imade i ito i icertain i idata ior i iinstructions, ithe ilower i
idown i ithe i icache i ilevel i ithe i idata i ior i iinstructions i iare iwritten,
iType i iof i iCache i iMemory i iis i idivided i iinto idifferent ilevels ithat iare iL1, iL2, iL3:
• Level i i1 i i(L1) i icache i ior i iPrimary i iCache: i iL1 i iis i ithe iprimary i itype i icache i
imemory. i iThe i iSize i iof i ithe i iL1 icache i i ivery i i ismall i i icomparison i i ito i i iothers i i
ithat i i iis ibetween i i2KB i ito i i64KB, i iit i idepends i ion i icomputer iprocessor. i iIt i iis i
iextremely i ifast i ibut i irelatively i ismall, iand i iis i i i iusually i iembedded i iin i ithe i iprocessor i
ichip i(CPU).Examples iof iregisters iare iaccumulator, iaddress iregister, iProgram icounter ietc.
• Level i i2 i i(L2) i icache i ior i iSecondary i iCache: i i iL2 i iis isecondary itype i icache i
imemory. i iThe iSize iof ithe iL2 icache iis imore icapacious i ithan i iL1 i ithat i iis i ibetween
i256KB ito i512KB.L2 icache iis iLocated ion icomputer imicroprocessor. i iAfter i isearching i ithe i
iInstructions i iin iL1 i iCache, i iif i inot i ifound i ithen i iit i isearched i iinto i iL2 icache iby
icomputer imicroprocessor. iThe ihigh-speed isystem i i ibus i i iinterconnecting i i ithe i i icache i i
ito i i i ithe imicroprocessor.
• Level i i3 i i(L3) i icache i ior i iMain i iMemory: i iThe i iL3 icache iis ilarger iin isize ibut
ialso islower iin ispeed ithan iL1 i iand i iL2,it's i isize i iis i ibetween i i1MB i ito i i8MB.In iMulti-
core iprocessors, ieach icore imay ihave iseparate iL1 i iand i iL2,but i iall i icore i ishare i ia i
icommon i iL3 i icache. iL3 icache idouble ispeed ithan ithe iRAM.
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Demand iPaging
Paging i iis i ia i itechnique i iin i iwhich i iphysical i imemory i iis i ibroken iinto iblocks iof ithe
isame isize icalled ipages i(size iis ipower iof i2, ibetween i512 ibytes iand i8192 ibytes) iWhen ia
iprocess iis ito ibe i iexecuted, i iits i icorresponding i ipages i iare i iloaded i iinto i iany iavailable
imemory iframes. iLogical iaddress ispace iof ia iprocess ican i ibe i inon-contiguous i iand i ia i
iprocess i iis i iallocated i iphysical imemory i i iwhenever i i ithe i i ifree i i imemory i i iframe i i iis i
i iavailable. iOperating i isystem i ikeeps i itrack i iof i iall i ifree i iframes. i iOperating isystem i
ineeds i i“n” i ifree i iframes i ito i irun i ia i iprogram i iof i isize i i“n” ipages. i iExternal
ifragmentation iis i iavoided i iby i iusing i ipaging itechnique. i iA i idemand i ipaging i isystem i iis i
iquite i isimilar i ito i ia ipaging i i isystem i i iwith i i iswapping i i iwhere i i iprocesses i i ireside i i
iin isecondary imemory iand ipages iare iloaded ionly ion idemand, inot iin i iadvance. i iWhen i ia i
icontext i iswitch i ioccurs, i ithe i ioperating
isystem idoes inot icopy iany iof ithe iold
iprogram’s ipages iout ito ithe i idisk i ior i iany i
iof i ithe i inew i iprogram’s i ipages i iinto i ithe i
imain imemory i iinstead, i iit i ijust i ibegins i
iexecuting i ithe i inew i iprogram iafter iloading
ithe ifirst ipage iand ifetches ithat iprogram’s ipages
ias ithey iare ireferenced.
Address igenerated iby iCPU iis idivided iinto itwo
- Page inumber i(p) i i: i i ipage inumber iis
iused i ias i ian i iindex iinto i ia i ipage i itable i
iwhich i icontains ibase i iaddress i iof ieach ipage
iin iphysical imemory.
- Page i ioffset i i(d) i i: ipage i ioffset i iis i
icombined i iwith i ibase iaddress ito idefine ithe
iphysical imemory iaddress.
Advantagesiof DemandiPaging:
Listed below are the iadvantages iof idemand
ipaging iamong iothers:
• iLarge ivirtual imemory.
• iMore iefficient iuse iof imemory.
• iThere iis ino ilimit ion idegree iof imultiprogramming.
Disadvantages i iof i iDemand i iPaging: i i
Some i idisadvantages i iof idemand ipaging iinclude:
Number i iof i itables i iand i ithe i iamount i iof i iprocessor ioverhead i ifor i ihandling i ipage i
iinterrupts i iare i igreater ithan iin ithe icase iof ithe isimple ipaged i imanagement itechniques.
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iPage iFault
A i ipage i ifault i iis i ia i itype i iof i iinterrupt, i iraised i iby i ithe i ihardware iwhen i ia i irunning i
iprogram i iaccesses i ia i imemory i ipage i ithat i iis imapped i iinto i ithe i ivirtual i iaddress i
ispace, i ibut i inot i iloaded i iin iphysical i imemory, i i[10]. i iThe i ivirtual i imemory i isystem i
iuses isomething i icalled i ia i i“page i itable” i ito i imap i ivirtual i iaddresses i ito iphysical i
iaddresses. i iSince i iour i imachine i icould i ipossibly i ihave iless iRAM ithan iour iprogram ithinks
iit ihas, iit’s ipossible ito ihave imore i ivirtual i iaddresses i ithan i iphysical i iaddresses. i iThat i
imeans inot i iall i ivirtual i iaddresses i iin i ia i ipage i itable i iwill i ihave i ia i ivalid icorresponding
i iphysical i iaddress i i(i.e. i inot i iall i ivirtual i iaddresses iwill ihave ia ivalid ientry iin ithe ipage
itable). iIf ia ivirtual iaddress ihas ino ivalid ientry iin ithe ipage itable, ithen iany iattempt iby iyour
iprogram i ito i iaccess i ithat i ivirtual i iaddress i iwill i icause i ia ipage ifault ito i ioccur ia i ipage i
ifault i iis i ivery i imuch ilike i ian i iexception, i iexcept i iin i ihardware, i irather i ithan i isoftware.
iThe ipage ifault ihappens ibecause ithe irequested ivirtual iaddress iactually icorresponds ito ia ipage
ithat iis icurrently isitting ion idisk, irather ithan iin iRAM i(and itherefore ithe ivirtual iaddress
icannot ipossibly ibe itranslated iinto ia iphysical iaddress).
Page ireplacement ialgorithms iare ithe itechniques iwith iwhich ian ioperating isystem idecides
iwhich imemory ipages ito iswap iout ior iwrite ito i idisk iwhen i ia ipage iof imemory ineeds ito i ibe
iallocated, i[12]. iPaging ihappens iwhenever ia ipage ifault ioccurs iand ia ifree ipage i icannot i ibe i
iused i ifor i iallocation i ipurpose i iaccounting i ito ireason ithat ipages iare inot iavailable ior ithe
inumber iof ifree ipages iis ilower ithan irequired ipages. iWhen ithe ipage ithat iwas iselected ifor
ireplacement iand iwas ipaged iout, iis ireferenced iagain, iit ihas ito iread iin ifrom idisk, iand ithis
irequires ifor iI/O icompletion. i
• Replace i ithe i ipage i ithat i iwill i inot i ibe i iused i ifor i ithe ilongest iperiod iof itime.
iUse ithe itime iwhen ia ipage iis ito ibe iused.
Least iRecently iUsed i(LRU) ialgorithm: iPage i iwhich i ihas i inot i ibeen iused ifor ithe ilongest
itime iin i imain imemory iis ithe ione iwhich iwill ibe iselected ifor ireplacement.
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• Easy i ito i iimplement, i ikeep i ia i ilist, i ireplace i ipages i iby ilooking iback iinto itime.
First-in i iFirst-out (FIFO) i i– i iFirst i iin i iFirst i iout i iis i ia i icache ireplacement i
ialgorithm i ithat i ireplaces i ithe i icache i iline i ithat i ihas ibeen iin ithe icache ithe ilongest.
Belady's Algorithm: i iThe i imost i iefficient i icaching i ialgorithm iwould i ibe i ito i ialways i
idiscard i ithe i iinformation i ithat i iwill i inot i ibe ineeded ifor ithe ilongest itime iin ithe
ifuture. iThis ioptimal iresult iis ireferred i ito i ias i iBelady's i ioptimal i ialgorithm i ior i ithe i
iclairvoyant ialgorithm. iSince iit iis igenerally iimpossible ito ipredict ihow ifar iin ithe ifuture
iinformation iwill ibe ineeded, ithis iis igenerally inot iimplementable i iin i ipractice. i iThe i
ipractical i iminimum i ican i ibe icalculated i ionly i iafter i iexperimentation, i iand i ione i ican i
icompare ithe ieffectiveness iof ithe iactually ichosen icache ialgorithm. i
Least Recently Used (LRU): i iThis i ialgorithm i idiscards i ithe ileast irecently iused iitems
ifirst. iThis ialgorithm irequires ikeeping itrack iof iwhat iwas iused iwhen, iwhich iis iexpensive
iif ione iwants ito imake isure ithe ialgorithm ialways idiscards ithe ileast irecently iused iitem.
iGeneral iimplementations iof ithis itechnique irequire ikeeping i i i"age i i ibits" i i ifor i i icache-
lines i i iand i i itrack i i ithe i i i"Least iRecently i iUsed" i icache-line i ibased i ion i iage-bits. i
iIn i isuch i ian iimplementation, ievery itime ia icache-line iis iused, ithe iage iof iall iother i i
icache-lines i i ichanges. i i iLRU i i iis i i iactually i i ia i i ifamily i i iof icaching ialgorithms
iwith imembers iincluding: i2Q iby iTheodore iJohnson iand iDennis iShasha iand iLRU/K iby
iPat iO'Neil, iBetty iO'Neil iand iGerhard iWeikum.
Random iReplacement i(RR): iRandomly iselects ia icandidate iitem i iand i idiscards i iit i ito i
imake i ispace i iwhen i inecessary. i iThis ialgorithm idoes inot irequire ikeeping iany
iinformation iabout ithe iaccess i ihistory. i iFor i iits i isimplicity, i iit i ihas i ibeen i iused i iin i
iARM iprocessors. iIt iadmits iefficient istochastic isimulation.
Segmented iLRU(SLRU): i iAn i iSLRU i icache i iis i idivided i iinto itwo isegments,ia i
iprobationary i i isegment i i iand i i ia i i iprotected isegment. iLines iin ieach isegment iare
iordered ifrom ithe imost ito ithe ileast irecently iaccessed. iData ifrom imisses iis iadded ito ithe
icache i iat ithe i imost i irecently i iaccessed i iend i iof i ithe i iprobationary isegment. i iHits i
iare i iremoved ifrom i iwherever i ithey i icurrently ireside i iand i iadded i ito i ithe i imost i
irecently i iaccessed iend i iof i ithe iprotected i isegment. i iLines iin i ithe iprotected i isegment
ihave ithus ibeen iaccessed iat ileast itwice. iThe iprotected isegment iis ifinite, iso i imigration i
iof ia i iline i ifrom ithe i iprobationary i isegment i ito i ithe iprotected isegment imay iforce ithe
imigration iof ithe iLRU iline iin ithe iprotected isegment ito ithe imost irecently iused i(MRU)
iend iof ithe i iprobationary isegment, igiving i ithis i iline i ianother i ichance i ito ibe i iaccessed
i ibefore i ibeing ireplaced. iThe size i ilimit i ion i ithe iprotected isegment iis ian iSLRU
iparameter ithat ivaries iaccording ito iithe i i iI/O iworkload i i ipatterns. i i iWhenever i i idata i i
imust i i ibe idiscarded ifrom i ithe i icache, i ilines i iare i iobtained i ifrom i ithe i iLRU iend iof
ithe iprobationary isegment.
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•Paging i iFile: i iWith i ivirtual i imemory, i ithe i icomputer iwrites i iprogram i ipages i ithat i ihave
i inot i ibeen i irecently iused i ito i ian i iarea i ion i ithe i ihard i idrive i icalled i ia i ipaging ifile.
iThe ifile isaves ithe idata icontained iin ithe ipages; iif ithe iprogram ineeds iit iagain, ithe ioperating
isystem ireloads i iit i iwhen i iRAM i ibecomes i iavailable. i iWhen imany i i iprograms i i icompete
i i ifor i i iRAM, i i ithe i i iact i i iof iswapping i ipages i ito i ithe i ifile i ican i islow i ia i
icomputer's iprocessing i ispeed, i ias i iit i ispends i imore i itime i idoing imemory i imanagement i
ichores i iand i iless i itime i igetting iuseful i iwork i idone. i i
P a g e | 12
•VM ias ia iTool ifor iCaching: iConceptually, ia ivirtual imemory i iis i iorganized i ias i ian i iarray
i iof i iN i icontiguous ibyte-sized i icells i istored i ion i idisk. i iEach i ibyte i ihas i ia iunique i
ivirtual i iaddress i ithat i iserves i ias i ian i iindex i iinto ithe i iarray. i iThe i icontents i iof i ithe i
iarray i ion i idisk i iare icached iin imain imemory. iAs iwith iany iother icache iin ithe i imemory i
ihierarchy, i ithe i idata i ion i idisk i i(the i ilower ilevel) i iis i ipartitioned i iinto i iblocks i ithat i
iserve i ias i ithe itransfer i i iunits i i ibetween i i ithe i i idisk i i iand i i ithe i i imain imemory i(the
iupper ilevel).
• i iUnallocated: i iPages i ithat i ihave i inot i iyet i ibeen i iallocated i i(or icreated) iby ithe iVM i
isystem. iUnallocated i iblocks ido i inot ihave iany i idata i iassociated i iwith i ithem, i iand i ithus i
ido i inot i ioccupy i iany
space ion idisk.
• i iCached: Allocated i i ipages i i ithat i i iare i i icurrently i i icached i i iin iphysical imemory.
• iUncached: iAllocated ipages ithat iare inot icached iin iphysicalmemory
VM i ias i ia i iTool i ifor i iMemory i iManagement: i iThe icombination iof idemand ipaging iand
iseparate ivirtual iaddress i ispaces i ihas i ia i iprofound i iimpact i ion i ithe i iway ithat i imemory i
iis i iused i iand i imanaged i iin i ia i isystem. i iIn iparticular, i iVirtual i iMemory i isimplifies i
ilinking i iand iloading, ithe isharing iof icode iand idata, iand iallocating imemory ito iapplications.
• i iSimplifying i ilinking: i iA i iseparate i iaddress i ispace iallows ieach iprocess ito iuse ithe isame
ibasic iformat iforits imemory iimage, iregardless iof iwhere ithe icode iand idata iactually ireside iin
iphysical imemory.
• iSimplifying iloading: iVirtual imemory ialso imakes iit i ieasy i ito i iload i iexecutable i iand i
ishared i iobject i ifiles into imemory.
• i iSimplifying i i isharing: i i iSeparate i i iaddress i i ispaces iprovide i i ithe i i ioperating i i
isystem i i iwith i i ia i i iconsistent imechanism i i ifor i i imanaging i i isharing i i ibetween i i iuser
iprocesses i i iand i i ithe i i ioperating i i isystem i i iitself. i i iIn general, ieach iprocess ihas iits iown
iprivate icode, idata, iheap, i iand i istack i iareas i ithat i iare i inot i ishared i iwith i iany iother i
iprocess. i iIn i ithis i icase, i ithe i ioperating i isystem icreates i i ipage i i itables i i ithat i i imap i i
ithe i i icorresponding virtual ipages ito idisjoint iphysical ipages. iHowever, iin isome iinstances iit
iis idesirable ifor iprocesses ito ishare icode iand idata.
P a g e | 13
8. Conclusion
In this we Learn about cache memory and virtual memory and its Enhancement. iComputer imemory
iis iorganized iin ia ihierarchy, iwith ithe ismallest, ifastest imemory iat ithe itop iand ithe ilargest,
islowest imemory iat ithe ibottom.Cache imemory igives ifaster iaccess ito imain imemory, iwhile
ivirtual imemory iuses idisk istorage ito igive ithe iillusion iof ihaving ia ilarge imain imemory.Cache
imaps iblocks iof imain imemory ito iblocks iof icache imemory. iVirtual imemory imaps ipage
iframes ito ivirtual ipages. There iare ithree igeneral itypes iof icache: iDirect imapped, ifully
iassociative iand iset iassociative. Virtual memory is a technique for allowing the computer to act
as though it has more physical memory by using the hard drive (which is almost always much
larger than main memory) as temporary storage space. If the session reaches apoint where programs
are asking for more memory space than is available, the operating system will look for the pages
of RAM that have been least recently accessed, and will move their contents off to the hard
drive to make room for the new requests for space in main RAM. If one of those other programs
then comes back and attempts to access one of the pages that is no longer resident, the CPU traps this
situation and lets the operating system know that page is needed again, at which point the operating
system will go and retrieve it from the hard drive again and swap it with something else.
Memory virtualization does have other uses beyond artificial expansion of physical RAM, such as
giving appearance of having their own unique address space to run in, which helps to isolate
them from other processes running on the system.
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9. References
II. Jacob Queen (2018). “Why is Virtual Memory Important?” John Papiewski
(2018). “The Concept of VirtualMemory in Computer Architecture. Available From
www.smallbuisness.chron.com/Concept-Virtual-memory.
III. Cicnavi (2010). “What is Virtual Memory and why do we need it?” Available
fromwww.utilizewindow.com.available from www.techwalla.com/articles/why-is-virtual-
memory-important.
IV. Santosh .S. Padwal, Ahishi . P. Duthate, Shivkumar Vishnupurikar and P.M. Chawman,
(2012). “Cache Memory organization”. International Journal of Networking and
Parallel computing. Vol 1, issue 2, November 2012. Page 12-16.