Compal LA-6841P

A B C D E
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1 1
PWWAA
2
Marseille LC 2
L-A6841P REV 0.1 Schematic

3
Intel Penryn/ Cantiga/ ICH9M 3
2010-07-22 Rev. 0.1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2009/06/12 Deciphered Date 2010/06/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PWWAA LA6841P M/B
Date: Monday, August 16, 2010 Sheet 1 of 44
A B C D E
A B C D E
Model Name : PWWAA

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Compal Confidential
Fan Control Intel Penryn Processor Thermal Sensor Clock Generator
File Name : LA-6841P APL5607 EMC1402-1 SLG8SP556VTR
page 4 uPGA-478 Package page 4 page 16
1
(Socket P) page 4,5,6
1
FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)
Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2

CRT Intel Cantiga Dual Channel BANK 0, 1, 2, 3 page 14,15
page 18
GM45/GL40 1.5V DDR3 800/1066
LCD Conn.
page 17
uFCBGA-1329
page 7,8,9,10,11,12,13
2 2
PCIeMini Card
WiMax DMI x 4 C-Link
USB
USB port 7
page 25 5V 480MHz USB USB/B Int. Camera
5V 480MHz
USB port 0,1 USB port 11
PCIeMini Card PCIe 1x [2,4,5] page 23 page 17
WLAN 1.5V 2.5GHz(250MB/s)
PCIe port 4
page 25
Intel ICH9-M
SATA port 1 SATA HDD0
5V 1.5GHz(150MB/s) page 23
RJ45 RTL8105E 10/100M PCIe 1x
page 26 PCIe port 3 page 26 1.5V 2.5GHz(250MB/s) BGA-676
SATA port 4 SATA ODD
USB 5V 1.5GHz(150MB/s) page 23
RTS5138E 2IN1 5V 480MHz
USB port 10 page 29 page 19,20,21,22
3 3
3.3V 33 MHz
LPC BUS HD Audio 3.3V/1.5V 24.576MHz/48Mhz
Power/B HDA Codec

page 24
Debug Port ENE KB926 D2 ALC259
page 29
page 31 page 30
RTC CKT.
page 20
DC/DC Interface CKT. Touch Pad Int.KBD SPI ROM Int.

page 24 page 24 page 31 MIC CONN MIC CONN HP CONN SPK CONN
page 33 page 30 page 30 page 30 page 30
4 4
Power Circuit DC/DC

page 34,35,36,37,38,39,40
Block Diagrams
0.1
PWWAA LA6841P M/B
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A B C D E
Voltage Rails www.rosefix.com STATE

SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
Power Plane Description S1 S3 S5 G3 Full ON HIGH HIGH HIGH HIGH
VIN Adapter power supply (19V) ON ON ON OFF S1(Power On Suspend) LOW HIGH HIGH HIGH
1 1
B+ AC or battery power rail for power circuit. ON ON ON ON
S3 (Suspend to RAM) LOW LOW HIGH HIGH
+CPU_CORE Core voltage for CPU ON OFF OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH
+1.05VS 1.05V switched power rail ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW
+1.5VS 1.5V switched power rail ON OFF OFF OFF
+1.5V 1.5 power rail for DDR ON ON OFF OFF G3 LOW LOW LOW LOW
+1.8VS 1.8V power rail ON ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON OFF
+3VL 3.3V always on power rail ON ON ON ON
+3V_SB 3.3V power rail for SB ON ON OFF OFF
+3V_LAN 3.3V power rail for LAN ON ON OFF OFF BTO Option Table
+3VS 3.3V switched power rail ON OFF OFF OFF
Function Card Reader Camera WLAN Energy Star

+5VALW 5V always on power rail ON ON ON OFF
2
description (X) Always Always 2
+5V_SB 5V power rail for SB ON ON OFF OFF

explain Camera WLAN Energy Star
+5VS 5V switched power rail ON OFF OFF OFF
+VSB VSB always on power rail ON ON ON OFF BTO CAM@ WLAN@
+RTCVCC RTC power ON ON ON ON
External PCI Devices

DEVICE PCI DEVICE ID IDSEL# REQ/GNT# PIRQ
3 3
EC SM Bus1 address EC SM Bus2 address

Power Device Address Power Device Address
+3VL EC KB926 D2 +3VS EC KB926 D2
CPU THM Sen
+3VL Smart Battery 0001 011X b +3VS SMSC SMC1402 1001 101Xb
ICH9M SM Bus address

Power Device Address
+3V_SB ICH9M
Clock Generator 1101 001Xb
4 +3VS (SLG8SP556V) 4
+3VS DDR DIMM0 1001 000Xb

+3VS DDR DIMM1 1001 010Xb
Notes List
0.1
PWWAA LA6841P M/B
A B C D E
5 4 3 2 1
<7> H_A#[3..16]
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H_A#3 J4
@
JCPUA
A[3]# ADS# H1 H_ADS# <7>
+3VS
ADDR GROUP_0
H_A#4 L5 E2
A[4]# BNR# H_BNR# <7>
H_A#5 L4 G5
A[5]# BPRI# H_BPRI# <7>
H_A#6 K5 1
0.1U_0402_16V4Z
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# <7>
H_A#8 N2 F21 C1
A[8]# DRDY# H_DRDY# <7>
H_A#9 J1 E1 U1
A[9]# DBSY# H_DBSY# <7> 2
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# <7>
H_A#12 P2 1 8
A[12]# VDD SMCLK EC_SMB_CK2 <30>
CONTROL
D H_A#13 L2 D20 H_IERR# R1 1 2 56_0402_5% +1.05VS D
H_A#14 A[13]# IERR# H_INIT# H_THERMDA
P4 A[14]# INIT# B3 H_INIT# <20> 2 DP SMDATA 7 EC_SMB_DA2 <30>
H_A#15 P1 C2
H_A#16 A[15]# H_THERMDC
R1 A[16]# LOCK# H4 H_LOCK# <7> 1 2 3 DN ALERT# 6 1 2 +3VS
M1 2200P_0402_50V7K R2 10K_0402_5%
<7> H_ADSTB#0 ADSTB[0]#
C1 H_RESET# CPU_THERM# 4 5 @ Reserve for source control
RESET# H_RESET# <7> THERM# GND
<7> H_REQ#0 K3 REQ[0]# RS[0]# F3 H_RS#0 <7>
H2 F4 R3
<7> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <7> if use XDP,these resistor are 51ohm
<7> H_REQ#2 K2 REQ[2]# RS[2]# G3 H_RS#2 <7> +3VS 1 2
J3 G2 +1.05VS 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
<7> H_REQ#3 REQ[3]# TRDY# H_TRDY# <7>
<7> H_REQ#4 L1 REQ[4]#
Address:0100_1100 EMC1402-1
G6 XDP_TDO 1 2 Address:0100_1101 EMC1402-2
<7> H_A#[17..35] HIT# H_HIT# <7>
H_A#17 Y2 E4 R14 54.9_0402_1%
A[17]# HITM# H_HITM# <7>
H_A#18 U5 XDP_TMS 1 2
H_A#19 A[18]# R4 54.9_0402_1%
R3 A[19]# BPM[0]# AD4
ADDR GROUP_1
H_A#20 W6 AD3 XDP_TDI 1 2
H_A#21 A[20]# BPM[1]# R5 54.9_0402_1%
U4 AD1
H_A#22
H_A#23
Y5
A[21]#
A[22]#
BPM[2]#
BPM[3]# AC4
XDP_TCK +5VS
FAN Control Circuit
U1 AC2 1 2
XDP/ITP SIGNALS
H_A#24 A[23]# PRDY# R6 54.9_0402_1%
R4 A[24]# PREQ# AC1
H_A#25 T5 A[25]# TCK AC5 XDP_TCK XDP_TRST# 1 2 1A
H_A#26 T3 AA6 XDP_TDI R7 54.9_0402_1%
H_A#27 A[26]# TDI XDP_TDO
W2 A[27]# TDO AB3 PAD T13
H_A#28 W5 AB5 XDP_TMS +1.05VS 1 2
H_A#29 A[28]# TMS XDP_TRST# R8 @ 56_0402_5%
Y4 A[29]# TRST# AB6
H_A#30 U2 C20 XDP_DBRESET# 1 2 2
A[30]# DBR# XDP_DBRESET# <21>
H_A#31 V4 R9 56_0402_5%
A[31]#
2
JFAN
B
H_A#32 W3 C3
H_A#33 A[32]# 10U_0805_10V4Z +FAN1
AA4 A[33]# THERMAL 1
1 1
E
C H_A#34 AB2 H_PROCHOT# 3 1 2 C
A[34]# OCP# <21> 2
C
H_A#35 AA3 D21 H_PROCHOT# Q6 2 3
A[35]# PROCHOT# H_THERMDA @ MMBT3904_SOT23 U2 3
<7> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC PROCHOT# PU: 68Ohm near CPU and MVP6. 1 8 C4 4
H_A20M# THERMDC EN GND @ 1000P_0402_25V8J GND
<20> H_A20M# A6 A20M# 56Ohm near CPU if no used. 2 VIN GND 7 5 GND
1
ICH
H_FERR# A5 C7 +FAN1 3 6
<20> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <8,20> VOUT GND
H_IGNNE# C4 4 5 ACES_85204-0300N
<20> H_IGNNE# IGNNE# <30> EN_DFAN1 VSET GND
1 @
<20> H_STPCLK#
H_STPCLK# D5 STPCLK#
10mil APL5607KI-TRG_SO8
H_INTR C6 H CLK C5
<20> H_INTR LINT0
H_NMI B4 A22 H_THERMDA, H_THERMDC routing together, 10U_0805_10V4Z R10 10K_0402_5%
<20> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <16> 2
H_SMI# A3 A21 2 1 +3VS
<20> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <16> Trace width / Spacing = 10 / 10 mil
M4 RSVD[01] FAN_SPEED1 <30>
N5 RSVD[02] 2
T2 RSVD[03]
V3 C6
RSVD[04]
B2 0.01U_0402_16V7K
RESERVED
RSVD[05] 1 @
D2 RSVD[06]
D22 RSVD[07]
Reserve for D3 RSVD[08]
F6
debug RSVD[09]
close to South
Bridge
Penryn
H_FERR# 2 1
B C596 @ 180P_0402_50V8J B
H_SMI# 2 1
C597 @ 180P_0402_50V8J
H_INIT# 2 1
C598 @ 180P_0402_50V8J
H_NMI 2 1
C599 @ 180P_0402_50V8J
H_A20M# 2 1
C600 @ 180P_0402_50V8J
H_INTR 2 1
C601 @ 180P_0402_50V8J
H_IGNNE# 2 1
C602 @ 180P_0402_50V8J
H_STPCLK# 2 1
C603 @ 180P_0402_50V8J
Reserve for
debug
close to CPU
A A

Penryn(1/3)-AGTL+/THM/FAN
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
www.rosefix.com
<7> H_D#[0..15] @
H_D#[32..47] <7>
A4
A8
A11
A14
A16
@
JCPUD
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
P6
P21
P24
R2
R5
JCPUB A19 R22
H_D#0 H_D#32 VSS[006] VSS[087]
E22 D[0]# D[32]# Y22 A23 VSS[007] VSS[088] R25
H_D#1 F24 AB24 H_D#33 AF2 T1
H_D#2 D[1]# D[33]# H_D#34 VSS[008] VSS[089]
E26 D[2]# D[34]# V24 B6 VSS[009] VSS[090] T4
DATA GRP 0
D H_D#3 G22 V26 H_D#35 B8 T23 D
D[3]# D[35]# VSS[010] VSS[091]
DATA GRP 2
H_D#4 F23 V23 H_D#36 B11 T26
H_D#5 D[4]# D[36]# H_D#37 VSS[011] VSS[092]
G25 D[5]# D[37]# T22 B13 VSS[012] VSS[093] U3
H_D#6 E25 U25 H_D#38 B16 U6
H_D#7 D[6]# D[38]# H_D#39 VSS[013] VSS[094]
E23 D[7]# D[39]# U23 B19 VSS[014] VSS[095] U21
H_D#8 K24 Y25 H_D#40 B21 U24
H_D#9 D[8]# D[40]# H_D#41 VSS[015] VSS[096]
G24 D[9]# D[41]# W22 B24 VSS[016] VSS[097] V2
H_D#10 J24 Y23 H_D#42 C5 V5
H_D#11 D[10]# D[42]# H_D#43 VSS[017] VSS[098]
J23 D[11]# D[43]# W24 C8 VSS[018] VSS[099] V22
H_D#12 H22 W25 H_D#44 C11 V25
H_D#13 D[12]# D[44]# H_D#45 VSS[019] VSS[100]
F26 D[13]# D[45]# AA23 C14 VSS[020] VSS[101] W1
H_D#14 K22 AA24 H_D#46 C16 W4
H_D#15 D[14]# D[46]# H_D#47 VSS[021] VSS[102]
H23 D[15]# D[47]# AB25 C19 VSS[022] VSS[103] W23
<7> H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 <7> C2 VSS[023] VSS[104] W26
<7> H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 <7> C22 VSS[024] VSS[105] Y3
<7> H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 <7> C25 VSS[025] VSS[106] Y6
<7> H_D#[16..31] H_D#[48..63] <7> D1 VSS[026] VSS[107] Y21
D4 VSS[027] VSS[108] Y24
H_D#16 N22 AE24 H_D#48 D8 AA2
H_D#17 D[16]# D[48]# H_D#49 VSS[028] VSS[109]
K25 D[17]# D[49]# AD24 D11 VSS[029] VSS[110] AA5
H_D#18 P26 AA21 H_D#50 D13 AA8
D[18]# D[50]# VSS[030] VSS[111]
H_D#19 R23 D[19]# D[51]# AB22 H_D#51 Resistor placed within D16 VSS[031] VSS[112] AA11
H_D#20 L23 AB21 H_D#52 D19 AA14
D[20]# D[52]# 0.5" of CPU pin.Trace VSS[032] VSS[113]
DATA GRP 1
H_D#21 M24 AC26 H_D#53 D23 AA16
D[21]# D[53]# VSS[033] VSS[114]
DATA GRP 3
H_D#22 L22 D[22]# D[54]# AD20 H_D#54 should be at least 25 D26 VSS[034] VSS[115] AA19
H_D#23 M23 AE22 H_D#55 E3 AA22
H_D#24 D[23]# D[55]# H_D#56
mils away from any other VSS[035] VSS[116]
P25 D[24]# D[56]# AF23 E6 VSS[036] VSS[117] AA25
H_D#25 P23 D[25]# D[57]# AC25 H_D#57 toggling signal. E8 VSS[037] VSS[118] AB1
H_D#26 P22 AE21 H_D#58 COMP[0,2] trace width is E11 AB4
C H_D#27 D[26]# D[58]# H_D#59 VSS[038] VSS[119] C
T24 AD21 E14 AB8
+1.05VS Close to H_D#28 R24
D[27]# D[59]#
AC22 H_D#60 18 mils. COMP[1,3] trace E16
VSS[039] VSS[120]
AB11
D[28]# D[60]# VSS[040] VSS[121]
CPU pin H_D#29 L25 D[29]# D[61]# AD23 H_D#61 width is 5 mils. E19 VSS[041] VSS[122] AB13
H_D#30 T25 AF22 H_D#62 E21 AB16
AD26 D[30]# D[62]# VSS[042] VSS[123]
1
H_D#31 N25 AC23 H_D#63 E24 AB19

within D[31]# D[63]# VSS[043] VSS[124]
<7> H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 <7> F5 VSS[044] VSS[125] AB23
R11 500mils. <7> H_DSTBP#1 M26 DSTBP[1]# DSTBP[3]# AF24 H_DSTBP#3 <7>
COMP0 1 2 F8 VSS[045] VSS[126] AB26
1K_0402_1% N24 AC20 R12 27.4_0402_1% F11 AC3
<7> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <7> VSS[046] VSS[127]
COMP1 1 2 F13 AC6
2
+CPU_GTLREF +CPU_GTLREF COMP0 R13 54.9_0402_1% VSS[047] VSS[128]

AD26 GTLREF COMP[0] R26 F16 VSS[048] VSS[129] AC8
C23 MISC U26 COMP1 COMP2 1 2 F19 AC11
TEST1 COMP[1] VSS[049] VSS[130]
1
D25 AA1 COMP2 R15 27.4_0402_1% F2 AC14

TEST2 COMP[2] COMP3 COMP3 VSS[050] VSS[131]
C24 TEST3 COMP[3] Y1 1 2 F22 VSS[051] VSS[132] AC16
R17 AF26 R18 54.9_0402_1% F25 AC19
2K_0402_1% TEST4 H_DPRSTP# VSS[052] VSS[133]
AF1 TEST5 DPRSTP# E5 H_DPRSTP# <8,20,40> G4 VSS[053] VSS[134] AC21
A26 B5 H_DPSLP# G1 AC24
H_DPSLP# <20>
2
TEST6 DPSLP# VSS[054] VSS[135]

C3 TEST7 DPWR# D24 H_DPW R# <7> G23 VSS[055] VSS[136] AD2
B22 D6 H_PW RGOOD G26 AD5
<8,16> CPU_BSEL0 BSEL[0] PWRGOOD H_PW RGOOD <20> VSS[056] VSS[137]
B23 D7 H_CPUSLP# H3 AD8
<8,16> CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# <7> VSS[057] VSS[138]
<8,16> CPU_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# <40> H6 VSS[058] VSS[139] AD11
layout note: Please use "Daisy Chain" H21 VSS[059] VSS[140] AD13
Penryn H24 AD16
to layout and the signal (H_DPRSTP#) J2
VSS[060] VSS[141]
AD19
VSS[061] VSS[142]
is routed from ICH9 to power IC, J5 VSS[062] VSS[143] AD22
then to NB and CPU J22 VSS[063] VSS[144] AD25
J25 VSS[064] VSS[145] AE1
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs K1 VSS[065] VSS[146] AE4
K4 VSS[066] VSS[147] AE8
K23 VSS[067] VSS[148] AE11
B B
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 K26 VSS[068] VSS[149] AE14
Reserve for L3 VSS[069] VSS[150] AE16
H_CPUSLP# 2 1 L6 AE19
C650 @ 180P_0402_50V8J debug L21
VSS[070] VSS[151]
AE23
VSS[071] VSS[152]
166 0 1 1 H_PW RGOOD 2 1 close to CPU L24 VSS[072] VSS[153] AE26
C651 @ 180P_0402_50V8J M2 A2
H_DPRSTP# VSS[073] VSS[154]
2 1 M5 VSS[074] VSS[155] AF6
C652 @ 180P_0402_50V8J M22 AF8
VSS[075] VSS[156]
200 0 1 0 H_DPSLP# 2 1 M25 VSS[076] VSS[157] AF11
C653 @ 180P_0402_50V8J N1 AF13
VSS[077] VSS[158]
N4 VSS[078] VSS[159] AF16
N23 VSS[079] VSS[160] AF19
266 0 0 0 N26 VSS[080] VSS[161] AF21
P3 VSS[081] VSS[162] A25
VSS[163] AF25
Penryn
.
A A

Penryn(2/3)-AGTL+/GND
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
Near CPU CORE regulator
ESR <= 1.5m ohm

Capacitor > 1980uF
www.rosefix.com Place these capacitors on L8
(North side,Secondary Layer)
+CPU_CORE
1
C11
1
C12
1
C13
1
C14
1
C15
1
C16
1
C17
1
C18
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

2 2 2 2 2 2 2 2
D D
+CPU_CORE +CPU_CORE +CPU_CORE
@
JCPUC
A7 AB20 330U_6.3V_M_R15 330U_6.3V_M_R15 1 1 1 1 1 1 1 1
VCC[001] VCC[068] C19 C20 C21 C22 C23 C24 C25 C26
A9 VCC[002] VCC[069] AB7
A10 AC7 1 1 1 1 Place these capacitors on L8
VCC[003] VCC[070] (North side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
A12 VCC[004] VCC[071] AC9
+ + + + 2 2 2 2 2 2 2 2
A13 VCC[005] VCC[072] AC12
A15 AC13 C79 C80 C81 C82
VCC[006] VCC[073]
A17 VCC[007] VCC[074] AC15
2 2 2 2 need to change P/N
A18 VCC[008] VCC[075] AC17
+CPU_CORE
A20 VCC[009] VCC[076] AC18
B7 AD7 330U_6.3V_M_R15 330U_6.3V_M_R15
VCC[010] VCC[077]
B9 VCC[011] VCC[078] AD9
B10 VCC[012] VCC[079] AD10 1 1 1 1 1 1 1 1
B12 AD12 C27 C28 C29 C30 C31 C32 C33 C34
VCC[013] VCC[080] Place these capacitors on L8
B14 VCC[014] VCC[081] AD14
B15 AD15 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC[015] VCC[082] 2 2 2 2 2 2 2 2
B17 VCC[016] VCC[083] AD17
B18 VCC[017] VCC[084] AD18
B20 VCC[018] VCC[085] AE9
C9 VCC[019] VCC[086] AE10
+CPU_CORE
C10 VCC[020] VCC[087] AE12
C12 VCC[021] VCC[088] AE13
C13 VCC[022] VCC[089] AE15
C15 VCC[023] VCC[090] AE17 1 1 1 1 1 1 1 1
C17 AE18 C35 C36 C37 C38 C39 C40 C41 C42
VCC[024] VCC[091] Place these capacitors on L8
C18 VCC[025] VCC[092] AE20
C D9 AF9 (Sorth side,Secondary Layer) 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C
VCC[026] VCC[093] 2 2 2 2 2 2 2 2
D10 VCC[027] VCC[094] AF10
D12 VCC[028] VCC[095] AF12
D14 VCC[029] VCC[096] AF14
D15 VCC[030] VCC[097] AF15
D17
D18
VCC[031] VCC[098] AF17
AF18
Mid Frequence Decoupling
VCC[032] VCC[099] +1.05VS
E7 VCC[033] VCC[100] AF20
E9 VCC[034] 4.5A
E10 VCC[035] VCCP[01] G21
E12 V6 1 Place these inside socket cavity on L8
VCC[036] VCCP[02] +1.05VS (North side Secondary)
E13 VCC[037] VCCP[03] J6
E15 K6 +
VCC[038] VCCP[04] C146
E17 VCC[039] VCCP[05] M6
E18 VCC[040] VCCP[06] J21 1 1 1 1 1 1
2 330U_6.3V_M_R15 C44 C45 C46 C47 C48 C49
E20 VCC[041] VCCP[07] K21
F7 VCC[042] VCCP[08] M21
F9 N21 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
VCC[043] VCCP[09] 2 2 2 2 2 2
F10 VCC[044] VCCP[10] N6
F12 VCC[045] VCCP[11] R21
F14 VCC[046] VCCP[12] R6
F15 VCC[047] VCCP[13] T21
F17 VCC[048] VCCP[14] T6
F18 VCC[049] VCCP[15] V21
F20 VCC[050] VCCP[16] W21
AA7 VCC[051] Near pin B26
AA9 VCC[052] VCCA[01] B26 +1.5VS
AA10 VCC[053] VCCA[02] C26 1 1
AA12 C51
B VCC[054] C50 B
AA13 VCC[055] VID[0] AD6 CPU_VID0 <40>
AA15 AF5 CPU_VID1 <40> 0.01U_0402_16V7K 10U_0805_6.3V6M
VCC[056] VID[1] 2 2
AA17 VCC[057] VID[2] AE5 CPU_VID2 <40>
AA18 VCC[058] VID[3] AF4 CPU_VID3 <40>
AA20 VCC[059] VID[4] AE3 CPU_VID4 <40>
AB9 VCC[060] VID[5] AF3 CPU_VID5 <40>
AC10 VCC[061] VID[6] AE2 CPU_VID6 <40>
AB10 VCC[062]
AB12 VCC[063]
AB14 AF7 VCCSENSE VCCSENSE <40>
VCC[064] VCCSENSE
AB15 VCC[065]
AB17 VCC[066]
AB18 AE7 VSSSENSE VSSSENSE <40>
VCC[067] VSSSENSE
Penryn
.
+CPU_CORE
VCCSENSE 100_0402_1% 2 1 R19
VSSSENSE 100_0402_1% 2 1 R20
A Close to CPU pin A
within 500mils.
Length match within 25 mils.

The trace width/space/other is Penryn(3/3)-PWR/Bypass
14/7/25. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
www.rosefix.com <5> H_D#[0..63]

H_D#0
H_D#1
H_D#2
F2
G8
F8
U3A
H_D#_0
H_D#_1
H_D#_2
H_A#_3
H_A#_4
H_A#_5
H_A#_6
A14
C15
F16
H13
H_A#3
H_A#4
H_A#5
H_A#6
H_A#[3..35] <4>
H_D#3 E6 C18 H_A#7

H_D#4 H_D#_3 H_A#_7 H_A#8
G2 H_D#_4 H_A#_8 M16
H_D#5 H6 J13 H_A#9
H_D#6 H_D#_5 H_A#_9 H_A#10
H2 H_D#_6 H_A#_10 P16
D H_D#7 F6 R16 H_A#11 D
H_D#8 H_D#_7 H_A#_11 H_A#12
D4 H_D#_8 H_A#_12 N17
H_D#9 H3 M13 H_A#13
H_D#10 H_D#_9 H_A#_13 H_A#14
M9 H_D#_10 H_A#_14 E17
H_D#11 M11 P17 H_A#15
H_D#12 H_D#_11 H_A#_15 H_A#16
J1 H_D#_12 H_A#_16 F17
H_D#13 J2 G20 H_A#17
H_D#14 H_D#_13 H_A#_17 H_A#18
N12 H_D#_14 H_A#_18 B19
H_D#15 J6 J16 H_A#19
H_D#16 H_D#_15 H_A#_19 H_A#20
P2 H_D#_16 H_A#_20 E20
H_D#17 L2 H16 H_A#21
H_D#18 H_D#_17 H_A#_21 H_A#22
R2 H_D#_18 H_A#_22 J20
H_D#19 N9 L17 H_A#23
H_D#20 H_D#_19 H_A#_23 H_A#24
L6 H_D#_20 H_A#_24 A17
H_D#21 M5 B17 H_A#25
H_D#22 H_D#_21 H_A#_25 H_A#26
J3 H_D#_22 H_A#_26 L16
H_D#23 N2 C21 H_A#27
H_D#24 H_D#_23 H_A#_27 H_A#28
R1 H_D#_24 H_A#_28 J17
H_D#25 N5 H20 H_A#29
H_D#26 H_D#_25 H_A#_29 H_A#30
N6 H_D#_26 H_A#_30 B18
H_D#27 P13 K17 H_A#31
H_D#28 H_D#_27 H_A#_31 H_A#32
N8 H_D#_28 H_A#_32 B20
H_D#29 L7 F21 H_A#33
H_D#30 H_D#_29 H_A#_33 H_A#34
N10 H_D#_30 H_A#_34 K21
H_D#31 M3 L20 H_A#35
H_D#32 H_D#_31 H_A#_35
Y3 H_D#_32
H_D#33 AD14 H12
H_D#_33 H_ADS# H_ADS# <4>
H_D#34 Y6 B16
H_D#_34 H_ADSTB#_0 H_ADSTB#0 <4>
H_D#35 Y10 G17
H_D#_35 H_ADSTB#_1 H_ADSTB#1 <4>
C H_D#36 Y12 A9 C
H_D#_36 H_BNR# H_BNR# <4>
HOST
H_D#37 Y14 F11
H_D#_37 H_BPRI# H_BPRI# <4>
H_D#38 Y7 G12
H_D#_38 H_BREQ# H_BR0# <4>
H_D#39 W2 E9
H_D#_39 H_DEFER# H_DEFER# <4>
H_D#40 AA8 B10
H_D#_40 H_DBSY# H_DBSY# <4>
H_D#41 Y9 AH7
H_D#_41 HPLL_CLK CLK_MCH_BCLK <16>
H_D#42 AA13 AH6
H_D#_42 HPLL_CLK# CLK_MCH_BCLK# <16>
H_D#43 AA9 J11
H_D#_43 H_DPWR# H_DPW R# <5>
H_D#44 AA11 F9
H_D#_44 H_DRDY# H_DRDY# <4>
H_D#45 AD11 H9
H_D#_45 H_HIT# H_HIT# <4>
H_D#46 AD10 E12
H_D#_46 H_HITM# H_HITM# <4>
H_D#47 AD13 H11
H_D#_47 H_LOCK# H_LOCK# <4>
H_D#48 AE12 C9
H_D#_48 H_TRDY# H_TRDY# <4>
H_D#49 AE9
H_D#50 H_D#_49
AA2 H_D#_50
H_D#51 AD8 H_D#_51
Layout Note: H_D#52 AA3 H_D#_52
H_D#53 AD3 J8
H_RCOMP / +H_VREF / H_SWNG H_D#54 AD7
H_D#_53 H_DINV#_0
L3
H_DINV#0 <5>
H_D#_54 H_DINV#_1 H_DINV#1 <5>
trace width and spacing is 10/20 H_D#55 AE14 H_D#_55 H_DINV#_2 Y13 H_DINV#2 <5>
H_D#56 AF3 Y1
H_D#_56 H_DINV#_3 H_DINV#3 <5>
within 100 mils from NB H_D#57 AC1 H_D#_57
H_D#58 AE3 L10
H_D#_58 H_DSTBN#_0 H_DSTBN#0 <5>
H_D#59 AC3 M7
+1.05VS +1.05VS H_D#_59 H_DSTBN#_1 H_DSTBN#1 <5>
H_D#60 AE11 AA5
H_D#61 AE8 AE6
H_D#62 AG2 H_D#_62
1
H_D#63 AD6 L9
H_D#_63 H_DSTBP#_0 H_DSTBP#0 <5>
R22 M8
B H_DSTBP#_1 H_DSTBP#1 <5> B
R21 221_0402_1% AA6
H_DSTBP#_2 H_DSTBP#2 <5>
1K_0402_1% H_SW NG C5 AE5
H_SWING H_DSTBP#_3 H_DSTBP#3 <5>
H_SWING=0.3125*VCCP H_RCOMP E3
1 2
+H_VREF H_RCOMP H_SW NG H_RCOMP

H_REQ#_0 B15 H_REQ#0 <4>
H_REQ#_1 K13 H_REQ#1 <4>
1
1 1 H_REQ#_2 F13 H_REQ#2 <4>

R23 C52 R24 B13
H_REQ#_3 H_REQ#3 <4>
2K_0402_1% 0.1U_0402_16V4Z 24.9_0402_1% R25 C53 C12 B14
<4> H_RESET# H_CPURST# H_REQ#_4 H_REQ#4 <4>
@ 100_0402_1% 0.1U_0402_16V4Z E11
<5> H_CPUSLP#
2
2 2 H_CPUSLP#
B6 H_RS#0 <4>
2
H_RS#_0
H_RS#_1 F12 H_RS#1 <4>
Near B3 pin +H_VREF A11 H_AVREF H_RS#_2 C8 H_RS#2 <4>
B11 H_DVREF
CANTIGA ES_FCBGA1329
GM45R3@
A A

Cantiga GMCH(1/7)-GTL
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
Strap Pin Table
www.rosefix.com
U3B +1.5V
011 = FSB667
CFG[2:0] 010 = FSB800 M36 RSVD1 SA_CK_0 AP24 DDRA_CLK0 <14>
1
000 = FSB1067 N36
RSVD2 SA_CK_1
AT21 DDRA_CLK1 <14>
R33 AV24 R26
RSVD3 SB_CK_0 DDRB_CLK0 <15>
0 = DMI x 2 T33 AU20 1K_0402_1%
RSVD4 SB_CK_1 DDRB_CLK1 <15>
COMPENSATION
CFG5 Internal pull-up 1 = DMI x 4 *(Default) AH9 RSVD5
AH10 AR24 DDRA_CLK0# <14>
2
RSVD6 SA_CK#_0 +SM_RCOMP_VOH
0 = iTPM Host Interface is enabled can support disble by SW. AH12
RSVD7 SA_CK#_1
AR21 DDRA_CLK1# <14>
CFG6 Internal pull-up 1 = iTPM Host Interface is Disabled *(Default) AH13
K12
RSVD8 SB_CK#_0 AU24
AV20
DDRB_CLK0# <15>
RSVD9 SB_CK#_1 DDRB_CLK1# <15> 1 1
1
0 = Intel Management Engine Crypto Transport Layer Security PAD AL34 2.2U_0603_6.3V6K
RSVD10 C54 C55
AK34 BC28 DDRA_CKE0 <14>
(TLS) cipher suite with no confidentiality AN35
RSVD11 SA_CKE_0
AY28 DDRA_CKE1 <14>
0.01U_0402_16V7K R27
D RSVD12 SA_CKE_1 2 2 D
CFG7 Internal pull-up T18 AM35 RSVD13 SB_CKE_0 AY36 DDRB_CKE0 <15> SM_DRAMRST# would be 3.01K_0402_1%
1 = Intel Management Engine Crypto TLS cipher suite with T24 BB36 DDRB_CKE1 <15> needed for DDR3 only
2
RSVD14 SB_CKE_1
confidentiality *(Default) BA17 DDRA_SCS0# <14>
SA_CS#_0 +SM_RCOMP_VOL
AY16 DDRA_SCS1# <14>
SA_CS#_1
0 = Lane Reversal Enable B31 RSVD15 SB_CS#_0 AV16 DDRB_SCS0# <15> For Cantiga 80 Ohm
1
CFG9 Internal pull-up 1 = Normal Operation *(Default) B2
RSVD16 SB_CS#_1
AR13 DDRB_SCS1# <15> 1 1
DDR CLK/ CONTROL/

M1 2.2U_0603_6.3V6K
RSVD17
RSVD
0 = PCIe Loopback Enable BD17 C56 C57 R28
SA_ODT_0 DDRA_ODT0 <14>
CFG10 Internal pull-up 1 = Disable*(Default) SA_ODT_1
AY17 DDRA_ODT1 <14>
0.01U_0402_16V7K 1K_0402_1%
2 2
AY21 BF15 DDRB_ODT0 <15>
2
RSVD20 SB_ODT_O +1.5V +1.5V
01 = All Z Mode Enabled SB_ODT_1
AY13 DDRB_ODT1 <15>
CFG[13:12] 00 = Reserved
SMRCOMP
10 = XOR Mode Enabled BG22 R29 1 2 80.6_0402_1%
SM_RCOMP
2
Internal pull-up 11 = Normal Operation*(Default) BG23 BH21 SMRCOMP# R30 1 2 80.6_0402_1%
RSVD22 SM_RCOMP# R31
BF23
RSVD23 +SM_RCOMP_VOH
0 = Dynamic ODT Disabled BH18 RSVD24 SM_RCOMP_VOH BF28 1K_0402_1%
CFG16 Internal pull-up 1 = Dynamic ODT Enabled *(Default) BF18 BH28 +SM_RCOMP_VOL
RSVD25 SM_RCOMP_VOL
20mil
1
0 = Normal Operation AV42 +SM_VREF
SM_VREF
CFG19 Internal pull-down 1 = DMI Lane Reversal Enable *(Default) SM_PWROK
AR36 DDR3_SM_PWROK <38>
2
BF17 SM_REXT 1 2 1
SM_REXT R33 499_0402_1% R34
CFG20
Internal pull-down
0 = Only PCIE or [SDVO/DP/HDMI] is operational. * (Default) SM_DRAMRST# BC36
C58 1K_0402_1%
SM_DRAMRST# <14,15>
(PCIE/SDVO select) 1 = PCIE/[SDVO/DP/HDMI] are operating simu. 0.1U_0402_16V4Z
CLK_DREF_96M 2 @
B38 CLK_DREF_96M <16>
1
DPLL_REF_CLK CLK_DREF_96M#
A38 CLK_DREF_96M# <16>
DPLL_REF_CLK# CLK_DREF_SSC
E41 CLK_DREF_SSC <16>
DPLL_REF_SSCLK CLK_DREF_SSC#
DPLL_REF_SSCLK# F41 CLK_DREF_SSC# <16>
CLK
F43 CLK_MCH_3GPLL <16>
PEG_CLK
E43 CLK_MCH_3GPLL# <16>
C PEG_CLK# C
DMI_RXN_0 AE41 DMI_ITX_MRX_N0 <19>

DMI_RXN_1 AE37 DMI_ITX_MRX_N1 <19>
AE47 DMI_ITX_MRX_N2 <19>
DMI_RXN_2 +1.05VS
DMI_RXN_3 AH39 DMI_ITX_MRX_N3 <19>
DMI_RXP_0 AE40 DMI_ITX_MRX_P0 <19>

<5,16> CPU_BSEL0
R35 2 1 1K_0402_5% MCH_CLKSEL0 T25 AE38 DMI_ITX_MRX_P1 <19>
CFG_0 DMI_RXP_1
1
R36 2 1 1K_0402_5% MCH_CLKSEL1 R25 AE48 +3VS
<5,16> CPU_BSEL1 CFG_1 DMI_RXP_2 DMI_ITX_MRX_P2 <19>
<5,16> CPU_BSEL2
R37 2 1 1K_0402_5% MCH_CLKSEL2 P25 AH40 DMI_ITX_MRX_P3 <19>
R38
CFG_2 DMI_RXP_3 Lane reversal 1K_0402_5%
T14 PAD P20 CFG_3
T15 PAD MCH_CFG_5 P24 AE35 DMI_MTX_IRX_N0 <19>
CFG_4 DMI_TXN_0
1
R39 2@ 2.21K_0402_1%
DMI
1 C25 AE43 DMI_MTX_IRX_N1 <19>
2
R40 MCH_CFG_6 CFG_5 DMI_TXN_1
1 2@ 2.21K_0402_1% N24 AE46 DMI_MTX_IRX_N2 <19>
R41 R42
R43 MCH_CFG_7 CFG_6 DMI_TXN_2
1 2@ 2.21K_0402_1% M24 AH42 DMI_MTX_IRX_N3 <19>
54.9_0402_1% 1K_0402_5%
CFG_7 DMI_TXN_3
2
CFG
B
E21
R44 MCH_CFG_9 CFG_8
1 2@ 2.21K_0402_1% C23 AD35 DMI_MTX_IRX_P0 <19>
2
CFG_9 DMI_TXP_0
E
R45 1 2@ 2.21K_0402_1% MCH_CFG_10 C24 AE44 MCH_TSATN# 3 1
CFG_10 DMI_TXP_1 DMI_MTX_IRX_P1 <19> MCH_TSATN_EC# <30>
C
N21 AF46 Q7
CFG_11 DMI_TXP_2 DMI_MTX_IRX_P2 <19>
R46 1 2@ 2.21K_0402_1% MCH_CFG_12 P21 AH43 MMBT3904_SOT23-3
MCH_CFG_13 CFG_12 DMI_TXP_3 DMI_MTX_IRX_P3 <19>
R47 1 2@ 2.21K_0402_1% T21
CFG_13
R20
CFG_14
M20
+3VS R48 MCH_CFG_16 CFG_15
1 2@ 2.21K_0402_1% L21
CFG_16
H21 CFG_17
P29
GRAPHICS VID
T16 PAD MCH_CFG_19 CFG_18
R49 1 2 4.02K_0402_1% R28
R50 1 2@ 4.02K_0402_1% MCH_CFG_20 T28
CFG_19
CFG_20 GFX_VID_0
B33 Strap Pin Table
B32
GFX_VID_1
B GFX_VID_2
G33 SDVO_CTRLDATA 0 = SDVO interface disabled *(Default) B
PM_SYNC#_R GFX_VID_3 F33 (Internal pull-down) 1 = SDVO interface enabled
<21> PM_SYNC# R51 1 2 0_0402_5% R29 E33
PM_SYNC# GFX_VID_4
+3VS 1 2 PM_EXTTS#_R <5,20,40> H_DPRSTP# B7 DDPC_CTRLDATA 0 = Digital display (iHDMI/DP) interface disabled *(Default)
R52 10K_0402_5% PM_DPRSTP#
N33 PM_EXT_TS#_0 (Internal pull-down) 1 = Digital display (iHDMI/DP) interface enabled
PM
<14,15> PM_EXTTS# R53 1 2 0_0402_5% PM_EXTTS#_R P32

GMCH_PWROK PM_EXT_TS#_1
AT40 C34
PWROK GFX_VR_EN
<19,25,26,30,31> PLT_RST# R54 1 2 100_0402_5% MCH_RSTIN# AT11
R55 NB_THERMTRIP# RSTIN# +1.05VS
<4,20> H_THERMTRIP# 1 2 0_0402_5% T20
R56 0_0402_5% DPRSLPVR THERMTRIP#
<21,40> PM_DPRSLPVR 1 2 R32
DPRSLPVR
2
BG48 AH37 R57
NC_1 CL_CLK CL_CLK0 <21>
Use VGATE for GMCH_PWROK BF48 AH36 1K_0402_1%
NC_2 CL_DATA CL_DATA0 <21>
ME
BD48 AN36 ICH_PWROK Width:Spacing

GMCH_PWROK NC_3 CL_PWROK
<21,30,40> VGATE 1 2 BC48 AJ35 CL_RST#0 <21> 12mil:12mil CL_VREF
1
R58 @ 0_0402_5% NC_4 CL_RST# +CL_VREF
BH47 AH34 should be
NC_5 CL_VREF
<21,30> ICH_PWROK 1 2 BG47
NC_6
+CL_VREF=0.355V 0.35 V
2
R59 0_0402_5% BE47 1
NC_7 C59 R60
BH46 N28
NC_8 DDPC_CTRLCLK
NC
BF46 M28 0.1U_0402_16V4Z 499_0402_1%

NC_9 DDPC_CTRLDATA SDVO_SCLK
BG45 G36
NC_10 SDVO_CTRLCLK T17 PAD 2
BH44 E36
1
NC_11 SDVO_CTRLDATA
BH43 K36 CLKREQ_3GPLL# <16>
NC_12 CLKREQ#
MISC
BH6 NC_13 ICH_SYNC# H36 MCH_ICH_SYNC# <21>

BH5
NC_14
BG4
NC_15 MCH_TSATN# +3VS
BH3 NC_16 TSATN# B12
BF3
NC_17 SDVO_SCLK 2
BH2 1
NC_18 R61 2.2K_0402_5%
BG2
NC_19
BE2 B28
NC_20 HDA_BCLK
BG1 NC_21 HDA_RST# B30
A A
BF1 B29
NC_22 HDA_SDI
BD1 NC_23 HDA_SDO C29
BC1 A28
HDA
NC_24 HDA_SYNC
F1
NC_25
A47 NC_26
GM45R3@ Security Classification Compal Secret Data Compal Electronics, Inc.
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
www.rosefix.com
D D
<14> DDR_A_D[0..63] <15> DDR_B_D[0..63]
U3D U3E
DDR_A_D0 AJ38 BD21 DDR_B_D0 AK47 BC16
SA_DQ_0 SA_BS_0 DDR_A_BS0 <14> SB_DQ_0 SB_BS_0 DDR_B_BS0 <15>
DDR_A_D1 AJ41 BG18 DDR_B_D1 AH46 BB17
DDR_A_D2 AN38 AT25 DDR_B_D2 AP47 BB33
DDR_A_D3 AM38 DDR_B_D3 AP46
DDR_A_D4 SA_DQ_3 DDR_B_D4 SB_DQ_3
AJ36 SA_DQ_4 SA_RAS# BB20 DDR_A_RAS# <14> AJ46 SB_DQ_4
DDR_A_D5 AJ40 BD20 DDR_B_D5 AJ48 AU17
SA_DQ_5 SA_CAS# DDR_A_CAS# <14> SB_DQ_5 SB_RAS# DDR_B_RAS# <15>
DDR_A_D6 AM44 AY20 DDR_B_D6 AM48 BG16
SA_DQ_6 SA_WE# DDR_A_W E# <14> SB_DQ_6 SB_CAS# DDR_B_CAS# <15>
DDR_A_D7 AM42 DDR_B_D7 AP48 BF14
SA_DQ_7 SB_DQ_7 SB_WE# DDR_B_W E# <15>
DDR_A_D8 AN43 DDR_B_D8 AU47
AN44 SA_DQ_9 AU46 SB_DQ_9
DDR_A_D10 AU40 DDR_B_D10 BA48
AT38 SA_DQ_11 DDR_A_DM[0..7] <14> AY48 SB_DQ_11
DDR_A_D12 AN41 DDR_B_D12 AT47
DDR_A_D13 SA_DQ_12 DDR_A_DM0 DDR_B_D13 SB_DQ_12
AN39 SA_DQ_13 SA_DM_0 AM37 AR47 SB_DQ_13
DDR_A_D14 AU44 AT41 DDR_A_DM1 DDR_B_D14 BA47
SA_DQ_14 SA_DM_1 SB_DQ_14 DDR_B_DM[0..7] <15>
DDR_A_D15 AU42 AY41 DDR_A_DM2 DDR_B_D15 BC47 AM47 DDR_B_DM0
DDR_A_D16 SA_DQ_15 SA_DM_2 DDR_A_DM3 DDR_B_D16 SB_DQ_15 SB_DM_0 DDR_B_DM1
AV39 SA_DQ_16 SA_DM_3 AU39 BC46 SB_DQ_16 SB_DM_1 AY47
DDR_A_D17 AY44 BB12 DDR_A_DM4 DDR_B_D17 BC44 BD40 DDR_B_DM2
BA40 SA_DQ_18 SA_DM_5 AY6 BG43 SB_DQ_18 SB_DM_3 BF35
DDR_A_D19 BD43 AT7 DDR_A_DM6 DDR_B_D19 BF43 BG11 DDR_B_DM4
AV41 SA_DQ_20 SA_DM_7 AJ5 BE45 SB_DQ_20 SB_DM_5 BA3
DDR_A_D21 AY43 DDR_B_D21 BC41 AP1 DDR_B_DM6
B
SA_DQ_21 SB_DQ_21 SB_DM_6
A
DDR_A_D22 BB41 DDR_B_D22 BF40 AK2 DDR_B_DM7
SA_DQ_22 DDR_A_DQS[0..7] <14> SB_DQ_22 SB_DM_7
DDR_A_D23 BC40 AJ44 DDR_A_DQS0 DDR_B_D23 BF41
DDR_A_D24 SA_DQ_23 SA_DQS_0 DDR_A_DQS1 DDR_B_D24 SB_DQ_23
AY37 SA_DQ_24 SA_DQS_1 AT44 BG38 SB_DQ_24 DDR_B_DQS[0..7] <15>
DDR_A_D25 BD38 BA43 DDR_A_DQS2 DDR_B_D25 BF38 AL47 DDR_B_DQS0
SA_DQ_25 SA_DQS_2 SB_DQ_25 SB_DQS_0
MEMORY
C DDR_A_D26 AV37 BC37 DDR_A_DQS3 DDR_B_D26 BH35 AV48 DDR_B_DQS1 C
MEMORY
DDR_A_D27 SA_DQ_26 SA_DQS_3 DDR_A_DQS4 DDR_B_D27 SB_DQ_26 SB_DQS_1 DDR_B_DQS2
AT36 SA_DQ_27 SA_DQS_4 AW12 BG35 SB_DQ_27 SB_DQS_2 BG41
DDR_A_D28 AY38 BC8 DDR_A_DQS5 DDR_B_D28 BH40 BG37 DDR_B_DQS3
DDR_A_D29 SA_DQ_28 SA_DQS_5 DDR_A_DQS6 DDR_B_D29 SB_DQ_28 SB_DQS_3 DDR_B_DQS4
BB38 SA_DQ_29 SA_DQS_6 AU8 BG39 SB_DQ_29 SB_DQS_4 BH9
DDR_A_D30 AV36 AM7 DDR_A_DQS7 DDR_B_D30 BG34 BB2 DDR_B_DQS5
DDR_A_D31 SA_DQ_30 SA_DQS_7 DDR_B_D31 SB_DQ_30 SB_DQS_5 DDR_B_DQS6
AW36 SA_DQ_31 BH34 SB_DQ_31 SB_DQS_6 AU1
DDR_A_D32 BD13 DDR_B_D32 BH14 AN6 DDR_B_DQS7
SA_DQ_32 DDR_A_DQS#[0..7] <14> SB_DQ_32 SB_DQS_7
DDR_A_D33 AU11 AJ43 DDR_A_DQS#0 DDR_B_D33 BG12
DDR_A_D34 SA_DQ_33 SA_DQS#_0 SB_DQ_33
BC11 SA_DQ_34 SA_DQS#_1 AT43 DDR_A_DQS#1 DDR_B_D34 BH11 SB_DQ_34 DDR_B_DQS#[0..7] <15>
DDR_A_D35 BA12 BA44 DDR_A_DQS#2 DDR_B_D35 BG8 AL46 DDR_B_DQS#0
SA_DQ_35 SA_DQS#_2 SB_DQ_35 SB_DQS#_0
SYSTEM
DDR_A_D36 BD37 DDR_A_DQS#3 DDR_B_D36 AV47 DDR_B_DQS#1
SYSTEM
AU13 SA_DQ_36 SA_DQS#_3 BH12 SB_DQ_36 SB_DQS#_1

DDR_A_D37 AV13 AY12 DDR_A_DQS#4 DDR_B_D37 BF11 BH41 DDR_B_DQS#2
DDR_A_D38 SA_DQ_37 SA_DQS#_4 SB_DQ_37 SB_DQS#_2
BD12 SA_DQ_38 SA_DQS#_5 BD8 DDR_A_DQS#5 DDR_B_D38 BF8 SB_DQ_38 SB_DQS#_3 BH37 DDR_B_DQS#3
DDR_A_D39 BC12 AU9 DDR_A_DQS#6 DDR_B_D39 BG7 BG9 DDR_B_DQS#4
DDR_A_D40 SA_DQ_39 SA_DQS#_6 SB_DQ_39 SB_DQS#_4
BB9 SA_DQ_40 SA_DQS#_7 AM8 DDR_A_DQS#7 DDR_B_D40 BC5 SB_DQ_40 SB_DQS#_5 BC2 DDR_B_DQS#5
DDR_A_D41 BA9 DDR_B_D41 BC6 AT2 DDR_B_DQS#6
DDR_A_D42 SA_DQ_41 DDR_B_D42 SB_DQ_41 SB_DQS#_6
AU10 SA_DQ_42 DDR_A_MA[0..14] <14> AY3 SB_DQ_42 SB_DQS#_7 AN5 DDR_B_DQS#7
DDR_A_D43 AV9 DDR_B_D43 AY1
DDR_A_D44 SA_DQ_43 DDR_A_MA0 DDR_B_D44 SB_DQ_43
BA11 SA_DQ_44 SA_MA_0 BA21 BF6 SB_DQ_44 DDR_B_MA[0..14] <15>
DDR_A_D45 BD9 BC24 DDR_A_MA1 DDR_B_D45 BF5 AV17 DDR_B_MA0
DDR
SA_DQ_45 SA_MA_1 SB_DQ_45 SB_MA_0
DDR
DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D46 BA1 BA25 DDR_B_MA1

DDR_A_D47 SA_DQ_46 SA_MA_2 DDR_A_MA3 DDR_B_D47 SB_DQ_46 SB_MA_1 DDR_B_MA2
BA6 SA_DQ_47 SA_MA_3 BH24 BD3 SB_DQ_47 SB_MA_2 BC25
DDR_A_D48 AV5 BG25 DDR_A_MA4 DDR_B_D48 AV2 AU25 DDR_B_MA3
AV7 SA_DQ_49 SA_MA_5 BA24 AU3 SB_DQ_49 SB_MA_4 AW25
DDR_A_D50 AT9 BD24 DDR_A_MA6 DDR_B_D50 AR3 BB28 DDR_B_MA5
AN8 SA_DQ_51 SA_MA_7 BG27 AN2 SB_DQ_51 SB_MA_6 AU28
DDR_A_D52 AU5 BF25 DDR_A_MA8 DDR_B_D52 AY2 AW28 DDR_B_MA7
AU6 SA_DQ_53 SA_MA_9 AW24 AV1 SB_DQ_53 SB_MA_8 AT33
DDR_A_D54 AT5 BC21 DDR_A_MA10 DDR_B_D54 AP3 BD33 DDR_B_MA9
B DDR_A_D55 SA_DQ_54 SA_MA_10 DDR_A_MA11 DDR_B_D55 SB_DQ_54 SB_MA_9 DDR_B_MA10 B
AN10 SA_DQ_55 SA_MA_11 BG26 AR1 SB_DQ_55 SB_MA_10 BB16
DDR_A_D56 AM11 BH26 DDR_A_MA12 DDR_B_D56 AL1 AW33 DDR_B_MA11
AM5 SA_DQ_57 SA_MA_13 BH17 AL2 SB_DQ_57 SB_MA_12 AY33
DDR_A_D58 AJ9 AY25 DDR_A_MA14 DDR_B_D58 AJ1 BH15 DDR_B_MA13
DDR_A_D59 SA_DQ_58 SA_MA_14 DDR_B_D59 SB_DQ_58 SB_MA_13 DDR_B_MA14
AJ8 SA_DQ_59 AH1 SB_DQ_59 SB_MA_14 AU33
DDR_A_D60 AN12 DDR_B_D60 AM2
AM13 SA_DQ_61 AM3 SB_DQ_61
DDR_A_D62 AJ11 DDR_B_D62 AH3
AJ12 SA_DQ_63 AJ3 SB_DQ_63
CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329
GM45R3@ GM45R3@
A A

0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
+3VS
1
R64
1
R66
1
www.rosefix.com
2
10K_0402_5%
2
10K_0402_5%
2
LCTLA_CLK
LCTLB_DATA
Reserve
<17> NB_PW M
<30> UMA_ENBKL
UMA_LCD_EDID_CLK <17> UMA_LCD_EDID_CLK

LCTLA_CLK
LCTLB_DATA
L32
G32
M32
M33
UMA_LCD_EDID_CLK K33
U3C
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
PEG_COMPI
PEG_COMPO
T37
T36
within 500 mils
PEG_COMP 1
R65
10mils
2
49.9_0402_1%
+1.05VS
R67 2.2K_0402_5% <17> UMA_LCD_EDID_DATA UMA_LCD_EDID_DATAJ33 H44

UMA_LCD_EDID_DATA UMA_ENVDD L_DDC_DATA PEG_RX#_0
1 2 <17> UMA_ENVDD M29 L_VDD_EN PEG_RX#_1 J46
R68 2.2K_0402_5% L44
R69 1 PEG_RX#_2
2 LVDS_IBG C44 LVDS_IBG PEG_RX#_3 L40
D 2.37K_0402_1% Spacing=20mil B43 N41 D
R501 1 LVDS_VBG PEG_RX#_4
2 0_0402_5% E37 LVDS_VREFH PEG_RX#_5 P48
L_DDC_DATA R502 1 2 0_0402_5% E38 N44
LVDS_VREFL PEG_RX#_6
PEG_RX#_7 T43
0 = LFP Disable *(Default) <17> UMA_LCD_TXCLK- C41 LVDSA_CLK# PEG_RX#_8 U43
1 = LFP Card Present; PCIE disable <17> UMA_LCD_TXCLK+ C40 LVDSA_CLK PEG_RX#_9 Y43
B37 LVDSB_CLK# PEG_RX#_10 Y48
A37 LVDSB_CLK PEG_RX#_11 Y36
LVDS
PEG_RX#_12 AA43
<17> UMA_LCD_TXOUT0- H47 LVDSA_DATA#_0 PEG_RX#_13 AD37
<17> UMA_LCD_TXOUT1- E46 LVDSA_DATA#_1 PEG_RX#_14 AC47
<17> UMA_LCD_TXOUT2- G40 LVDSA_DATA#_2 PEG_RX#_15 AD39
A40 LVDSA_DATA#_3
PEG_RX_0 H43
<17> UMA_LCD_TXOUT0+ H48 LVDSA_DATA_0 PEG_RX_1 J44
<17> UMA_LCD_TXOUT1+ D45 LVDSA_DATA_1 PEG_RX_2 L43
GRAPHICS
<17> UMA_LCD_TXOUT2+ F40 LVDSA_DATA_2 PEG_RX_3 L41
B40 LVDSA_DATA_3 PEG_RX_4 N40
PEG_RX_5 P47
A41 LVDSB_DATA#_0 PEG_RX_6 N43
H38 LVDSB_DATA#_1 PEG_RX_7 T42
G37 LVDSB_DATA#_2 PEG_RX_8 U42
J37 LVDSB_DATA#_3 PEG_RX_9 Y42
PEG_RX_10 W47
B42 LVDSB_DATA_0 PEG_RX_11 Y37
G38 LVDSB_DATA_1 PEG_RX_12 AA42
F37 LVDSB_DATA_2 PEG_RX_13 AD36
K37 LVDSB_DATA_3 PEG_RX_14 AC48
PCI-EXPRESS
PEG_RX_15 AD40
C C
PEG_TX#_0 J41
1 2 TV_COMPS PEG_TX#_1 M46
R70 75_0402_1% TV_COMPS F25 M47
TVA_DAC PEG_TX#_2
1 2 TV_LUMA TV_LUMA H25 TVB_DAC PEG_TX#_3 M40
R71 75_0402_1% TV_CRMA K25 M42
TVC_DAC PEG_TX#_4
1 2 TV_CRMA PEG_TX#_5 R48
TV
R72 75_0402_1% H24 N38
TV_RTN PEG_TX#_6
PEG_TX#_7 T40
PEG_TX#_8 U37
PEG_TX#_9 U40
C31 TV_DCONSEL_0 PEG_TX#_10 Y40
E32 TV_DCONSEL_1 PEG_TX#_11 AA46
PEG_TX#_12 AA37
PEG_TX#_13 AA40
1 2 UMA_CRT_B AD43
R73 150_0402_1% PEG_TX#_14
PEG_TX#_15 AC46
1 2 UMA_CRT_G
R74 150_0402_1% UMA_CRT_B E28 J42
<18> UMA_CRT_B CRT_BLUE PEG_TX_0
1 2 UMA_CRT_R L46
R75 150_0402_1% UMA_CRT_G PEG_TX_1
<18> UMA_CRT_G G28 CRT_GREEN PEG_TX_2 M48
PEG_TX_3 M39
VGA
UMA_CRT_R J28 M43
<18> UMA_CRT_R CRT_RED PEG_TX_4
PEG_TX_5 R47
+3VS G29 N37
R76 2.2K_0402_5% CRT_IRTN PEG_TX_6
PEG_TX_7 T39
1 2 UMA_CRT_CLK UMA_CRT_CLK H32 U36
<18> UMA_CRT_CLK CRT_DDC_CLK PEG_TX_8
R77 2.2K_0402_5% UMA_CRT_DATA J32 U39
<18> UMA_CRT_DATA CRT_DDC_DATA PEG_TX_9
1 2 UMA_CRT_DATA UMA_CRT_HSYNC J29 Y39
B <18> UMA_CRT_HSYNC CRT_HSYNC PEG_TX_10 B
2 1UMA_CRT_IREF E29 CRT_TVO_IREF PEG_TX_11 Y46
R78 1.02K_0402_1% AA36
PEG_TX_12
PEG_TX_13 AA39
UMA_CRT_VSYNC L29 AD42
<18> UMA_CRT_VSYNC CRT_VSYNC PEG_TX_14
PEG_TX_15 AD46
GM45R3@
A A

0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
www.rosefix.com
+1.5V
DDR PWR
10U_0805_10V4Z
AP33
AN33
BH32
U3F
DDR2,667MHz,2600mA
DDR2,800MHz,3000mA
VCC_SM_1
VCC_SM_2
VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
W28
V28
W26
V26
+1.05VS
Int. Graphic
Extnal Graphic: 1210.34mA
integrated Graphic: 1930.4mA
Intel Management Engine Link:508.12mA
VCC_SM_3 VCC_AXG_NCTF_4
BG32 W25
BF32 VCC_SM_5 VCC_AXG_NCTF_6 V25
390U_2.5V_M_R10
1 BD32 W24
1 1 1 BC32 VCC_SM_7 VCC_AXG_NCTF_8 V24
D C78 + BB32 W23 +1.05VS NB Core,Intel Management Engine Link U3G D
VCC
C69 C70 C71 BA32 V23
VCC_SM_9 VCC_AXG_NCTF_10 0.22U_0402_10V4Z 0.1U_0402_16V4Z
AY32 VCC_SM_10 VCC_AXG_NCTF_11 AM21 AG34 VCC_1
2 2 2 2 AW32 AL21 AC34
VCC_SM_11 VCC_AXG_NCTF_12 1 1 VCC_2
AV32 AK21 C72 @ C73 1 1 1 1 AB34
VCC_SM_12 VCC_AXG_NCTF_13 + + VCC_3
AU32 VCC_SM_13 VCC_AXG_NCTF_14 W21 AA34 VCC_4
10U_0805_10V4Z 0.1U_0402_16V4Z AT32 V21 C74 C75 C76 C77 Y34
SM
VCC_SM_14 VCC_AXG_NCTF_15 VCC_5
AR32 U21 V34
VCC CORE
VCC_SM_15 VCC_AXG_NCTF_16 2 330U_6.3V_M_R15
2 330U_6.3V_M_R15
2 2 2 2 VCC_6
AP32 VCC_SM_16 VCC_AXG_NCTF_17 AM20 U34 VCC_7
AN32 AK20 10U_0805_10V4Z 0.22U_0402_10V4Z AM33
BH31 VCC_SM_18 VCC_AXG_NCTF_19 W20 Intel: VCC -- 220U*2, ESR 12mOhm AK33 VCC_9
BG31 U20 AJ33
BF31 VCC_SM_20 VCC_AXG_NCTF_21 AM19 AG33 VCC_11
BG30 AL19 AF33
BH29 AK19
BG29 AJ19
BF29 VCC_SM_24 VCC_AXG_NCTF_25 AH19
BD29 AG19 AE33
BC29 VCC_SM_26 VCC_AXG_NCTF_27 AF19 AC33 VCC_14
BB29 AE19 AA33
BA29 AB19 Y33
AY29 AA19 W33
AW29 Y19 V33
GFX NCTF
POWER
AV29 VCC_SM_31 VCC_AXG_NCTF_32 W19 U33 VCC_19
AU29 V19 AH28
AT29 VCC_SM_33 VCC_AXG_NCTF_34 U19 AF28 VCC_21
AR29 AM17 AC28
AP29 AK17 AA28
VCC_AXG_NCTF_37 AH17 AJ26 VCC_24
VCC_AXG_NCTF_38 AG17 AG26 VCC_25
AF17 AE26
VCC_AXG_NCTF_39 VCC_26
BA36 AE17 AC26
C VCC_SM_36/NC VCC_AXG_NCTF_40 VCC_27 +1.05VS C
BB24 VCC_SM_37/NC VCC_AXG_NCTF_41 AC17 AH25 VCC_28
VCC
BD16 AB17 AG25
VCC_SM_38/NC VCC_AXG_NCTF_42 VCC_29
BB21 Y17 AF25
VCC_SM_39/NC VCC_AXG_NCTF_43 VCC_30
AW16 VCC_SM_40/NC VCC_AXG_NCTF_44 W17 AG24 VCC_31 VCC_NCTF_1 AM32
AW13 VCC_SM_41/NC VCC_AXG_NCTF_45 V17 AJ23 VCC_32 VCC_NCTF_2 AL32
AT13 AM16 AH23 AK32
VCC_SM_42/NC VCC_AXG_NCTF_46 VCC_33 VCC_NCTF_3
VCC_AXG_NCTF_47 AL16 AF23 VCC_34 VCC_NCTF_4 AJ32
AK16 T32 AH32
VCC_AXG_NCTF_48 VCC_35 VCC_NCTF_5
POWER
VCC_AXG_NCTF_49 AJ16 VCC_NCTF_6 AG32
AH16 AE32
VCC_AXG_NCTF_50 VCC_NCTF_7
8700mA VCC_AXG_NCTF_51 AG16 VCC_NCTF_8 AC32
AF16 AA32
VCC_AXG_NCTF_52 VCC_NCTF_9
Y26 VCC_AXG_1 VCC_AXG_NCTF_53 AE16 VCC_NCTF_10 Y32
AE25 AC16 W32
VCC_AXG_2 VCC_AXG_NCTF_54 VCC_NCTF_11
For layout placement un-mound C123 and mound C84 AB25
VCC_AXG_3 VCC_AXG_NCTF_55
AB16
VCC_NCTF_12
U32
AA25 AA16 AM30
Int. Graphic AE24
VCC_AXG_5 VCC_AXG_NCTF_57
Y16
VCC_NCTF_14
AL30
AC24 W16 AK30
+1.05VS +1.05VS VCC_AXG_6 VCC_AXG_NCTF_58 VCC_NCTF_15
AA24 V16 AH30
Y24 VCC_AXG_8 VCC_AXG_NCTF_60 U16 VCC_NCTF_17 AG30
10U_0805_10V4Z 0.47U_0603_10V7K 0.1U_0402_16V4Z AE23 AF30
VCC_AXG_9 VCC_NCTF_18
1 AC23 AE30
C225 VCC_AXG_10 VCC_NCTF_19
1 1 1 1 1 1 AB23 AC30
NCTF
+ VCC_AXG_11 VCC_NCTF_20
AA23 AB30
330U_6.3V_M_R15 C85 C86 C87 C88 C89 C90 VCC_AXG_12 VCC_NCTF_21
AJ21 AA30
AG21 Y30
2 2 2 2 2 2 2 VCC_AXG_14 VCC_NCTF_23
AE21 VCC_AXG_15 VCC_NCTF_24 W30
10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z AC21 V30
AA21 U30
VCC
Intel:AXG and AXG_NCTF -- 220U*2, ESR 15mOhm Y21
AL29
VCC
AH20 AK29
For layout issue to separate 220u*1 to +1.05VS VCC_AXG_19 VCC_NCTF_28
AF20 AJ29
B VCC_AXG_20 VCC_NCTF_29 B
AE20 VCC_AXG_21 VCC_NCTF_30 AH29
AC20 VCC_AXG_22 VCC_NCTF_31 AG29
AB20 AE29
AA20 AC29
GFX
T17 AA29
T16 Y29
AM15 W29
AL15 V29
AE15 AL28
AJ15 VCC_AXG_30 VCC_NCTF_39 AK28
AH15 VCC_AXG_31 VCC_NCTF_40 AL26
AG15 AK26
AF15 VCC_AXG_33 VCC_NCTF_42 AK25
AB15 AK24
AA15 VCC_AXG_35 VCC_NCTF_44 AK23
Y15
VCC_AXG_36
V15
VCC_AXG_37
U15
VCC_AXG_38
AN14
VCC_AXG_39
AM14
VCC_AXG_40
U14 AV44 VCCSM_LF1
VCC SM LF
VCC_AXG_41 VCC_SM_LF1
T14 VCC_AXG_42 VCC_SM_LF2 BA37 VCCSM_LF2
AM40 VCCSM_LF3
VCC_SM_LF3
VCC_SM_LF4 AV21 VCCSM_LF4
AY5 VCCSM_LF5 CANTIGA ES_FCBGA1329
VCC_SM_LF5
PAD T3 AJ14 AM10 VCCSM_LF6 GM45R3@
VCC_AXG_SENSE VCC_SM_LF6
PAD T4 AH14 VSS_AXG_SENSE VCC_SM_LF7 BB13 VCCSM_LF7
1 1 C93 1 1 C95 1 1 C96 1
0.22U_0603_10V7K 0.47U_0603_10V7K 1U_0402_6.3V4Z
C91 C92 C94 C97

0.1U_0402_16V4Z 2 2 0.1U_0402_16V4Z 2 2 0.22U_0603_10V7K 2 2 1U_0402_6.3V4Z 2
A A
GM45R3@

0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
+3VS_TVCRT_DACBG
2
CRT
R80 1
0_0603_5% 1
C99
2
0.1U_0402_16V4Z
+3VS_TVCRT_DAC
0.01U_0402_25V4Z
1
C100
2
www.rosefix.com
Pin B27
R81,R82,PN change to SM01000DR00
+3VS_TVCRT_DACBG
C101
2
0.01U_0402_25V4Z
1
C102
0.1U_0402_16V4Z
1
2
TV
Pin A25
GNDtoB25
+3VS
2
R79
1
C98
+3VS_TVCRT_DACBG
BLM18PG181SN1D_0603 1
10U_0805_10V4Z
2
B27
U3H
73mA
FSB=1067Mhz,852mA
VTT_1
U13
T13
AGTL+
+1.05VS
+3VS_TVCRT_DAC VCCA_CRT_DAC_1 VTT_2 1

,footprint no change A26 U12 1 1 1 1 @ C103
VCCA_CRT_DAC_2 VTT_3 +
VTT_4 T12
+1.05VS +1.05VS_DPLLA +1.05VS +1.05VS_DPLLB U11 C104 C105 C106 C107
VTT_5
R81 R82 5mA VTT_6 T11 0.47U_0603_10V7K
2 2
2.2U_0603_6.3V6K 4.7U_0805_10V4Z
2 2
4.7U_0805_10V4Z
2 330U_6.3V_M_R15
CRT
D 10U_0805_10V4Z 10U_0805_10V4Z D
2 1 2 1 +3VS_TVCRT_DACBG A25 VCCA_DAC_BG VTT_7 U10
10U_FLC-453232-100K_0.25A_10%
1 10U_FLC-453232-100K_0.25A_10%
1 T10 Intel: VTT 270U*1 ESR 12mOhm
VTT_8
1 1 1 1 B25 VSSA_DAC_BG VTT_9 U9
C108 + C109 + T9
220U_B2_2.5VM C110 C111 220U_B2_2.5VM C112 C113 VTT_10
U8
@ VTT_11
2 2 2
Pin F47 @
2 2 2
Pin L48 VTT_12 T8
VTT
VCCA_DPLLA64.8mA
+1.05VS_DPLLA F47 U7
0.1U_0402_16V4Z 0.1U_0402_16V4Z VTT_13
VTT_14 T7
+1.05VS_DPLLB L48 VCCA_DPLLB64.8mA VTT_15 U6
T6
VTT_16
PLL
+1.05VS +1.05VS_AHPLL +1.05VS +1.05VS_MPLL +1.05VS_AHPLL AD1 VCCA_HPLL 24mA VTT_17 U5
T5
+1.8V_TXLVDS VTT_18
VCCA_MPLL 139.2mA
R83 R84 +1.05VS_MPLL AE1 V3
VTT_19
2 1 2 1 LVDS VTT_20
U3
KC FBM-L11-160808-121LMT
1 0603 1 MBK2012121YZF_0805 1 1 13.2mA VTT_21
V2
A PEG A LVDS
1 2 C117 +1.8V_TXLVDS J48 U2
C115 C116 C114 R85 0.5_0805_1% C118 VCCA_LVDS VTT_22
VTT_23 T2
4.7U_0805_10V4Z 10U_0805_10V4Z Pin AE12 1000P_0402_50V7K J47 V1
2 0.1U_0402_16V4Z
2 2 VSSA_LVDS VTT_24
Pin J48 VTT_25 U1
+1.05VS
Pin AD1 0.1U_0402_16V4Z GND to J47 414uA +1.05VS_AXF
+1.5VS_PEG_BG AD48
VCCA_PEG_BG NB I/O R86
1 2
2 1 0_0603_5%
+1.5VS_PEG_BG +1.05VS_PEGPLL
50mA C119
PCIe&DMI +1.05VS_PEGPLL AA48
VCCA_PEG_PLL
C120
1U_0402_6.3V4Z 10U_0805_10V4Z
1 2 1 2 @
+1.5VS 1
R87 0_0603_5% 1 667MTs,480mA
C121 Pin B22
C122 0.1U_0402_16V4Z
800MTs,720mA
0.1U_0402_16V4Z 2
PCIe&DMI AR20
VCCA_SM_1
POWER
2
C
Pin AD48 Pin AA48 DDR3 +1.05VS_A_SM
AP20
VCCA_SM_2 +1.5V_SM_CK C
+1.05VS AN20 DDR2 +1.5V
R88 VCCA_SM_3
AR17
VCCA_SM_4 Host Interface I/O and HSIO R89
A SM
1 2 4.7U_0805_10V4Z AP17
VCCA_SM_5 321.35mA 1 2
0_0805_5% 1 1 1 AN17 B22 +1.05VS_AXF 1 1 0_0805_5%
VCCA_SM_6 VCC_AXF_1
AXF
AT16 VCCA_SM_7 VCC_AXF_2 B21
C124 C125 C126 AR16 A21 C127 R90 C128
VCCA_SM_8 VCC_AXF_3 0.1U_0402_16V4Z 1_0805_1% 10U_0805_10V4Z
AP16 VCCA_SM_9
2 2 2 2 2 @
DDR2,667MHz,119.85mA C129
10U_0805_10V4Z 1U_0402_6.3V4Z Pin BF21
DDR2,800MHz,124mA
Pin AR20 1 2
VCC_SM_CK_1 BF21 +1.5V_SM_CK
SM CK
667MTs,24mA VCC_SM_CK_2
BH20 10U_0805_10V4Z
800MTs,26mA VCC_SM_CK_3 BG20
DDR3 BF20 +1.8V_TXLVDS +1.8V
+1.05VS +1.05VS_A_SM_CK VCC_SM_CK_4
AP28
VCCA_SM_CK_1 LVDS R91
R92 AN28 1 2
0.1U_0402_16V4Z VCCA_SM_CK_2
11 2 AP25
VCCA_SM_CK_3 1 1 0_0603_5%
0_0603_5% 1 1 1 AN25
VCCA_SM_CK_4 118.8mA
C155 AN24 K47 +1.8V_TXLVDS C130 C131
VCCA_SM_CK_5 VCC_TX_LVDS
A CK
1U_0402_6.3V4Z C132 C133 C134 AM28 1000P_0402_50V7K 10U_0805_10V4Z
2 VCCA_SM_CK_NCTF_1 2 2
AM26
10U_0805_10V4Z 2 2 2 VCCA_SM_CK_NCTF_2
2.2U_0603_6.3V4Z AM25
VCCA_SM_CK_NCTF_3 105.3mA Pin K47
AL25 C35 +3VS
+3VS_TVCRT_DAC VCCA_SM_CK_NCTF_4 VCC_HV_1
TV Pin AP28 AM24
VCCA_SM_CK_NCTF_5 VCC_HV_2
B35
HV
AL24 A35
0.01U_0402_25V4Z VCCA_SM_CK_NCTF_6 VCC_HV_3 D3
AM23
VCCA_SM_CK_NCTF_7
1 1 AL23 VCCA_SM_CK_NCTF_8 +3VS 2 R93 1 1 2 +1.05VS
1782mA 1 10_0603_5%
C135 C136 V48 +1.05VS C137 CH751H-40PT_SOD323-2
0.1U_0402_16V4Z VCC_PEG_1
2 2
Pin B24 VCC_PEG_2
U48 0.1U_0402_16V4Z
PEG
VCC_PEG_3
V47
2
Pin C35
B
79mA VCC_PEG_4
U47
B
B24 VCCA_TV_DAC_1 VCC_PEG_5 U46
+3VS_TVCRT_DAC A24 VCCA_TV_DAC_2
TV
+1.5VS +1.5VS_TVDAC +1.5VS +1.5VS_QDAC R94 50mA 456mA
R95 TV R96 TV 1 2 A32 AH48 +1.05VS
VCC_HDA VCC_DMI_1 +1.05VS
HDA
2 1 0.1U_0402_16V4Z 2 1 0.01U_0402_25V4Z 0_0402_5% AF48 PCIe&DMI
VCC_DMI_2
DMI
0_0603_5% 1 1 1 0_0603_5% 1 1 AH47
VCC_DMI_3 10U_0805_10V4Z
AG47
VCC_DMI_4
C139 C140 C141 C142 C143 35mA 1 1
@ 10U_0805_10V4Z Pin M25 0.1U_0402_16V4Z Pin L282 +1.5VS_TVDAC M25
2 2 2 2 VCCD_TVDAC
D TV/CRT
C144 C145
VCCD_QDAC500uA
0.01U_0402_25V4Z +1.5VS_QDAC L28
2
10U_0805_10V4Z 2
157.2mA Pin V48
+1.05VS_DHPLL AF1
VCCD_HPLL VTTLF1
+1.05VS +1.05VS_DHPLL
50mA VTTLF1
A8
AA47 L1 VTTLF2
+1.05VS_PEGPLL VCCD_PEG_PLL VTTLF2
VTTLF
R98 AB2 VTTLF3 PCIe&DMI
VTTLF3 +1.05VS
1 2 60.31mA 1 1 1
0_0402_5% 2 M38
VCCD_LVDS_1
LVDS
+1.8V_LVDS L37 C147 C148 C149 1

C150 VCCD_LVDS_2 0.47U_0603_10V7K 0.47U_0603_10V7K 0.47U_0603_10V7K C151
Pin AF1 2 2 2 0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CANTIGA ES_FCBGA1329 2
Pin AH48
GM45R3@
+1.05VS PCIe&DMI +1.05VS_PEGPLL

A L1 +1.8V_LVDS A
2 1 0.1U_0402_16V4Z R99 LVDS
BLM18PG121SN1D_0603 1 +1.8V 2 1
0_0603_5% 1
R100 C152
1_0805_1% C153
2 1U_0402_6.3V4Z
2 1 C154 2
10U_0805_10V4Z Pin AA47 Pin M38
Crestline GMCH (6/7)-VCC
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
www.rosefix.com
U3I U3J
AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

AR48 AE36 L12 Y8
VSS_2 VSS_101 VSS_200 VSS_298
AL48 VSS_3 VSS_102 P36 AW21 VSS_201 VSS_299 L8
BB47 VSS_4 VSS_103 L36 AU21 VSS_202 VSS_300 E8
AW47 VSS_5 VSS_104 J36 AP21 VSS_203 VSS_301 B8
AN47 VSS_6 VSS_105 F36 AN21 VSS_204 VSS_302 AY7
AJ47 B36 AH21 AU7
AF47 VSS_8 VSS_107 AH35 AF21 VSS_206 VSS_304 AN7
AD47 AA35 AB21 AJ7
AB47 VSS_10 VSS_109 Y35 R21 VSS_208 VSS_306 AE7
Y47 U35 M21 AA7
T47 VSS_12 VSS_111 T35 J21 VSS_210 VSS_308 N7
D D
N47 VSS_13 VSS_112 BF34 G21 VSS_211 VSS_309 J7
L47 VSS_14 VSS_113 AM34 BC20 VSS_212 VSS_310 BG6
G47 VSS_15 VSS_114 AJ34 BA20 VSS_213 VSS_311 BD6
BD46 AF34 AW20 AV6
BA46 AE34 AT20 AT6
AY46 VSS_18 VSS_117 W34 AJ20 VSS_216 VSS_314 AM6
AV46 B34 AG20 M6
AR46 VSS_20 VSS_119 A34 Y20 VSS_218 VSS_316 C6
AM46 VSS_21 VSS_120 BG33 N20 VSS_219 VSS_317 BA5
V46 BC33 K20 AH5
R46 VSS_23 VSS_122 BA33 F20 VSS_221 VSS_319 AD5
P46 AV33 C20 Y5
H46 VSS_25 VSS_124 AR33 A20 VSS_223 VSS_321 L5
F46 AL33 BG19 J5
BF44 AH33 A18 H5
AH44 AB33 BG17 F5
AD44 VSS_29 VSS_128 P33 BC17 VSS_227 VSS_325 BE4
AA44 L33 AW17
VSS_30 VSS_129 VSS_228
Y44 VSS_31 VSS_130 H33 AT17 VSS_229 VSS_327 BC3
U44 N32 R17 AV3
T44 K32 M17 AL3
M44 F32 H17 R3
F44
BC43
VSS_35
VSS_36
VSS_134
VSS_135
C32
A31
C17 VSS_233 VSS VSS_331
VSS_332
P3
F3
AV43 AN29 BA16 BA2
AU43 VSS_38 VSS_137 T29 VSS_334 AW2
AM43 N29 AU16 AU2
J43 K29 AN16 AR2
C43 VSS_41 VSS_140 H29 N16 VSS_239 VSS_337 AP2
BG42
AY42
VSS_42
VSS_43
VSS VSS_141
VSS_142
F29
A29
K16
G16
VSS_240
VSS_241
VSS_338
VSS_339
AJ2
AH2
AT42 BG28 E16 AF2
C VSS_44 VSS_143 VSS_242 VSS_340 C
AN42 VSS_45 VSS_144 BD28 BG15 VSS_243 VSS_341 AE2
AJ42 BA28 AC15 AD2
AE42 AV28 W15 AC2
N42 VSS_48 VSS_147 AT28 A15 VSS_246 VSS_344 Y2
L42 VSS_49 VSS_148 AR28 BG14 VSS_247 VSS_345 M2
BD41 AJ28 AA14 K2
AU41 VSS_51 VSS_150 AG28 C14 VSS_249 VSS_347 AM1
AM41 AE28 BG13 AA1
AH41 VSS_53 VSS_152 AB28 BC13 VSS_251 VSS_349 P1
AD41 Y28 BA13 H1
AA41 VSS_55 VSS_154 P28
Y41 K28 U24
U41 VSS_57 VSS_156 H28 AN13 VSS_255 VSS_352 U28
T41 F28 AJ13 U25
M41 C28 AE13 U29
G41 BF26 N13
B41 AH26 L13 AF32
VSS_61 VSS_160 VSS_259 VSS_NCTF_1
BG40 AF26 G13 AB32
BB40 AB26 E13 V32
AV40 VSS_64 VSS_163 AA26 BF12 VSS_262 VSS_NCTF_4 AJ30
AN40 C26 AV12 AM29
H40 B26 AT12 AF29
E40 BH25 AM12 AB29
AT39 BD25 AA12 U26
VSS NCTF
AM39 BB25 J12 U23
AJ39 AV25 A12 AL20
AE39 VSS_71 VSS_170 AR25 BD11 VSS_269 VSS_NCTF_11 V20
N39 AJ25 BB11 AC19
L39 AC25 AY11 AL17
B39 Y25 AN11 AJ17
BH38 N25 AH11 AA17
BC38 L25 U17
B VSS_76 VSS_175 VSS_NCTF_16 B
BA38 VSS_77 VSS_176 J25 Y11 VSS_275
AU38 VSS_78 VSS_177 G25 N11 VSS_276
AH38 E25 G11 BH48
VSS_79 VSS_178 VSS_277 VSS_SCB_1
AD38 VSS_80 VSS_179 BF24 C11 VSS_278 VSS_SCB_2 BH1
AA38 AD12 BG10 A48
Y38 AY24 AV10 C1
VSS SCB
U38 AT24 AT10 A3
T38 AJ24 AJ10
J38 AH24 AE10
F38 VSS_86 VSS_185 AF24 AA10 VSS_284
C38 VSS_87 VSS_186 AB24 M10 VSS_285
BF37 R24 BF9 E1
VSS_88 VSS_187 VSS_286 NC_26
BB37 VSS_89 VSS_188 L24 BC9 VSS_287 NC_27 D2
AW37 K24 AN9 C3
VSS_90 VSS_189 VSS_288 NC_28
AT37 VSS_91 VSS_190 J24 AM9 VSS_289 NC_29 B4
AN37 G24 AD9 A5
VSS_92 VSS_191 VSS_290 NC_30
AJ37 F24 G9 A6
VSS_93 VSS_192 VSS_291 NC_31
H37 E24 B9 A43
VSS_94 VSS_193 VSS_292 NC_32
C37 BH23 BH8 A44
VSS_95 VSS_194 VSS_293 NC_33
BG36 AG23 BB8 B45
VSS_96 VSS_195 VSS_294 NC_34
BD36 Y23 AV8 C46
NC
VSS_97 VSS_196 VSS_295 NC_35
AK15 VSS_98 VSS_197 B23 AT8 VSS_296 NC_36 D47
AU36 A23 B47
VSS_99 VSS_198 NC_37
VSS_199 AJ6 NC_38 A46
F48
CANTIGA ES_FCBGA1329 NC_39
E48
GM45R3@ NC_40
NC_41 C48
B48
NC_42
GM45R3@
A A

0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
+V_DDR3_DIMM_REF
0.1U_0402_16V4Z
www.rosefix.com
DDR_A_D0
1
3
5
JDDRH
VREF_DQ
VSS2
VSS1
DQ4
2
4
6
DDR_A_D4
DDR_A_D5
DDR3 SO-DIMM A
REVERSE TYPE
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
<9>
<9>
2.2U_0603_6.3V4Z
DDR_A_D1 DQ0 DQ5
1 1 7 DQ1 VSS3 8 DDR_A_D[0..63] <9>
9 10 DDR_A_DQS#0
CD1 DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
CD2
11 DM0 DQS0 12 DDR_A_DM[0..7] <9>
13 VSS5 VSS6 14
2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16 DDR_A_MA[0..14] <9>
DDR_A_D3 17 18 DDR_A_D7
DQ3 DQ7
19 VSS7 VSS8 20
DDR_A_D9 DQ8 DQ12 DDR_A_D13
D 23 DQ9 DQ13 24 D
25 VSS9 VSS10 26
close to JDDRH.1 DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS#1 DM1
29 DQS1 RESET# 30 SM_DRAMRST# <8,15> +1.5V
31 VSS11 VSS12 32
35 DQ11 DQ15 36
1
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20 RD1
DDR_A_D17 DQ16 DQ20 DDR_A_D21 1K_0402_1%
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
2
47 DQS2 VSS17 48 +V_DDR3_DIMM_REF
49 50 DDR_A_D22
VSS18 DQ22
1
DDR_A_D19 DQ18 DQ23 RD2
53 DQ19 VSS19 54
55 56 DDR_A_D28 1K_0402_1%
DDR_A_D24 VSS20 DQ28 DDR_A_D29
57 DQ24 DQ29 58
DDR_A_D25 59 60
2
DQ25 VSS21 DDR_A_DQS#3
61 VSS22 DQS#3 62
DDR_A_DM3 63 64 DDR_A_DQS3
DM3 DQS3 <BOM Structure>
65 VSS23 VSS24 66
69 DQ27 DQ31 70
71 VSS25 VSS26 72
<8> DDRA_CKE0 73 CKE0 CKE1 74 DDRA_CKE1 <8>

C 75 76 C
+1.5V VDD1 VDD2 +1.5V
77 78 RD6 1 2
NC1 A15 DDR_A_MA14 @ 0_0402_5%
<9> DDR_A_BS2 79 BA2 A14 80 Layout Note:
81 VDD3 VDD4 82
DDR_A_MA12 83 84 DDR_A_MA11 Place near JDDRH Layout Note: Place these 4 Caps near Command
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 88 and Control signals of DIMMA
DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
89 A8 A6 90
DDR_A_MA5 91 92 DDR_A_MA4
A5 A4
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0 +1.5V
97 A1 A0 98
99 VDD9 VDD10 100
<8> DDRA_CLK0 101 CK0 CK1 102 DDRA_CLK1 <8>
<8> DDRA_CLK0# 103 CK0# CK1# 104 DDRA_CLK1# <8>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
105 VDD11 VDD12 106 1
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
DDR_A_MA10 107 108 1 1 1 1 1 1 1 1 1 1
A10/AP BA1 DDR_A_BS1 <9>
CD13
CD14
CD15
CD16
+
CD7
CD8
CD9
CD10
CD11
CD12
<9> DDR_A_BS0 109 BA0 RAS# 110 DDR_A_RAS# <9>
111 112 CD45 @
VDD13 VDD14 @ @ @ @ 330U_6.3V_M_R15
<9> DDR_A_W E# 113 WE# S0# 114 DDRA_SCS0# <8> 2 2 2 @ 2 2 @ 2 2 2 2 2 2
<9> DDR_A_CAS# 115 CAS# ODT0 116 DDRA_ODT0 <8> +V_DDR3_DIMM_REF
117 VDD15 VDD16 118
DDR_A_MA13 119 120 RD4
A13 ODT1 DDRA_ODT1 <8>
<8> DDRA_SCS1# 121 S1# NC2 122 1 2
123 124 0_0402_5%
VDD17 VDD18 +DDR_VREF_CA_DIMMA
125 NCTEST VREF_CA 126
127 VSS27 VSS28 128
DDR_A_D32 129 130 DDR_A_D36
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z
131 DQ33 DQ37 132
B B
133 VSS29 VSS30 134
DDR_A_DQS#4 135 136 DDR_A_DM4 1 1
137 DQS4 VSS31 138
DDR_A_D38
Layout Note:
CD4
CD3
139 VSS32 DQ38 140
DDR_A_D34 141 142 DDR_A_D39 Place near JDDRH.203 & JDDRH.204
DDR_A_D35 DQ34 DQ39 2 2
143 DQ35 VSS33 144
145 146 DDR_A_D44
147 DQ40 DQ45 148
DDR_A_D41 149 150
DQ41 VSS35 DDR_A_DQS#5 +0.75VS
151 VSS36 DQS#5 152 close to JDDRH.126
DM5 DQS5
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
159 DQ43 DQ47 160
161 VSS39 VSS40 162
10U_0805_6.3V6M
DDR_A_D48 163 164 DDR_A_D52 2 2 2 2 1
CD22
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170 DDR_A_DM6 @
DDR_A_DQS6 DQS#6 DM6 1 1 1 1 2
171 DQS6 VSS43 172
DDR_A_D54
CD18
CD19
CD20
CD21
173 VSS44 DQ54 174
DDR_A_D50 175 176 DDR_A_D55
DDR_A_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_A_D60
181 DQ56 DQ61 182
DDR_A_D57 183 184
DQ57 VSS47 DDR_A_DQS#7
185 VSS48 DQS#7 186
DM7 DQS7
A 189 VSS49 VSS50 190 A
DDR_A_D58 191 192 DDR_A_D62
193 DQ59 DQ63 194
RD3 1 2 195 196
10K_0402_5% VSS51 VSS52
197 SA0 EVENT# 198 PM_EXTTS# <8,15>
+3VS 199 VDDSPD SDA 200 PM_SMBDATA <15,16,21,25>
10K_0402_5%
201 202
Compal Electronics, Inc.
0.1U_0402_16V4Z
Compal Secret Data

2.2U_0603_6.3V4Z
SA1 SCL PM_SMBCLK <15,16,21,25> Security Classification

1
1 1 +0.75VS 203 VTT1 VTT2 204 +0.75VS

CD6 2009/06/12 2010/06/12 Title
Issued Date Deciphered Date
CD5
RD5
205 G1 G2 206
DDRII-SODIMM0
2 2 LOTES_AAA-DDR-111-K01 Size Document Number Rev
2
CONN@ 0.1
PWWAA LA6841P M/B
5 4 3 2 1
A B C D E
+V_DDR3_DIMM_REF
0.1U_0402_16V4Z
www.rosefix.com
DDR_B_D0
1
3
5
JDDRL
VREF_DQ
VSS2
VSS1
DQ4
2
4
6
DDR_B_D4
DDR_B_D5
DDR3 SO-DIMM B
REVERSE TYPE
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
<9>
<9>
2.2U_0603_6.3V4Z
DDR_B_D1 DQ0 DQ5
1 1 7 DQ1 VSS3 8 DDR_B_D[0..63] <9>
9 10 DDR_B_DQS#0
CD23 DDR_B_DM0 VSS4 DQS#0 DDR_B_DQS0
CD24
11 DM0 DQS0 12 DDR_B_DM[0..7] <9>
13 VSS5 VSS6 14
2 2 DDR_B_D2 DDR_B_D6
15 DQ2 DQ6 16 DDR_B_MA[0..14] <9>
DDR_B_D3 17 18 DDR_B_D7
DQ3 DQ7
19 VSS7 VSS8 20
DDR_B_D9 DQ8 DQ12 DDR_B_D13
1 23 DQ9 DQ13 24 1
25 VSS9 VSS10 26
close to JDDRL.1 DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1
29 DQS1 RESET# 30 SM_DRAMRST# <8,14>
31 VSS11 VSS12 32
35 DQ11 DQ15 36
37 VSS13 VSS14 38
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
47 DQS2 VSS17 48
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19 DDR_B_D28
55 VSS20 DQ28 56
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_B_DQS#3
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
69 DQ27 DQ31 70
71 VSS25 VSS26 72
<8> DDRB_CKE0 73 CKE0 CKE1 74 DDRB_CKE1 <8>

2 75 76 2
+1.5V VDD1 VDD2 +1.5V
77 78 RD10 1 2
NC1 A15 DDR_B_MA14 @ 0_0402_5%
<9> DDR_B_BS2 79 BA2 A14 80 Layout Note:
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11 Place near JDDRL Layout Note: Place these 4 Caps near Command
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 88 and Control signals of DIMMB
DDR_B_MA8 VDD5 VDD6 DDR_B_MA6
89 A8 A6 90
DDR_B_MA5 91 92 DDR_B_MA4
A5 A4
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0 +1.5V
97 A1 A0 98
99 VDD9 VDD10 100
<8> DDRB_CLK0 101 CK0 CK1 102 DDRB_CLK1 <8>
<8> DDRB_CLK0# 103 CK0# CK1# 104 DDRB_CLK1# <8>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
105 VDD11 VDD12 106
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
DDR_B_MA10 107 108
22U_0805_6.3V6M
1 1 1 1
22U_0805_6.3V6M
A10/AP BA1 DDR_B_BS1 <9> 1 1 1 1 1 1
CD38
CD37
CD36
CD35
CD29
CD30
CD31
CD32
CD33
CD34
<9> DDR_B_BS0 109 BA0 RAS# 110 DDR_B_RAS# <9>
111 VDD13 VDD14 112
113 114 @ @
<9> DDR_B_W E# WE# S0# DDRB_SCS0# <8> 2 2 2 2 2 2 2 2 2 2
115 116 @ @
<9> DDR_B_CAS# CAS# ODT0 DDRB_ODT0 <8> +V_DDR3_DIMM_REF
117 VDD15 VDD16 118
DDR_B_MA13 119 120
A13 ODT1 DDRB_ODT1 <8>
<8> DDRB_SCS1# 121 S1# NC2 122
123 124 RD7
VDD17 VDD18 +DDR_VREF_CA_DIMMB
125 NCTEST VREF_CA 126 1 2
127 128 0_0402_5%
DDR_B_D32 VSS27 VSS28 DDR_B_D36
129 130
0.1U_0402_16V4Z
2.2U_0603_6.3V4Z

131 DQ33 DQ37 132
3 3
133 VSS29 VSS30 134
DDR_B_DQS#4 135 136 DDR_B_DM4 1 1
137 DQS4 VSS31 138
DDR_B_D38
Layout Note:
CD28
CD27
139 VSS32 DQ38 140

DDR_B_D34 141 142 DDR_B_D39 Place near JDDRL.203 & JDDRL.204
DDR_B_D35 DQ34 DQ39 2 2
143 DQ35 VSS33 144
145 146 DDR_B_D44
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS35 DDR_B_DQS#5 +0.75VS
151 VSS36 DQS#5 152 close to JDDRL.126
DDR_B_DM5 153 154 DDR_B_DQS5
DM5 DQS5
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
159 DQ43 DQ47 160
161 VSS39 VSS40 162
10U_0805_6.3V6M
DDR_B_D48 163 164 DDR_B_D52 2 2 2 2 1
CD44
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170 DDR_B_DM6
DDR_B_DQS6 DQS#6 DM6 1 1 1 1 @2
171 DQS6 VSS43 172
DDR_B_D54
CD40
CD42
CD41
CD43
173 VSS44 DQ54 174
DDR_B_D50 175 176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_B_D60
181 DQ56 DQ61 182
DDR_B_D57 183 184
DQ57 VSS47 DDR_B_DQS#7
185 VSS48 DQS#7 186
DDR_B_DM7 187 188 DDR_B_DQS7
DM7 DQS7
4 189 VSS49 VSS50 190 4
DDR_B_D58 191 192 DDR_B_D62
193 DQ59 DQ63 194
RD8 1 2 195 196
10K_0402_5% VSS51 VSS52
197 SA0 EVENT# 198 PM_EXTTS# <8,14>
+3VS 199 VDDSPD SDA 200 PM_SMBDATA <14,16,21,25>
1 RD9 2 201 202
Compal Electronics, Inc.
0.1U_0402_16V4Z
Compal Secret Data

2.2U_0603_6.3V4Z
10K_0402_5% +0.75VS SA1 SCL PM_SMBCLK <14,16,21,25> Security Classification

1 1 203 VTT1 VTT2 204 +0.75VS
CD25 2009/06/12 2010/06/12 Title
Issued Date Deciphered Date
CD26 205 G1 G2 206
DDRII-SODIMM0
2 2 TYCO_2-2013289-1 Size Document Number Rev
CONN@ 0.1
PWWAA LA6841P M/B
A B C D E
A B C D E F G H
+1.05VS_CK505 +3VS_CK505
FSC
CLKSEL2
0
FSB
CLKSEL1
0
FSA
CLKSEL0
0
www.rosefix.com
CPU
MHz
266
SRC
MHz
100
PCI
MHz
33.3
REF
MHz
14.318
DOT_96 USB
MHz
96.0
MHz
48.0
+1.05VS
R108
1 2
80mA
0_0805_5% 1
2
C213
0.1U_0402_16V4Z
10U_0805_10V4Z
1
C214
2 2
1
C215
0.1U_0402_16V4Z
10U_0805_10V4Z
1
2
C216
1
2
0.1U_0402_16V4Z
C217
0.1U_0402_16V4Z
1
C218
2 2
1
C219
0.1U_0402_16V4Z
+3VS
R107
1 2
0_0805_5% 1
2
250mA
C206
0.1U_0402_16V4Z
10U_0805_10V4Z
1
2
C207
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C208
1
2
C209
2
1
0.1U_0402_16V4Z
C210
0.1U_0402_16V4Z
1
2
C211
1
2
C212
0.1U_0402_16V4Z
0 0 1 133 100 33.3 14.318 96.0 48.0

+3VS_CK505
0 1 0 200 100 33.3 14.318 96.0 48.0 U4
1
SDA 9 PM_SMBDATA <14,15,21,25> 1
55 VDD_SRC
0 1 1 166 100 33.3 14.318 96.0 48.0 SCL 10 PM_SMBCLK <14,15,21,25>
6 VDD_REF
1 0 0 333 100 33.3 14.318 96.0 48.0 12 VDD_PCI CPU_0 71 CLK_CPU_BCLK <4>
CPU
72 VDD_CPU CPU_0# 70 CLK_CPU_BCLK# <4>
1 0 1 100 100 33.3 14.318 96.0 48.0
19 VDD_48 CPU_1 68 CLK_MCH_BCLK <7>
+1.05VS_CK505 NB
1 1 0 400 100 33.3 14.318 96.0 48.0 27 VDD_PLL3 CPU_1# 67 CLK_MCH_BCLK# <7>
1 1 1 Reserved 66 VDD_CPU_IO SRC_0/DOT_96 24 CLK_DREF_96M <8>

NB (96MHz)
31 VDD_PLL3_IO SRC_0#/DOT_96# 25 CLK_DREF_96M# <8>
62 VDD_SRC_IO
LCDCLK/27M 28 CLK_DREF_SSC <8>
52 VDD_SRC_IO NB_SSC (100MHz)
CLK_XTAL_OUT Routing the place 22ohm for damping resistor LCDCLK#/27M_SS 29 CLK_DREF_SSC# <8>
when loading is two device,If one 23 VDD_IO
Y1 trace at device use 33ohm
CLK_XTAL_IN 1 2 38 32
least 10mil VDD_SRC_IO SRC_2 CLK_PCIE_ICH <19>
2 2 ICH-DMI
14.318MHZ_16PF_7A14300083 2 R131 1 22_0402_5% 33
<29> CLK_48M_CR SRC_2# CLK_PCIE_ICH# <19>
C221 C220
22P_0402_50V8J 22P_0402_50V8J 1 R117 2 22_0402_5% CLK_FSA 20
2 1 1 <21> CLK_48M_ICH USB_0/FS_A 2
SRC_3 35 CLK_PCIE_SATA <20>
FSB CPU_BSEL1 2 FS_B/TEST_MODE SATA
SRC_3# 36 CLK_PCIE_SATA# <20>
CLK_FSC 7 REF_0/FS_C/TEST_
<21> CLK_14M_ICH R111 1 2 33_0402_5% CLK_14ICH 8 39
REF_1 SRC_4 CLK_W LAN <25>
WLAN
SRC_4# 40 CLK_W LAN# <25>
2 1 CLK_FSA 1
<5,8> CPU_BSEL0 <21> CK_PW RGD CKPWRGD/PD#
R116 2.2K_0402_5%
11 NC SRC_6 57
CPU_BSEL1
<5,8> CPU_BSEL1
SRC_6# 56
2 1 CLK_FSC 53
<5,8> CPU_BSEL2 <21> H_STP_CPU# CPU_STOP#
R109 10K_0402_5% 61
SRC_7 CLK_MCH_3GPLL <8>
<21> H_STP_PCI# 54 PCI_STOP# 3G_PLL
SRC_7# 60 CLK_MCH_3GPLL# <8>
CLK_XTAL_IN 5 XTAL_IN SRC8_LAN R513 1
SRC_8/CPU_ITP 64 2 CLK_LAN <26>
CLK_XTAL_OUT 4 0_0402_5% LAN
XTAL_OUT SRC8_LAN# R514 1
SRC_8#/CPU_ITP# 63 2 CLK_LAN# <26>
close to U4 befor R115 0_0402_5%
EMI request 6/25
13 44 SRC9_LAN R511 1 @ 2
PCI_1 SRC_9 0_0402_5%
2 R115 1 2 33_0402_5% CLK_DDR 14 45 SRC9_LAN# R512 1 @ 2
<31> CLK_PCI_DDR PCI_2 SRC_9# 0_0402_5%
3 C854 3
15 PCI_3
1
33P_0402_50V8J
R113 1 SRC_10 50 Reserve (Check layout)
@ 2CLK_EC 16 PCI_4/SEL_LCDCL
33_0402_5% 51
<30> CLK_PCI_EC R112 1 SRC_10#
2 2CLK_ICH 17 PCIF_5/ITP_EN
<19> CLK_PCI_ICH 33_0402_5%
C856 48
SRC_11
33P_0402_50V8J
1
@ 18 VSS_PCI SRC_11# 47
+3VS
3 VSS_REF
CLKREQ_SATA# CLKREQ_SATA#
0 = SRC8/SRC8# (100MHz) 22 VSS_48 CLKREQ_3# 37 CLKREQ_SATA# <21> 2
R125
1
10K_0402_5%
CLK_ICH CLKREQ_W LAN# CLKREQ_W LAN#
1 = ITP/ITP# (266MHz) 26 VSS_IO CLKREQ_4# 41 CLKREQ_W LAN# <25> 2
R124
1
10K_0402_5%
CLKREQ_6# CLKREQ_6#
0 = Enable DOT96 & SRC1(UMA) 69 VSS_CPU CLKREQ_6# 58 2
R119
1
10K_0402_5%
CLK_EC CLKREQ_3GPLL# CLKREQ_3GPLL#
1 = Enable SRC0 & 27MHz(DIS) 30 VSS_PLL3 CLKREQ_7# 65 CLKREQ_3GPLL# <8> 2
R118
1
10K_0402_5%
34 43 CLKREQ_LAN# CLKREQ_LAN# 2 1
VSS_SRC CLKREQ_9# CLKREQ_LAN# <26>
R123 10K_0402_5%
59 49 CLKREQ_10# Reserve CLKREQ_10# 2 1
+3VS +3VS VSS_SRC SLKREQ_10# R126 10K_0402_5%
42 46 CLKREQ_11# CLKREQ_11# 2 1
VSS_SRC CLKREQ_11# R120 10K_0402_5%
1
73 THERMAL_PAD USB_1/CLKREQ_A# 21
R121 PM R122
4
10K_0402_5% 10K_0402_5% 4
@ @ SLG8SP556VTR_QFN72_10X10
2
CLK_ICH CLK_EC
1
R127 R128
10K_0402_5% GM 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Clock Generator
2
0.1
PWWAA LA6841P M/B
A B C D E F G H
5 4 3 2 1
www.rosefix.com LCD/PANEL BD. Conn.

+LCD_VDD +3VS
1
R621 R622 +3VS
150_0603_5% 100K_0402_5% W=60mils
6 2
2
D 2 D
C853
0.1U_0402_16V7K
3
S
Q17A Inrush current = 0A
2N7002DW -T/R7_SOT363-6 1 G
Q18
2 1 2 2
R623 47K_0402_5% 2 AO3413_SOT23
3
D
1
C671 +LCD_VDD
0.01U_0402_25V7K W=60mils
1
<10> UMA_ENVDD 5
Q17B
2N7002DW -T/R7_SOT363-6 1 1
4
1
C672 C673
R626 4.7U_0805_10V4Z 0.1U_0402_16V4Z
100K_0402_5% @ 2 2
2
1.5A
+LCDVDD_R 2 L16 1 +LCD_VDD
0_0805_5%
1 1
C674 C675
0.1U_0402_16V4Z 4.7U_0805_10V4Z
C 2 2 C
+3VS_LVDS_CAM
CAM@
0.1U_0402_16V4Z @ D84
CAM@ 0_0402_5% R837 1 2 2
2 1 C766 1
CAM@ 3
L85 0_0603_5% W=20mils JLVDS @
2 1 +3VS R104 1 2 1 2 UMA_LCD_EDID_CLK <10> PACDN042Y3R_SOT23-3
2 1 USB20_P11_R 1 2
<19> USB20_P11 3 3 4 4 UMA_LCD_EDID_DATA <10>
USB20_N11_R 5 6 INT_MIC_CLK
<19> USB20_N11 5 6 INT_MIC_CLK <27>
3 4 7 8 INT_MIC_DATA
3 4 7 8 INT_MIC_DATA <27>
Camera <10> UMA_LCD_TXOUT0+ 9 9 10 10 INVT_PW M_R
@ W CM2012F2SF-900T04_0805 11 12 BKOFF#_R
<10> UMA_LCD_TXOUT0- 11 12
<10> UMA_LCD_TXOUT1+ 13 13 14 14
2 1 <10> UMA_LCD_TXOUT1- 15 15 16 16
CAM@ 0_0402_5% R841 17 18
<10> UMA_LCD_TXOUT2+ 17 18
<10> UMA_LCD_TXOUT2- 19 19 20 20 +3VS
<10> UMA_LCD_TXCLK+ 21 21 22 22
23 24 +LCDVDD_R
<10> UMA_LCD_TXCLK- 23 24
25 25 26 26
27 27 28 28 +LCD_INV
1 2 BKOFF#_R 29 30
<30> BKOFF# 29 30
33_0402_5% R137
31 GND1
To prevent EC pin from damage 1 32 GND2
R627 B+
B B
10K_0402_5% ACES_88242-3001 Rated Current MAX:600mA
L3 2 1
FBMA-L11-201209-221LMA30T_0805
2
1 1
C391 C676
68P_0402_50V8J 0.1U_0402_25V6
2 2
<30> INVT_PW M 1 R217 2 0_0402_5%
<10> NB_PW M 1 R204 2 0_0402_5% INVT_PW M_R
@
A A

NB9M GDDR2A
0.1
PWWAA LA6841P M/B
5 4 3 2 1
A B C D E
CRT CONNECTOR +5VS
www.rosefix.com
1
D55 D56 D57 D58 +CRT_VCC_R +CRT_VCC
2 F3 30mil
1 1 2
3 RB491D_SOT23-3 1.1A_6V_MINISMDC110F-2 1
+3VS If=1A
DAN217_SC59 DAN217_SC59 DAN217_SC59 C679
3
@ @ @ @ 0.1U_0402_16V4Z
2
JCRT
L18 6
CRT_R_L 6
<10> UMA_CRT_R 1 2 11 11
1 NBQ100505T-800Y_0402 CRT_R_L 1 1
1
7 7
L19 CRT_DDC_DAT 12
CRT_G_L CRT_G_L 12
<10> UMA_CRT_G 1 2 2 2
NBQ100505T-800Y_0402 8
HSYNC 8
13 13
L20 CRT_B_L 3
CRT_B_L 3
<10> UMA_CRT_B 1 2 +CRT_VCC 9 9
NBQ100505T-800Y_0402 VSYNC 14 16
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
2.2P_0402_50V8C
14 G
4 4 G 17
150_0402_1%
150_0402_1%
150_0402_1%
1 1 1 1 1 1 10 10
1
CRT_DDC_CLK 15
R670 R671 R672 C680 C681 C682 C683 C684 C685 15
5 5
2 2 2 2 2 2 ALLTO_C10532-11505-L_15P-T
@
2
+CRT_VCC
+CRT_VCC
1 2 2 1
C686 0.1U_0402_16V4Z R673 10K_0402_5%
5
1
1
+3VS
OE#
P
2 4 D_CRT_HSYNC 1 2 HSYNC R677 R678
<10> UMA_CRT_HSYNC A Y L21 10_0402_5% 2.2K_0402_5% 2.2K_0402_5%
G
U38
SN74AHCT1G125GW _SOT353-5 D_CRT_VSYNC 1 2 VSYNC
2
2 L22 10_0402_5% 2
10P_0402_50V8J
10P_0402_50V8J
2
+CRT_VCC Q19A
1 1
C687 C688 <10> UMA_CRT_DATA 1 6 CRT_DDC_DAT
5
1
@ @
5
2 2 Q19B 2N7002DW -T/R7_SOT363-6
OE#
P
<10> UMA_CRT_VSYNC 2 A Y 4
<10> UMA_CRT_CLK 4 3 CRT_DDC_CLK
U39 G
1 1
SN74AHCT1G125GW _SOT353-5 1 1 2N7002DW -T/R7_SOT363-6
3
C689 C690
C850 C849 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @
3 3
4 4

CRT\TV\LVDS
0.1
PWWAA LA6841P M/B
A B C D E
5 4 3 2 1
www.rosefix.com D11
C8
D9
E12
E9
U9B
AD0
AD1
AD2
AD3
AD4
PCI
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
F1
G4
B6
A7
F13
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_GNT#0 <21>
PCI_PIRQB#
PCI_PERR#
PCI_TRDY#
1
2
3
RP15
8
7
6
+3VS
C9 F12 PCI_REQ#3 4 5
AD5 GNT2#/GPIO53 PCI_REQ#3
E10 AD6 REQ3#/GPIO54 E6
B7 F6 8.2K_0804_8P4R_5%
AD7 GNT3#/GPIO55 STRAP_A16 <21>
C7 RP16
AD8 PCI_STOP#
D C5 AD9 C/BE0# D8 1 8 D
G11 B4 PCI_DEVSEL# 2 7
AD10 C/BE1# PCI_FRAME#
F8 AD11 C/BE2# D6 3 6
F11 A5 PCI_REQ#1 4 5
AD12 C/BE3#
E7 AD13
A3 D3 PCI_IRDY# 8.2K_0804_8P4R_5%
AD14 IRDY# RP17
D2 AD15 PAR E3
F10 R1 PCI_PLOCK# 1 8
AD16 PCIRST# PCI_DEVSEL# PCI_IRDY#
D5 AD17 DEVSEL# C6 2 7
D10 E4 PCI_PERR# PCI_PIRQD# 3 6
AD18 PERR# PCI_PLOCK# PCI_REQ#2
B3 AD19 PLOCK# C2 4 5
F7 J4 PCI_SERR#
AD20 SERR# PCI_STOP# 8.2K_0804_8P4R_5%
C3 AD21 STOP# A4
F3 F5 PCI_TRDY#
AD22 TRDY# PCI_FRAME#
F4 AD23 FRAME# D7
C1 AD24
G7 AD25 PLTRST# C14 PLT_RST# <8,25,26,30,31> C257
H7 D4 CLK_PCI_ICH R179
AD26 PCICLK CLK_PCI_ICH <16>
D1 R2 CLK_PCI_ICH 2 1 1 2
AD27 PME# @ 10_0402_5%
G5 AD28
H6 @ 10P_0402_50V8J
AD29
G1 AD30
H3 AD31
+3VS +3VS
RP18 RP19
1 8 PCI_PIRQA# PCI_PIRQA# J5
Interrupt I/F H4 PCI_PIRQE# PCI_PIRQE# 1 8
PCI_PIRQF# PCI_PIRQB# PIRQA# PIRQE#/GPIO2 PCI_PIRQF# PCI_SERR#
2 7 E1 PIRQB# PIRQF#/GPIO3 K6 2 7
3 6 PCI_PIRQH# PCI_PIRQC# J6 F2 PCI_PIRQG# PCI_PIRQG# 3 6
C PCI_REQ#0 PCI_PIRQD# PIRQC# PIRQG#/GPIO4 PCI_PIRQH# PCI_PIRQC# C
4 5 C4 PIRQD# PIRQH#/GPIO5 G2 4 5
8.2K_0804_8P4R_5% ICH9-M ES_FCBGA676 8.2K_0804_8P4R_5%

ICH9R3@
U9D
N29 PERN1 DMI0RXN V27 DMI_MTX_IRX_N3 <8>
N28 PERP1 DMI0RXP V26 DMI_MTX_IRX_P3 <8>
P27 PETN1 DMI0TXN U29 DMI_ITX_MRX_N3 <8>
P26 U28
Direct Media Interface

PETP1 DMI0TXP DMI_ITX_MRX_P3 <8>
L29 PERN2 DMI1RXN Y27 DMI_MTX_IRX_N2 <8>
L28 PERP2 DMI1RXP Y26 DMI_MTX_IRX_P2 <8>
M27 PETN2 DMI1TXN W29 DMI_ITX_MRX_N2 <8>
M26 PETP2 DMI1TXP W28 DMI_ITX_MRX_P2 <8>
Lane reversal
PCI - Express
<26> PCIE_IRX_C_LANTX_N3 J29 PERN3 DMI2RXN AB27 DMI_MTX_IRX_N1 <8>
For LAN <26> PCIE_IRX_C_LANTX_P3
C262 2
J28 PERP3 DMI2RXP AB26 DMI_MTX_IRX_P1 <8>
<26> PCIE_ITX_C_LANRX_N3 1 0.1U_0402_16V7K PCIE_ITX_LANRX_N3 K27 PETN3 DMI2TXN AA29 DMI_ITX_MRX_N1 <8>
<26> PCIE_ITX_C_LANRX_P3 C263 2 1 0.1U_0402_16V7K PCIE_ITX_LANRX_P3 K26 AA28
<25> PCIE_IRX_C_W LANTX_N4 G29 PERN4 DMI3RXN AD27 DMI_MTX_IRX_N0 <8>

For WLAN <25> PCIE_IRX_C_W LANTX_P4
C264 2
G28 PERP4 DMI3RXP AD26 DMI_MTX_IRX_P0 <8>
<25> PCIE_ITX_C_W LANRX_N4 1 0.1U_0402_16V7K PCIE_ITX_W LANRX_N4 H27 PETN4 DMI3TXN AC29 DMI_ITX_MRX_N0 <8>
<25> PCIE_ITX_C_W LANRX_P4 C265 2 1 0.1U_0402_16V7K PCIE_ITX_W LANRX_P4 H26 AC28
E29 PERN5 DMI_CLKN T26 CLK_PCIE_ICH# <16>
E28 PERP5 DMI_CLKP T25 CLK_PCIE_ICH <16>
F27 PETN5
B B
F26 PETP5 DMI_ZCOMP AF29
DMI_IRCOMP
Within 500 mils
DMI_IRCOMP AF28 1 2 +1.5VS
C29 R180 24.9_0402_1%
PERN6/GLAN_RXN
C28 PERP6/GLAN_RXP USBP0N AC5 USB20_N0 <23>
+3VALW
RP21
D27 PETN6/GLAN_TXN USBP0P AC4 USB20_P0 <23> USB/B-Left
D26 PETP6/GLAN_TXP USBP1N AD3 USB20_N1 <23>
5 4 USB_OC#4 USBP1P AD2 USB20_P1 <23> USB/B-Left
6 3 USB_OC#6 D23 SPI_CLK USBP2N AC1
7 2 USB_OC#11 D24 SPI_CS0# USBP2P AC2
8 1 USB_OC#10 <21> SPI_CS#1 F23 SPI_CS1#GPIO58/CLGPIO6 USBP3N AA5
10K_0804_8P4R_5% AA4
USBP3P
RP22
<21> ICH_SPI_MOSI D25
E23
SPI_MOSI SPI USBP4N AB2
AB3
USB_OC#5 SPI_MISO USBP4P
5 4 USBP5N AA1
6 3 USB_OC#0 N4 AA2
USB_OC#8 <23,30> USB_OC#0 OC0#/GPIO59 USBP5P
7 2 N5 OC1#/GPIO40 USBP6N W5
USB_OC#2 USB_OC#2
8 1
10K_0804_8P4R_5% USB_OC#3
N6
P6
OC2#/GPIO41 USB USBP6P W4
Y3
OC3#/GPIO42 USBP7N USB20_N7 <25>
USB_OC#4 M1 Y2 WiMax(WLAN)
OC4#/GPIO43 USBP7P USB20_P7 <25>
1 2 USB_OC#9 USB_OC#5 N2 OC5#/GPIO29 USBP8N W1
R183 10K_0402_5% USB_OC#6 M4 W2
OC6#/GPIO30 USBP8P
1 2 USB_OC#3 USB_OC#7 M3 OC7#/GPIO31 USBP9N V2
R184 10K_0402_5% USB_OC#8 N3 V3
OC8#/GPIO44 USBP9P
1 2 USB_OC#7 USB_OC#9 N1 OC9#/GPIO45 USBP10N U5 USB20_N10 <29>
R187 10K_0402_5% USB_OC#10 P5 OC10#/GPIO46 USBP10P U4 USB20_P10 <29> Card reader(3 IN 1)
USB_OC#11 P3 U1
OC11#/GPIO47 USBP11N USB20_N11 <17>
USBP11P U2 USB20_P11 <17> Int. Camera
Within 500 mils USBBIAS AG2 USBRBIAS
A 1 2 AG1 USBRBIAS# A
R186
22.6_0402_1% ICH9-M ES_FCBGA676
ICH9R3@

ICH9M(1/4)-PCI
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
www.rosefix.com
D D
C270
15P_0402_50V8J
2 1
X1
10M_0402_5%
1
3 NC OSC 4
R189
2 NC OSC 1
32.768KHZ_12.5PF_Q13MC14610002 U9A
2
ICH_RTCX1 C23 K5
RTCX1 FWH0/LAD0 LPC_AD0 <30,31>
2 1 ICH_RTCX2 C24 K4
RTCX2 FWH1/LAD1 LPC_AD1 <30,31>
FWH2/LAD2 L6 LPC_AD2 <30,31>
C272 ICH_RTCRST# A25 K2
RTCRST# FWH3/LAD3 LPC_AD3 <30,31>
15P_0402_50V8J ICH_SRTCRST# F20
SM_INTRUDER# SRTCRST#
CMOS Setting, near DDR Door J1
C22 INTRUDER# FWH4/LFRAME# K3 LPC_FRAME# <30,31>
RTC
LPC
+RTCVCC R190 1 2 ICH_RTCRST# 1 2 B22 J3
<21> ICH_INTVRMEN INTVRMEN LDRQ0#
20K_0402_5% SHORT PADS A22 J1
<21> LAN100_SLP LAN100_SLP LDRQ1#/GPIO23
C273 1 2 GATEA20 1 2 +3VS
1U_0402_6.3V6K E25 N7 GATEA20 R191 @ 10K_0402_5%
GLAN_CLK A20GATE GATEA20 <30>
AJ27 H_DPRSTP# 2 1 +1.05VS
A20M# H_A20M# <4>
C13 R192 @ 56_0402_5%
LAN_RSTSYNC H_FERR#
ITPM Setting, near DDR Door J2 DPRSTP# AJ25 H_DPRSTP# <5,8,40> 2
R193
1
56_0402_5%
F14 LAN_RXD0 DPSLP# AE23 H_DPSLP# <5>
R194 1 2ICH_SRTCRST# 1 2 G13
20K_0402_5% SHORT PADS LAN_RXD1 FERR# R195 1
D14 LAN_RXD2 FERR# AJ26 2 56_0402_5%H_FERR# H_FERR# <4>
LAN / GLAN
C274 1 2
C 1U_0402_6.3V6K D13 AD22 C
LAN_TXD_0 CPUPWRGD H_PW RGOOD <5>
D12 LAN_TXD_1
E13 LAN_TXD_2 IGNNE# AF25 H_IGNNE# <4>
R196 1 2 SM_INTRUDER# KB_RST# R197 2 @ 1 10K_0402_5% +3VS
1M_0402_5% B10 AE22
GPIO56 INIT# H_INIT# <4>
AG25
CPU
INTR H_INTR <4>
+1.5VS 1 R198 2 GLAN_COMP B28 GLAN_COMPI RCIN# L3 KB_RST#
KB_RST# <30> 2 1 +1.05VS
24.9_0402_1% B27 +1.05VS 1 2 R199
FBMA-10-100505-301T GLAN_COMPO R201 330_0402_5%
NMI AF23 H_NMI <4>
2
B
<27> AZ_BITCLK_HD R200 AZ_BITCLK AF6 AF24 56_0402_5% @
HDA_BIT_CLK SMI# H_SMI# <4>
<27> AZ_SYNC_HD R205 1 2 33_0402_5% AZ_SYNC AH4 HDA_SYNC
C
2 AH27 H_THERMTRIP# 3 1 2SC2411K_SOT23
STPCLK# H_STPCLK# <4>
close to U9A <27> AZ_RST_HD# R209 1 2 33_0402_5% AZ_RST# AE7 HDA_RST#
Q10 @
befor R200 C855 AG26 THRMTRIP_ICH# 1 2 H_THERMTRIP#
THRMTRIP# H_THERMTRIP# <4,8>
33P_0402_50V8J <27> AZ_SDIN0_HD AF4 R208 54.9_0402_1%
1 HDA_SDIN0 TP12
@ AG4 HDA_SDIN1 TP12 AG27 PAD T5
1
AH3 HDA_SDIN2
AE5 D50
IHDA
HDA_SDIN3 DAN202UT106_SC70-3
SATA4RXN AH11 SATA_IRX_C_DTX_N4 <23>
AZ_SDOUT AG5 AJ11 @
<21> AZ_SDOUT HDA_SDOUT SATA4RXP SATA_IRX_C_DTX_P4 <23>
R212 1 2 33_0402_5% AZ_SDOUT
<27> AZ_SDOUT_HD SATA4TXN AG12 SATA_ITX_DRX_N4 <23> SATA ODD
AG7 AF12 SATA_ITX_DRX_P4 <23>
3
HDA_DOCK_EN#/GPIO33 SATA4TXP
AE8 HDA_DOCK_RST#/GPIO34
ENTRIP1_HW <37>
SATA_LED# AG8
SATA_LED# SATALED#
+3VS 1 2 SATA5RXN AH9
R215 10K_0402_5% AJ16 AJ9
SATA0RXN SATA5RXP
AH16 SATA0RXP SATA5TXN AE10
AF17 SATA0TXN SATA5TXP AF10
B B
AG17 SATA0TXP ENTRIP2_HW <37>
SATA_CLKN AH18 CLK_PCIE_SATA# <16>
SATA
<23> SATA_IRX_C_DTX_N1 AH13 SATA1RXN SATA_CLKP AJ18 CLK_PCIE_SATA <16>
<23> SATA_IRX_C_DTX_P1 AJ13 SATA1RXP SATARBIAS# AJ7
1ST HDD AG14 AH7 SATARBIAS
<23> SATA_ITX_DRX_N1 SATA1TXN SATARBIAS
<23> SATA_ITX_DRX_P1 AF14 SATA1TXP
2
R216
10mils width
ICH9-M ES_FCBGA676 24.9_0402_1% less than
ICH9R3@
500mils
1
+RTCVCC D10 +RTCBATT
2 +3VL
1
1 3 1 2
R16 1K_0402_5%
C271 CHN202UPT SC-70
1
0.1U_0402_16V4Z
2 R16 locate around
+
RTC battery
@ JRTC
LOTES_AAA-BAT-054-K01
A A
-

2
ICH9M(2/4)-LAN,IDELPC,RTC
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
+3VS
4.7K_0402_5% 2
www.rosefix.com
1 R223
R221 1
R224 1
2 4.7K_0402_5%
2 4.7K_0402_5%
+3VALW
+3VS
2
4.7K_0402_5% 2 1
R226 R971 for EMI request
1 6 ICH_SMBDATA 100K_0402_5%
<14,15,16,25> PM_SMBDATA
BT@ CLK_14M_ICH 1 2 1 2
5
U9C R228 C276
1
Q4A ICH_SMBCLK @ 10_0402_5% @ 4.7P_0402_50V8C
G16 SMBCLK SATA0GP/GPIO21 AH23
2N7002DW -T/R7_SOT363-64 ICH_SMBCLK ICH_SMBDATA CLK_48M_ICH
<14,15,16,25> PM_SMBCLK 3
LINKALERT#
A13
E17
SMBDATA SMB SATA1GP/GPIO19 AF19
AE21
1
R229
2 1
C277
2
SATA
GPIO
LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36 BT_PW R# <25>
D 2N7002DW -T/R7_SOT363-6 ME_EC_CLK1 C17 AD20 @ 10_0402_5% @ 4.7P_0402_50V8C D
R230 10K_0402_5% LINKALERT# Q4B ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37
+3VALW 1 2 B18 SMLINK1
R232 1 2 10K_0402_5% ME_EC_CLK1 H1 CLK_14M_ICH
CLK14 CLK_14M_ICH <16>
R233 10K_0402_5% ME_EC_DATA1 ICH_RI# AF3 CLK_48M_ICH
R234
1
1
2
2 10K_0402_5% ICH_RI#
F19 RI# clocks CLK48 CLK_48M_ICH <16>
S4_STATE# 1 2 +3VALW
R236 1 2 10K_0402_5% XDP_DBRESET# R4 P1 R235 @ 10K_0402_5%
SUS_STAT#/LPCPD# SUSCLK EC_CLK <30>
XDP_DBRESET# G19 ICH_LOW _BAT# 2 1
<4> XDP_DBRESET# SYS_RESET#
+3VALW R238 1 2 10K_0402_5% EC_LID_OUT# C16 R237 8.2K_0402_5%
SLP_S3# PM_SLP_S3# <30>
<8> PM_SYNC# M6 PMSYNC#/GPIO0 SLP_S4# E16 PM_SLP_S4# <30>
R240 1 2 10K_0402_5% PM_CLKRUN# G17
SLP_S5# PM_SLP_S5# <30>
SYS / GPIO
<30> EC_LID_OUT# EC_LID_OUT# A17 2 R239 1 1 R275 @2 +3VALW
SMBALERT#/GPIO11 S4_STATE# 0_0402_5% 1K_0402_5%
S4_STATE#/GPIO26 C10
R242 1 2 1K_0402_5% SB_W AKE# A14 SB_RSMRST# 1 Q11 3
C
+3VALW <16> H_STP_PCI# STP_PCI# EC_RSMRST# <30>
E19 G20 ICH_PW ROK 1 2
E
<16> H_STP_CPU# STP_CPU# PWROK
+3VS R244 1 2 10K_0402_5% SERIRQ R241 @ MMBT3906_SOT23-3
R245 1 2 @ 8.2K_0402_5% EC_THERM# PM_CLKRUN# L4 M2 10K_0402_5%
B
PM_DPRSLPVR <8,40>
2
Power MGT
CLKRUN# DPRSLPVR/GPIO16
THRM# not 1 2 +3VALW
+3VS R246 1 2 10K_0402_5% OCP# used, 8.2K to <26> SB_W AKE# SB_W AKE# E20 B13 ICH_LOW _BAT# R243
WAKE# BATLOW#
1
<30,31> SERIRQ SERIRQ M5 4.7K_0402_5%
ICH_ACIN 10K PU to EC_THERM# SERIRQ D11B D11A @
+3VS 1 2 <30> EC_THERM# AJ23 THRM# PWRBTN# R3 PBTN_OUT# <30>
R248 330K_0402_5% +3VS. BAV99DW -7_SOT363 BAV99DW -7_SOT363
1 2 VGATE D21 D20 1 2 @ @
<30,36> ACIN <8,30,40> VGATE VRMPWRGD LAN_RST#
D12 CH751H-40PT_SOD323-2 R247 0_0402_5%
PAD TP11 A20 D22 SB_RSMRST#
T6
6
R250 1 8.2K_0402_5% EC_SMI# TP11 RSMRST#
2 2 1
+3VALW
R251 1 2 10K_0402_5% EC_SCI#
<4> OCP#
OCP#
ICH_ACIN
AG19 GPIO1 CK_PWRGD R5 CK_PW RGD <16>
R249
2.2K_0402_5%
@ RSMRST# circuit
AH21 GPIO6
+3VS 1 R807 2 100K_0402_5% 2HDD_DET# AG21 GPIO7 CLPWROK R6 ICH_PW ROK
ICH_PW ROK <8,30>
<30> EC_SMI# EC_SMI# A21
C EC_SCI# GPIO8 +3VS D66 C
<30> EC_SCI# C12 GPIO12 SLP_M# B16
HDMI_HPD C21 ICH_PW ROK 2 1 SB_RSMRST#
GPIO13
AE18 GPIO17 CL_CLK0 F24 CL_CLK0 <8>
1
+3VS R253 1 2 8.2K_0402_5% BT_DET# K1 B19 CH751H-40PT_SOD323-2
GPIO
GPIO18 CL_CLK1
Controller Link
2HDD_DET# AF8 R252
BT_DET# GPIO20 3.24K_0402_1% D68
AJ22 SCLOCK/GPIO22 CL_DATA0 F22 CL_DATA0 <8>
+3VALW R255 2 1 @ 10K_0402_5% GPIO57 A9 C19 1 2
GPIO27 CL_DATA1 <35,37> POK
R257 2 1 100K_0402_5% D19
2
GPIO28
<16> CLKREQ_SATA# L1 SATACLKREQ#/GPIO35 CL_VREF0 C25 +CL_VREF0_ICH CH751H-40PT_SOD323-2
AE19 SLOAD/GPIO38 CL_VREF1 A19 Width:Spacing
1
+3VS 1 R809 2 100K_0402_5% CIR_EN# CIR_EN# AG22 12mil:12mil 2
SDATAOUT0/GPIO39 R254
AF21 SDATAOUT1/GPIO48 CL_RST0# F21 CL_RST#0 <8>
1 2 HDMI_HPD AH24 D18 453_0402_1% C278
R744 100K_0402_5% GPIO57 GPIO49 CL_RST1# 0.1U_0402_16V4Z
A8 GPIO57/CLGPIO5 1
A16
2
SB_SPKR MEM_LED/GPIO24 SUS_PW R_ACK 1
<27> SB_SPKR M7 SPKR GPIO10/SUS_PWR_ACK C18 2 +3VALW
iTPM Physical Presence AJ24 C11 R256 10K_0402_5%
MISC
<8> MCH_ICH_SYNC# MCH_SYNC# GPIO14/AC_PRESENT
ICH_TP3 B21 C20
TP8 TP3 WOL_EN/GPIO9
Assert = iTPM Physical Presence Enable T7 PAD AH20 TP8
CLGPIO5 TP9 AJ20
De-assert = iTPM disable T8 PAD
TP10 TP9
Mobil Platform T9 PAD AJ21 TP10 SUS_PWR_ACK Mobile Platform used only
**Only used in iAMT w/ME Firmware
GPIO57 Desktop Platform used only ICH9-M ES_FCBGA676 GPIO10
ICH9R3@ Desktop Platform used only
B
ICH9M Strap Pin Internal TPM Strap(Internal pull-down) Internal VR Enable Strap B
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5) Flash Descriptor Security Override Strap
+3VS 1 2 ICH_SPI_MOSI <19> SPI_MOSI Low= Disable
R258 @ 1K_0402_5% Low= Descriptor Security override
High= iTPM enable by MCH strap*
Low = Internal VR Disabled GPIO33 High= Default* (Internal pull-up)
ICH_INTVRMEN High = Internal VR Enabled(Default)
No Reboot Strap (Internal pull-up)
+RTCVCC 1 2 ICH_INTVRMEN <20>
+3VS 1 2 SB_SPKR SB_SPKR Low= *Default R259 330K_0402_5%
R261 @ 1K_0402_5% 1 2 ICH8M LAN100 SLP Strap
High= "No Reboot" R260 @ 0_0402_5%
LAN100_SLP <20>
DMI Termination Voltage
(Internal VR for VccLAN1.05 and VccCL1.05) GPIO49 Low= Desktop used
High= Mobile* (Internal pull-up)
Boot BIOS Strap (Internal pull-up) Low = Internal VR Disabled
ICH_LAN100_SLP High = Internal VR Enabled(Default)
PCI_GNT#0 SPI_CS#1 Boot BIOS Loaction
1 2 PCI_GNT#0 <19>
R263 @ 1K_0402_5%
0 0 RESERVED
1
R265
2
@ 1K_0402_5%
SPI_CS#1 <19> 0 1 SPI
1 0 PCI XOR Chain Entrance Strap
1 1 LPC* (Default) ICH_TP3 HDA_SDOUT Description
(Internal pull-up) (Internal pull-down)
0 0 RSVD
A16 Swap Override Strap +3VS
R266 @ 1K_0402_5%
AZ_SDOUT <20> 0 1 Enter XOR Chain
A 1 2 STRAP_A16 <19> A
R267 @ 1K_0402_5% Low= A16 swap override Enable 1 0 Normal Operation (Default)
PCI_GNT#3 ICH_TP3
High= Default* (Internal pull-up) R268 @ 1K_0402_5% 1 1 Set PCIE port config bit 1

ICH9M(3/4)-USB,GPIO,PCIE
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
U9F
www.rosefix.com
+RTCVCC A23
VCCRTC
6uA at G3 state VCC1_05[01]
A15 +1.05VS U9E
1 1 1 B15 1 1 AA26 H5
VCC1_05[02] VSS[001] VSS[107]
+ICH_V5REF A6
V5REF 2mA VCC1_05[03]
C15 AA27
VSS[002] VSS[108]
J23
C279 C280 C281 D15 C282 C283 AA3 J26
1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_05[04] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[003] VSS[109]
E15 AA6 J27
2 2 2 VCC1_05[05] 2 2 VSS[004] VSS[110]
+ICH_V5REF_SUS AE1
V5REF_SUS
2mA VCC1_05[06]
F15 AB1
VSS[005] VSS[111]
AC22
L11 AA23 K28
VCC1_05[07] VSS[006] VSS[112]
AA24
VCC1_5_B[01] 646mA 1634mA VCC1_05[08]
L12 AB28
VSS[007] VSS[113]
K29
AA25 L14 AB29 L13
D13 VCC1_5_B[02] VCC1_05[09] VSS[008] VSS[114]
AB24 L16 AB4 L15
CH751H-40PT_SOD323-2 VCC1_5_B[03] VCC1_05[10] VSS[009] VSS[115]
AB25 L17 AB5 L2
VCC1_5_B[04] VCC1_05[11] VSS[010] VSS[116]
+3VS 2 1 AC24 L18 AC17 L26
VCC1_5_B[05] VCC1_05[12] +1.5VS_DMIPLL_ICH +1.5VS VSS[011] VSS[117]
AC25 M11 AC26 L27
+ICH_V5REF VCC1_5_B[06] VCC1_05[13] VSS[012] VSS[118]
+5VS 2 1 AD24 M18 AC27 L5
R269 1 VCC1_5_B[07] VCC1_05[14] 0.01U_0402_16V7K L13 1 VSS[013] VSS[119]
CORE
D AD25 P11 2 AC3 L7 D
100_0402_5% VCC1_5_B[08] VCC1_05[15] MBK1608121YZF_0603 VSS[014] VSS[120]
AE25 P18 1 AD1 M12
C284 VCC1_5_B[09] VCC1_05[16] VSS[015] VSS[121]
AE26 T11 AD10 M13
1U_0402_6.3V4Z VCC1_5_B[10] VCC1_05[17] C285 C286 VSS[016] VSS[122]
AE27 T18 AD12 M14
2 VCC1_5_B[11] VCC1_05[18] 10U_0805_10V4Z VSS[017] VSS[123]
AE28 U11 AD13 M15
VCC1_5_B[12] VCC1_05[19] 2 VSS[018] VSS[124]
AE29 U18 AD14 M16
VCC1_5_B[13] VCC1_05[20] VSS[019] VSS[125]
F25 V11 AD17 M17
VCC1_5_B[14] VCC1_05[21] VSS[020] VSS[126]
G25 V12 AD18 M23
D14 VCC1_5_B[15] VCC1_05[22] +1.05VS VSS[021] VSS[127]
H24 V14 AD21 M28
CH751H-40PT_SOD323-2 VCC1_5_B[16] VCC1_05[23] VSS[022] VSS[128]
H25 V16 AD28 M29
VCC1_5_B[17] VCC1_05[24] VSS[023] VSS[129]
+3VALW 2 1 J24 V17 AD29 N11
VCC1_5_B[18] VCC1_05[25] VSS[024] VSS[130]
VCCA3GP
J25 V18 1 AD4 N12
+ICH_V5REF_SUS VCC1_5_B[19] VCC1_05[26] VSS[025] VSS[131]
+5VALW 2 1 K24 AD5 N13
R270 VCC1_5_B[20] C287 VSS[026] VSS[132]
2 K25 AD6 N14
100_0402_5% VCC1_5_B[21] 4.7U_0805_10V4Z VSS[027] VSS[133]
L23 AD7 N15
C289 VCC1_5_B[22] 2 VSS[028] VSS[134]
L24
VCC1_5_B[23] 23mA VCCDMIPLL R29 AD9
VSS[029] VSS[135]
N16
1U_0402_6.3V4Z L25 AE12 N17
1 VCC1_5_B[24] VSS[030] VSS[136]
M24 W23 AE13 N18
VCC1_5_B[25] VCC_DMI[1] +1.05VS VSS[031] VSS[137]
M25
VCC1_5_B[26] 48mA VCC_DMI[2]
Y23 AE14
VSS[032] VSS[138]
N26
N23 AE16 N27
VCC1_5_B[27] VSS[033] VSS[139]
N24 AB23 AE17 P12
VCC1_5_B[28] V_CPU_IO[1] VSS[034] VSS[140]
N25
VCC1_5_B[29]
2mA V_CPU_IO[2]
AC23 1 1 1 AE2
VSS[035] VSS[141]
P13
P24 AE20 P14
+1.5VS_PCIE_ICH VCC1_5_B[30] C290 C291 C292 VSS[036] VSS[142]
P25 AG29 AE24 P15
VCC1_5_B[31]
R24
VCC1_5_B[32] 308mAVCC3_3[01]
VCC3_3[02]
AJ6 0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
2 2
4.7U_0805_10V4Z AE3
VSS[037]
VSS[038]
VSS[143]
VSS[144]
P16
+1.5VS L14 2 1 10U_0805_10V4Z 2.2U_0603_6.3V6K R25 AC10 AE4 P17
KC FBM-L11-201209-221LMAT_0805 VCC1_5_B[33] VCC3_3[07] VSS[039] VSS[145]
1 R26 AE6 P2
VCC1_5_B[34] VSS[040] VSS[146]
1 1 1 R27 AD19 AE9 P23
+ VCC1_5_B[35] VCC3_3[03] +3VS VSS[041] VSS[147]
VCCP_CORE
C293 T24 AF20 AF13 P28
220U_6.3V_M C294 C295 C296 VCC1_5_B[36] VCC3_3[04] VSS[042] VSS[148]
T27 AG24 AF16 P29
VCC1_5_B[37] VCC3_3[05] VSS[043] VSS[149]
T28
VCC1_5_B[38] VCC3_3[06]
AC20 close to AG29 close to AG24 AF18
VSS[044] VSS[150]
P4
2 2 10U_0805_10V4Z
2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
For power consumption measurement T29
U24
VCC1_5_B[39]
1 1 1 1 1 1 1
AF22
AH26
VSS[045] VSS[151]
P7
R11
C VCC1_5_B[40] C297 VSS[046] VSS[152] C
U25 B9 AF26 R12
VCC1_5_B[41] VCC3_3[08] C298 C299 C300 C301 C302 C303 VSS[047] VSS[153]
V24 F9 AF27 R13
VCC1_5_B[42] VCC3_3[09] 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[048] VSS[154]
V25 G3 AF5 R14
+1.5VS +1.5VS_SATAPLL_ICH VCC1_5_B[43] VCC3_3[10] 2 2 2 2 2 2 2 VSS[049] VSS[155]
U23 G6 AF7 R15
VCC1_5_B[44] VCC3_3[11] VSS[050] VSS[156]
PCI
W24 J2 AF9 R16
L15 1 VCC1_5_B[45] VCC3_3[12] VSS[051] VSS[157]
2 W25
VCC1_5_B[46] VCC3_3[13]
J7 close to AD19 close to B9, G6, K7 close to AJ6 AG13
VSS[052] VSS[158]
R17
MBK1608121YZF_0603 1 1 K23 K7 AG16 R18
VCC1_5_B[47] VCC3_3[14] +3VS VSS[053] VSS[159]
Y24 AG18 R28
C304 C305 VCC1_5_B[48] VSS[054] VSS[160]
Y25 AG20 T12
VCC1_5_B[49] VSS[055] VSS[161]
10U_0805_10V4Z
2
1U_0402_6.3V4Z
2
11mA VCCHDA
AJ4 AG23
VSS[056] VSS[162]
T13
1 AG3 T14
VSS[057] VSS[163]
47mA 11mA VCCSUSHDA
AJ3 AG6
VSS[058] VSS[164]
T15
AJ19 C306 AG9 T16
VCCSATAPLL 0.1U_0402_16V4Z VSS[059] VSS[165]
AH12 T17
2 VSS[060] VSS[166]
1342mA VCCSUS1_05[1]
AC8 TP_VCCSUS1_05_ICH_1 @ PAD T10 AH14
VSS[061] VSS[167]
T23
+1.5VS AC16 F17 TP_VCCSUS1_05_ICH_2 @ PAD T11 AH17 B26
VCC1_5_A[01] VCCSUS1_05[2] VSS[062] VSS[168]
1 1 AD15 AH19 U12
VCC1_5_A[02] +3VALW VSS[063] VSS[169]
AD16 AH2 U13
C307 C308 VCC1_5_A[03] VSS[064] VSS[170]
AE15 AD8 AH22 U14
ARX
1U_0402_6.3V4Z 1U_0402_6.3V4Z AF15 AH25 U15
2 2 VCC1_5_A[05] VSS[066] VSS[172]
AG15 F18 +VCCSUS1_5_ICH_INT 1 AH28 U16
close to AE15 close to AF11 AH15
VCC1_5_A[07] 1 AH5
VSS[068] VSS[174]
U17
AJ15
VCC1_5_A[08] 212mA C310 C309 AH8
VSS[069] VSS[175]
AD23
A18 0.1U_0402_16V4Z AJ12 U26
VCCSUS3_3[01] 0.1U_0402_16V4Z 2 VSS[070] VSS[176]
AC11 D16 AJ14 U27
VCCPSUS
2
Symbol S0 S3 S4/S5 AD11
VCC1_5_A[10] VCCSUS3_3[03]
D17 AJ17
VSS[072] VSS[178]
U3
AE11 E22 AJ8 V1
AF11 B11 V13
VCC1_5_A[12] VSS[074] VSS[180]
ATX
VCCLAN1_05 VCC_1_05 VCCLAN3_3 VCCLAN3_3 AG10

VCC1_5_A[13]
B14
VSS[075] VSS[181]
V15
AG11 B17 V23
VCC1_5_A[14] VSS[076] VSS[182]
AH10 B2 V28
VCC1_5_A[15] VSS[077] VSS[183]
VCCCL1_5 VCC_1_5_A VCCCL3_3 VCCCL3_3 close to AC9 AJ10
VCC1_5_A[16] VCCSUS3_3[05]
AF1 +3VALW B20
VSS[078] VSS[184]
V29
B
+1.5VS B23 V4 B
VSS[079] VSS[185]
AC9 1 1 1 B5 V5
VCC1_5_A[17] VSS[080] VSS[186]
VCCCL1_05 VCC_1_05 VCCCL3_3 VCCCL3_3 B8
VSS[081] VSS[187]
W26
1 1 AC18 C311 C312 C313 C26 W27
C314 C315 VCC1_5_A[18] 0.022U_0402_16V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z VSS[082] VSS[188]
AC19 C27 W3
VCC1_5_A[19] 2 2 VSS[083] VSS[189]
VCCSUS1_5 VCC_1_5_A VCCSUS3_3 VCCSUS3_3 VCCSUS3_3[06]
T1 close to T1 close to AF1 2 E11
VSS[084] VSS[190]
Y1
0.1U_0402_16V4Z AC21 T2 E14 Y28
2 2 VCC1_5_A[20] VCCSUS3_3[07] VSS[085] VSS[191]
T3 E18 Y29
0.1U_0402_16V4Z VCCSUS3_3[08] VSS[086] VSS[192]
VCCSUS1_05 VCC_1_05 VCCSUS3_3 VCCSUS3_3 G10
VCC1_5_A[21] VCCSUS3_3[09]
T4 E2
VSS[087] VSS[193]
Y4
G9 T5 E21 Y5
Internal voltage regulators power these wells inside the ICH9 VCCSUS3_3[11]
T6 E24
VSS[089] VSS[195]
AG28
close to AC14 AC12 U6 E5 AH6
VCCPUSB
and current for this rail is accounted for in the sourcing voltage VCC1_5_A[23] VCCSUS3_3[12] VSS[090] VSS[196]
AC13 U7 E8 AF2
rail current requirements. AC14
VCC1_5_A[24] VCCSUS3_3[13]
V6 F16
VSS[091] VSS[197]
B25
close to AC7 close to AJ5 VCCSUS3_3[15]
V7 F28
VSS[093]
VCCUSBPLL 11mA
+1.5VS AJ5 W6 F29
VCCSUS3_3[16] VSS[094]
1 1 W7 G12
VCCSUS3_3[17] VSS[095]
USB CORE
AA7 Y6 G14 A1
C316 C317 VCC1_5_A[26] VCCSUS3_3[18] VSS[096] VSS_NCTF[01]
AB6 Y7 G18 A2
0.1U_0402_16V4Z 0.1U_0402_16V4Z VCC1_5_A[27] VCCSUS3_3[19] VSS[097] VSS_NCTF[02]
AB7 T7 G21 A28
2 2 VCC1_5_A[28] VCCSUS3_3[20] VSS[098] VSS_NCTF[03]
AC6 G24 A29
VCC1_5_A[29] VSS[099] VSS_NCTF[04]
AC7 G26 AH1
VCC1_5_A[30] VSS[100] VSS_NCTF[05]
G27 AH29
VCCLAN1_05_INT_ICH VSS[101] VSS_NCTF[06]
A10 G8 AJ1
VCCLAN1_05[1] VCCCL1_05_INT_ICH VSS[102] VSS_NCTF[07]
1 A11 G22 H2 AJ2
VCCLAN1_05[2] VCCCL1_05 VCCCL1_5_INT_ICH VSS[103] VSS_NCTF[08]
G23 1 H23 AJ28
C318 VCCCL1_5 VSS[104] VSS_NCTF[09]
+3VS A12 1 1 H28 AJ29
VCCLAN3_3[1] VSS[105] VSS_NCTF[10]
0.1U_0402_16V4Z
2 1
+1.5VS
B12
VCCLAN3_3[2] 78mA C319 H29
VSS[106] VSS_NCTF[11]
B1
A24 +3VS C320 C321 0.1U_0402_16V4Z B29
C322 VCCCL3_3[1] 1U_0402_6.3V4Z 0.1U_0402_16V4Z 2 VSS_NCTF[12]
VCCCL3_3[2]
B24
2 2
close to G22
GLAN POWER
2
0.1U_0402_16V4Z A27
VCCGLANPLL 23mA
1 close to G23 ICH9-M ES_FCBGA676
D28 ICH9R3@
A VCCGLAN1_5[1] A
C323 D29
VCCGLAN1_5[2] 80mA
0.1U_0402_16V4Z E26
2 VCCGLAN1_5[3]
E27
+1.5VS VCCGLAN1_5[4]
A26
VCCGLAN3_3 1mA
1 ICH9-M ES_FCBGA676
ICH9R3@
C324
+3VS Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z Issued Date 2009/06/12 Deciphered Date 2010/06/12 Title
2
ICH9M(4/4)-POWER&GND
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
SATA HDD Conn.

+5VS
1
1.2A
C697
10U_0805_10V4Z
1
www.rosefix.com
Place closely JHDD SATA CONN.
C698
0.1U_0402_16V4Z
1
C699
0.1U_0402_16V4Z
1
C700
0.1U_0402_16V4Z
+5VS
1
C721
SATA ODD Conn
1.1A
1
Place components close to ODD CONN.
C722 C723
1 1 1
@ C724 C725
2 2 2 2 10U_0805_10V4Z 10U_0805_10V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2
D D
JODD
GND 1
2 SATA_ITX_C_DRX_P4_ODD
A+ SATA_ITX_C_DRX_N4_ODD
A- 3
GND 4
5 SATA_IRX_DTX_N4_ODD
B- SATA_IRX_DTX_P4_ODD
B+ 6
GND 7
JHDD
GND 1 DP 8
2 SATA_ITX_C_DRX_P1 C713 1 2 0.01U_0402_25V7K 9 +5VS
A+ SATA_ITX_DRX_P1 <20> +5V
3 SATA_ITX_C_DRX_N1 C715 1 2 0.01U_0402_25V7K 10
A- SATA_ITX_DRX_N1 <20> +5V
GND 4 MD 11
5 SATA_IRX_DTX_N1 C717 1 2 0.01U_0402_25V7K 15 12
B- SATA_IRX_C_DTX_N1 <20> GND GND
6 SATA_IRX_DTX_P1 C719 1 2 0.01U_0402_25V7K 14 13
B+ SATA_IRX_C_DTX_P1 <20> GND GND
GND 7
SANTA_206401-1_RV
8 CONN@
V33 +3VS
V33 9
V33 10
C 11 C
GND
GND 12
GND 13
14 SATA_ITX_C_DRX_P4_ODD C733 1 2 0.01U_0402_25V7K
V5 +5VS SATA_ITX_DRX_P4 <20>
15 SATA_ITX_C_DRX_N4_ODDC734 1 2 0.01U_0402_25V7K W=60mils
V5 SATA_ITX_DRX_N4 <20>
16
GND
V5
17 SATA_IRX_DTX_N4_ODD
SATA_IRX_DTX_P4_ODD
C735 1
C736 1
2 0.01U_0402_25V7K
0.01U_0402_25V7K
SATA_IRX_C_DTX_N4 <20>
+5VALW 1.4A
U42
+USB_VCCA
For EMI request
Reserved 18 2 SATA_IRX_C_DTX_P4 <20>
GND 19 1 GND OUT 8 2 1
20 2 7 C693 1000P_0402_50V7K
V12 IN OUT
24 GND V12 21 3 IN OUT 6
23 GND V12 22 <30> USB_EN# 4 EN# FLG 5 USB_OC#0 <19,30>
1
G528_SO8
SANTA_191201-1 C752
CONN@ 4.7U_0805_10V4Z
this is temp. footprint 2 @
USB Conn
+USB_VCCA
C84 +USB_VCCA
2 1
+
220U_6.3V_M
B C63 B
2 1 C60
2 1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
<BOM
2R843Structure>
0_0402_5%
1 C64
2 1 C61
<BOM
2 Structure>
0_0402_5%
1 2 1
1000P_0402_50V7K R842
W=60mils 1000P_0402_50V7K W=60mils
@ W CM2012F2SF-900T04_0805 JUSB1 @
3 3 @ W CM2012F2SF-900T04_0805 JUSB2 @
4 4 USB20_N0_R
1 VCC GND 5
<19> USB20_N0 2 D- GND 6 3 3 4 4 1 VCC GND 5
<19> USB20_P0 USB20_P0_R 3 7 <19> USB20_N1 USB20_N1_R 2 6
D+ GND USB20_P1_R D- GND
2 2 1 1 4 GND GND 8 <19> USB20_P1 3 D+ GND 7
2 2 1 1 4 GND GND 8
2
L87 ALLTOP C107L8-10405-L
L86 D62 @ ALLTOP C107L8-10405-L
3
D65 @
2 1 2 1 PJDLC05_SOT23-3
PJDLC05_SOT23-3
<BOM
R839Structure>
0_0402_5% <BOM
R838Structure>
0_0402_5%
1
A A
1

SATA-HDD/ODD/USB
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
www.rosefix.com POWER/B Connector Check footprint and pin define
D D
JPOW ER
ON/OFFBTN# 1 1
<30,32> ON/OFFBTN#
2 2
3 3
2
4 4
D79 5 G1
PACDN042Y3R_SOT23-3 6 G2
@
ACES_85201-0405N
CONN@
1
C please close to JKB1
Touch/B Connector C
KEYBOARD CONN KSO16 1 2

C821 100P_0402_50V8J SW 2
KSO17 1 2
Right Switch 1 3
C818 100P_0402_50V8J
KSO2 1 2 TP_SW R 2 4 SMT1-05-A_4P
C789 100P_0402_50V8J
KSO1 1 2
Check signal to TP module through FFC
6
5
C790 100P_0402_50V8J
KSI[0..7] KSO0 1 2
KSI[0..7] <30>
C791 100P_0402_50V8J
KSO[0..17] KSO4 1 2 JTouch
KSO[0..17] <30>
C792 100P_0402_50V8J 1
KSO3 +5VS 1
1 2 <30> TP_CLK 2 2
C795 100P_0402_50V8J 3
<30> TP_DATA 3
KSO5 1 2 TP_SW L 4
JKB C796 100P_0402_50V8J TP_SW R 4
5 5 G7 7
JKB34 1 2 +3VS KSO14 1 2 6 8
34 KSO16 R755 300_0402_5% C797 100P_0402_50V8J SW 3 6 G8
33 Left Switch
3
KSO6 1 2 1 3 P-TW O_161021-06021_6P-T
32 KSO17 C798 100P_0402_50V8J D22 @
31 KSO7 TP_SW L SMT1-05-A_4P
30 1 2 2 4 PACDN042Y3R_SOT23-3
C799 100P_0402_50V8J @
29
3
KSO2 KSO13 1 2
6
5
28 KSO1 C800 100P_0402_50V8J D21
1
27 KSO0 KSO8
26 1 2 PACDN042Y3R_SOT23-3
KSO4 C801 100P_0402_50V8J @
25 KSO3 KSO9
24 1 2
B KSO5 C802 100P_0402_50V8J B
1
23 KSO14 KSO10
22 1 2
KSO6 C803 100P_0402_50V8J
21 KSO7 KSO11
20 1 2
KSO13 C804 100P_0402_50V8J
19 KSO8 KSO12
18 1 2
KSO9 C805 100P_0402_50V8J
17 KSO10 KSO15
16 1 2
KSO11 C807 100P_0402_50V8J
15 KSO12 KSI7
14 1 2
KSO15 C808 100P_0402_50V8J
13 KSI7 KSI2
12 1 2
KSI2 C810 100P_0402_50V8J
11 KSI3 KSI3
10 1 2
KSI4 C811 100P_0402_50V8J
9 KSI0 KSI4
8 1 2
KSI5 C812 100P_0402_50V8J
7 KSI6 KSI0
6 1 2
KSI1 C813 100P_0402_50V8J
5 JKB4 KSI5
4 2 1 +3VS 1 2
CAPS_LED# R762 300_0402_5% C814 100P_0402_50V8J
3 CAPS_LED# <30>
KSI6 1 2
2 NUM_LED# C815 100P_0402_50V8J
1 NUM_LED# <30>
KSI1 1 2
ACES_88170-3400 C816 100P_0402_50V8J
@ CAPS_LED# 1 2
C817 100P_0402_50V8J
NUM_LED# 1 2
A
C819 100P_0402_50V8J A

USB/BT/FP/Int. Cam
0.1
PWWAA LA6841P M/B
5 4 3 2 1
www.rosefix.com
+3V_W LAN +3V_W LAN +1.5VS
Default
PCIe Mini Card-WLAN/WiMax PJ18 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 1 1 +3VS 1 1 1 1 1 1
@ JUMP_43X79 CM17 CM18 CM19 CM20 CM21 CM22
+3V_W LAN PJ19 2 2 2 2 2 2

+1.5VS 2 1 0.01U_0402_25V4Z 4.7U_0805_10V4Z 0.01U_0402_25V4Z 4.7U_0805_10V4Z
2 1 +3VALW
JW LAN @ JUMP_43X79
1 1 2 2
3 3 4 4
BT_CTRL 5 6
5 6
<16> CLKREQ_W LAN# 7 7 8 8
9 9 10 10
<16> CLK_W LAN# 11 11 12 12
<16> CLK_W LAN 13 13 14 14
15 15 16 16
17 17 18 18
19 19 20 20 XMIT_OFF# <30>
21 21 22 22 PLT_RST# <8,19,26,30,31> WLAN&BT Combo module circuits
<19> PCIE_IRX_C_W LANTX_N4 23 23 24 24
<19> PCIE_IRX_C_W LANTX_P4 25 25 26 26 BT BT
27 27 28 28 on module on module
29 29 30 30 PM_SMBCLK <14,15,16,21>
<19> PCIE_ITX_C_W LANRX_N4 31 31 32 32 PM_SMBDATA <14,15,16,21> Enable Disable
<19> PCIE_ITX_C_W LANRX_P4 33 33 34 34
35 35 36 36 USB20_N7 <19>
WLAN/ WiFi 37 37 38 38 USB20_P7 <19> WiMax BT_CRTL H L
+3V_W LAN 39 39 40 40
41 41 42 42
43 43 44 44 BT_PWR# L H
45 45 46 46
47 47 48 48
<30> E51_TXD
R110 1 2 0_0402_5% E51_TXD_R 49 49 50 50 **If +3V_WLAN is +3VS, please
R106 1 2 0_0402_5% E51_RXD_R 51 52
<30> E51_RXD 51 52 remove D77
53 GND1 GND2 54
Debug card using D77 @
2
SUSP# 1 2 BT_CTRL
<30,33,39> SUSP#
R959 FOX_AS0B226-S40N-7F
100K_0402_5% @ CH751H-40PT_SOD323-2
D
1
2 Q47
<21> BT_PW R#
1
G BT@
S 2N7002_SOT23-3
3
Add BT_CTRL for WLAN & BT
Combo module at DVT

PCIe-WLAN/HDDVD/NAND/NEW
0.1
PWWAA LA6841P M/B
A B C D E
<19> PCIE_IRX_C_LANTX_P3
<19> PCIE_IRX_C_LANTX_N3
www.rosefix.com
CL1
CL2
1
1
2 0.1U_0402_16V7K PCIE_IRX_LANTX_P3
2 0.1U_0402_16V7K
<19> PCIE_ITX_C_LANRX_P3
PCIE_IRX_LANTX_N3
22
23
17
UL1
HSOP
HSON
LED3/EEDO
LED1/EESK
LED0
31
37
40
30 RL2 2 1 10K_0402_5% +LAN_REGOUT

LL1,CL13 will be changed to
2.2uH&4.7uF after EVT test
1
LL1
8105E_VB@
2
+LAN_VDD10
CL4,CL5,CL6,CL7 close to
Pin 27,39,47,48
+3V_LAN
HSIP EECS/SCL RL1

<19> PCIE_ITX_C_LANRX_N3 18 HSIN EEDI/SDA 32 2 1 10K_0402_5% 2.2UH +-5% NLC252018T-2R2J-N
1 2 1 2
Layout Note: LL1 must be 8105E_VB@ 0.1U_0402_16V4Z CL4
1 RL19 @ 0_0402_5% 16 1 LAN_MDI0+ within 200mil to Pin36, CL13 CL9 1 2 1
<16> CLKREQ_LAN# CLKREQB MDIP0
2 LAN_MDI0- CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z CL5
MDIN0 LAN_MDI1+ 200mil to LL1 2 1
8105E_VB@
<8,19,25,30,31> PLT_RST# 25 PERSTB MDIP1 4 1 2
+3V_LAN 5 LAN_MDI1- +LAN_REGOUT: Width =60mil 0.1U_0402_16V4Z CL6
MDIN1
<16> CLK_LAN 19 REFCLK_P NC/MDIP2 7 1 2
20 8 0.1U_0402_16V4Z CL7
<16> CLK_LAN# REFCLK_N NC/MDIN2
NC/MDIP3 10
2 @ 1 CLKREQ_LAN# NC/MDIN3 11
RL8 10K_0402_5% LAN_X1 43 CKXTAL1
1 2 SB_W AKE# LAN_X2 44 CKXTAL2 DVDD10 13 +LAN_VDD10
RL3 @ 10K_0402_5% 29 +LAN_VDD10 +LAN_EVDD10
DVDD10
41
SB_W AKE# DVDD10
<21> SB_W AKE# 28 2 1
LANWAKEB 0_0603_5% LL2
+3VS
1 2 CL19,CL20,CL21,CL22 close to
ISOLATEB 26 27 +3V_LAN
ISOLATEB DVDD33
39 CL18 CL17 Pin 3,13,29,45
+3V_LAN DVDD33 1U_0402_6.3V4Z 0.1U_0402_16V4Z +LAN_VDD10
1
14 12 2 1
NC/SMBCLK AVDD33 +3V_LAN
RL6 @ 15 42 1 2
1K_0402_1% NC/SMBDATA AVDD33
1 RL22 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 Close to Pin 21 0.1U_0402_16V4Z CL19
RL22 need always pull-high 48 1 2
for RTL8105E Efuse mode AVDD33 0.1U_0402_16V4Z CL20
2
ISOLATEB ENSW REG 33 1 2

ENSWREG 0.1U_0402_16V4Z CL21
EVDD10 21 +LAN_EVDD10
+LAN_VDDREG 34 1 2
VDDREG 0.1U_0402_16V4Z CL22
35 3 +LAN_VDD10
RL7 VDDREG AVDD10
6
15K_0402_5% AVDD10 +3V_LAN +LAN_VDDREG
9
2 AVDD10 2
1 2 46 45
RL5 2.49K_0402_1% RSET AVDD10
2 1
24 36 +LAN_REGOUT 0_0603_5% LL3 1 2
GND REGOUT 8105E_VB@
49
PGND UL1 CL28 CL29
4.7U_0603_6.3V6K 0.1U_0402_16V4Z
RTL8105E-GR QFN _6X6 8105E_VB@ 2 1 8105E_VB@
8105E_VB@
@ ISOLATEB 8105E_VC@
Need to change to non-LED type
<30,33> W OL_EN#
RL11 0_0402_5%
+3V_LAN
<30> W OL_EN
RL12 0_0402_5% LAN Conn.
RL4 JLAN
0_0402_5% 8105E_VB@
8
PR4-
ENSW REG 7 PR4+
RJ45_MIDI1- 6
RL23 PR2-
YL1
LAN_X1 1 2 LAN_X2 0_0402_5% 8105E_VC@ 5
PR3-
25MHZ_20PF_7A25000012 4 PR3+
3
1 1 3
RJ45_MIDI1+ 3
CL26 CL27 PR2+
27P_0402_50V8J 27P_0402_50V8J RJ45_MIDI0- 2
2 2 PR1-
RJ45_MIDI0+ 1
PR1+
SHLD1 9
SHLD2 10
SANTA_130452-C
@
UL3
LAN_MDI0+ 1 16 RJ45_MIDI0+ 1000P_1808_3KV7K

LAN_MDI0- TD+ TX+ RJ45_MIDI0- CL42 1000P_0402_50V7K RJ45_GND LANGND
2 15 1 2
TD- TX- CL36
3 CT CT 14 2 1 1 2
4 13 RL15 75_0402_1% 2 1
NC NC
2
5 12 CL41 1000P_0402_50V7K D69
NC NC RJ45_GND CL37 CL38 @
6 11 2 1 1 2
LAN_MDI1+ CT CT RJ45_MIDI1+ RL13 75_0402_1% PJDLC05_SOT23-3 4.7U_0603_6.3V6K
7 10 120P_0402_50V8J
LAN_MDI1- RD+ RX+ RJ45_MIDI1- 1 2
8 RD- RX- 9
Place these components 1 1 LFE8456E-R

4 colsed to LAN chip CL35 CL34
4
1
0.1U_0402_25V4K 0.1U_0402_25V4K
2 2
CL35 and CL34 for EMI request place near pin 3 and pin 6
RTL8105E 10/100 LAN
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PWWAA LA6841P M/B 0.1
A B C D E
5 4 3 2 1
www.rosefix.com
Codec 600 mA RA2
+PVDD1 0.1U_0402_16V4Z 1 2 0.1U_0402_16V4Z +5VS
Beep sound
1 1 0_0603_5% 1 1
CA57 CA44
CA43
2
CA56
JA1 2 2 2 2
2
+3VS 1 2 0.1U_0402_16V4Z +DVDD_IO JUMP_43X39 10U_0805_10V4Z 10U_0805_10V4Z
RA19 0_0603_5%
EC Beep
1
1 1 @ place close to chip RA7
CA2 CA1 1 2
<30> EC_BEEP#
1
+1.5VS 1 @ 2 47K_0402_5%
D RA20 0_0603_5% 10U_0805_10V4Z +3VS_DVDD RA11 D
2 2 +PVDD2 0.1U_0402_16V4Z
1 2 +5VS
place close to chip 0_0603_5%
1
CA61
1
@ CA62
1 1
PCI Beep RA8
CA13
RA1 0.1U_0402_16V4Z 35 mA CA63 CA58
<21> SB_SPKR 1 2 1 2 MONO_IN
+3VS 2 1 0.1U_0402_16V4Z @ 47K_0402_5%
0_0603_1% 2 2 2 2 0.1U_0402_16V4Z
1 1
+AVDD 10U_0805_10V4Z 10U_0805_10V4Z
CA8 CA7 RA3
10U_0805_10V4Z 68 mA 10U_0805_10V4Z 0.1U_0402_16V4Z 1
@ 2 +5VS
2 2 0_0603_5%
1
1
39
46
25
38
1 1 1 1
9
UA1 CA3 CA4 CA5 CA6 RA12 CA18
10K_0402_5% 0.1U_0402_16V4Z
PVDD1
PVDD2
AVDD1
AVDD2
DVDD_IO
DVDD
2
place close to chip
2
2 2 2 2
10U_0805_10V4Z 0.1U_0402_16V4Z
23 LINE1_L SPK_OUT_L+ 40 SPKL+ <28>

24 LINE1_R SPK_OUT_L- 41 SPKL- <28>
14 LINE2_L SPK_OUT_R+ 45 SPKR+ <28>
4.7U_0805_10V4Z CA23 15 44
LINE2_R SPK_OUT_R- SPKR- <28>
<28> MIC1_R_L 2 1
Ext. Mic 21 32 RA4 75_0402_1%
MIC1_L HP_OUT_L HP_L <28>
<28> MIC1_R_R 2 1 22 MIC1_R HP_OUT_R 33 RA5 75_0402_1%
HP_R <28> place close to chip
4.7U_0805_10V4Z CA29
AZ_BITCLK_HD
C
Int. Mic 16
17
MIC2_L @ C
MIC2_R @
SYNC 10 AZ_SYNC_HD <20> 1 2 1 2
+3VS R746 10_0402_5%
INT_MIC_DATA 2 6 CA80 22P_0402_50V8J
<17> INT_MIC_DATA GPIO0/DMIC_DATA BCLK AZ_BITCLK_HD <20>
@
2
INT_MIC_CLK RA46 3 close to Audio Codec(UA1) for EMI AZ_SYNC_HD 1 2
<17> INT_MIC_CLK GPIO1/DMIC_CLK
1 FBMA-10-100505-301T 5 AZ_SDOUT_HD <20> R222
SDATA_OUT 4.7K_0402_5% @ CA81 22P_0402_50V8J
CA83 EC_MUTE#
4 PD# 8 AZ_SDIN0_HD_R 2 1 @
<30> EC_MUTE# SDATA_IN AZ_SDIN0_HD <20>
27P_0402_50V8J @ RA6 33_0402_5% AZ_RST_HD# 1 2
1
2
EC_MUTE# 11 47 CA82 22P_0402_50V8J
<20> AZ_RST_HD# RESET# EAPD
SPDIFO 48
1
1 2 MONO_IN 12
RA45 CA12 100P_0402_50V8J PCBEEP
MONO_OUT 20
4.7K_0402_5% SENSE_A 13 SENSE A

29 place close to chip
2
MIC2_VREFO
18 SENSE B
MIC1_VREFO_R 30 +MIC1_VREFO_R CA28 10U_0805_10V4Z
EC control EC_MUTE# behavior: 1 2 36 CBP LDO_CAP 28 1 2
CA15
High-state / low-state 2.2U_0603_6.3V4Z 35 27 AC_VREF
CBN VREF +MIC1_VREFO_R +MIC1_VREFO_L
+MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1%
CA51 1 MIC1_VREFO_L JDREF
2 0.1U_0603_50V7K 1 1
43 PVSS2 CPVEE 34 1 2
42 CA14 2.2U_0603_6.3V4Z CA17 CA16 1 1
B CA47 1 PVSS1 B
2 0.1U_0603_50V7K 49 DVSS2 AVSS1 26 10U_0805_10V4Z @ @
2 2 @ CA37 CA36
7 DVSS1 AVSS2 37
CA48 1 2 0.1U_0603_50V7K 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z
ALC259-GR_QFN48_7X7 2 2
CA49 1 2 0.1U_0603_50V7K place close to chip
CA50 1 2 0.1U_0603_50V7K
DGND AGND
1 2
RA18 0_0603_5%
Sense Pin Impedance Codec Signals Function

place close to chip
39.2K PORT-I (PIN 32, 33) Headphone out SENSE_A
<28> MIC_SENSE 2 1
RA10 20K_0402_1%
20K PORT-B (PIN 21, 22) Ext. MIC
SENSE A <28> NBA_PLUG
RA21 39.2K_0402_1%
10K PORT-C (PIN 23, 24)
5.1K (PIN 48)

A A
39.2K PORT-E (PIN 14, 15)
SENSE B 20K PORT-F (PIN 16, 17) Int. MIC

10K PORT-H (PIN 20) Issued Date 2009/01/23 Deciphered Date 2010/01/23 Title
HD CODEC ALC272
0.1
PWWAA LA6841P M/B
5 4 3 2 1
Speaker Connector
www.rosefix.com
placement near Audio Codec UA1
Ext. Mic
<27> MIC1_R_L
<27> MIC1_R_R
2
2
RA31
1K_0402_5%
1K_0402_5%
1
1
2
RA32
1
2.2K_0402_5%
MIC1_L
MIC1_R
+MIC1_VREFO_L
RA22 2 1 +MIC1_VREFO_R
RA33 2.2K_0402_5%
RA30
SPKR+ 2 1 SPK_R1
<27> SPKR+
0_0603_5% 1
CA25
@ 10U_0805_10V4Z 2
2 CA27
1 1U_0402_6.3V4Z
@
CA26 1
RA34 @ 10U_0805_10V4Z
SPKR- 2 SPK_R2
<27> SPKR- 2 1
0_0603_5%
RA35
SPKL+ 2 1 SPK_L1
<27> SPKL+
0_0603_5% 1
CA19
@ 10U_0805_10V4Z 2
2 CA24
1 1U_0402_6.3V4Z
@
CA20 1
RA36 @ 10U_0805_10V4Z
SPKL- 2 SPK_L2
<27> SPKL- 2 1
0_0603_5%
HeadPhone/LINE Out JACK

JLINE
5 5
@ DA4 PJDLC05_SOT23-3
3 <27> NBA_PLUG 4 4 GND 10
1 GND 9
2 LA6 1 2 HP_R_L 3 8
<27> HP_R 3 8
KC FBM-L11-160808-121LMT 0603 6 7
6 7
JSPK LA7 1 2 HP_L_L 2
<27> HP_L 2
SPK_L1 1 KC FBM-L11-160808-121LMT 0603 1
SPK_L2 1 1
2 2
SPK_R1 3 1 FOX_JA63331-B39S4-7F
SPK_R2 3 CONN@
4 4 3
1 CA45 CA46 CA11 @
@ DA5 PJDLC05_SOT23-3 ACES_85204-0400N 2 100P_0402_50V8J 100P_0402_50V8J
@ 2
3
1 DA6 @ 0.1U_0402_16V4Z
2 PJDLC05_SOT23-3
For EMI
Ext.MIC/LINE IN JACK
JEXMIC
5 5
<27> MIC_SENSE 4 4 GND 10

GND 9
MIC1_R LA8 1 2 MIC1_L_R 3 8
3 8
KC FBM-L11-160808-121LMT 0603 6 7
6 7
MIC1_L LA9 1 2 MIC1_L_L 2 2
KC FBM-L11-160808-121LMT 0603 1 1
FOX_JA63331-B39S4-7F
3 1 CONN@
1
2 CA41 CA42 CA21
100P_0402_50V8J 100P_0402_50V8J
DA7 @ 2
PJDLC05_SOT23-3 0.1U_0402_16V4Z
For EMI

AUDIO AMP/MIC/SPK/VR
0.1
PWWAA LA6841P M/B
5 4 3 2 1
www.rosefix.com @
CC2
100P_0402_50V8J
2 1
D D
RC1
6.19K_0402_1% UC1
2 1 1 REFE
GPIO0 17
R63 1 2 0_0402_5% 2
+3VS_CR <19> USB20_N10 DM
R62 2 0_0402_5% CLK_48M_CR
<19> USB20_P10 1 3 DP CLK_IN 24 CLK_48M_CR <16>< 48MHz >
+3VS 1 2 4 3V3_IN XD_D7 23
RC4 0_0603_5% +VCC_3IN1 5
+V1_8 CARD_3V3
6 V18 SP14 22
1 1 1 21 SD_DATA2_MS_DATA5
CC1 CC3 CC4 SP13 MS_DATA1_SD_DATA3
7 XD_CD# SP12 20
4.7U_0805_10V4Z 0.1U_0402_16V4Z 1U_0402_6.3V4Z 19
SDW P_MSCLK_R SDW P_MSCLK SP11 SDCMD
1 2 8 SP1 SP10 18
2 2 2 RC24 0_0402_5% 9 SP2 SP9 16
1 SD_DATA1 10 15 MS_DATA2_SDCLK 1 2 MS_DATA2_SDCLK_R
SP3 SP8
EPAD
SD_DATA0 11 14 RC22 0_0402_5%
CC10 SP4 SP7 SDCD#
12 SP5 SP6 13 1 CC9
10P_0402_50V8J 10P_0402_50V8J
2 RTS5138@ RTS5138-GR_QFN24_4X4 @
@
25
2
UC1
For EMI request

For EMI request
C RTS5137@ C
for EMI request

< 2 in 1 Card Reader >
CLK_48M_CR
1
JREAD R748
1 MS_DATA1_SD_DATA3 @ 10_0402_5%
D3 SDCMD
CMD 2
3
2
VSS1
VDD 4 +VCC_3IN1 1
5 MS_DATA2_SDCLK_R
CLK C785
VSS2 6 1 1
CC6 CC5 @ 22P_0402_50V8J
SD_DATA0 2
D0 7
8 SD_DATA1 0.1U_0402_16V4Z 1U_0402_6.3V4Z
D1 SD_DATA2_MS_DATA5 2 2
D2 9
10 SDW P_MSCLK_R
WP SDCD#
CD 11
GND1 12
B B
GND2 13
GND3 14
GND4 15
TAITW _PSDAT3-09GLAS1N14N @
A A

RTS5138 Card Reader
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom PWWAA LA6841P M/B 0.1
5 4 3 2 1
5 4 3 2 1
+3VL
www.rosefix.com
+3VL Reserve for EMI test
0.1U_0402_16V4Z 0.1U_0402_16V4Z
1 1 C771 1 1 2 2 C769
C770 1 2 PLT_RST# 1 2
C772 C773 C774 C775 C784 100P_0402_50V8J
1000P_0402_50V7K1000P_0402_50V7K 0.1U_0402_16V4Z @
2 2 2 2 1 1 EC_SMI# 1 2
111
125
0.1U_0402_16V4Z 0.1U_0402_16V4Z C781 100P_0402_50V8J
22
33
96
67
9
for EMI request U43 @
KB_RST# 1 2
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
CLK_PCI_EC C783 100P_0402_50V8J
@
1
D D
R738 1 21 BATT_TEMPA 1 2
<20> GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F
@ 10_0402_5% 2 23 C776 100P_0402_50V8J
<20> KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 EC_BEEP# <27>
3 26 ACIN_D 1 2
<21,31> SERIRQ SERIRQ# FANPWM1/GPIO12
4 27 C779 100P_0402_50V8J
<20,31> LPC_FRAME# ACOFF <34,36>
2
LFRAME# ACOFF/FANPWM2/GPIO13
1 <20,31> LPC_AD3 5 LAD3
<20,31> LPC_AD2 7 LAD2 PWM Output
C778 8 63 BATT_TEMPA
<20,31> LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMPA <35>
@ 22P_0402_50V8J
2 <20,31> LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I/AD2/GPIO3A 65 ADP_I <36>
CLK_PCI_EC 12 AD Input 66
<16> CLK_PCI_EC PCICLK AD3/GPIO3B ADP_V <36>
13 75 +5VS
<8,19,25,26,31> PLT_RST# PCIRST#/GPIO05 AD4/GPIO42 +3VALW
ECRST# 37 76
+3VL R739 ECRST# SELIO2#/AD5/GPIO43 TP_CLK
<21> EC_SCI# 20 SCI#/GPIO0E 1 2
1
47K_0402_5% 38 4.7K_0402_5% R740
ECRST# RN3 CLKRUN#/GPIO1D TP_DATA LID_SW #
2 1 DAC_BRIG/DA0/GPIO3C 68 1 2 2 1
100K_0402_5% 70 4.7K_0402_5% R741 47K_0402_5% R766
EN_DFAN1/DA1/GPIO3D EN_DFAN1 <4>
2 1 DA Output IREF/DA2/GPIO3E 71 IREF <36>
C780 0.1U_0402_16V4Z KSI0 55 72 CHGVADJ <36>
2
KSI1 KSI0/GPIO30 DA3/GPIO3F
56 KSI1/GPIO31
KSI2 57 SYSON 1 2
KSI3 KSI2/GPIO32 4.7K_0402_5% R743
58 KSI3/GPIO33 PSCLK1/GPIO4A 83 EC_MUTE# <27>
KSI4 59 84 VR_ON 1 2
+3VL KSI4/GPIO34 PSDAT1/GPIO4B USB_EN# <23>
KSI5 60 85 10K_0402_5% R262
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86
+3VL
1 2 KSO1 KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK <24>
R595 47K_0402_5% KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA <24>
1 2 KSO2 KSO1 40 1 2
R596 47K_0402_5% KSO2 KSO1/GPIO21 R742 330K_0402_5%
41 KSO2/GPIO22
C KSO3 42 97 VGATE D64 C
KSO3/GPIO23 SDICS#/GPXOA00 VGATE <8,21,40>
to avoid EC entry ENE test mode KSO4 43 KSO4/GPIO24 SDICLK/GPXOA01 98 W OL_EN# <26,33>
ACIN_D 2 1 ACIN <21,36>
KSO5
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
CH751H-40PT_SOD323-2
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW # <31>
KSO7 46 SPI Device Interface
KSO8 KSO7/GPIO27
47 KSO8/GPIO28
KSO9 48 119 ENBKL 1 2
KSI[0..7] KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO <31> UMA_ENBKL <10>
KSO10 49 120 R745 0_0402_5%
<24> KSI[0..7] KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI <31>
KSO11 50 SPI Flash ROM 126 1 2
KSO[0..17] KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK <31>
KSO12 51 128 R749 0_0402_5% 2
<24> KSO[0..17] KSO12/GPIO2C SPICS# SPI_CS# <31>
KSO13 52 1 2
KSO14 KSO13/GPIO2D C857 R747 100K_0402_5%
53 KSO14/GPIO2E
RP23 KSO15 54 73 33P_0402_50V8J
KSO16 KSO15/GPIO2F CIR_RX/GPIO40 1
81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74 @
+3VL 1 8 EC_SMB_CK1 KSO17 82 89
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG <36>
2 7 EC_SMB_DA1 90
BATT_CHGI_LED#/GPIO52 BATT_FULL_LED# <32>
+3VS 3 6 EC_SMB_CK2 91
CAPS_LED#/GPIO53 CAPS_LED# <24>
4 5 EC_SMB_DA2 EC_SMB_CK1 77 GPIO 92
<35> EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW _LED# <32>
EC_SMB_DA1 78 93
<35> EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55
2.2K_8P4R_5% EC_SMB_CK2 79 SM Bus 95 SYSON
<4> EC_SMB_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON <38,39>
EC_SMB_DA2 80 121 VR_ON
<4> EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON <40>
127 ACIN_D
AC_IN/GPIO59
<21> PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# <21>

<21> PM_SLP_S5# 14 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 101 EC_LID_OUT# <21>
<21> EC_SMI# 15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON <32,37>
16 LID_SW#/GPIO0A EC_SWI#/GPXO06 103
17 104 PM_PW ROK
B <26> W OL_EN SUSP#/GPIO0B ICH_PWROK/GPXO06 B
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# <17>
<8> MCH_TSATN_EC# 19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 XMIT_OFF# <25>
<17> INVT_PW M 25 EC_THERM#/GPIO11 GPXO10 107
<4> FAN_SPEED1 28 FAN_SPEED1/FANFB1/GPIO14 GPXO11 108
29 FANFB2/GPIO15
<25> E51_TXD 30 EC_TX/GPIO16
<25> E51_RXD 31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110 PM_SLP_S4# <21>
32 112 ENBKL
<24,32> ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXID2
<32> PW R_LED# 34 PWR_LED#/GPIO19 GPXID3 114
<24> NUM_LED# 36 NUMLED#/GPIO1A GPI GPXID4 115 EC_THERM# <21>
116 ICH_PW ROK 1 2
GPXID5 SUSP# <25,33,39>
117 R231 10K_0402_5%
GPXID6 PBTN_OUT# <21>
@ 118 PM_PW ROK 1 2
GPXID7 USB_OC#0 <19,23>
CRY1 R101 1 2 0_0402_5% 122 R264 10K_0402_5%
CRY2 R102 1 XCLK1 +3VS
2 0_0402_5% 123 XCLK0 V18R 124 +EC_V18R
@
AGND
R97 1 2 0_0402_5% 1 2
GND
GND
GND
GND
GND
<21> EC_CLK
1 C782 C777 0.1U_0402_16V4Z
1
5
4.7U_0805_10V4Z
R624 C451 KB926QFE0_LQFP128_14X14 VGATE 2
P
11
24
35
94
113
69
R389 100K_0402_5% @ B
4
18P_0402_50V8J
2 Y ICH_PW ROK <8,21>

CRY1 1 2CRY2 PM_PW ROK 1 A
G
2
@ 10M_0402_5% U5
3
NC7SZ08P5X_NL_SC70-5
1 1 1 2
A
R752@ 0_0402_5% A
1
C449 C450
Y4 To reduce CMOS dischage fail rate
18P_0402_50V8J
OSC
OSC
18P_0402_50V8J
2 2
NC
NC

2
ENE-KB926 RevD2
32.768KHZ_12.5PF_Q13MC14610002 0.1
PWWAA LA6841P M/B
5 4 3 2 1
Lid SW LPC Debug Port
SPI Flash (16Mb*1)
www.rosefix.com
+3VL
+3VALW
U48
APX9132ATI-TRL_SOT23-3
Please place the PAD under DDR DIMM.
+3VS
H1
2 3
GND
VDD VOUT LID_SW # <30>
6 5
1 20mils 1 1
1
C786 U47 1 2 7 4
<21,30> SERIRQ PLT_RST# <8,19,25,26,30>
8 4 C822 C823 R761 0_0402_5%
0.1U_0402_16V4Z VCC VSS 0.1U_0402_16V4Z 10P_0402_50V8J
2 2 2
3 W <20,30> LPC_AD3 8 3 LPC_AD2 <20,30>
7 HOLD
<20,30> LPC_AD1 9 2 LPC_AD0 <20,30>
<30> SPI_CS# 1 S
<30> SPI_CLK 6 C <20,30> LPC_FRAME# 10 1 CLK_PCI_DDR <16>
<30> EC_SO_SPI_SI 5 D Q 2 EC_SI_SPI_SO <30>
2
MX25L1605DM2I-12G_SO8-200mil @ DEBUG_PAD R764
22_0402_5%
1
2
SPI_CLK 2 R953 1 1 2
33_0402_5% C852 33P_0402_50V8J C820
22P_0402_50V8J
reserve for EMI, close to U46 1
for EMI
close to the H9 boss
+3VALW +5VS B+
+5VALW
1
1 1 C66
1 C62 C65
C68 0.1U_0402_10V6K
0.1U_0402_10V6K 0.1U_0402_10V6K 2
0.1U_0402_10V6K 2 2
2

SPI ROM/TP/KB/Debug
0.1
PWWAA LA6841P M/B
5 4 3 2 1
Power Button
www.rosefix.com
+3VL
ISPD
ZZZ
DC-IN
PJP1
PCB PJP1
2
45@
R765
D DAZ0HE00100 D
SW 5 @ 100K_0402_5%
TJG-533-V-T/R_6P U3 U3
1
1 3 ON/OFFBTN#
ON/OFFBTN# <24,30> 51_ON# <34>
TOP side
2 4 1
C646
NB_GL40_R3 NB_GL40_R1
6
0.1U_0402_16V4Z
6
5
@ Q28A CANTIGA GL40 CANTIGA GL40

SW 6@ 2 2N7002DW -T/R7_SOT363-6 GL40R3@ GL40R1@
TJG-533-V-T/R_6P
<30,37> EC_ON 2 another at page36
1 3
2
U3 U9
1
BTM side 2 4 For EMI request R767
10K_0402_5%
NB_GM45_R1 SB_R1
6
5
1
debug phase using CANTIGA GM45 ICH9-M ES
GM45R1@ ICH9R1@
Screw Hole
C C
Vf=2.0V(typ),2.4V(max)
DC-IN LED If=30mA(max) footprint is SC510UYG000 H5 H6 H8 H9 H10 H11 H12 H13 H14
R768 D67 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
+5VALW 1 2 510_0402_5%
2 1 PW R_LED# <30>
@ @ @ @ @ @ @ @ @
1
HT-110UYG-CT_YEL/GRN
H2 H26
BATT CHARGE/FULL LED H_2P7x3P2N
@
H_2P7N
@
Vf=1.9V(typ),2.4V(max) for amber
1
Vf=2.0V(typ),2.4V(max) for green
If=30mA(max) 510_0402_5%
D70 R773
2 1 2 BATT_CHG_LOW _LED# <30>
footprint is SC510UDG000
+5VALW 1 510_0402_5%
R774
3 1 2 BATT_FULL_LED# <30>
H36 H33 H34 H35
CPU
HT-210UD/UYG_AMB/GRN
H_3P7 H_3P7 H_3P7 H_3P7
1
@ @ @ @
B B
SB
H15 H16
H_5P0N H_5P0N
MINI CARD @ @
1
H18 H19
H_3P3 H_3P3
@ @
1
PCB Fedical Mark PAD
FD1 FD2 FD3 FD4
A
@ @ @ @ A
1
Comm. SW/ Sub Conn./LEDS
0.1
PWWAA LA6841P M/B
5 4 3 2 1
A B C D E
Inrush current = 0A
+3VALW TO +3VS
+3VALW www.rosefix.com +3VS
1
Vgs=10V,Id=9A,Rds=18.5mohm
1
+5VALW TO +5VS
+5VALW
Inrush current = 0A
+5VS
1
4.7U_0805_10V4Z
1
+1.5V
+1.5V to +1.5VS
+1.5VS
4.7U_0805_10V4Z
Q32 C824 C825 4.7U_0805_10V4Z Q33 C826 C827 Vgs=10V,Id=14.5A,Rds=6mohm 1 1

Q34 C828 C829
470_0805_5%
470_0805_5%
8 D S 1 8 D S 1
470_0805_5%
7 D S 2 7 D S 2 8 D S 1
2
2 2 R781 2 2 R782
6 D S 3 6 D S 3 7 D S 2
2 2 R783
1 5 D G 4 5 D G 4 6 D S 3 1
1U_0402_6.3V4Z 1U_0402_6.3V4Z 5 4
SI4800BDY_SO8 D G
1 R784 2 +VSB SI4800BDY_SO8 1 R785 2 +VSB 1U_0402_6.3V4Z
3 1
3 1
1 1 47K_0402_5% 1 1 47K_0402_5% FDS6676AS_SO8 1 R786 2
0.01U_0402_25V7K
4.7U_0805_10V4Z
0.022U_0402_25V7K
4.7U_0805_10V4Z
+VSB
3 1
1
6
C831 1 FDS6676AS 1 220K_0402_5%
4.7U_0805_10V4Z
6
C830 R787 Q35A C832 C833 R788 Q36A
0.1U_0402_25V6
C835
330K_0402_5% Q35B 200K_0402_5% Q36B C834 R789 Q37A
2 2 SUSP 2 2 @ SUSP 5 820K_0402_5% Q37B
2 5 2
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 2 2 SUSP 5
2
2
2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6 2N7002DW -T/R7_SOT363-6
2
2N7002DW -T/R7_SOT363-6
4
+3VALW TO +3V_LAN
+3VALW +3VALW TO +3V_SB
+3VALW
2
Vgs=-4.5V,Id=3A,Rds<97mohm
R793
100K_0402_5% 2
@ C839 Q41
1
2 0.1U_0402_16V7K AO3413_SOT23 2
1
3
S
@ PJ35
1
1 G
<26,30> W OL_EN# 1 2 2 JUMP_43X39
R795@ 47K_0402_5% 2 @ +3V_LAN
2
C837 D
1
0.01U_0402_25V7K @
@ Inrush current = 0A 2
1
1 1 1 1
C43 C67
C840 C841 1U_0402_6.3V4Z
4.7U_0805_10V4Z 10U_0805_6.3V6M 10U_0805_6.3V6M
@ 2 2 2 2
3 3
+5VALW
2
+0.75VS
R796
100K_0402_5%
2
R802
1
470_0805_5% SUSP
<38> SUSP
3
1
Q28B
2N7002DW -T/R7_SOT363-6
D
1
<25,30,39> SUSP# 5 another at page35
Q30 2 SUSP
2
2N7002_SOT23-3 G
4
S another at page35
3
R799
10K_0402_5%
1
4 4

DC-DC INTERFACE
0.1
PSWAA LA6511P M/B
A B C D E
A B C D
www.rosefix.com PF1
PL1
SMB3025500YA_2P
VIN
PR1
PreCHG
PD1
PQ1
TP0610K-T1-E3_SOT23-3
DC301001M80 DC_IN_S1 1 2 DC_IN_S2 1 2

VIN 1 2 2 1 3 1 B+
1K_1206_5%
@ PJP1 RLS4148_LL34-2
7A_24VDC_429007.W RML PR2
1
1
+ 1 1 2 1
1000P_0402_50V7K
1000P_0402_50V7K
100P_0402_50V8J
100P_0402_50V8J
1K_1206_5% PR3 PR4
+ 2
1
PR5 100K_0402_5% 100K_0402_5%
PC4
PC1
PC2
2
PC3
3 1 2
2
-
1K_1206_5%
2
- 4
PR6
SINGA_2DW -0005-B03 1 2
1
1K_1206_5%
PR7
PR12
1 2 100K_0402_5%
1K_1206_5%
1 2
1
VIN PD2
<30,36> ACOFF 2
1 2 2
2
<37> +5VALW P 3
PD3
RB715F_SOT323-3 PQ2 PQ3
RLS4148_LL34-2 DTC115EUA_SC70-3
3
DTC115EUA_SC70-3
1
1
1
PR8 PR9
PQ4 68_1206_5% 68_1206_5%
2 TP0610K-T1-E3_SOT23-3 2
2
PD4
2 1 N1 3 1
BATT+ VS
RLS4148_LL34-2
1
1
1
PC5
PR10 PC6
0.1U_0603_25V7K
100K_0402_1% 0.22U_0603_25V7K
2
2
2
2
PR11
<32> 51_ON# 1 2
22K_0402_1%
PJ3
+3VLP 2 2 1 1 +3VL
@ JUMP_43X39
(100mA,40mils ,Via NO.= 2)
PJ332 PJ76
+3VALW P 2 2 1 1 +3VALW +0.75VSP 2 2 1 1 +0.75VS
3
@ JUMP_43X118 @ JUMP_43X79 3
(5A,200mils ,Via NO.= 10) (0.98A,40mils ,Via NO.= 2)

OCP=7.7A
PJ352
+5VALW P 2 2 1 1 +5VALW
PJ153
@ JUMP_43X118 2 1
2 1
(5A,200mils ,Via NO.= 10) @ JUMP_43X118
OCP=7.9A
PJ152
PJ182 +1.5VP 2 2 1 1 +1.5V
+1.8VP 2 1 +1.8V @ JUMP_43X118

2 1
@ JUMP_43X39
(7.5A,300mils ,Via NO.= 15)
(1.46A,60mils ,Via NO.= 3) OCP=8.87A
PJ402 ACIN
PJ2 2 2 1 1
Precharge detector
@ JUMP_43X118
+VSBP 2 2 1 1 +VSB Min. typ. Max.
@ JUMP_43X39 PJ403
+1.05VSP 2 1 +1.05VS
H-->L 14.42V 14.74V 15.23V
(120mA,40mils ,Via NO.= 1) 2 1
4
@ JUMP_43X118 L-->H 15.39V 15.88V 16.39V 4
(7.5A,300mils ,Via NO.=15)

OCP=8.41A

DCIN & DETECTOR
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS KSWAA 0.1
A B C D
A B C D
www.rosefix.com
VMB
1
PF2 PL2 1
@ PJP2 10A_125V_451010MRL SMB3025500YA_2P
1 BATT_S1 1 2 1 2
1 BATT+
2 2
BATT_P3
3 3
4 BATT_P4
+3VLP PH1 under CPU botten side :
4 BATT_P5
5 5 CPU thermal protection at 90 degree C
1
10 6 EC_SMDA PC8
GND 6 EC_SMCA PR14 PC7
11
12
GND 7 7
8 1K_0402_1% 1000P_0402_50V7K 0.01U_0402_25V7K Recovery at 56 degree C
2
GND 8
13 GND 9 9
2
SUYIN_200045MR009G171ZR
PD6
2
VL
1
1
3 PR15
1
1
PD5 23.2K_0402_1%
PJSOT24C_SOT23-3 PC9
PJSOT24C_SOT23-3
2
0.1U_0402_16V4Z
2
PR16 SE070104Z80
2
6.49K_0402_1% PR18
2 1 10.7K_0402_1%
+3VLP PU1
1
1 8
1
VCC TMSNS1
1
PH1
PR19 2 GND RHYST1 7
100K_0402_1%_NCP15W F104F03RC
1K_0402_1%
<37> VS_ON 3 6
2
2 OT1 TMSNS2 2
2
2
4 OT2 RHYST2 5
PR20 PR21 BATT_TEMPA <30>
100_0402_1% G718TM1U_SOT23-8
100_0402_1%
1
EC_SMB_DA1 <30>
EC_SMB_CK1 <30>
Rset = 3 * Rtmh
Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
Rtmh at 90C = 7.79K, Rtml at 56C = 26.1K

Rset = 3 * 7.79K = 23.37K ==> 23.2K
Rhyst = (23.2K * 26.1K) / (3 * 26.1K - 23.2K) = 10.99K ==> 10.7K
PQ5
TP0610K-T1-E3_SOT23-3
B+ 3 1 +VSBP
0.22U_0603_25V7K
100K_0402_1%
1
3 3
PC10
1
1
PR23
PC11 @
VL @ 0.1U_0603_25V7K
2
2
2
PR24
2
1 2
PR25 22K_0402_1%
100K_0402_1%
1
D
PR26
1 2 2 PQ6
<21,37> POK
G SSM3K7002FU_SC70-3
0_0402_5%
S
3
1
@ PC12
.1U_0402_16V7K
2
4 4

BATTERY CONN / OTP
A B C D
A B C D
www.rosefix.com
2
PR215
PQ203 P2 PQ204 P3 B+ PC236
CHG_B+ PQ207
AO4435_SO8 AO4407A_SO8 0.02_1206_1% 10U_1206_25V6M PL201 AO4435_SO8
1
VIN 8 1 1 8 1 4 2 1 1 8
7 2 2 7 HCB2012KF-121T50_0805 2 7
6 3 3 6 2 3 CSIN 3 6
5 5 5
10U_1206_25V6M
10U_1206_25V6M
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
CSIP
4
1
1
PC231
PC232
PC233
PC234
PC235
VIN PreCHG
2
PC211 PR236
1 2
VIN
2
1
0.1U_0603_25V7K
5600P_0402_25V7K
47K_0402_1%
1
1
2
1 1
6251VDD
PR210 LDO 5.075V
1
PC210
200K_0402_1% PR212 PR226 PR237
2
ACSETIN
200K_0402_1% 191K_0402_1% 10K_0402_1%
2
2.2U_0603_6.3V6K
PD201
1 1
RB751V-40_SOD323-2 ACSETIN
1000P_0402_25V8J
1
PC212
1 1
3
1
1.26V
1
PC217
2
PR228
PR227 14.3K_0402_1% PQ215
2 2
2
PR216 10_1206_5% DTC115EUA_SC70-3
2
10K_0402_1%
2
PQ210 <30> FSTCHG 2 1 PU200
1
1
DTA144EUA_SC70-3 PC218 PC222
3
1 24 DCIN 2 1 PR238 2200P_0402_25V7K
1
VDD DCIN
1
2
0.1U_0603_25V7K 100K_0402_1%
PR213 PR217
BATT_ON 2 2 23 ACPRN <37>
2
PQ211 150K_0402_1% 100K_0402_1% ACSET ACPRN
DTC115EUA_SC70-3 PR229 20_0402_5%
2
2
6251_EN 3 22 1 2 CSON BATT_ON
6
D EN CSON
1
D
PC219
3
5
6
7
8
2 0.047U_0402_16V7K ACPRN 2
G 4 21 1 2 CSOP PQ201 G
1
CELLS CSOP AO4466L_SO8 PQ216
PR230 20_0402_5% S
3
S PQ212A PC213 SSM3K7002FU_SC70-3
1
DMN66D0LDW -7_SOT363-6 1 2 5 20 PR2312 1 20_0402_5%

ICOMP CSIN
2
PC220 4
PQ212B PC214 PR218 6800P_0402_25V7K
0.1U_0603_25V7K
DMN66D0LDW -7_SOT363-6 1 2 1 2 6 19 1 2
1
VCOMP CSIP PL202
3
2 D 2
10K_0402_1% PR232 2_0402_5% PR235

5 0.01U_0402_25V7K PR219 10UH_MSCDRI-104A-100M-E_4.6A_20% BATT+
3
2
1
G 1 2 7 18 LX_CHG 1 2 CHG 1 4
<30> ADP_I ICM PHASE
47K_0402_1%
1
5
6
7
8
S PC215 2 3
4
PR211 1 2 6251VREF 8 17 DH_CHG PQ202

47K_0402_5% PR220 VREF UGATE PR206
0.02_1206_1%
PACIN 154K_0402_1% PC205 4.7_1206_5%
10U_1206_25V6M
10U_1206_25V6M
10U_1206_25V6M
1 2 .1U_0402_16V7K PR205
<30> IREF 2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1 @
2
CHLIM BOOT
1
0_0603_5% 4 AO4466L_SO8
1
1
0.01U_0402_25V7K
0.1U_0603_25V7K
PC202
PC203
PC204
PR222 PD202
1
1
6251VREF
1 2 6251aclim 10 15 6251VDDP PC206
ACLIM VDDP
1
PQ213 RB751V-40_SOD323-2
PC216
2
PR221 75K_0402_1% 680P_0603_50V7K
DTC115EUA_SC70-3 1 2 6251VDD
2
3
2
1
ACOFF 2 120K_0402_1% 11 14 DL_CHG PR233 4.7_0603_5%
<30,34> ACOFF
2
VADJ LGATE
2
2
PC221
PR223 12 13 4.7U_0603_6.3V6M
1
GND PGND
20K_0402_1%
3
2 G5209S31U_SSOP24
PR224
<30> CHGVADJ 1 2
15.4K_0402_1%
2
PR225
3 3
31.6K_0402_1%
VIN
1
6251VDD
1
PR241
1
10K_0402_1% @ PR246
PR240 1 2 ACIN <21,30>
PR242 309K_0402_1%
47K_0402_1%
10K_0402_1% @ PR247
2
10K_0402_1%
2
PACIN 1 2 ADP_V <30>

1
1
Vin Detector
1
@ PR248 @ PC223
1
ACPRN 47K_0402_1% .1U_0402_16V7K

2 PR243
2
CP mode CHGVADJ=(Vcell-4)*9.445 14.3K_0402_1% High 18.089V
2
PQ214
Iada=0~3.421A(65W) CP= 92%*Iada; CP=3.15A DTC115EUA_SC70-3 Low 17.44V
2
3
Vaclim=0.6221V(65W) PR222=75K, PR223=20K
1.26 / 14.3 * 205.3 = 18.089V
CC=0.25A~3.6A
4
IREF=0.9133*Icharge Vcell CHGVADJ 4
IREF=0.228V~3.29V 4V 0V
VCHLIM need over 95mV 4.2V 1.889V
4.35V 3.30575V
CHARGER
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Huron river
A B C D
5 4 3 2 1
www.rosefix.com 2VREF_6182
1
PC363
1U_0603_10V6K
2
D D
PR362 PR364
13K_0402_1% 30K_0402_1%
1 2 1 2
PR363 PR365
UP6182_B+ 20K_0402_1% 19.1K_0402_1%
1 2 1 2 UP6182_B+
PL331
HCB2012KF-121T50_0805
ENTRIP1
ENTRIP2
B+ 1 2 +3VLP PR337 PR357
150K_0402_1% 150K_0402_1%
1 2 1 2
10U_1206_25V6M
2200P_0402_50V7K
1
PC366
1
PC360
PC367
10U_1206_25V6M
4.7U_0805_10V6K
8
7
6
5
5
6
7
8
PU330
PC368
10U_1206_25V6M
2
1
PQ331 PQ351
PC361
ENTRIP2
VFB2
TONSEL
VFB1
ENTRIP1
VREF
2
AO4466L_SO8
25
2
P PAD
4 4
7 VO2 VO1 24 POK <21,35>
C 8 23 C
PC335 VREG3 PGOOD PC355
1 PR335 PR355 AO4466L_SO8
2
3
3
2
1
0.1U_0603_25V7K
1 2 1 2 BST_3V 9 VBST2 VBST1 22 BST_5V 1 2 1 2 0.1U_0603_25V7K
PL332 0_0603_5% 0_0603_5% PL352
UG_3V 10 21 UG_5V
4.7UH_SIL1045R-4R7PF_6.3A_30% DRVH2 DRVH1 4.7UH_SIL1045R-4R7PF_6.3A_30%
LX_3V LX_5V
+5VALWP
+3VALWP 1 2 11 LL2 LL1 20 1 2
8
7
6
5
5
6
7
8
1
1
PQ332 LG_3V 12 19 LG_5V
DRVL2 DRVL1
SKIPSEL
PR336 PR356
330U_6.3V_M
VREG5
4.7_1206_5% 4.7_1206_5%
VCLK
1 1
GND
EN0
VIN
4 4
2
2
+ +
PC352
PC332
PR360 PQ352
13
14
15
16
17
18
330U_6.3V_M
1
1
PC336 499K_0402_1% TPS51125ARGER_QFN24_4X4 PC356
2 AO4712L_SO8 AO4712L_SO8 2
15mohm B+ 1 2 15mohm
1
2
3
3
2
1
680P_0603_50V7K 680P_0603_50V7K
2
2
SF000002O00
1
100K_0402_5%
Ipeak=5A
1
VL
PR361
Imax=3.5A PC362
1
1U_0402_6.3V6K
F=305KHz PC364
2
4.7U_0805_10V6K
2
Total Capacitor 220uF @ PR374 UP6182_B+ Ipeak=5A
2
0_0402_5%
ESR 15mohm ENTRIP11 2
ENTRIP1_HW <20> Imax=3.5A
@ PR375
F=245KHz
B 0_0402_5%
ENTRIP2_HW <20>
Total Capacitor 220uF B
ENTRIP2 1 2 ESR 15mohm
1
PC365
2VREF_6182 0.1U_0603_25V7K
2
D D
6
2 5
PQ360A G G PQ360B
DMN66D0LDW -7_SOT363-6 DMN66D0LDW -7_SOT363-6
S S
1
PR370
VL 2 1
100K_0402_1%
1
<35> VS_ON
PR371
VS 1 2 2
100K_0402_1%
2.2U_0603_10V6K
42.2K_0402_1%
PQ361
1
DTC115EUA_SC70-3
PR372
PC370
D
1
PR373
2
<36> ACPRN 1 2 2
2
G
A 200K_0402_1% A
S PQ362
3
1
SSM3K7002FU_SC70-3
<30,32> EC_ON 2 Security Classification Compal Secret Data Compal Electronics, Inc.
PQ363 Issued Date 2009/11/13 Deciphered Date 2009/04/28 Title
DTC115EUA_SC70-3 3VALWP/5VALWP
3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Huron river 0.1
5 4 3 2 1
5 4 3 2 1
www.rosefix.com
PL151
HCB2012KF-121T50_0805
1.5_B+ 1 2 B+
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2200P_0402_50V7K
D D
1
PC163
PC164
5
6
7
8
PC166
PR164 PQ151
2
255K_0402_1%
1 2
PR160 PR155
1 2 BST_1.5V 1 2
<30,39> SYSON
0_0402_5% 2.2_0603_1% AO4466L_SO8
3
2
1
1
PL152
15
14
PC160 @
1
PU150 PC155 1.8UH_SIL104R-1R8PF_9.5A_30%
.1U_0402_16V7K BST_1.5V-1 1 2 2 1 +1.5VP
EN_SKIP
TP
BST
2
2 13 DH_1.5V 0.1U_0603_25V7K
TON DH
LX_1.5V
Ipeak=7.5A
3 OUT LX 12
5
6
7
8
1
PR161 PR157
Imax=5.25A
1 2 4 11 1 2 PQ152 PR156
+5VALW VCC ILIM +5VALW 1 F=315KHz
100_0603_5% VFB=0.75V 15.4K_0402_1% 4.7_1206_5%
5 FB VDD 10 + PC152 Total Capacitor 880uF,
AO4712L_SO8 330U_6.3V_M ESR 5mohm
2
1
PC161 6 9 DL_1.5V 4
PGOOD DL
AGND
PGND
2
4.7U_0603_6.3V6K
2
2
1
PC162 PC156
G5603RU1U_TQFN14_3P5X3P5 4.7U_0805_10V6K 680P_0603_50V7K
3
2
1
2
C C
PR162
1 2
10K_0402_1%
1
PR163
10K_0402_1%
2
PR165
100K_0402_5%
1 2 +1.5V
1 2
<8> DDR3_SM_PW ROK
@ PC165 .1U_0402_16V7K
+1.5V
B B
1
PJ75
1
JUMP_43X79
@
2
2
PU75
1 VIN VCNTL 6 +3VALW
PC261 2 5
GND NC
2
4.7U_0805_6.3V6K
1
3 7 PC264
PR262 VREF NC
1
1K_0402_1% 4 8 1U_0603_10V6K
VOUT NC
9
2
TP
G2992F1U_SO8
PR260
.1U_0402_16V7K
+0.75VSP
1
0_0402_5% D
SSM3K7002FU_SC70-3
PQ260
PC263
1K_0402_1%
1 2 2
<33> SUSP
1
G
2
S PR263 PC262
3
1
10U_0603_6.3V6M
2
@ PC260
.1U_0402_16V7K
2
A For shortage changed A

1.8V / 1.5V / 0.75V
5 4 3 2 1
A B C D
www.rosefix.com 1.05VS_B+ 1
PL401
HCB2012KF-121T50_0805
2
B+
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1
100U_25V_M
10U_1206_25V6M
2200P_0402_50V7K
1
1
+
PC413
PC414
@ PC416
PC417
PR414
5
6
7
8
PC418
255K_0402_1% PQ401
2
1 2 2
1
PR410 1
0_0402_5% 4
<25,30,33> SUSP# 1 2
1
PC410 PR405 PC405 AO4466L_SO8 PL402
15
14
3
2
1
1
@ PU400 0_0603_5% 0.1U_0603_25V7K 1.8UH_SIL104R-1R8PF_9.5A_30%
.1U_0402_16V7K BST_1.05VS 1 2 1 2 2 1 +1.05VSP
EN_SKIP
TP
BST
2
2 13 DH_1.05VS
TON DH
1
5
6
7
8
PR411 3 12 LX_1.05VS PR406
100_0603_1% OUT LX PR407 PQ402 4.7_1206_5% 1
+5VALW 1 2 4 VCC ILIM 11 1 2 +5VALW +
15.4K_0402_1% PC402
1 2
5 FB VFB=0.75V VDD 10 1 2 330U_6.3V_M
4
PC412 2
6 PGOOD DL 9
AGND
PGND
4.7U_0805_10V6K PC406
2
DL_1.05VS 680P_0603_50V7K
AO4712L_SO8
3
2
1
G5603RU1U_TQFN14_3P5X3P5 Ipeak=7.5A
8
1
PC411 Imax=5.25A
4.7U_0603_6.3V6K
F=315KHz
2
Total Capacitor 1430uF,

ESR 2.5mohm
PR412
4.02K_0402_1%
1 2
2 2
1
PR413
10K_0402_1%
2
+3VALW
+5VALW
1
PJ181
1
JUMP_43X39
@
2
PC181
2
1U_0603_6.3V6M
2
1
PC182
4.7U_0805_6.3V6K
2
3 3
PU180
6 VCNTL
5 VIN VOUT 3 +1.8VP
PR183 9 4
VIN VOUT
1
0_0402_5%
22U_0805_6.3V6M
0.01U_0402_25V7K
1
1 2 8 PR181
<30,38> SYSON EN
PC184
PC185
7 2 3K_0402_1%
GND
POK FB
2
2
1
@ PC183
1
0.01U_0402_25V7K APL5930KAI-TRG_SO8
2
PR182
2.4K_0402_1%
2
4 4

1.05V / 1.8V
A B C D
5 4 3 2 1
www.rosefix.com +5VALW
2
<6>
<6>
<6>
<6>
<6>
<6>
<6>
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0
PR541
+CPU_B+ PL502
<30>
1_0603_5%
VR_ON
D
FBMA-L18-453215-900LMA90T_1812 D
1 2 B+
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PR550 0_0402_5%
0.022U_0402_16V7K
1 1 1 1
1
PC538
100U_25V_M
100U_25V_M
100U_25V_M
100U_25V_M
<8,21> PM_DPRSLPVR 1 2
2.2U_0603_6.3V6K
1
+ + + +
PC539
PC541
PC542
PC543
PC544
PC545
@ PC549
@ PC550
PR551 0_0402_5%
2
PR548
PR547
PR546
PR545
PR544
PR543
PR542
PR549
<5,8,20> H_DPRSTP# 1 2
2
5
2 2 2 2
PQ501
PR553 0_0402_5%
1
1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
+3VS 1 2
1U_0603_6.3V6M
4
1
+3VS
PC540
PL503
2
2
2.2_0603_1% 0.22U_0603_10V7K 0.36UH_PCMC104T-R36MN1R17_30A_20%
1.91K_0402_1%
PR505 PC505 TPCA8030-H_SOP-ADV8-5
3
2
1
1 1 2 1 2 1 4 +CPU_CORE
2
PR520
BOOT_CPU1
1
PR521
48
47
46
45
44
43
42
41
40
39
38
37
2 3
1
499_0402_1% PU500 PQ502 PR506
1
4.7_1206_5%
10K_0402_1%
MDU2653RH_POW ERDFN56-8-5 PR557
3.65K_0805_1%
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
2
PR554
PR555
1_0402_5%
1
1 2
1 36 4
2
<8,21,30> VGATE PGOOD BOOT1 PC506 @ PR556 0_0603_5%
2
<5> H_PSI# 2 35 UGATE_CPU1 680P_0603_50V7K 1 2
PSI# UGATE1
2
3 34 PHASE_CPU1 VSUM 1 2
3
2
1
PMON PHASE1
VCC_PRM
C ISEN1 PC552 C
1 2 4 RBIAS PGND1 33
PR523 147K_0402_1% 0.22U_0603_10V7K
VR_TT# 5 32 LGATE_CPU1 +CPU_B+
VR_TT# LGATE1
5
6 31
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
NTC PVCC PQ503
7 ISL6266AHRZ-T_QFN48_7X7 30 LGATE_CPU2
SOFT LGATE2
1
PC546
PC547
PC548
8 OCSET PGND2 29
0.022U_0603_25V7K PC523 4
2
1 2 9 28 PHASE_CPU2
VW PHASE2 PL504
PR525 13K_0402_1% 10 27 UGATE_CPU2 0.36UH_PCMC104T-R36MN1R17_30A_20%
COMP UGATE2 TPCA8030-H_SOP-ADV8-5
1 2
3
2
1
11 26 BOOT_CPU2 1 2 1 2 1 4
FB BOOT2 PR515
1 2
1
1000P_0402_50V7K PC524 12 25 2.2_0603_1% PC515 2 3
FB2 NC
5
PR526 8.25K_0402_1% 0.22U_0603_10V7K PR516
4.7_1206_5%
DROOP
1 2 49 PQ504
TP
VDIFF
VSUM
ISEN2
ISEN1
VSEN
MDU2653RH_POW ERDFN56-8-5
GND
VDD
RTN
DFB
1
VIN
VO
3.65K_0805_1%
1 2
1 2
1
PR558
10K_0402_1%
1
PR559
PC525 1000P_0402_50V7K 4
13
14
15
16
17
18
19
20
21
22
23
24
PC516 PR561
680P_0603_50V7K 1_0402_5%
2
PR527 97.6K_0402_1% PC526 270P_0402_50V7K ISEN1
2
1
1 2 2 1 ISEN2
3
2
1
2
1 2 +5VALW @ PR560 0_0603_5%
PR528 VSUM 1 2
1
1 2 PR540 1_0603_5%
1K_0402_5% PC537
2
B PC527 220P_0402_50V8J 1U_0402_6.3V6K 1 2 B

2
100_0402_1% PC528 2200P_0402_50V7K PC555

1 2 1 2 PR539 0.22U_0603_10V7K
10_0603_5% VCC_PRM
PR529 1 2 1 2 +CPU_B+ ISEN2
1
PR530 1K_0402_1% PC536

PC530 330P_0603_50V8 0.1U_0603_25V7K Rfset = (Fsw/2232)^(-1.1202)
<6> VCCSENSE 1 2 1 2
2
Fsw = 339KHz
1
PR533 0_0402_5%
Rfset = 8.25K
1
PC531 PC529 VSUM

+CPU_CORE 1 2 330P_0603_50V8 0.01U_0603_50V7K
2
2.61K_0402_1%
Ipeak=38A
2
PR538
PR534 20_0402_5% 1 2
<6> VSSSENSE PR531 0_0402_5% Imax=26.6A
1
11K_0402_1%
PC532 180P_0402_50V8J
Iocp=60A
PR537
PR532 1 2
2 2
F=339KHz
20_0402_5% 1 2 1 2
PH501 Total Capacitor 1320uF,
2
PR536 1K_0402_1% PR535 4.53K_0402_1% ESR 3.75mohm

PC533 .1U_0402_16V7K 10K_0402_5%_ERTJ0ER103J
VCC_PRM 1 2
1
PC534 0.22U_0402_6.3V6K
PC535 2 1 2 1
0.22U_0603_10V7K
A A

+CPU_CORE
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom KSWAA 0.1
5 4 3 2 1
5 4 3 2 1
PIR (Product Improve Record)
NO DATE www.rosefix.com
REVISION CHANGE: 0.1 TO 0.2 PVT
PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------------------------------------
1. 07/23 32 Change R768,R773 from 120 ohm to 510 ohm for changed 5mA LED
2. 07/23 32 Chage LED power rail from +3valw to +5valw for changed 5mA LED
3. 07/23 23 del. L86,L87 EMI component for EMI request
D
4. 07/23 31 Add 1PCS(C62) 0.1uF_0402 on +3Valw-->GND for EMI request D
5. 07/23 31 Add 1PCS(C65) 0.1uF_0402 on +5Vs-->GND for EMI request
6. 07/23 31 Add 0.1uF_0402(C66) on B+-->GND close to H8 for EMI request
7. 07/23 28 JLINE and JEXMIC change from DC2300006300 to DC230004L00 for SMT DFx request
8. 07/27 30 change R742 from +3VALW to +3VL for LED no function issue
9. 07/27 8 add test pad ON U3.E36,U3.AK34 for ATE request
10. 07/27 33 change part number of Q30 (SB770020010) for Reduce BOM part type
11. 07/27 32 Change D67(power on LED) from SC510UYG000 to SC500009D00 for changed 5mA LED
12. 07/27 32 Change D70(DC in LED) from SC510UDG000 to SC500009800 for changed 5mA LED
13. 07/29 14 un-mount CD7,CD8,CD9,CD10,CD11,CD12,CD30,CD31,CD32,CD34,and mount(22uF) CD29,CD33 for design change
14. 07/29 11 For +1.5V ,C78 from 330uF to 390u (SF000002O00) for design change
15. 07/29 12 Change R82 and R81 from inductor to Bead for design change
16. 07/29 15 +0.75VS filter un-mount CD22 and CD44 for design change
17. 08/03 25 un-mount D77 for If +3V_WLAN is +3VS, please un-mount D77
C C
B B
A A

PIR
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
www.rosefix.com
REVISION CHANGE: 0.2 TO 0.3 Pre-MP
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------------------------------------
1. 08/09 29 Change net V1_8 to +v1_8 for power trace
2. 08/09 32 add R774 for LED control
D D
3. 08/12 32 un-mount SW5 and SW6 for Pre-MP do need power SW
4. 08/12 20 add R16 (for RTC battery) for design change
5. 08/13 26 add D69 and un-mount CL38 for EMI request
6. 08/13 26 CL37 from 0.1uF to 120pF for EMI request
7. 08/13 26 add CL35 for EMI request
8. 08/13 27 add CA51 for EMI request
9. 08/13 33 add C67 and C43 for EMI request
C C
B B
A A

PIR
0.1
PWWAA LA6841P M/B
5 4 3 2 1
5 4 3 2 1
www.rosefix.com
REVISION CHANGE: 0.1 TO 1.0
NO DATE PAGE MODIFICATION LIST PURPOSE
---------------------------------------------------------------------------------------------------------------------------------------------------
D D
C C
B B
A A

PIR
0.1
PWWAA LA6841P M/B
5 4 3 2 1
Page# Item Title
www.rosefix.com
Version Change List ( P. I. R. List ) for Power Circuit
Solution Description
PVT : modification from EVT
P35 mount ESD diode mount PD5, PD6
P36 EMI request add PC236 10uF
P37 EMI request add PC367 10uF, PC368 2200pF
P37 change 3/5V IC main source change PU330 to UP6182
P38 EMI request add PC166 2200pF
P39 EMI request add PC417 10uF, PC418 2200pF
P40 adjust loadine change PR535 to 3.09K
P34 unify source change PD1 to SC11N414880

P36 unify source change PQ216 to SB000009610
P37 unify source change PQ362 to SB000009610
P40 unify source change PL502 to SM010020720
P40 turn on speed too quick change PQ502, PQ504 to MDU2653RH
P37 change cap to 330uF with same price change PC332, PC352 to SF000002000
P38 change cap to 330uF with same price change PC152 to SF000002000
P39 change cap to 330uF with same price change PC402 to SF000002000
P36 EMI request to mount snubber circuit, ISN caps add PR206, PC206; PC234, PC235
P37 EMI request to mount snubber circuit add PR336, PC336; PR356, PC356
P38 EMI request to mount snubber circuit & boost resistor add PR156, PC156; change PR155 to 2.2ohm
P39 EMI request to mount snubber circuit add PR406, PC406
P40 EMI request to mount snubber circuit add PR506, PC506; PR516, PC516
PreMP : modification from PVT

P34 increase precharge design margin add PR12 1K
P35 change OTP setting change PR15 to 23.2K, PR18 to 10.7K
P35 change source chagne PC9 to SE070104Z80
P37 change 3/5V IC main source change PU330 to TPS51125A
P38 change 0.75V IC main source change PU75 to G2992
P40 adjust loadine change PR535 to 4.53K
P40 adjust transient stability change PR527 to 220pF

PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
PWWAA LA6841P M/B

Compal LA-6841P

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A B C D E

L-A6841P REV 0.1 Schematic

Intel Penryn/ Cantiga/ ICH9M 3

2010-07-22 Rev. 0.1

Security Classification Compal Secret Data Compal Electronics, Inc.

Model Name : PWWAA

Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2

Power/B HDA Codec

DC/DC Interface CKT. Touch Pad Int.KBD SPI ROM Int.

Power Circuit DC/DC

Voltage Rails www.rosefix.com STATE

Power Plane Description S1 S3 S5 G3 Full ON HIGH HIGH HIGH HIGH

Function Card Reader Camera WLAN Energy Star

+5V_SB 5V power rail for SB ON ON OFF OFF

External PCI Devices

EC SM Bus1 address EC SM Bus2 address

ICH9M SM Bus address

+3VS DDR DIMM0 1001 000Xb

Security Classification Compal Secret Data Compal Electronics, Inc.

H_D#31 N25 AC23 H_D#63 E24 AB19

+CPU_GTLREF +CPU_GTLREF COMP0 R13 54.9_0402_1% VSS[047] VSS[128]

D25 AA1 COMP2 R15 27.4_0402_1% F2 AC14

TEST6 DPSLP# VSS[054] VSS[135]

Security Classification Compal Secret Data Compal Electronics, Inc.

Near CPU CORE regulator

ESR <= 1.5m ohm

10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M

VCCSENSE 100_0402_1% 2 1 R19

VSSSENSE 100_0402_1% 2 1 R20

A Close to CPU pin A

Length match within 25 mils.

www.rosefix.com <5> H_D#[0..63]

H_D#3 E6 C18 H_A#7

+H_VREF H_RCOMP H_SW NG H_RCOMP

1 1 H_REQ#_2 F13 H_REQ#2 <4>

Security Classification Compal Secret Data Compal Electronics, Inc.

Strap Pin Table

DDR CLK/ CONTROL/

DMI_RXN_0 AE41 DMI_ITX_MRX_N0 <19>

DMI_RXP_0 AE40 DMI_ITX_MRX_P0 <19>

<14,15> PM_EXTTS# R53 1 2 0_0402_5% PM_EXTTS#_R P32

BD48 AN36 ICH_PWROK Width:Spacing

BF46 M28 0.1U_0402_16V4Z 499_0402_1%

BH6 NC_13 ICH_SYNC# H36 MCH_ICH_SYNC# <21>

AU13 SA_DQ_36 SA_DQS#_3 BH12 SB_DQ_36 SB_DQS#_1

DDR_A_D46 AY8 BG24 DDR_A_MA2 DDR_B_D46 BA1 BA25 DDR_B_MA1

Security Classification Compal Secret Data Compal Electronics, Inc.

UMA_LCD_EDID_CLK <17> UMA_LCD_EDID_CLK

R67 2.2K_0402_5% <17> UMA_LCD_EDID_DATA UMA_LCD_EDID_DATAJ33 H44

Security Classification Compal Secret Data Compal Electronics, Inc.

C91 C92 C94 C97

Security Classification Compal Secret Data Compal Electronics, Inc.

+3VS_TVCRT_DAC VCCA_CRT_DAC_1 VTT_2 1

+1.8V_LVDS L37 C147 C148 C149 1

+1.05VS PCIe&DMI +1.05VS_PEGPLL

AU48 VSS_1 VSS_100 AM36 BG21 VSS_199 VSS_297 AH8

Security Classification Compal Secret Data Compal Electronics, Inc.

<8> DDRA_CKE0 73 CKE0 CKE1 74 DDRA_CKE1 <8>

Compal Secret Data

SA1 SCL PM_SMBCLK <15,16,21,25> Security Classification

1 1 +0.75VS 203 VTT1 VTT2 204 +0.75VS

<8> DDRB_CKE0 73 CKE0 CKE1 74 DDRB_CKE1 <8>

DDR_B_D33 DQ32 DQ36 DDR_B_D37