verilog coding style

behavioral
gate level
register transfer level
verilog laungague and syntex
bitwise operation
system task

data type
verilog operation
loops in verilog
permitive
time derivativtes
blocking and non blocking

combination verilog code

sequential verilog code
fsm verilog code

Verilog Reserved Words (Keywords)

Always Block
Bitwise Operators
Case Statement
Concatenation Operator { }
Conditional Operator (?)
For Loop
Forever Loop
Function
Logical Operators &&, ||, !
Reduction Operators
Relational Operators
Repeat Loop
Replication Operator { }
Shift Operator <<, >>
Task
While Loop

Half Adder
Full Adder
Ripple Carry Adder
Carry Lookahead Adder
Register-based FIFO
UART Serial Port Module
Binary to BCD: The Double Dabbler
7-Segment Display
LFSR - Linear Feedback Shift Register
Multiplexer (Mux)

Verilog HDL Syntax And Semantics

Gate Level Modeling

User Defined Primitives

Verilog Operators

Verilog Behavioral Modeling

Procedural Timing Control

Task And Functions

System Task and Function

Art of Writing TestBenches

Modeling Memories And FSM

Parameterized Modules

Verilog Synthesis Tutorial

Verilog PLI Tutorial

What's new in Verilog 2001

Assertions In Verilog

Compiler Directives