2M EIC1998 exam answers

Part A
A1 (i) 12 mA, 0.6 + 20µ ¥ 100k = 2.6 V.
(ii) (1.3 – 0.6) / 100k ¥ 600 = 4.2 mA, 12 – 4.2 mA ¥ 1k = 7.8 V.
A2 (i) ‘supply’: ia = 300 mA at vab =0, up to ia = 0 at vab = 15 V;
‘reverse Zener’: zero ia up to 10 V then linear increase to 500 mA at 15 V.
(ii) Same as ‘supply’ up to vab = 10V, then ia rises to 500 mA at vab = 15 V.
(iii) -0.6 V source in series with arrow-upwards perfect diode.
A3 (i) (-560 ¥ 10-3) ¥ (-7 ¥ 10-9) = 3.92 mV lux-1. (ii) potential divider: 155.1
kΩ.
A4 (i) 5 kW. (ii) 0 kW (no pressure). (iii) 10 kW.
1
A5 (i) vo = - v dt = - 101 vit .
RC Ú i
a = 0V, b = -2 µA, c = -2 µA, d = 0.2t V, e = (2t + 0.002) mA.
(ii) 0.2t = 12-14: about 70 s.
A6 (i) 20 log 5 = 14 dB. LP at 5wc: gain = -14 dB (see Handbook),
hence 14 – 14 = 0 dB.
Phase shift (LP at 0.2wc) = -12° - 90° = -102°.
(ii) Gain falls at -6 dB/oct until -14 dB at 5 kHz, then flat.
Phase rises from 90°, through 135° at 5 kHz, to 180°.
-( A1 D2 + A2 )
A7
(1 - tA2 )D - tA1D3
A8 (i) 212 = 4096, 20/4096 = 4.88 mV, (ii) 2¥106 samples s-1.

Part B
B1 (i) (a) show operating point with v > 0, i > 0, (b) with v > 0, i < 0.
(ii) Straight line through vi = 0.80 V at vL = 0, vL = 14.0 V at vi = 4.80 V.
Data show limiting at top and and tend to origin at low end.
(iii) Input offset 0.8 V, voltage gain 10.9 dB.
(iv) (4.16 V, 24 mA); (6 V, 16.7 mA); (8V, 12.5 mA); (10V, 10 mA);
(16 V, 6.25 mA) all 100 mA.
(v) Tangent to 100 mW curve from 15V: 560 Ω.
(vi) 0.6 + 41µA ¥ 100 kΩ = 4.7 V.
 B2 (i) Description implies that resistance measured to conventional accuracy (e.g.
2%)
will be 100Ω at any temperature.
(ii)PRC 100 in upper right or lower left position, 100 Ω resistors in others.
(iii) Required gain 10.39. 103.9 kΩ = 100 kΩ + 3.9 kΩ.
(iv) a = c = 5 V, b = d = 103.9 / 113.9 ¥ 5 = 4.561 V, e = 0V.
(v) Ground resistance becomes 103.9k // 10 M = 102.83 k.
Hence v+ = v– = 4.557 V, hence inv. input current = feedback current = 44.3
µA.
Hence vo = 5 – (103.9+10)k Ω ¥ 44.3 µA = –0.04577 V. Hence ∆T = –0.4577
°C.
B3 (i) Subtractor, vi - vf then ¥4.7.
È 1 ˘
(ii) Now: T = 4.7Í1 + 12 + 12 t x D˙ , tx = 0.2 s.
Î t xD ˚
Several possible ways to implement. E.g.: Stage 1 unchanged; its output
also connected to inputs of integrator and differentiator (both 0.2s = 680 nF ¥
300 kΩ) and inverting amp (gain 1). Integrator and differentiator outputs
connected through new 20 kΩ resistors to inverting input of IC2 (making it a
summing amp).
È 1 ˘ 1 1 1
(iii) FG = const.¥ Í1+ 12 + 12 t x D˙ . LF: Æ 2 so –180°. HF: Æ D
Î t xD ˚ (1+ tD) D D
so 90°.
B4 (i) p/60 mV s rad-1.
1000k 1 0.1
(ii) T = where t CL = .
1 + 0.5k 1 + t CLD 1+ 0.5k
(iii) k = 8, 20 kΩ and 160 kΩ.
(iv) There is no position sensor in system: position errors accumulate
uncontrollably.
B5 (i) At 1 Hz: original loop phase shift = 102°. f = -Tdw = -360Td f = –3.6°.
New loop phase shift = -105.6. Similarly for remaining f.
(ii) Original system: 11.0 dB (insufficient), 50° (good).
Modified system: 7.8 dB (low), 41° (not bad).
(iii) Shift gain origin up by (11 – 8.8) = 2.2 dB: phase margin remains 41°.
System is marginally stable and gain should be further reduced.

†
†