DIVFREC

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity DivFrec is
port (
clk : in std_logic;
clk1 : out std_logic
);
end DivFrec;

architecture Behavioral of DivFrec is

signal clk1_aux : std_logic;

begin

divisor:process(clk)

variable temp: integer range 0 to 100000000 :=0; -- por el oscilador de 100 MHz
begin

if(clk'event and clk='1') then

if(temp=50000000) then
clk1_aux<=not(clk1_aux);
temp:=0;
else
temp:=temp+1;
end if;
end if;
end process;
clk1 <= clk1_aux;

end Behavioral;

RAM
entity ram is
Port (
data_in : in STD_LOGIC_VECTOR (3 downto 0);--conectado a A
data_out : out STD_LOGIC_VECTOR (3 downto 0);
addr : in STD_LOGIC_VECTOR (3 downto 0);--conectado a B
wr_ena : in STD_LOGIC;
clk : in STD_LOGIC
);
end ram;

architecture beha_ram of ram is

type vector_array is array (0 to 15) of std_logic_vector(3 downto 0);
signal memory:vector_array;
begin
process(clk)
 begin
if(clk'event and clk='1')then
if (wr_ena='1') then
memory(conv_integer(addr))<=data_in;
--data_out<="0000";
else
data_out <= memory(conv_integer(addr));
end if;
end if;
end process;
end beha_ram;

ROM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity rom is
Port (
addr : in std_logic_vector(3 downto 0);
data : out std_logic_vector(3 downto 0)
);
end rom;

architecture Behavioral of rom is

type vector_array is array (0 to 15) of std_logic_vector (3 downto 0);

constant memory:vector_array:=( "1111",
"1110",
"1101",
"1100",
"1011",
"1010",
"1001",
"1000",
"0111",
"0110",
"0101",
"0100",
"0011",
"0010",
"0001",
"0000"
);

begin
data <= memory(conv_integer(addr));
end Behavioral;
FSM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity fsm is
Port (
x : in STD_LOGIC;
z_out : out STD_LOGIC_VECTOR (3 downto 0);
z : out std_logic_vector(1 downto 0);
rst : in std_logic;
clk_fsm : in std_logic
);
end fsm;

architecture Behavioral of fsm is

type estados is (std0,std1,std2,std3,std4,std5,std6,std7);

attribute ENUM_ENCODING: STRING;
attribute ENUM_ENCODING of estados: type is
"0000 0001 0010 0011 0100 0101 0110 0111";
signal pr_estado, nx_estado : estados;

begin

process (rst,clk_fsm)
begin
if(rst='1') then
pr_estado<=std0;
elsif (clk_fsm'event and clk_fsm='1') then
pr_estado<=nx_estado;
end if;
end process;

process (x,pr_estado)
begin
case pr_estado is
when std0 =>
z_out<="0000";
z<="00";
if (x='0') then
nx_estado<=std0;
else
nx_estado<=std1;
end if;
when std1 =>
z_out<="0001";
z<="00";
if (x='0') then
 nx_estado<=std1;
else
nx_estado<=std2;
end if;
when std2 =>
z_out<="0010";
z<="00";
if (x='0') then
nx_estado<=std2;
else
nx_estado<=std3;
end if;
when std3 =>
z_out<="0011";
z<="10";
if (x='0') then
nx_estado<=std3;
else
nx_estado<=std4;
end if;
when std4 =>
z_out<="0100";
z<="01";
if (x='0') then
nx_estado<=std0;
else
nx_estado<=std5;
end if;
when std5 =>
z_out<="0101";
z<="11";
if (x='0') then
nx_estado<=std5;
else
nx_estado<=std6;
end if;
when std6 =>
z_out<="0110";
z<="11";
if (x='0') then
nx_estado<=std6;
else
nx_estado<=std7;
end if;
when std7 =>
z_out<="0111";
z<="11";
if (x='0') then
nx_estado<=std7;
else
nx_estado<=std0;
end if;
 end case;
end process;
end Behavioral;

CLK

# Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

Switch
set_property PACKAGE_PIN V17 [get_ports {A[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {A[0]}]

LED
set_property PACKAGE_PIN U16 [get_ports {z[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {z[0]}]

Display
set_property PACKAGE_PIN W7 [get_ports {resultado_out[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {resultado_out[0]}]

Button

set_property PACKAGE_PIN U18 [get_ports clk_m]

set_property IOSTANDARD LVCMOS33 [get_ports clk_m]