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1 1

Compal Confidential
2 2

NEW71/91 M/B Schematics Document


Intel Arrandale Processor with DDRIII + Ibex Peak-M
NV N11P-GV2H

3 2009-12-23 3

REV:0.1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Wednesday, December 23, 2009 Sheet 1 of 56
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Clock Generator
Compal Confidential IDT: 9LVS3199AKLFT
Model Name : NEW71/91 Realtek: RTM890N-631-VB-GRT
133/120/100/96/14.318MHZ to PCH
File Name : LA5893P Fan Control
page 41 page 12
1 1

100MHz PCI-E 2.0x16 5GT/s PER LANE


PEG(DIS) Intel Memory BUS(DDRIII)
133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3 page 10,11
NV N11P-GV2H
page
Arrandale (UMA/DIS) 1.5V DDRIII 800/1066
22,23,24,25,26,27

LVDS(DIS) Processor
rPGA988A
page 4,5,6,7,8,9
HDMI(DIS) CRT(DIS)
FDI x8 DMI x4 USB conn x3 Bluetooth CMOS Camera Card Reader
(UMA) USB port 1 Conn RTS5160
USB port 0, 2 on USB port 11 USB port 8 USB port 9
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz USB/B page 35 page 35 page 28 page 35
page 30 page 29 page 28 2.7GT/s 1GB/s x4
2 USBx14 3.3V 48MHz 2
HDMI(UMA) LVDS(UMA)
CRT(UMA) Intel 3.3V 24MHz
HDMI HD Audio
Level Shift TMDS(UMA) Ibex Peak-M
page 30
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s) 100MHz PCH HDA Codec
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz page 13,14,15,16 ALC272X
port 2 port 1 17,18,19,20,21
SPI page 39

MINI Card x2 LAN(GbE)


WLAN, WWAN
USB port 12,13
BCM57780
page 34 page 32 SPI ROM x1 Audio AMP
port 0 port 1 TI TPS6017
page 13 page 40
SATA HDD SATA CDROM
Conn. page 31
Conn. page 31
3
RJ45 LPC BUS 3

page 33
33MHz
Int. Speaker Phone Jack x 2
Sub-board ENE KB926 page 40 page 40
page 36
LS-5891P
USB/B 2 Ports
RTC CKT. USB Port 0,2 page 35
page 15
Touch Pad Int.KBD
LS-5896P page 37 page 37
Card Reader
Power On/Off CKT. USB Port9 CPU XDP
page 38 RTS5160
page 35 page 5
EC ROM
page 37
DC/DC Interface CKT. LS-5893P LS-5894P PCH XDP
4
page 42 Power/B LID_SW/B 4

page 38 page 21

Power Circuit DC/DC LS-5895P


3G Security Classification Compal Secret Data Compal Electronics, Inc.
USB Port10,13page 35 Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
page 43~53 Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Friday, December 18, 2009 Sheet 2 of 56
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

Full ON HIGH HIGH HIGH HIGH ON ON ON ON


Voltage Rails
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
B+ AC or battery power rail for power circuit. N/A N/A N/A
+CPU_CORE Core voltage for CPU ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+VGFX_CORE Core voltage for Arrandale GPU (only for arrandaleCPU) ON OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF Board ID / SKU ID Table for AD channel
+1.0VSDGPU +1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU ON OFF OFF Vcc 3.3V +/- 5%
+1.05VS_VTT +1.05VS_VTTP to +1.05VS_VTT switched power rail for ARD CPU ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF 0 0 0 V 0 V 0 V
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VALW +3VALW always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VALW_EC +3VALW always to KBC ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+3V +3VALW to +3V power rail for PCH (Short Jumper) ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
2 2
+3VS +3VALW to +3VS power rail ON OFF OFF
+5VALW +5VALWP to +5VALW power rail ON ON ON*
BOARD ID Table BTO Option Table
+5V +5VALW to +5V switched power rail for PCH (Short resister) ON ON ON*
BTO Item BOM Structure
+5VS +5VALW to +5VS switched power rail ON OFF OFF Board ID PCB Revision
UMA UMA@
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* 0 0.1
UMA Only UMA ONLY@
+RTCVCC RTC power ON ON ON 1 0.2
Discrete DIS@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 2 0.3
Discrete Only DIS ONLY@
3 1.0
VRAM X76@
4
Switchable SG@
EC SM Bus1 address EC SM Bus2 address 5
Connector CONN@
6
3G 3G@
Device Address Device Address 7
Smart Battery 0001 011X b
Blue Tooth BT@
Unpop @
PCH SM Bus address USB Port Table XDP XDP@
NonSG NonSG@
3 External
3
Device Address USB 2.0 USB 1.1 Port USB Port NEW71 71@ 3

Clock Generator (9LVS3199AKLFT,


NEW91 91@
1101 0010b 0 USB/B (Right Side)
RTM890N-631-VB-GRT) UHCI0
DDR DIMM0 1001 000Xb
1 USB Port (Left Side)
DDR DIMM2
2 USB/B (Right Side)
1001 010Xb UHCI1
3
EHCI1
4
BOM Config UHCI2
5
VRAM P/N :
NEW71 SKU 6 Samsung : SA000035720 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!)
DISCTETE ONLY
BT@,3G@,DIS@,DIS ONLY@,NonSG@,71@,X7621@,XDP@ UHCI3
7 Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO! )
8 Camera
NEW91 SKU UHCI4
DISCTETE ONLY 9 Card Reader
BT@,3G@,DIS@,DIS ONLY@,NonSG@,91@,X7621@,XDP@
10 SIM Card
EHCI2 UHCI5
11 Blue Tooth
12 Mini Card(WLAN)
VRAM BOM Config UHCI6
13 Mini Card(GPS)
X7621@: X76198BOL21 ALT. GROUP PARTS 1G SAM
4 4
X7622@ X76198BOL22 ALT. GROUP PARTS 1G HYN

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 3 of 56

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5 4 3 2 1

JCPU1E

JCPU1A R485 AJ13


PEG_IRCOMP RSVD32
PEG_ICOMPI B26 1 2 49.9_0402_1% RSVD33 AJ12

DMI_PTX_HRX_N0
10mil PEG_ICOMPO A26
R493
A24 DMI_RX#[0] PEG_RCOMPO B27 AP25 RSVD1
DMI_PTX_HRX_N1 C23 A25 EXP_RBIAS 1 2 750_0402_1% AL25 AH25
DMI_PTX_HRX_N2 DMI_RX#[1] PEG_RBIAS RSVD2 RSVD34
DMI_PTX_HRX_N3
B22 DMI_RX#[2] 15mil PEG_GTX_C_HRX_N15
AL24 RSVD3 RSVD35 AK26
A21 DMI_RX#[3] PEG_RX#[0] K35 AL22 RSVD4
J34 PEG_GTX_C_HRX_N14 AJ33 AL26
DMI_PTX_HRX_P0 PEG_RX#[1] PEG_GTX_C_HRX_N13 RSVD5 RSVD36
B24 DMI_RX[0] PEG_RX#[2] J33 AG9 RSVD6 RSVD_NCTF_37 AR2
DMI_PTX_HRX_P1 D23 G35 PEG_GTX_C_HRX_N12 M27
DMI_RX[1] PEG_RX#[3] RSVD7

DMI
DMI_PTX_HRX_P2 B23 G32 PEG_GTX_C_HRX_N11 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10 RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 J17 SA_DIMM_VREF (CFD Only) RSVD39 AJ27 D
F31 PEG_GTX_C_HRX_N9 H17
DMI_HTX_PRX_N0 PEG_RX#[6] PEG_GTX_C_HRX_N8 SB_DIMM_VREF (CFD Only)
D24 DMI_TX#[0] PEG_RX#[7] D35 G25 RSVD11
DMI_HTX_PRX_N1 G24 E33 PEG_GTX_C_HRX_N7 G17
DMI_HTX_PRX_N2 DMI_TX#[1] PEG_RX#[8] PEG_GTX_C_HRX_N6 RSVD12
F23 DMI_TX#[2] PEG_RX#[9] C33 E31 RSVD13 RSVD_NCTF_40 AP1
DMI_HTX_PRX_N3 H23 D32 PEG_GTX_C_HRX_N5 E30 AT2
DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N4 RSVD14 RSVD_NCTF_41
PEG_RX#[11] B32
DMI_HTX_PRX_P0 D25 C31 PEG_GTX_C_HRX_N3 AT3
DMI_HTX_PRX_P1 DMI_TX[0] PEG_RX#[12] PEG_GTX_C_HRX_N2 RSVD_NCTF_42
F24 DMI_TX[1] PEG_RX#[13] B28 RSVD_NCTF_43 AR1
DMI_HTX_PRX_P2 E23 B30 PEG_GTX_C_HRX_N1
DMI_HTX_PRX_P3 DMI_TX[2] PEG_RX#[14] PEG_GTX_C_HRX_N0
G23 DMI_TX[3] PEG_RX#[15] A31

J35 PEG_GTX_C_HRX_P15 R58 AL28


PEG_RX[0] PEG_GTX_C_HRX_P14 3.01K_0402_1% @ CFG0 RSVD45
PEG_RX[1] H34 1 2 AM30 CFG[0] RSVD46 AL29
H33 PEG_GTX_C_HRX_P13 AM28 AP30
H_FDI_TXN0 PEG_RX[2] PEG_GTX_C_HRX_P12 R61 CFG[1] RSVD47
E22 FDI_TX#[0] PEG_RX[3] F35 AP31 CFG[2] RSVD48 AP32
H_FDI_TXN1 D21 G33 PEG_GTX_C_HRX_P11 3.01K_0402_1% 1 DIS@ 2 CFG3 AL32 AL27
H_FDI_TXN2 FDI_TX#[1] PEG_RX[4] PEG_GTX_C_HRX_P10 R60 @ CFG4 CFG[3] RSVD49
D19 FDI_TX#[2] PEG_RX[5] E34 1 2 AL30 CFG[4] RSVD50 AT31
H_FDI_TXN3 D18 F32 PEG_GTX_C_HRX_P9 3.01K_0402_1% AM31 AT32
H_FDI_TXN4 FDI_TX#[3] PEG_RX[6] PEG_GTX_C_HRX_P8 CFG[5] RSVD51
G21 FDI_TX#[4] PEG_RX[7] D34 AN29 CFG[6] RSVD52 AP33
H_FDI_TXN5 PEG_GTX_C_HRX_P7 R59 @ CFG7
H_FDI_TXN6
E19
F21
FDI_TX#[5]
FDI_TX#[6]
PCI EXPRESS -- GRAPHICS PEG_RX[8]
PEG_RX[9]
F33
B33 PEG_GTX_C_HRX_P6 3.01K_0402_1%
1 2 AM32
AK32
CFG[7]
CFG[8]
RSVD53
RSVD_NCTF_54
AR33
AT33
Intel(R) FDI

H_FDI_TXN7 G18 D31 PEG_GTX_C_HRX_P5 AK31 AT34

RESERVED
FDI_TX#[7] PEG_RX[10] PEG_GTX_C_HRX_P4 CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 AK28 CFG[10] RSVD_NCTF_56 AP35
C30 PEG_GTX_C_HRX_P3 WW41 Recommend not pull down AJ28 AR35
H_FDI_TXP0 PEG_RX[12] PEG_GTX_C_HRX_P2 CFG[11] RSVD_NCTF_57
D22 FDI_TX[0] PEG_RX[13] A28 PCIE2.0 Jitter is over on ES1 AN30 CFG[12] RSVD58 AR32
H_FDI_TXP1 C21 B29 PEG_GTX_C_HRX_P1 AN32
H_FDI_TXP2 FDI_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0 CFG[13]
D20 FDI_TX[2] PEG_RX[15] A30 AJ32 CFG[14]
H_FDI_TXP3 C18 AJ29 E15
C H_FDI_TXP4 FDI_TX[3] PEG_HTX_GRX_N15 C586 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N15 CFG[15] RSVD_TP_59 C
G22 FDI_TX[4] PEG_TX#[0] L33 1 2 AJ30 CFG[16] RSVD_TP_60 F15
H_FDI_TXP5 E20 M35 PEG_HTX_GRX_N14 C561 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N14 AK30 A2
H_FDI_TXP6 FDI_TX[5] PEG_TX#[1] PEG_HTX_GRX_N13 C584 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N13 CFG[17] KEY R146
F20 FDI_TX[6] PEG_TX#[2] M33 1 2 H16 RSVD_TP_86 RSVD62 D15
H_FDI_TXP7 G19 M30 PEG_HTX_GRX_N12 C559 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N12 C15 0_0402_5%
FDI_TX[7] PEG_TX#[3] PEG_HTX_GRX_N11 C582 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N11 RSVD63 RSVD64_R 2 @
PEG_TX#[4] L31 1 2 RSVD64 AJ15 1
F17 K32 PEG_HTX_GRX_N10 C557 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N10 AH15 RSVD65_R 2 @ 1
15 H_FDI_FSYNC0 FDI_FSYNC[0] PEG_TX#[5] RSVD65
E17 M29 PEG_HTX_GRX_N9 C580 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N9 R147
15 H_FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
J31 PEG_HTX_GRX_N8 C555 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N8 B19 0_0402_5%
PEG_TX#[7] PEG_HTX_GRX_N7 C578 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N7 R497 RSVD15
15 H_FDI_INT C17 FDI_INT PEG_TX#[8] K29 1 2 A19 RSVD16
H30 PEG_HTX_GRX_N6 C553 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N6 0_0402_5%
PEG_TX#[9] PEG_HTX_GRX_N5 C576 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N5 @ H_RSVD17_R
15 H_FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29 1 2 1 2 A20 RSVD17
D17 F29 PEG_HTX_GRX_N4 C551 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N4 1 @ 2 H_RSVD18_R B20
15 H_FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11] RSVD18
E28 PEG_HTX_GRX_N3 C574 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N3 AA5
PEG_TX#[12] PEG_HTX_GRX_N2 C549 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N2 R501 RSVD_TP_66
PEG_TX#[13] D29 1 2 U9 RSVD19 RSVD_TP_67 AA4
D27 PEG_HTX_GRX_N1 C572 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N1 0_0402_5% T9 R8
PEG_TX#[14] PEG_HTX_GRX_N0 C547 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N0 RSVD20 RSVD_TP_68
PEG_TX#[15] C26 1 2 RSVD_TP_69 AD3
AC9 RSVD21 RSVD_TP_70 AD2
L34 PEG_HTX_GRX_P15 C585 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P15 AB9 AA2
PEG_TX[0] PEG_HTX_GRX_P14 C560 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P14 RSVD22 RSVD_TP_71
PEG_TX[1] M34 1 2 RSVD_TP_72 AA1
M32 PEG_HTX_GRX_P13 C583 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P13 R9
PEG_TX[2] DMI_PTX_HRX_N[0..3] 15 RSVD_TP_73
L30 PEG_HTX_GRX_P12 C558 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P12 AG7
PEG_TX[3] DMI_PTX_HRX_P[0..3] 15 RSVD_TP_74
M31 PEG_HTX_GRX_P11 C581 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P11 C1 AE3
PEG_TX[4] PEG_HTX_GRX_P10 C556 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P10 RSVD_NCTF_23 RSVD_TP_75
PEG_TX[5] K31 1 2 DMI_HTX_PRX_N[0..3] 15 A3 RSVD_NCTF_24
M28 PEG_HTX_GRX_P9 C579 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P9
PEG_TX[6] DMI_HTX_PRX_P[0..3] 15
H31 PEG_HTX_GRX_P8 C554 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P8 V4
PEG_TX[7] PEG_HTX_GRX_P7 C577 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P7 RSVD_TP_76
PEG_TX[8] K28 1 2 H_FDI_TXN[0..7] 15 RSVD_TP_77 V5
G30 PEG_HTX_GRX_P6 C552 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P6 N2
PEG_TX[9] H_FDI_TXP[0..7] 15 RSVD_TP_78
G29 PEG_HTX_GRX_P5 C575 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P5 J29 AD5
PEG_TX[10] PEG_HTX_GRX_P4 C550 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P4 RSVD26 RSVD_TP_79
PEG_TX[11] F28 1 2 J28 RSVD27 RSVD_TP_80 AD7
B PEG_HTX_GRX_P3 C573 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P3 B
PEG_TX[12] E27 1 2 PEG_GTX_C_HRX_N[0..15] 22 RSVD_TP_81 W3
D28 PEG_HTX_GRX_P2 C548 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P2 A34 W2
PEG_TX[13] PEG_GTX_C_HRX_P[0..15] 22 RSVD_NCTF_28 RSVD_TP_82
C27 PEG_HTX_GRX_P1 C571 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P1 A33 N3
PEG_TX[14] PEG_HTX_GRX_P0 C546 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_P0 RSVD_NCTF_29 RSVD_TP_83
PEG_TX[15] C25 1 2 PEG_HTX_C_GRX_N[0..15] 22 RSVD_TP_84 AE5
PEG_HTX_C_GRX_P[0..15] 22 C35 RSVD_NCTF_30 RSVD_TP_85 AD9
B35 RSVD_NCTF_31
IC,AUB_CFD_rPGA,R1P0 AP34
CONN@ VSS

IC,AUB_CFD_rPGA,R1P0
CONN@

eDP Signals Mapping CFG0 - PCI-Express Configuration Select CFG4 - Display Port Presence
H_FDI_FSYNC0 R519 1 DIS ONLY@
2 1K_0402_5%
H_FDI_FSYNC1 R517 1 DIS ONLY@ 1K_0402_5%
eDP Singal PEG Singals Lane Reversal 2
*1:Single PEG *1:Disabled; No Physical Display Port
H_FDI_INT R513 1 DIS ONLY@ 1K_0402_5%
eDP_TX0 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P0 2 0:Bifurcation enabled attached to Embedded Display Port
H_FDI_LSYNC0 R520 1 DIS ONLY@ 1K_0402_5% 0:Enabled; An external Display Port
eDP_TX#0 PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N0 H_FDI_LSYNC1
2
R515 1 DIS ONLY@
2 1K_0402_5% device is connected to the Embedded
eDP_TX1 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P1 CheckList0.8 1.22 CFG3 - PCI-Express Static Lane Reversal
Display Port
eDP_TX#1 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N1 Auburndale Graphics Disable
*:Default
A eDP_TX2 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P2 *1 :Normal Operation A
0 :Lane Numbers Reversed
eDP_TX#2 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N2 15 -> 0, 14 -> 1, ...
eDP_TX3 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P3
eDP_TX#3 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N3 Security Classification Compal Secret Data Compal Electronics, Inc.
eDP_AUX PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P2 Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

eDP_AUX# PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N2 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (1/6) DMI,FDI,PEG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
eDP_HPD# PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P3 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 4 of 56
5 4 3 2 1
5 4 3 2 1

JCPU1B
R512 2 1 20_0402_1% H_COMP3 AT23 COMP3
BCLK A16 CLK_CPU_BCLK 18

MISC
R507 2 1 20_0402_1% H_COMP2 AT24 B16
COMP2 BCLK# CLK_CPU_BCLK# 18
R521 2 1 49.9_0402_1% H_COMP1 CLK_CPU_XDP 2009/08/14

CLOCKS
G16 COMP1 BCLK_ITP AR30
AT30 CLK_CPU_XDP#
R503 2 BCLK_ITP# remove DP REF SSCLK
1 49.9_0402_1% H_COMP0 AT26 COMP0
PEG_CLK E16 CLK_CPU_DMI 14
PEG_CLK# D16 CLK_CPU_DMI# 14
PAD @ SKTOCC#_R AH24 CLK_CPU_DP_R R504 1 2 0_0402_5%
T7 SKTOCC#
A18 CLK_CPU_DP_R CLK_CPU_DP#_R R510 1 2 0_0402_5%
DPLL_REF_SSCLK CLK_CPU_DP#_R
D
DPLL_REF_SSCLK# A17 D
H_CATERR# AK14 CATERR# +1.05VS_VTT

THERMAL
2009/08/14 #425302
CP_S3PowerReduction
SM_DRAMRST# F6 SM_DRAMRST# 10
R547 1 2 H_PECI_R AT15 WhitePaper_Rev1.0 XDP_PRDY# R89 1 @ 2 51_0402_5%
18 H_PECI PECI
0_0402_5% AL1 SM_RCOMP_0 1 2 XDP_TMS R496 1 @ 2 51_0402_5%
SM_RCOMP[0] SM_RCOMP_1 R567 100K_0402_5% +1.05VS_VTT XDP_TDI_R R495 @ 51_0402_5%
SM_RCOMP[1] AM1 1 2
AN1 SM_RCOMP_2 XDP_PREQ# R90 1 @ 2 51_0402_5%
H_PROCHOT# SM_RCOMP[2] R539 1
53 H_PROCHOT# AN26 PROCHOT# 2 10K_0402_5% XDP_TCLK R62 1 @ 2 51_0402_5%
AN15 PM_EXTTS#0 R538 1 2 10K_0402_5%
PM_EXT_TS#[0]

DDR3
MISC
AP15 PM_EXTTS#1_R R548 1 2 0_0402_5%
PM_EXT_TS#[1] PM_EXTTS#0_1 10,11
R124 1 2 H_THERMTRIP#_R AK15
18 H_THERMTRIP# THERMTRIP#
0_0402_5%
XDP_TRST# R499 1 2 51_0402_5%
AT28 XDP_PRDY#
PRDY# XDP_PREQ# SM_RCOMP_0 R578 1
PREQ# AP27 2 100_0402_1%
SM_RCOMP_1 R576 1 2 24.9_0402_1%
AN28 XDP_TCLK SM_RCOMP_2 R573 1 2 130_0402_1%
H_CPURST# TCK XDP_TMS
AP26 RESET_OBS# TMS AP28

PWR MANAGEMENT
AT27 XDP_TRST#
TRST# XDP_TDI_R R488 1 2 0_0402_5% XDP_TDI

JTAG & BPM


R123 1 2 H_PM_SYNC_R AL15 AT29 XDP_TDI_R XDP_TDO_M R475 1 @ 2 0_0402_5% XDP_TDO
15 H_PM_SYNC PM_SYNC TDI
0_0402_5% AR27 XDP_TDO_R
TDO

1
AR29 XDP_TDI_M
R122 1 H_CPUPW RGD_1 TDI_M XDP_TDO_M R480
2 AN14 VCCPWRGOOD_1 TDO_M AP29
0_0402_5% 0_0402_5%
AN25 XDP_DBR#_R R87 1 2 0_0402_5% XDP_DBRESET# XDP_DBRESET# 15,21
C R121 1 H_CPUPW RGD_0 DBR# C
18 H_CPUPW RGD 2 AN27

2
0_0402_5% VCCPWRGOOD_0 XDP_TDI_M @
1 2
AJ22 XDP_OBS0 XDP_TDO_R R481 1 2 0_0402_5%
R150 1 PM_DRAM_PW RGD_R BPM#[0] XDP_OBS1 R476 0_0402_5%
15 PM_DRAM_PW RGD 2 AK13 SM_DRAMPWROK BPM#[1] AK22
0_0402_5% AK24 XDP_OBS2
BPM#[2] XDP_OBS3
BPM#[3] AJ24
H_VTTPW RGD 1 @ 2 H_VTTPW RGD_R AM15 AJ25 XDP_OBS4
R540 0_0402_5% VTTPWRGOOD BPM#[4] XDP_OBS5
BPM#[5] AH22
XDP_OBS6
JTAG MAPPING 2009/09/16 update
BPM#[6] AK23
H_PW RGD_XDP R489 1 2 H_PW RGD_XDP_R AM26 AH23 XDP_OBS7
0_0402_5% TAPPWRGOOD BPM#[7]
Scan Chain STUFF -> R488 , R480 , R476
(Default) NO STUFF -> R475 , R481
R126 1 2 PLT_RST#_R AL14 2009/2/4
17,21,32,36 PLT_RST# RSTIN#
1.5K_0402_1% Delete dampling resistor for
power noise and Layout space CPU Only STUFF -> R488 ,R475
1

2009/2/4 NO STUFF -> R480 , R481 , R476


#414044 DG R125 IC,AUB_CFD_rPGA,R1P0 issue
750_0402_1% CONN@
Update Rev1.11
GMCH Only STUFF -> R481,R476
NO STUFF -> R488, R475 , R480
2

+1.05VS_VTT

R127 2 1 49.9_0402_1% H_CATERR#


R88 2 1 68_0402_5% H_PROCHOT#
R91 2 @ 1 68_0402_5% H_CPURST#
JP2
XDP Connector
1 GND0 GND1 2
B XDP_PREQ# B
2009/8/14 3 OBSFN_A0 OBSFN_C0 4
+3VALW XDP_PRDY# 5 6
change back to 2K OBSFN_A1 OBSFN_C1
7 GND2 GND3 8
XDP_OBS0 9 10
OBSDATA_A0 OBSDATA_C0
5

U38 R550 XDP_OBS1 11 12


H_VTTPW RGD 2 2K_0402_1% OBSDATA_A1 OBSDATA_C1
13 14
P

51 H_VTTPW RGD B GND4 GND5


4 1 2 H_VTTPW RGD_R XDP_OBS2 15 16
Y XDP_OBS3 OBSDATA_A2 OBSDATA_C2
1 A 17 OBSDATA_A3 OBSDATA_C3 18
G

19 GND6 GND7 20
MC74VHC1G08DFT2G_SC70-5 R542 21 22
3

OBSFN_B0 OBSFN_D0
23 OBSFN_B1 OBSFN_D1 24
1K_0402_1% 25 26 R83
XDP_OBS4 GND8 GND9 1K_0402_5%
27 28
2

XDP_OBS5 OBSDATA_B0 OBSDATA_D0


29 OBSDATA_B1 OBSDATA_D1 30 1 XDP@ 2 H_CPURST#
31 32 H_RESET#_R 1 @ 2 PLT_RST#
XDP_OBS6 GND10 GND11 R85
#425302 +3VALW
33 OBSDATA_B2 OBSDATA_D2 34
R197 XDP_OBS7 35 36 0_0402_5%
CP_S3PowerReduction Need to check Voltage Level 1K_0402_5% 37
OBSDATA_B3 OBSDATA_D3
38
H_CPUPW RGD 1 XDP@ 2 H_PW RGOOD_R GND12 GND13 CLK_CPU_XDP
WhitePaper_Rev0.7 39 PWRGOOD/HOOK0 ITPCLK/HOOK4 40
5

U11 R84 1 XDP@ 2 PBTN_OUT#_XDP 41 42 CLK_CPU_XDP#


+1.5V_1 15,21,36 PBTN_OUT# HOOK1 ITPCLK#/HOOK5
H_VTTPW RGD 0_0402_5%
B 2 43 44
P

+1.05VS_VTT VCC_OBS_AB VCC_OBS_CD +1.05VS_VTT


4 H_PW RGD_XDP 45 46 H_RESET#_R
Y HOOK2 RESET#/HOOK6 XDP_DBRESET#
A 1 1 47 HOOK3 DBR#/HOOK7 48 1 XDP@ 2 R81 +3VS
G

C211 49 50 1K_0402_5%
GND14 GND15
1

MC74VHC1G08DFT2G_SC70-5 @ 51 52 XDP_TDO 1 XDP@ 2 R79 +1.05VS_VTT


21 SMB_DATA_S3
3

R152 R151 0.1U_0402_16V4Z SDA TD0 XDP_TRST# 51_0402_5%


21 SMB_CLK_S3 53 SCL TRST# 54
@ 2 XDP_TDI
55 TCK1 TDI 56
1.1K_0402_1% 1.5K_0402_1% XDP_TCLK 57 58 XDP_TMS
TCK0 TMS
59 60
2

A GND16 GND17 A

PM_DRAM_PW RGD_R CONN@ SAMTE_BSH-030-01-L-D-A


1
1

R149
R148
@ 750_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
3.01K_0402_1% 2009/04/23 2009/08/01 2010/08/01 Title
Issued Date Deciphered Date
2

PROCESSOR (2/6) CLK,JTAG


2

Intel CRB 1.55 Update


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Change R68 to 1.1K_1%, R71 to 3.01K_1% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 5 of 56
5 4 3 2 1
5 4 3 2 1

JCPU1D
11 DDR_B_D[0..63]
11 DDR_B_DM[0..7]
JCPU1C
10 DDR_A_D[0..63] 11 DDR_B_DQS#[0..7]
10 DDR_A_DM[0..7] 11 DDR_B_DQS[0..7]
10 DDR_A_DQS#[0..7] 11 DDR_B_MA[0..15]
10 DDR_A_DQS[0..7]
10 DDR_A_MA[0..15] SB_CK[0] W8 DDR_B_CLK0 11
SB_CK#[0] W9 DDR_B_CLK0# 11
AA6 DDR_B_D0 B5 M3
SA_CK[0] DDR_A_CLK0 10 SB_DQ[0] SB_CKE[0] DDR_B_CKE0 11
AA7 DDR_B_D1 A5
SA_CK#[0] DDR_A_CLK0# 10 SB_DQ[1]
P7 DDR_B_D2 C3
SA_CKE[0] DDR_A_CKE0 10 SB_DQ[2]
DDR_A_D0 A10 DDR_B_D3 B3 V7
SA_DQ[0] SB_DQ[3] SB_CK[1] DDR_B_CLK1 11
DDR_A_D1 C10 DDR_B_D4 E4 V6
SA_DQ[1] SB_DQ[4] SB_CK#[1] DDR_B_CLK1# 11
D DDR_A_D2 C7 DDR_B_D5 A6 M2 D
SA_DQ[2] SB_DQ[5] SB_CKE[1] DDR_B_CKE1 11
DDR_A_D3 A7 Y6 DDR_B_D6 A4
SA_DQ[3] SA_CK[1] DDR_A_CLK1 10 SB_DQ[6]
DDR_A_D4 B10 Y5 DDR_B_D7 C4
SA_DQ[4] SA_CK#[1] DDR_A_CLK1# 10 SB_DQ[7]
DDR_A_D5 D10 P6 DDR_B_D8 D1
SA_DQ[5] SA_CKE[1] DDR_A_CKE1 10 SB_DQ[8]
DDR_A_D6 E10 DDR_B_D9 D2
DDR_A_D7 SA_DQ[6] DDR_B_D10 SB_DQ[9]
A8 SA_DQ[7] F2 SB_DQ[10] SB_CS#[0] AB8 DDR_B_CS0# 11
DDR_A_D8 D8 DDR_B_D11 F1 AD6
SA_DQ[8] SB_DQ[11] SB_CS#[1] DDR_B_CS1# 11
DDR_A_D9 F10 AE2 DDR_B_D12 C2
SA_DQ[9] SA_CS#[0] DDR_A_CS0# 10 SB_DQ[12]
DDR_A_D10 E6 AE8 DDR_B_D13 F5
SA_DQ[10] SA_CS#[1] DDR_A_CS1# 10 SB_DQ[13]
DDR_A_D11 F7 DDR_B_D14 F3
DDR_A_D12 SA_DQ[11] DDR_B_D15 SB_DQ[14]
E9 SA_DQ[12] G4 SB_DQ[15] SB_ODT[0] AC7 DDR_B_ODT0 11
DDR_A_D13 B7 DDR_B_D16 H6 AD1
SA_DQ[13] SB_DQ[16] SB_ODT[1] DDR_B_ODT1 11
DDR_A_D14 E7 AD8 DDR_B_D17 G2
SA_DQ[14] SA_ODT[0] DDR_A_ODT0 10 SB_DQ[17]
DDR_A_D15 C6 AF9 DDR_B_D18 J6
SA_DQ[15] SA_ODT[1] DDR_A_ODT1 10 SB_DQ[18]
DDR_A_D16 H10 DDR_B_D19 J3
DDR_A_D17 SA_DQ[16] DDR_B_D20 SB_DQ[19]
G8 SA_DQ[17] G1 SB_DQ[20]
DDR_A_D18 K7 DDR_B_D21 G5 D4 DDR_B_DM0
DDR_A_D19 SA_DQ[18] DDR_B_D22 SB_DQ[21] SB_DM[0] DDR_B_DM1
J8 SA_DQ[19] J2 SB_DQ[22] SB_DM[1] E1
DDR_A_D20 G7 DDR_B_D23 J1 H3 DDR_B_DM2
DDR_A_D21 SA_DQ[20] DDR_B_D24 SB_DQ[23] SB_DM[2] DDR_B_DM3
G10 SA_DQ[21] J5 SB_DQ[24] SB_DM[3] K1
DDR_A_D22 J7 B9 DDR_A_DM0 DDR_B_D25 K2 AH1 DDR_B_DM4
DDR_A_D23 SA_DQ[22] SA_DM[0] DDR_A_DM1 DDR_B_D26 SB_DQ[25] SB_DM[4] DDR_B_DM5
J10 SA_DQ[23] SA_DM[1] D7 L3 SB_DQ[26] SB_DM[5] AL2
DDR_A_D24 L7 H7 DDR_A_DM2 DDR_B_D27 M1 AR4 DDR_B_DM6
DDR_A_D25 SA_DQ[24] SA_DM[2] DDR_A_DM3 DDR_B_D28 SB_DQ[27] SB_DM[6] DDR_B_DM7
M6 SA_DQ[25] SA_DM[3] M7 K5 SB_DQ[28] SB_DM[7] AT8
DDR_A_D26 M8 AG6 DDR_A_DM4 DDR_B_D29 K4
DDR_A_D27 SA_DQ[26] SA_DM[4] DDR_A_DM5 DDR_B_D30 SB_DQ[29]
L9 SA_DQ[27] SA_DM[5] AM7 M4 SB_DQ[30]
DDR_A_D28 L6 AN10 DDR_A_DM6 DDR_B_D31 N5
DDR_A_D29 SA_DQ[28] SA_DM[6] DDR_A_DM7 DDR_B_D32 SB_DQ[31]
K8 SA_DQ[29] SA_DM[7] AN13 AF3 SB_DQ[32]
DDR_A_D30 N8 DDR_B_D33 AG1
C DDR_A_D31 SA_DQ[30] DDR_B_D34 SB_DQ[33] DDR_B_DQS#0 C
P9 SA_DQ[31] AJ3 SB_DQ[34] SB_DQS#[0] D5
DDR_A_D32 AH5 DDR_B_D35 AK1 F4 DDR_B_DQS#1
DDR_A_D33 SA_DQ[32] DDR_B_D36 SB_DQ[35] SB_DQS#[1] DDR_B_DQS#2
AF5 SA_DQ[33] AG4 SB_DQ[36] SB_DQS#[2] J4
DDR_A_D34 AK6 C9 DDR_A_DQS#0 DDR_B_D37 AG3 L4 DDR_B_DQS#3
SA_DQ[34] SA_DQS#[0] SB_DQ[37] SB_DQS#[3]
DDR SYSTEM MEMORY A

DDR_A_D35 AK7 F8 DDR_A_DQS#1 DDR_B_D38 AJ4 AH2 DDR_B_DQS#4


SA_DQ[35] SA_DQS#[1] SB_DQ[38] SB_DQS#[4]

DDR SYSTEM MEMORY - B


DDR_A_D36 AF6 J9 DDR_A_DQS#2 DDR_B_D39 AH4 AL4 DDR_B_DQS#5
DDR_A_D37 SA_DQ[36] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D40 SB_DQ[39] SB_DQS#[5] DDR_B_DQS#6
AG5 SA_DQ[37] SA_DQS#[3] N9 AK3 SB_DQ[40] SB_DQS#[6] AR5
DDR_A_D38 AJ7 AH7 DDR_A_DQS#4 DDR_B_D41 AK4 AR8 DDR_B_DQS#7
DDR_A_D39 SA_DQ[38] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D42 SB_DQ[41] SB_DQS#[7]
AJ6 SA_DQ[39] SA_DQS#[5] AK9 AM6 SB_DQ[42]
DDR_A_D40 AJ10 AP11 DDR_A_DQS#6 DDR_B_D43 AN2
DDR_A_D41 SA_DQ[40] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D44 SB_DQ[43]
AJ9 SA_DQ[41] SA_DQS#[7] AT13 AK5 SB_DQ[44]
DDR_A_D42 AL10 DDR_B_D45 AK2
DDR_A_D43 SA_DQ[42] DDR_B_D46 SB_DQ[45]
AK12 SA_DQ[43] AM4 SB_DQ[46]
DDR_A_D44 AK8 DDR_B_D47 AM3
DDR_A_D45 SA_DQ[44] DDR_B_D48 SB_DQ[47] DDR_B_DQS0
AL7 SA_DQ[45] AP3 SB_DQ[48] SB_DQS[0] C5
DDR_A_D46 AK11 C8 DDR_A_DQS0 DDR_B_D49 AN5 E3 DDR_B_DQS1
DDR_A_D47 SA_DQ[46] SA_DQS[0] DDR_A_DQS1 DDR_B_D50 SB_DQ[49] SB_DQS[1] DDR_B_DQS2
AL8 SA_DQ[47] SA_DQS[1] F9 AT4 SB_DQ[50] SB_DQS[2] H4
DDR_A_D48 AN8 H9 DDR_A_DQS2 DDR_B_D51 AN6 M5 DDR_B_DQS3
DDR_A_D49 SA_DQ[48] SA_DQS[2] DDR_A_DQS3 DDR_B_D52 SB_DQ[51] SB_DQS[3] DDR_B_DQS4
AM10 SA_DQ[49] SA_DQS[3] M9 AN4 SB_DQ[52] SB_DQS[4] AG2
DDR_A_D50 AR11 AH8 DDR_A_DQS4 DDR_B_D53 AN3 AL5 DDR_B_DQS5
DDR_A_D51 SA_DQ[50] SA_DQS[4] DDR_A_DQS5 DDR_B_D54 SB_DQ[53] SB_DQS[5] DDR_B_DQS6
AL11 SA_DQ[51] SA_DQS[5] AK10 AT5 SB_DQ[54] SB_DQS[6] AP5
DDR_A_D52 AM9 AN11 DDR_A_DQS6 DDR_B_D55 AT6 AR7 DDR_B_DQS7
DDR_A_D53 SA_DQ[52] SA_DQS[6] DDR_A_DQS7 DDR_B_D56 SB_DQ[55] SB_DQS[7]
AN9 SA_DQ[53] SA_DQS[7] AR13 AN7 SB_DQ[56]
DDR_A_D54 AT11 DDR_B_D57 AP6
DDR_A_D55 SA_DQ[54] DDR_B_D58 SB_DQ[57]
AP12 SA_DQ[55] AP8 SB_DQ[58]
DDR_A_D56 AM12 DDR_B_D59 AT9
DDR_A_D57 SA_DQ[56] DDR_B_D60 SB_DQ[59]
AN12 SA_DQ[57] AT7 SB_DQ[60]
DDR_A_D58 AM13 Y3 DDR_A_MA0 DDR_B_D61 AP9
DDR_A_D59 SA_DQ[58] SA_MA[0] DDR_A_MA1 DDR_B_D62 SB_DQ[61]
AT14 SA_DQ[59] SA_MA[1] W1 AR10 SB_DQ[62]
B DDR_A_D60 DDR_A_MA2 DDR_B_D63 DDR_B_MA0 B
AT12 SA_DQ[60] SA_MA[2] AA8 AT10 SB_DQ[63] SB_MA[0] U5
DDR_A_D61 AL13 AA3 DDR_A_MA3 V2 DDR_B_MA1
DDR_A_D62 SA_DQ[61] SA_MA[3] DDR_A_MA4 SB_MA[1] DDR_B_MA2
AR14 SA_DQ[62] SA_MA[4] V1 SB_MA[2] T5
DDR_A_D63 AP14 AA9 DDR_A_MA5 V3 DDR_B_MA3
SA_DQ[63] SA_MA[5] DDR_A_MA6 SB_MA[3] DDR_B_MA4
SA_MA[6] V8 SB_MA[4] R1
T1 DDR_A_MA7 DDR_B_BS0 AB1 T8 DDR_B_MA5
SA_MA[7] 11 DDR_B_BS0 SB_BS[0] SB_MA[5]
Y9 DDR_A_MA8 DDR_B_BS1 W5 R2 DDR_B_MA6
SA_MA[8] 11 DDR_B_BS1 SB_BS[1] SB_MA[6]
DDR_A_BS0 AC3 U6 DDR_A_MA9 DDR_B_BS2 R7 R6 DDR_B_MA7
10 DDR_A_BS0 SA_BS[0] SA_MA[9] 11 DDR_B_BS2 SB_BS[2] SB_MA[7]
DDR_A_BS1 AB2 AD4 DDR_A_MA10 R4 DDR_B_MA8
10 DDR_A_BS1 SA_BS[1] SA_MA[10] SB_MA[8]
DDR_A_BS2 U7 T2 DDR_A_MA11 R5 DDR_B_MA9
10 DDR_A_BS2 SA_BS[2] SA_MA[11] SB_MA[9]
U3 DDR_A_MA12 DDR_B_CAS# AC5 AB5 DDR_B_MA10
SA_MA[12] 11 DDR_B_CAS# SB_CAS# SB_MA[10]
AG8 DDR_A_MA13 DDR_B_RAS# Y7 P3 DDR_B_MA11
SA_MA[13] 11 DDR_B_RAS# SB_RAS# SB_MA[11]
T3 DDR_A_MA14 11 DDR_B_W E# DDR_B_W E# AC6 R3 DDR_B_MA12
DDR_A_CAS# SA_MA[14] DDR_A_MA15 SB_WE# SB_MA[12] DDR_B_MA13
10 DDR_A_CAS# AE1 SA_CAS# SA_MA[15] V9 SB_MA[13] AF7
DDR_A_RAS# AB3 P5 DDR_B_MA14
10 DDR_A_RAS# SA_RAS# SB_MA[14]
10 DDR_A_W E# DDR_A_W E# AE9 N1 DDR_B_MA15
SA_WE# SB_MA[15]

IC,AUB_CFD_rPGA,R1P0
CONN@
IC,AUB_CFD_rPGA,R1P0
A
CONN@ A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (3/6) DDRIII
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 6 of 56
5 4 3 2 1
5 4 3 2 1

JCPU1F

WW15 MOW
+CPU_CORE
Peak 21A +1.05VS_VTT
48A Continuous 18A
10U_0805_6.3V6M
AG35 AH14 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC1 VTT0_1
AG34 VCC2 VTT0_2 AH12
AG33 AH11 +CPU_CORE
VCC3 VTT0_3
AG32 VCC4 VTT0_4 AH10 1 1 1 1 1 1 1
D C258 C274 C286 C282 C288 C284 C281 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M D
AG31 VCC5 VTT0_5 J14
AG30 VCC6 VTT0_6 J13
AG29 VCC7 VTT0_7 H14 1 1 1 1 1 1 1 1 1
AG28 H12 2 2 2 2 2 2 2 C676 C677 C669 C674 C657 C652 C679 C262 C232
VCC8 VTT0_8
AG27 G14
VCC9 VTT0_9 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AG26 VCC10 VTT0_10 G13
AF35 G12 10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2
VCC11 VTT0_11
AF34 VCC12 VTT0_12 G11
AF33 F14 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
VCC13 VTT0_13
AF32
VCC14 VTT0_14
F13 (Place these capacitors between inductor and socket on Bottom)
AF31 VCC15 VTT0_15 F12
AF30 F11 +1.05VS_VTT
VCC16 VTT0_16 +CPU_CORE
AF29 VCC17 VTT0_17 E14
AF28 E12
VCC18 VTT0_18 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AF27 D14 1 1
VCC19 VTT0_19
AF26 D13
VCC20 VTT0_20 + +

1.1V RAIL POWER


AD35 D12 C268 C667 1 1 1 1 1 1 1
VCC21 VTT0_21 C242 C223 C257 C261 C269 C275 C155
AD34 D11
VCC22 VTT0_22
AD33 VCC23 VTT0_23 C14
AD32 C13 2 2
VCC24 VTT0_24 2 2 2 2 2 2 2
AD31 C12
VCC25 VTT0_25 330U_X_2VM_R6M 330U_X_2VM_R6M
AD30 C11
VCC26 VTT0_26 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
AD29 VCC27 VTT0_27 B14
AD28 VCC28 VTT0_28 B12 (Place these capacitors under CPU socket, top layer)
AD27 A14
VCC29 VTT0_29
AD26 VCC30 VTT0_30 A13 CSC (Current Sense Configuration)
AC35
VCC31 VTT0_31
A12 8/25 +1.05VS_VTT
AC34 A11
VCC32 VTT0_32
AC33 VCC33
AC32 +1.05VS_VTT
VCC34 CPU_VID0 R436 1
AC31 2 1K_0402_1%
VCC35 22U_0805_6.3V6M R451 1 @
AC30 AF10 2 1K_0402_1%
C VCC36 VTT0_33 C
AC29 VCC37 VTT0_34 AE10
AC28 AC10 CPU_VID1 R437 1 2 1K_0402_1% +CPU_CORE
VCC38 VTT0_35 1 1
CPU CORE SUPPLY

AC27 AB10 C278 C277 R452 1 @ 2 1K_0402_1%


VCC39 VTT0_36 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
AC26 VCC40 VTT0_37 Y10
AA35 W10 CPU_VID2 R438 1 2 1K_0402_1%
VCC41 VTT0_38 2 2 R453 1 @
AA34 U10 2 1K_0402_1% 1 1 1 1 1 1
VCC42 VTT0_39 22U_0805_6.3V6M C157 C276 C270 C256 C241 C231
AA33 VCC43 VTT0_40 T10
AA32 J12 CPU_VID3 R439 1 @ 2 1K_0402_1%
VCC44 VTT0_41 R454 1
AA31 VCC45 VTT0_42 J11 2 1K_0402_1%
AA30 J16 2 2 2 2 2 2
VCC46 VTT0_43 CPU_VID4 R440 1 @
AA29 VCC47 VTT0_44 J15 2 1K_0402_1%
AA28 R455 1 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC48
AA27 VCC49 (Place these capacitors on CPU cavity, Bottom Layer)
AA26 CPU_VID5 R441 1 2 1K_0402_1%
VCC50 R456 1 @
Y35 2 1K_0402_1%
VCC51
Y34
VCC52 CPU_VID6 R442 1 @
Y33 2 1K_0402_1%
VCC53 R457 1 +CPU_CORE
Y32 2 1K_0402_1%
VCC54
Y31
VCC55 H_DPRSLPVR R443 1
Y30 VCC56 2 1K_0402_1% 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
Y29 R458 1 @ 2 1K_0402_1%
VCC57
Y28 1 1 1 1 1 1
VCC58 H_PSI# R444 1 @
Y27 2 1K_0402_1% C222 C651 C658 C666 C665 C668
VCC59 R459 1
Y26 2 1K_0402_1%
VCC60
V35 AN33 H_PSI# 53
VCC61 PSI# 2 2 2 2 2 2
V34
POWER

VCC62
V33 VCC63
V32 AK35 CPU_VID0 53 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
VCC64 VID[0]
V31
VCC65 VID[1]
AK33 CPU_VID1 53 (Place these capacitors on CPU cavity, Bottom Layer)
V30 AK34 CPU_VID2 53
VCC66 VID[2]
V29 AL35 CPU_VID3 53
VCC67 VID[3]
CPU VIDS

V28 AL33 CPU_VID4 53


B VCC68 VID[4] B
V27 VCC69 VID[5] AM33 CPU_VID5 53
V26 VCC70 VID[6] AM35 CPU_VID6 53
U35 AM34 H_DPRSLPVR 53
VCC71 PROC_DPRSLPVR
U34 VCC72
U33
VCC73 @ T8
U32
VCC74 H_VTTVID1 PAD
U31 G15
VCC75 VTT_SELECT
U30
VCC76 VTT Rail
U29
VCC77
U28 VCC78 H_VTTVID1 = low, 1.1V
U27 VCC79 Auburndale +1.1VS_VTT=1.05V
U26 H_VTTVID1 = high, 1.05V
R35
VCC80 Clarksfield +1.1VS_VTT=1.1V
VCC81
R34
VCC82 +CPU_CORE
R33 VCC83
R32
VCC84 ISENSE
AN35 IMVP_IMON 53 4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)
R31
VCC85
R30 1 2 +CPU_CORE 1 1 1 1 1
VCC86 R435 100_0402_1%
R29
VCC87 VCCSENSE_R R450 1 VCCSENSE + + + + +
2 0_0402_5% C541 C97 C136 C251 C134
SENSE LINES

R28 AJ34 VCCSENSE 53


VCC88 VCC_SENSE VSSSENSE_R R449 1 VSSSENSE
R27 AJ35 2 0_0402_5% VSSSENSE 53
VCC89 VSS_SENSE
R26 @
VCC90 2 2 2 2 2
P35 1 2
VCC91 R448 100_0402_1%
P34 VCC92 VTT_SENSE B15 VTT_SENSE 51
P33 A15 VSS_SENSE_VTT 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M 330U_X_2VM_R6M
VCC93 VSS_SENSE_VTT R523 1
P32 2 0_0402_5% TOP side (under inductor)
VCC94
P31 VCC95
P30
VCC96
P29
VCC97 +CPU-CORE C,uF ESR, mohm Stuffing Option
P28
P27
VCC98 Decoupling
VCC99
A
P26 VCC100 SPCAP,Polymer 4X470uF 4m ohm/4 2X470uF A

16X22uF 3m ohm/12
MLCC 0805 X5R
16X10uF 3m ohm/16

IC,AUB_CFD_rPGA,R1P0 Security Classification Compal Secret Data Compal Electronics, Inc.


CONN@ Issued Date 2009/08/01 2010/08/01 Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (4/6) PWR,Bypass
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 7 of 56
5 4 3 2 1
5 4 3 2 1

+VGFX_CORE
JCPU1G
10U_0805_6.3V6M
22U_0805_6.3V6M AT21 VAXG1
AT19 VAXG2 VAXG_SENSE AR22 VCC_AXG_SENSE 52
C675

SENSE
LINES
1 1 1 1 1 AT18 VAXG3 VSSAXG_SENSE AT22 VSS_AXG_SENSE 52
2 C250 C272 C673 C672 AT16 VAXG4
1

D
+ AR21 D
R514 C802 UMA@ UMA@ UMA@ UMA@ VAXG5
AR19 VAXG6
UMA@ 2 2 2 2
0_0402_5% 0.1U_0402_16V4Z AR18 VAXG7
1 2
DIS ONLY@ UMA@ AR16 VAXG8 GFX_VID[0] AM22 GFXVR_VID_0 52
AP21 AP22 GFXVR_VID_1 52
2

VAXG9 GFX_VID[1]

GRAPHICS VIDs
330U_X_2VM_R6M 22U_0805_6.3V6M AP19 AN22
VAXG10 GFX_VID[2] GFXVR_VID_2 52
10U_0805_6.3V6M AP18 AP23
VAXG11 GFX_VID[3] GFXVR_VID_3 52
AP16 VAXG12 15A GFX_VID[4] AM23 GFXVR_VID_4 52
UMA@2
AN21 VAXG13 GFX_VID[5] AP24 GFXVR_VID_5 52 1

GRAPHICS
AN19 AN24 R98 330_0402_5%
VAXG14 GFX_VID[6] GFXVR_VID_6 52
AN18
AN16
VAXG15 Reserved for +1.5V to +1.5V_1
VAXG16 GFXVR_EN +1.5V_1 +1.5V
091211 EMI ADD 0.1U AM21 VAXG17 GFX_VR_EN AR25
GFXVR_DPRSLPVR_R R92
GFXVR_EN 52
AM19 VAXG18 GFX_DPRSLPVR AT25 1 2 0_0402_5% GFXVR_DPRSLPVR 52
AM18 AM24 J4
VAXG19 GFX_IMON GFXVR_IMON 52
AM16 VAXG20 2 2 1 1
AL21 R99 1 2 1K_0402_5%
VAXG21 DIS ONLY@ @ JUMP_43X118
AL19 VAXG22
AL18 VAXG23
AL16 J3
VAXG24 1U_0402_6.3V4Z 1U_0402_6.3V4Z 22U_0805_6.3V6M
AK21 VAXG25 VDDQ1 AJ1 2 2 1 1
AK19 VAXG26 VDDQ2 AF1 1
AK18 AE7 1 1 1 1 1 1 1 @ JUMP_43X118

- 1.5V RAILS
VAXG27 VDDQ3 C307 C308 C309 C306 C310 C303 C315 + C326
AK16 VAXG28 VDDQ4 AE4
AJ21 AC1 330U_D2_2V_Y
VAXG29 VDDQ5 J2
AJ19 VAXG30 VDDQ6 AB7
2 2 2 2 2 2 2 2
AJ18 VAXG31 VDDQ7 AB4 2 2 1 1 +1.5VS
AJ16 VAXG32 3A VDDQ8 Y1
@ JUMP_43X118
AH21 VAXG33 VDDQ9 W7

POWER
C AH19 W4 1U_0402_6.3V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z C
VAXG34 VDDQ10 22U_0805_6.3V6M
AH18
AH16
VAXG35 VDDQ11 U1
T7
Short for +1.5VS to +1.5V_1
VAXG36 VDDQ12
VDDQ13 T4
VDDQ14 P1
+1.05VS_VTT N7
VDDQ15
VDDQ16 N4 11/03 add four 0.1u 0402

DDR3
VDDQ17 L1 Intel suggest for S3 reduse
J24 VTT1_45 VDDQ18 H1

FDI
J23 VTT1_46
H25 +1.5V_1 +1.5V
1 1 VTT1_47
C253 C260 +1.05VS_VTT
C797
22U_0805_6.3V6M 22U_0805_6.3V6M P10 1 2 0.1U_0402_16V4Z
2 2 VTT0_59
VTT0_60 N10
L10 1 C798
VTT0_61 C267 0.1U_0402_16V4Z
VTT0_62 K10 1 2
+1.05VS_VTT 10U_0805_6.3V6M C799
2 0.1U_0402_16V4Z
1 2
+1.05VS_VTT

1.1V
J22 C800
VTT1_63 0.1U_0402_16V4Z
K26 VTT1_48 VTT1_64 J20 1 2
J27 VTT1_49 VTT1_65 J18 1

PEG & DMI


1 1 J26 H21 C283
C287 C285 VTT1_50 VTT1_66
J25 VTT1_51 VTT1_67 H20
H27 H19 22U_0805_6.3V6M
22U_0805_6.3V6M 22U_0805_6.3V6M VTT1_52 VTT1_68 2
G28 VTT1_53
2 2
G27 VTT1_54
B B
G26 VTT1_55
F26 +1.8VS
VTT1_56 R97
E26 VTT1_57 VCCPLL1 L26

1.8V
E25 0.6A L27 40mil 0_0805_5%
VTT1_58 VCCPLL2 +1.8VS_VCCSFR 2.2U_0603_6.3V4Z
VCCPLL3 M26 1 2

1 1 1 1 1
C230 C224 C235 C234 C233

1U_0402_6.3V4Z
2 2 2 2 2 22U_0805_6.3V6M

IC,AUB_CFD_rPGA,R1P0 1U_0402_6.3V4Z 4.7U_0805_10V4Z


CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (5/6) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 8 of 56
5 4 3 2 1
5 4 3 2 1

JCPU1H JCPU1I

AT20 VSS1 VSS81 AE34


AT17 VSS2 VSS82 AE33
AR31 VSS3 VSS83 AE32 K27 VSS161
AR28 VSS4 VSS84 AE31 K9 VSS162
AR26 VSS5 VSS85 AE30 K6 VSS163
AR24 VSS6 VSS86 AE29 K3 VSS164
D AR23 VSS7 VSS87 AE28 J32 VSS165 D
AR20 VSS8 VSS88 AE27 J30 VSS166
AR17 VSS9 VSS89 AE26 J21 VSS167
AR15 VSS10 VSS90 AE6 J19 VSS168
AR12 VSS11 VSS91 AD10 H35 VSS169
AR9 VSS12 VSS92 AC8 H32 VSS170
AR6 VSS13 VSS93 AC4 H28 VSS171
AR3 VSS14 VSS94 AC2 H26 VSS172
AP20 VSS15 VSS95 AB35 H24 VSS173
AP17 VSS16 VSS96 AB34 H22 VSS174
AP13 VSS17 VSS97 AB33 H18 VSS175
AP10 VSS18 VSS98 AB32 H15 VSS176
AP7 VSS19 VSS99 AB31 H13 VSS177
AP4 VSS20 VSS100 AB30 H11 VSS178
AP2 VSS21 VSS101 AB29 H8 VSS179
AN34 VSS22 VSS102 AB28 H5 VSS180
AN31 VSS23 VSS103 AB27 H2 VSS181
AN23 VSS24 VSS104 AB26 G34 VSS182
AN20 VSS25 VSS105 AB6 G31 VSS183
AN17 VSS26 VSS106 AA10 G20 VSS184
AM29 VSS27 VSS107 Y8 G9 VSS185
AM27 VSS28 VSS108 Y4 G6 VSS186
AM25 VSS29 VSS109 Y2 G3 VSS187
AM20 VSS30 VSS110 W35 F30 VSS188
AM17 VSS31 VSS111 W34 F27 VSS189
AM14 VSS32 VSS112 W33 F25 VSS190
AM11 VSS33 VSS113 W32 F22 VSS191
AM8 VSS34 VSS114 W31 F19 VSS192
AM5 VSS35 VSS115 W30 F16 VSS193
C AM2 W29 E35 C
VSS36 VSS116 VSS194
AL34 W28 E32
AL31
AL23
VSS37
VSS38
VSS39
VSS VSS117
VSS118
VSS119
W27
W26
E29
E24
VSS195
VSS196
VSS197
VSS
AL20 VSS40 VSS120 W6 E21 VSS198
AL17 VSS41 VSS121 V10 E18 VSS199
AL12 VSS42 VSS122 U8 E13 VSS200
AL9 VSS43 VSS123 U4 E11 VSS201
AL6 VSS44 VSS124 U2 E8 VSS202
AL3 VSS45 VSS125 T35 E5 VSS203
AK29 T34 E2 AT35 H_NCTF1 @ PAD T14
VSS46 VSS126 VSS204 VSS_NCTF1 H_NCTF2 @
AK27 VSS47 VSS127 T33 D33 VSS205 VSS_NCTF2 AT1 PAD T19
AK25 VSS48 VSS128 T32 D30 VSS206 VSS_NCTF3 AR34
AK20 VSS49 VSS129 T31 D26 VSS207 VSS_NCTF4 B34
AK17 T30 D9 B2

NCTF
VSS50 VSS130 VSS208 VSS_NCTF5 H_NCTF6 @
AJ31 VSS51 VSS131 T29 D6 VSS209 VSS_NCTF6 B1 PAD T18
AJ23 T28 D3 A35 H_NCTF7 @ PAD T15
VSS52 VSS132 VSS210 VSS_NCTF7
AJ20 VSS53 VSS133 T27 C34 VSS211
AJ17 VSS54 VSS134 T26 C32 VSS212
AJ14 VSS55 VSS135 T6 C29 VSS213
AJ11 VSS56 VSS136 R10 C28 VSS214
AJ8 VSS57 VSS137 P8 C24 VSS215
AJ5 VSS58 VSS138 P4 C22 VSS216
AJ2 VSS59 VSS139 P2 C20 VSS217
AH35 VSS60 VSS140 N35 C19 VSS218
AH34 VSS61 VSS141 N34 C16 VSS219
AH33 VSS62 VSS142 N33 B31 VSS220
AH32 VSS63 VSS143 N32 B25 VSS221
AH31 VSS64 VSS144 N31 B21 VSS222
B B
AH30 VSS65 VSS145 N30 B18 VSS223
AH29 VSS66 VSS146 N29 B17 VSS224
AH28 VSS67 VSS147 N28 B13 VSS225
AH27 VSS68 VSS148 N27 B11 VSS226
AH26 VSS69 VSS149 N26 B8 VSS227
AH20 VSS70 VSS150 N6 B6 VSS228
AH17 VSS71 VSS151 M10 B4 VSS229
AH13 VSS72 VSS152 L35 A29 VSS230
AH9 VSS73 VSS153 L32 A27 VSS231
AH6 VSS74 VSS154 L29 A23 VSS232
AH3 VSS75 VSS155 L8 A9 VSS233
AG10 VSS76 VSS156 L5
AF8 VSS77 VSS157 L2
AF4 VSS78 VSS158 K34
AF2 VSS79 VSS159 K33
AE35 VSS80 VSS160 K30

IC,AUB_CFD_rPGA,R1P0 IC,AUB_CFD_rPGA,R1P0
CONN@ CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR (6/6) VSS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Friday, December 18, 2009 Sheet 9 of 56
5 4 3 2 1
5 4 3 2 1

+1.5V +1.5V
DIMMA VREFDQ M1 Circuit JDIMM1
6 DDR_A_DQS#[0..7]
+DIMM_VREFDQA 1 VREF_DQ VSS1 2
+1.5V 3 4 DDR_A_D4
6 DDR_A_D[0..63] VSS2 DQ4
DDR_A_D0 5 6 DDR_A_D5
DDR_A_D1 DQ0 DQ5
6 DDR_A_DM[0..7] 1 1 7 DQ1 VSS3 8

1
C401 C402 9 10 DDR_A_DQS#0
R222 +DIMM_VREFDQA DDR_A_DM0 VSS4 DQS#0 DDR_A_DQS0
6 DDR_A_DQS[0..7] 11 DM0 DQS0 12
0.1U_0402_16V4Z 2.2U_0603_6.3V4Z 13 14
1K_0402_1% 2 2 DDR_A_D2 VSS5 VSS6 DDR_A_D6
6 DDR_A_MA[0..15] 15 16
DDR_A_D3 DQ2 DQ6 DDR_A_D7
20mil 17 18
2

DQ3 DQ7
19 20
DDR_A_D8 VSS7 VSS8 DDR_A_D12
21 DQ8 DQ12 22
1

DDR_A_D9 23 24 DDR_A_D13
R227 DQ9 DQ13
25 VSS9 VSS10 26
D DDR_A_DQS#1 DDR_A_DM1 D
27 DQS#1 DM1 28
1K_0402_1% DDR_A_DQS1 29 30 DIMM_DRAMRST#
DQS1 RESET#
31 32
2

DDR_A_D10 VSS11 VSS12 DDR_A_D14


33 34
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 36
DQ11 DQ15
37 VSS13 VSS14 38
DDR_A_D16 39 40 DDR_A_D20
DDR_A_D17 DQ16 DQ20 DDR_A_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS#2 DM2
DIMMA & DIMMB VREFCA circuit 47 DQS2 VSS17 48
49 50 DDR_A_D22
+1.5V DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 56
VSS20 DQ28
1

DDR_A_D24 57 58 DDR_A_D29
R203 +DIMM_VREFCA DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
1K_0402_1% DDR_A_DM3 VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
20mil 65 66
2

+1.5V DDR_A_D26 VSS23 VSS24 DDR_A_D30


#425302 67
DQ26 DQ30
68
DDR_A_D27 69 70 DDR_A_D31
CP_S3PowerReduction DQ27 DQ31
1

71 72
WhitePaper_Rev1.0 VSS25 VSS26

1
R201 R254
0_0402_5% R274
1K_0402_1% 1 @ 2
1K_0402_1% DDR_A_CKE0 73 74 DDR_A_CKE1
6 DDR_A_CKE0 DDR_A_CKE1 6
2

CKE0 CKE1
75 76

2
VDD1 VDD2 DDR_A_MA15
77 NC1 A15 78

D
3 1 DIMM_DRAMRST# DDR_A_BS2 79 80 DDR_A_MA14
5 SM_DRAMRST# DIMM_DRAMRST# 11 6 DDR_A_BS2 BA2 A14
Q17 81 82
BSS138LT1G_SOT23-3 DDR_A_MA12 VDD3 VDD4 DDR_A_MA11
83 84
C DDR_A_MA9 A12/BC# A11 DDR_A_MA7 C
85 86

G
C422

2
A9 A7
87 88
RST_GATE DDR_A_MA8 VDD5 VDD6 DDR_A_MA6
18 RST_GATE 1 2 89 90
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD7 VDD8 94
0.047U_0402_16V7K DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 100
DDR_A_CLK0 VDD9 VDD10 DDR_A_CLK1
6 DDR_A_CLK0 101 CK0 CK1 102 DDR_A_CLK1 6
DDR_A_CLK0# 103 104 DDR_A_CLK1#
6 DDR_A_CLK0# CK0# CK1# DDR_A_CLK1# 6
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 6
DDR_A_BS0 109 110 DDR_A_RAS#
6 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 6
111 112
DDR_A_WE# VDD13 VDD14 DDR_A_CS0#
113 114 DDR_A_CS0# 6
6 DDR_A_WE# DDR_A_CAS# WE# S0# DDR_A_ODT0
6 DDR_A_CAS# 115 116 DDR_A_ODT0 6
CAS# ODT0
117 118
DDR_A_MA13 VDD15 VDD16 DDR_A_ODT1 +DIMM_VREFCA
119 120 DDR_A_ODT1 6
DDR_A_CS1# A13 ODT1
6 DDR_A_CS1#
121
S1# NC2
122 20mil
123 VDD17 VDD18 124
125 126 DDR_VREF_CA_DIMMA R202 1 2 0_0402_5%
NCTEST VREF_CA
127 128
DDR_A_D32 VSS27 VSS28 DDR_A_D36
129 130
DDR_A_D33 DQ32 DQ36 DDR_A_D37
131 132
DQ33 DQ37
Layout Note: DDR_A_DQS#4
133
VSS29 VSS30
134
DDR_A_DM4
135 136
Place near JDIMM1 DDR_A_DQS4 DQS#4 DM4
137 DQS4 VSS31 138 1 1
139 140 DDR_A_D38 C358 C361
DDR_A_D34 VSS32 DQ38 DDR_A_D39
141 142
DDR_A_D35 DQ34 DQ39 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z
Layout Note: Place these 4 Caps near Command 143
DQ35 VSS33
144
DDR_A_D44 2 2
145 146
and Control signals of DIMMA DDR_A_D40 VSS34 DQ44 DDR_A_D45
147 148
B DDR_A_D41 DQ40 DQ45 B
149 DQ41 VSS35 150
+1.5V 151 152 DDR_A_DQS#5
DDR_A_DM5 VSS36 DQS#5 DDR_A_DQS5
153 154
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DM5 DQS5
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 160
DQ43 DQ47
1

1 1 1 1 1 1 1 1 1 1 161 162
C354 C355 C356 C405 C404 C406 C362 C363 C399 C400 + C425 DDR_A_D48 VSS39 VSS40 DDR_A_D52
163 164
330U_2.5V_M_R15 DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 166
@ DQ49 DQ53
167 168
2

2 2 2 2 2 2 2 2 2 2 DDR_A_DQS#6 VSS41 VSS42 DDR_A_DM6


169 DQS#6 DM6 170
DDR_A_DQS6 171 172
DQS6 VSS43 DDR_A_D54
173 VSS44 DQ54 174
DDR_A_D50 175 176 DDR_A_D55
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_A_D51 DQ50 DQ55
177 DQ51 VSS45 178
179 180 DDR_A_D60
DDR_A_D56 VSS46 DQ60 DDR_A_D61
181 182
DDR_A_D57 DQ56 DQ61
183 184
DQ57 VSS47 DDR_A_DQS#7
185 186
DDR_A_DM7 VSS48 DQS#7 DDR_A_DQS7
187 188
DM7 DQS7
189 190
DDR_A_D58 VSS49 VSS50 DDR_A_D62
Layout Note: DDR_A_D59
191 DQ58 DQ62 192
DDR_A_D63
193 194
Place near JDIMM1.203 & JDIMM1.204 DQ59 DQ63
195 VSS51 VSS52 196
R218 1 2 10K_0402_5% 197 198 PM_EXTTS#0_1
SA0 EVENT# PM_EXTTS#0_1 5,11
199 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SDATA 11,12
201 202 D_CK_SCLK
SA1 SCL D_CK_SCLK 11,12
1 1 203 204 +0.75VS
VTT1 VTT2
1

+0.75VS C403 C398


2.2U_0603_6.3V4Z R217 205 206
1U_0402_6.3V4Z 1U_0402_6.3V4Z 0.1U_0402_16V4Z G1 G2
2 2 10K_0402_5% FOX_AS0A626-U8RN-7F
A A
2

1 1 1 1 1
C394
DDR3 SO-DIMM A
C391
2
C388
2
C397
2
C396
2 2
10U_0805_6.3V6M H=8mm
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
1U_0402_6.3V4Z 1U_0402_6.3V4Z
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 10 of 56
5 4 3 2 1
5 4 3 2 1

+1.5V
+1.5V
2008/9/8 #400755 JDIMM2
6 DDR_B_DQS#[0..7] Calpella Clarksfield +DIMM_VREFDQB 1 2
VREF_DQ VSS1 DDR_B_D4
3 4
DDR3 SO-DIMM DDR_B_D0 5
VSS2 DQ4
6 DDR_B_D5
6 DDR_B_D[0..63] 1 1 DQ0 DQ5
VREFDQ Platform C433 C431 DDR_B_D1 7 8
DQ1 VSS3 DDR_B_DQS#0
6 DDR_B_DM[0..7] Design Guide Change Details 9 VSS4 DQS#0 10
2.2U_0603_6.3V4Z DDR_B_DM0 11 12 DDR_B_DQS0
2 2 DM0 DQS0
6 DDR_B_DQS[0..7] 13 VSS5 VSS6 14
DDR_B_D2 15 16 DDR_B_D6
DDR_B_D3 DQ2 DQ6 DDR_B_D7
6 DDR_B_MA[0..15] 17 DQ3 DQ7 18
0.1U_0402_16V4Z 19 20
DDR_B_D8 VSS7 VSS8 DDR_B_D12
21 DQ8 DQ12 22
D DDR_B_D9 DDR_B_D13 D
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS#1 DM1 DIMM_DRAMRST#
29 30 DIMM_DRAMRST# 10
DQS1 RESET#
DIMMB VREFDQ M1 Circuit 31
VSS11 VSS12
32
DDR_B_D10 33 34 DDR_B_D14
+1.5V DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 36
DQ11 DQ15
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DQ16 DQ20
1

DDR_B_D17 41 42 DDR_B_D21
R282 +DIMM_VREFDQB DQ17 DQ21
43 VSS15 VSS16 44
DDR_B_DQS#2 45 46 DDR_B_DM2
1K_0402_1% DDR_B_DQS2 DQS#2 DM2
47 DQS2 VSS17 48
20mil 49 50 DDR_B_D22
2

DDR_B_D18 VSS18 DQ22 DDR_B_D23


51 52
DDR_B_D19 DQ18 DQ23
53 54
DQ19 VSS19
1

55 56 DDR_B_D28
R281 DDR_B_D24 VSS20 DQ28 DDR_B_D29
57 58
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS21 60
1K_0402_1% 61 62 DDR_B_DQS#3
DDR_B_DM3 VSS22 DQS#3 DDR_B_DQS3
63 64
2

DM3 DQS3
65 66
DDR_B_D26 VSS23 VSS24 DDR_B_D30
67 DQ26 DQ30 68
DDR_B_D27 69 70 DDR_B_D31
DQ27 DQ31
71 72
VSS25 VSS26

DDR_B_CKE0 73 74 DDR_B_CKE1
6 DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 6
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
6 DDR_B_BS2 79 80
C BA2 A14 C
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 86
A9 A7
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 92
A5 A4
93 VDD7 VDD8 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 100
DDR_B_CLK0 VDD9 VDD10 DDR_B_CLK1
101 CK0 CK1 102 DDR_B_CLK1 6
6 DDR_B_CLK0 DDR_B_CLK0# DDR_B_CLK1#
103 104 DDR_B_CLK1# 6
6 DDR_B_CLK0# CK0# CK1#
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
DDR_B_BS0 A10/AP BA1 DDR_B_RAS# DDR_B_BS1 6
6 DDR_B_BS0 109 110 DDR_B_RAS# 6
BA0 RAS#
111 112
DDR_B_WE# VDD13 VDD14 DDR_B_CS0#
113 114 DDR_B_CS0# 6
6 DDR_B_WE# DDR_B_CAS# WE# S0# DDR_B_ODT0
6 DDR_B_CAS# 115 116 DDR_B_ODT0 6
CAS# ODT0
Layout Note: DDR_B_MA13
117
VDD15 VDD16
118
DDR_B_ODT1
119 A13 ODT1 120 DDR_B_ODT1 6
Place near JDIMM2 DDR_B_CS1# 121 122 20mil +DIMM_VREFCA
6 DDR_B_CS1# S1# NC2
123 124
VDD17 VDD18 DDR_VREF_CA_DIMMB R270 1
Layout Note: Place these 4 Caps near Command 125 126 2 0_0402_5%
NCTEST VREF_CA
127 128
and Control signals of DIMMB DDR_B_D32 129
VSS27 VSS28
130 DDR_B_D36
DDR_B_D33 DQ32 DQ36 DDR_B_D37
131 132
+1.5V DQ33 DQ37
133 VSS29 VSS30 134
DDR_B_DQS#4 135 136 DDR_B_DM4
10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_DQS4 DQS#4 DM4
137 138 1 1
DQS4 VSS31 DDR_B_D38 C414 C415
139 140
DDR_B_D34 VSS32 DQ38 DDR_B_D39
141 142
DQ34 DQ39
1

1 1 1 1 1 1 1 1 1 1 DDR_B_D35 143 144 2.2U_0603_6.3V4Z 0.1U_0402_16V4Z


DQ35 VSS33 2 2
C435

B C437 C436 C420 C418 C416 C429 C430 C417 C419 + C395 145 146 DDR_B_D44 B
330U_2.5V_M_R15 DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
2

10U_0805_6.3V6M 2 2 2 2 2 2 2 2 2 2 DQ41 VSS35 DDR_B_DQS#5


151 VSS36 DQS#5 152
DDR_B_DM5 153 154 DDR_B_DQS5
DM5 DQS5
155 156
DDR_B_D42 VSS37 VSS38 DDR_B_D46
157 158
10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 160
DQ43 DQ47
161 162
DDR_B_D48 VSS39 VSS40 DDR_B_D52
163 DQ48 DQ52 164
DDR_B_D49 165 166 DDR_B_D53
DQ49 DQ53
167 168
DDR_B_DQS#6 VSS41 VSS42 DDR_B_DM6
169 DQS#6 DM6 170
Layout Note: DDR_B_DQS6 171 172
DQS6 VSS43 DDR_B_D54
173 174
Place near JDIMM2.203 & JDIMM2.204 DDR_B_D50 175
VSS44 DQ54
176 DDR_B_D55
DDR_B_D51 DQ50 DQ55
177 178
DQ51 VSS45 DDR_B_D60
179 180
DDR_B_D56 VSS46 DQ60 DDR_B_D61
181 182
DDR_B_D57 DQ56 DQ61
183 184
+0.75VS DQ57 VSS47 DDR_B_DQS#7
185 186
DDR_B_DM7 VSS48 DQS#7 DDR_B_DQS7
187 DM7 DQS7 188
1U_0402_6.3V4Z 189 190
DDR_B_D58 VSS49 VSS50 DDR_B_D62
191 DQ58 DQ62 192
DDR_B_D59 193 194 DDR_B_D63
DQ59 DQ63
195 196
VSS51 VSS52 PM_EXTTS#0_1
1 1 1 1 1 C411 R279 1 2 10K_0402_5% 197 SA0 EVENT# 198 PM_EXTTS#0_1 5,10
C413 C412 C427 C426 199 200 D_CK_SDATA
+3VS VDDSPD SDA D_CK_SCLK D_CK_SDATA 10,12
1 2 201 202 D_CK_SCLK 10,12
10U_0805_6.3V6M R278 10K_0402_5% SA1 SCL
203 204 +0.75VS
2 2 2 2 2 VTT1 VTT2
1 1
1U_0402_6.3V4Z C432 C428 205 206
A G1 G2 A

1U_0402_6.3V4Z 1U_0402_6.3V4Z
2.2U_0603_6.3V4Z
2 2
0.1U_0402_16V4Z FOX_AS0A626-U4RN-7F
CONN@
DDR3 SO-DIMM B
H=4mm
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 11 of 56
5 4 3 2 1
A B C D E F G H

SM010014520 3000ma 220ohm@100mhz DCR 0.04

SM010014520 3000ma 220ohm@100mhz DCR 0.04 +CLK_3VS


+CLK_1.05VS 40mil
40mil 0.1U_0402_16V4Z
+1.05VS_VTT L76 2 1 +3VS L69 2 1
FBMA-L11-201209-221LMA30T_0805 FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1 1 1 1
C774 C757 C770 C737 C740 C750 C741
C782
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 10U_0805_10V4Z
2 2 2 2 2 2 2 2
1 1

10U_0805_10V4Z 0.1U_0402_16V4Z

L74 2 1
FBMA-L11-201209-221LMA30T_0805
SM010014520 3000ma 220ohm@100mhz DCR 0.04 @ +CLK_1.5VS
40mil
+1.5VS L75 2 1 0.1U_0402_16V4Z
FBMA-L11-201209-221LMA30T_0805
1 1 1 1 1
C768 C742 C771 C769
C781
10U_0805_10V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
2 2 2 2 2

0.1U_0402_16V4Z

2 +CLK_3VS 2
+CLK_3VS

+CLK_1.5VS Clock Generator


U47

1 32 D_CK_SCLK
VDD_USB_48 SCL D_CK_SCLK 10,11
2 31 D_CK_SDATA
VSS_48M SDA D_CK_SDATA 10,11
CLK_BUF_DREF_96M 3 30 REF_0/CPU_SEL R682 1 2 33_0402_5%
14 CLK_BUF_DREF_96M DOT_96 REF_0/CPU_SEL CLK_BUF_ICH_14M 14
CLK_BUF_DREF_96M# 4 29
14 CLK_BUF_DREF_96M# DOT_96# VDD_REF
R717 0_0402_5% @ 5 28 CLK_XTAL_IN
27M_CLK VDD_27 XTAL_IN CLK_XTAL_OUT
22 27M_CLK 1 2 6 27MHZ XTAL_OUT 27
1 2 27M_SSC 7 26
22 27M_SSC 27MHZ_SS VSS_REF
R716 0_0402_5% @ 8 25 CK505_PW RGD
USB_48 CKPWRGD/PD#
9 VSS_27M VDD_CPU 24
CLK_BUF_PCIE_SATA 10 23 CLK_BUF_CPU_BCLK
14 CLK_BUF_PCIE_SATA SATA CPU_0 CLK_BUF_CPU_BCLK 14
CLK_BUF_PCIE_SATA# 11 22 CLK_BUF_CPU_BCLK#
14 CLK_BUF_PCIE_SATA# SATA# CPU_0# CLK_BUF_CPU_BCLK# 14
12 VSS_SRC VSS_CPU 21
CLK_BUF_CPU_DMI 13 20
14 CLK_BUF_CPU_DMI SRC_1 CPU_1
CLK_BUF_CPU_DMI# 14 19
14 CLK_BUF_CPU_DMI# SRC_1# CPU_1#
+CLK_1.05VS 15 VDD_SRC_IO VDD_CPU_IO 18 +CLK_1.05VS
H_STP_CPU# 16 17 +CLK_1.5VS
CPU_STOP# VDD_SRC
33 TGND
IDT SA00003HR00
SLG8SP587VTR_QFN32_5X5

3 IDT: 9LRS3199AKLFT, SA000030P00 3

SILEGO: SLG8SP587V(WF), SA00002XY10


+3VS
Low Power:
IDT: 9LVS3199AKLFT, SA00003HR00

2
+3VS
Silego Have Internal Pull-Up Realtek: RTM890N-631-VB-GRT, SA00003HQ10 R693
IDT 9LVS3199AKLFT NC 10K_0402_5%
R691
R690 1 2 10K_0402_5% H_STP_CPU# +3VS 0_0402_5%

1
R678 CK505_PW RGD 1 @ 2 VGATE 15,53
4.7K_0402_5%
D
2

1
G

1 2 +3VS
2 CLK_ENABLE# 53
IDT Have Internal Pull-Down 14,21,34 PCH_SMBDATA 1 3 D_CK_SDATA G
S Q48
D

3
FOR Realtek Q46 2N7002E-T1-GE3_SOT23-3
2N7002E-T1-GE3_SOT23-3

R683 1 2 10K_0402_5% REF_0/CPU_SEL +3VS


R677
4.7K_0402_5% C755
2

CLK_XTAL_IN
G

1 2 +3VS 2 1

1
PIN 30 CPU_0 CPU_1 14,21,34 PCH_SMBCLK 1 3 D_CK_SCLK 27P_0402_50V8J
Y4
D

Q45 14.31818MHZ 20PF 7A14300003 C762


0 (Default) 133MHz 133MHz 2N7002E-T1-GE3_SOT23-3 27P_0402_50V8J

2
4 4
Change to 5x3.2 CLK_XTAL_OUT 2 1

1 100MHz 100MHz

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Clock Generator (CK505)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 12 of 56
A B C D E F G H
5 4 3 2 1

+RTCBATT
+RTCVCC 1 2 PCH_RTCRST#
R215 C723

2
20K_0402_1% RC Delay 18~25mS 18P_0402_50V8J
2 1 PCH_RTCX1 R336
close to RAM door X2
20mil 1K_0402_5%

1
1 2 3 4

1
R671 @ NC OSC R615
10K_0603_5% 2 1
C366 NC OSC 10M_0402_5% U41A +RTCBATT_R
1U_0603_10V6K 32.768KHZ_12.5PF_Q13MC14610002
REV1.0

1
1 2 C722 B13 D33 LPC_AD0
RTCX1 FWH0 / LAD0 LPC_AD0 36
D 2 1 PCH_RTCX2 D13 B33 LPC_AD1 D
RTCX2 FWH1 / LAD1 LPC_AD1 36
C32 LPC_AD2 D8
FWH2 / LAD2 LPC_AD2 36
18P_0402_50V8J A32 LPC_AD3 BAS40-04_SOT23-3
FWH3 / LAD3 LPC_AD3 36
+RTCVCC 1 2 PCH_SRTCRST# PCH_RTCRST# C14 +RTCVCC
R214 RTCRST# LPC_FRAME#
C34 LPC_FRAME# 36 20mil

2
20K_0402_1% +RTCVCC PCH_SRTCRST# FWH4 / LFRAME#
RC Delay 18~25mS D17 SRTCRST# +CHGRTC
A34 1

RTC

LPC
R213 1 LDRQ0#
close to RAM door 2 1M_0402_5% SM_INTRUDER# A16 INTRUDER# LDRQ1# / GPIO23 F34 C724
1 2 modify to 330K 20mil
R675 @ R212 1 2 330K_0402_1% PCH_INTVRMEN A14 AB9 SERIRQ 0.1U_0402_16V4Z
INTVRMEN SERIRQ SERIRQ 36 2
10K_0603_5%
C365 INTVRMEN - Integrated SUS 1.05V VRM Enable High - Enable Internal VRs
1U_0603_10V6K HDA for AUDIO
1 2 39 HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_PCH A30
R330 33_0402_5% HDA_BCLK SATA_DTX_C_PRX_N0
SATA0RXN AK7 SATA_DTX_C_PRX_N0 31
(HDA_SYNC Have internal Pull-Down) 39 HDA_SYNC_AUDIO 1 2 HDA_SYNC_PCH D29 AK6 SATA_DTX_C_PRX_P0 SATA_DTX_C_PRX_P0 31 SATA for HDD1
R327 33_0402_5% HDA_SYNC SATA0RXP SATA_PTX_DRX_N0
SATA0TXN AK11 SATA_PTX_DRX_N0 31
HDA_SYNC (SPKR Have internal Pull-Down) 39 PCH_SPKR PCH_SPKR P1 AK9 SATA_PTX_DRX_P0
SPKR SATA0TXP SATA_PTX_DRX_P0 31
On Die PLL VR is supplied by HDA_RST_PCH#
39 HDA_RST_AUDIO# 1 2 C30 HDA_RST#
1.5V when sampled High, R328 33_0402_5% AH6 SATA_DTX_C_PRX_N1
SATA1RXN SATA_DTX_C_PRX_N1 31
1.8V when sampled Low. AH5 SATA_DTX_C_PRX_P1 SATA_DTX_C_PRX_P1 31 SATA for ODD
SATA1RXP SATA_PTX_DRX_N1
39 HDA_SDIN0 G30 HDA_SDIN0 SATA1TXN AH9 SATA_PTX_DRX_N1 31
AH8 SATA_PTX_DRX_P1
SATA1TXP SATA_PTX_DRX_P1 31
F30 HDA_SDIN1
+3VS R650 AF11
1K_0402_5% SATA2RXN
E32 AF9 2/10 SATA2, SATA3 not support on HM55

IHDA
@ PCH_SPKR HDA_SDIN2 SATA2RXP
1 2 HDA_SDO ,This signal has a weak internal pull-down SATA2TXN AF7
Have internal PD resistor. Should not be Pull High F32 HDA_SDIN3 SATA2TXP AF6
C C
1 2 SERIRQ AH3
R237 HDA_SDOUT_PCH SATA3RXN
39 HDA_SDOUT_AUDIO 1 2 B29 HDA_SDO SATA3RXP AH1
10K_0402_5% R324 33_0402_5% AF3
SATA3TXN
If GPIO33 pull down, ME will not working. SATA3TXP AF1
GPIO33 can not pull down PCH_GPIO33# H32
For factory update ME, pull down resistor pull

SATA
HDA_DOCK_EN# / GPIO33
(manufacturing environments) SATA4RXN AD9
under door. J30 AD8
PCH_GPIO33# HDA_DOCK_RST# / GPIO13 SATA4RXP
SATA4TXN AD6
SATA4TXP AD5
D
1

21 PCH_JTAG_TCK PCH_JTAG_TCK M3 AD3


JTAG_TCK SATA5RXN
36 ME_OVERRIDE 2 SATA5RXP AD1
G Q39 21 PCH_JTAG_TMS K3 AB3
JTAG_TMS SATA5TXN
1

S AB1
3

R580 2N7002E-T1-GE3_SOT23-3 SATA5TXP


21 PCH_JTAG_TDI K1 JTAG_TDI
100K_0402_5% +1.05VS_PCH

JTAG
21 PCH_JTAG_TDO J2 JTAG_TDO SATAICOMPO AF16
2

21 PCH_JTAG_RST# J4 AF15 SATA_COMP R205 1 2 37.4_0402_1%


TRST# SATAICOMPI

GPIO33 has a weak internal pull-up


PCH_SPI_CLK_1 R665 1 2 0_0402_5% PCH_SPI_CLK BA2 +3VS
NOTE: Asserting the GPIO33 low on the rising SPI_CLK
edge of PWROK will also halt Intel Management PCH_SPI_CS0# R662 1 2 15_0402_5% PCH_SPI_CS0#_R AV3 PCH_SATALED# R652 1 2 10K_0402_5%
SPI_CS0#
Engine after chipset bringup and disable
runtime Intel Management Engine features. 2009/08/23 @ PCH_SPI_CS1# AY3 T3
T24 PAD SPI_CS1# SATALED# PCH_SATALED# 37 +3VS
B This is a debug mode and must not be Debug Port DG1.7 P27.28 B
asserted after manfacturing/ debug. TDO,TDI,TMS PCH_SPI_MOSI_1 R664 1 2 15_0402_5% PCH_SPI_MOSI AY1 Y9
GPIO21 Project ID2 R267 1 2 10K_0402_5%
SPI_MOSI SATA0GP / GPIO21
Pull Up for Production Units PCH_SPI_MISO_1 R661

SPI
1 2 33_0402_5% PCH_SPI_MISO AV1 SPI_MISO SATA1GP / GPIO19 V1 R260 1 SG@ 2 10K_0402_5%
unpop TDO,TDI,TMS resister
+1.05VS_PCH +3V

1
IBEXPEAK-M_FCBGA107
PCH_GPIO21 21
R259 R268
2008 Intel MOW36/MOW50 PCH_GPIO19 21
51_0402_5% 2 @ 1 R646 NonSG@ @
200_0402_5% 2 1 R726 TDO: 10K_0402_5% 10K_0402_5%
100_0402_5% 2 1 R725 PCH_JTAG_TMS Reserved on ES1 Sample

2
Mount R724, R722 on ES2 Sample
51_0402_5% 2 @ 1 R644
200_0402_5% 2 1 R724
100_0402_5% 2 1 R722 PCH_JTAG_TDO MP mount R646, R644, +3VS
R645, R643 and remove U18
51_0402_5% 2 @ 1 R645 others PCH_SPI_CS0# 1 8
200_0402_5% 2 CS# VCC
1 R728 +3VS R301 1 2 3.3K_0402_5% SPI_W P1# 3 WP# SCLK 6 PCH_SPI_CLK_1 PCH_SPI_CLK_1 @ 1 2
100_0402_5% 2 1 R727 PCH_JTAG_TDI R271 1 2 3.3K_0402_5% SPI_HOLD1# 7 5 PCH_SPI_MOSI_1 C729 10P_0402_50V8J
HOLD# SI PCH_SPI_MISO_1
4 GND SO 2
51_0402_5% 2 @ 1 R643
20K_0402_5% 2 1 R721 MX25L3205DM2I-12G SOP 8P
10K_0402_5% 2 1 R723 PCH_JTAG_RST# SA000021A00
GPIO19 GPIO37
SPI ROM Footprint 200mil PCH_GPIO19 VGA_PRSNT_L#

dGPU 0 0
A
4.7K_0402_5% 2 1 R647 PCH_JTAG_TCK
iGPU 0 1 A

* SG 1 X
S3 CRB 1.1 Change to 4.7K
+3VS

Security Classification Compal Secret Data Compal Electronics, Inc.


1K_0402_5% 2 @ 1 R663 PCH_SPI_MOSI 2009/08/01 2010/08/01 Title
Issued Date Deciphered Date
enable iTPM: SPI_MOSI High THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
MOSI This signal has a weak internal pull-down
resistor. This signal must be sampled low.
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 13 of 56
5 4 3 2 1
5 4 3 2 1

U41B
1. Connect Directly
REV1.0 EXPRESS CARD, MINI1, MINI2
PCIE_DTX_C_PRX_N1 BG30 B9 EC_LID_OUT# 2. Level Shift1, Pull-Up to +3VS
32 PCIE_DTX_C_PRX_N1 PERN1 SMBALERT# / GPIO11 EC_LID_OUT# 36
PCIE_DTX_C_PRX_P1 BJ30
32 PCIE_DTX_C_PRX_P1 PERP1 CLOCK GEN, DIMM1, DIMM2
For PCIE LAN 32 PCIE_PTX_C_DRX_N1 C335 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N1 BF29 H14 PCH_SMBCLK PCH_SMBCLK 12,21,34
C339 0.1U_0402_16V7K PCIE_PTX_DRX_P1 PETN1 SMBCLK
32 PCIE_PTX_C_DRX_P1 2 1 BH29 PETP1 PCH_SMBDATA
3. Level Shift2, Pull-Up to +3VS
SMBDATA C8 PCH_SMBDATA 12,21,34
34 PCIE_DTX_C_PRX_N2
PCIE_DTX_C_PRX_N2 AW30 LAN
PCIE_DTX_C_PRX_P2 BA30 PERN2
34 PCIE_DTX_C_PRX_P2
C332 2 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BC30 PERP2 PCH_GPIO60
4. Level Shift3, Pull-Up to +3VS
For Wireless LAN 34 PCIE_PTX_C_DRX_N2
C334 2
1
0.1U_0402_16V7K PCIE_PTX_DRX_P2 BD30 PETN2 SML0ALERT# / GPIO60 J14
CPU & PCH XDP
34 PCIE_PTX_C_DRX_P2 1 PETP2
D
SML0CLK C6 D
AU30

SMBus
PERN3
AT30 PERP3 SML0DATA G8
AU32 PETN3
AV32 PETP3
M14 PCH_GPIO74
SML1ALERT# / GPIO74
BA32 PERN4
BB32 E10 PCH_SML1CLK
PERP4 SML1CLK / GPIO58
BD32 PETN4 DGPU_PW R_EN 18,21,38,42
BE32 G12 PCH_SML1DAT +3V
PETP4 SML1DATA / GPIO75

PCI-E*

1
BF33 PERN5

1
For Mini2 2009/08/25: remove PCIE5 BH33 T13 R275
PERP5 CL_CLK1

Controller
BG32 R636 DIS@
PETN5 10K_0402_5%
BJ32 PETP5 CL_DATA1 T11
10K_0402_5%

Link

2
BA34 T9

2
PERN6 CL_RST1#
AW34 PERP6

2
G
BC34 PETN6
BD34 PETP6
H1 PEG_CLKREQ#_R 1 3
PEG_A_CLKRQ# / GPIO47 PEG_CLKREQ# 22
AT34

S
PERN7

1
2/10 PCIE7, PCIE8 not support on HM55 AU34 Q18
PERP7 R247 DIS@ R276
AU36 PETN7 CLKOUT_PEG_A_N AD43 CLK_PEG_VGA# 22
AV36 AD45 CLK_PEG_VGA 22 @ @
PETP7 CLKOUT_PEG_A_P 2.2K_0402_5% 2.2K_0402_5%
BG34 AN4 CLK_CPU_DMI# 5

2
PERN8 CLKOUT_DMI_N

PEG
BJ34 PERP8 CLKOUT_DMI_P AN2 CLK_CPU_DMI 5
BG36 PETN8
C BJ36 2N7002E-T1-GE3_SOT23-3 C
PETP8
CLKOUT_DP_N / CLKOUT_BCLK1_N AT1
CLKOUT_DP_P / CLKOUT_BCLK1_P AT3
32 CLK_PCIE_LAN# AK48 CLKOUT_PCIE0N
For PCIE LAN 32 CLK_PCIE_LAN AK47 CLKOUT_PCIE0P

From CLK BUFFER


CLKIN_DMI_N AW24 CLK_BUF_CPU_DMI# 12
R258 1 2 0_0402_5% PCH_GPIO73 P9 BA24
32 LAN_CLKREQ# PCIECLKRQ0# / GPIO73 CLKIN_DMI_P CLK_BUF_CPU_DMI 12

34 CLK_PCIE_MINI1# AM43 CLKOUT_PCIE1N CLKIN_BCLK_N AP3 CLK_BUF_CPU_BCLK# 12


For Wireless LAN 34 CLK_PCIE_MINI1 AM45 CLKOUT_PCIE1P CLKIN_BCLK_P AP1 CLK_BUF_CPU_BCLK 12
R266 1 2 0_0402_5% PCH_GPIO18 U4
34 MINI1_CLKREQ# PCIECLKRQ1# / GPIO18
21 PCH_GPIO18 CLKIN_DOT_96N F18 CLK_BUF_DREF_96M# 12 6/9 MOW23 Request add 25MHz crystal
E18 CLK_BUF_DREF_96M 12
AM47
CLKIN_DOT_96P supporting Integrated Graphics
CLKOUT_PCIE2N
AM48 CLKOUT_PCIE2P
CLKIN_SATA_N / CKSSCD_N AH13 CLK_BUF_PCIE_SATA# 12
PCH_GPIO20 N4 AH12 R563
21 PCH_GPIO20 PCIECLKRQ2# / GPIO20 CLKIN_SATA_P / CKSSCD_P CLK_BUF_PCIE_SATA 12
DIS ONLY@
0_0402_5%
CLK_BUF_ICH_14M 12
AH42 CLKOUT_PCIE3N REFCLK14IN P41 1 2
AH41 CLKOUT_PCIE3P 1 2 1 2
R163 10_0402_5% C319 10P_0402_50V8J
PCH_GPIO25 A8 J42 1109 RF request
PCIECLKRQ3# / GPIO25 CLKIN_PCILOOPBACK CLK_PCI_FB 17
2009/08/25: Change back to +3V C693 UMA@
+3V 27P_0402_50V8J
remove mini2 XTAL25_IN
AM51 CLKOUT_PCIE4N XTAL25_IN AH51 1 2
2009/08/25: remove mini2 clk AM53 AH53 XTAL25_OUT
CLKOUT_PCIE4P XTAL25_OUT
1

1
B B
R241 MINI2_CLKREQ#_1 M9 AF38 XCLK_RCOMP R170 1 2 90.9_0402_1% +1.05VS_PCH R564 Y2
PCIECLKRQ4# / GPIO26 XCLK_RCOMP 1M_0402_5% 25MHZ_20PF_7A25000012
10K_0402_5% UMA@ UMA@

2
+3VS Change to 5x3.2
AJ50 T45 Project Structure ID
2

2
CLKOUT_PCIE5N CLKOUTFLEX0 / GPIO64
AJ52 CLKOUT_PCIE5P 1 2
MINI2_CLKREQ#_1 R156 1 2 10K_0402_5%
+3VS PCH_GPIO44 H6 P43 PROJECT_ID1 @ C694
Clock Flex

PCIECLKRQ5# / GPIO44 CLKOUTFLEX1 / GPIO65 R144 1 2 10K_0402_5% 27P_0402_50V8J


UMA@
10K_0402_5% 2 1 R265 MINI1_CLKREQ# AK53 T42 PROJECT_ID0 R157 1 2 10K_0402_5%
10K_0402_5% 2 CLKOUT_PEG_B_N CLKOUTFLEX2 / GPIO66
1 R649 PCH_GPIO20 AK51 CLKOUT_PEG_B_P
@
R167 1 2 10K_0402_5%
PCH_GPIO56 P13 N50 +3VS
PEG_B_CLKRQ# / GPIO56 CLKOUTFLEX3 / GPIO67
Schematic_Checklist_Rev1.6

2
Muxed with PCIECLKRQ1#. IBEXPEAK-M_FCBGA107
GPIO18 Main (core) power well (+V3.3S) If not used, requires 8.2-k to 10-k pull-up to +Vcc_3.3 (+V3.3S)
Project Structure PCH_SML1CLK 6 1 EC_SMB_CK2 EC_SMB_CK2 22,36
Muxed with PCIECLKREQ3#
GPIO25 Resume (Sus) well (+V3.3A) If not used, requires 8.2-k to 10-k pull-up to +V3.3A rail.
GPIO21 GPIO65 GPIO66 Q19A
Structure
ID2 ID1 ID0 2N7002DW H_SOT363-6

+3V +3VS
0 0 0 NEW70 Pull high +3VS at KB926 side
0 0 1 NEW80

5
10K_0402_5% 2 1 R623 EC_LID_OUT#
2.2K_0402_5% 2 1 R602 PCH_SMBCLK
2.2K_0402_5% 2 1 R626 PCH_SMBDATA
0 1 0 NEW90 PCH_SML1DAT 3 4 EC_SMB_DA2
A EC_SMB_DA2 22,36 A

10K_0402_5% 2 1 R208 PCH_GPIO60


* 1 0 0 NEW71/91 Q19B
2N7002DW H_SOT363-6
2.2K_0402_5% 2 1 R639 PCH_SML1CLK
2.2K_0402_5% 2 1 R249 PCH_SML1DAT

+3V 9/1: Change to +3VS 10K_0402_5% 2 1 R207 PCH_GPIO74 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
2009/08/13: Change back to +3V PCH (2/9) PCIE, SMBUS, CLK
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
10K_0402_5% 2 1 R244 PCH_GPIO44 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
10K_0402_5% 2 1 R206 PCH_GPIO56 Custom
10K_0402_5% 2 1 R624 PCH_GPIO25 10K_0402_5% 2 1 R257 PCH_GPIO73
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 14 of 56
5 4 3 2 1
5 4 3 2 1

DMI_HTX_PRX_N[0..3]
4 DMI_HTX_PRX_N[0..3]
DMI_HTX_PRX_P[0..3]
4 DMI_HTX_PRX_P[0..3]
DMI_PTX_HRX_N[0..3]
4 DMI_PTX_HRX_N[0..3]
DMI_PTX_HRX_P[0..3]
4 DMI_PTX_HRX_P[0..3]

H_FDI_TXN[0..7]
4 H_FDI_TXN[0..7]
D U41C D
H_FDI_TXP[0..7] H_FDI_TXN0
4 H_FDI_TXP[0..7]
DMI_HTX_PRX_N0 BC24
REV1.0 FDI_RXN0 BA18
BH17 H_FDI_TXN1
DMI_HTX_PRX_N1 BJ22 DMI0RXN FDI_RXN1 H_FDI_TXN2
DMI1RXN FDI_RXN2 BD16
DMI_HTX_PRX_N2 AW20 BJ16 H_FDI_TXN3
DMI_HTX_PRX_N3 BJ20 DMI2RXN FDI_RXN3 H_FDI_TXN4
DMI3RXN FDI_RXN4 BA16
+3VS BE14 H_FDI_TXN5
DMI_HTX_PRX_P0 FDI_RXN5 H_FDI_TXN6
BD24 DMI0RXP FDI_RXN6 BA14
DMI_HTX_PRX_P1 BG22 BC12 H_FDI_TXN7
DMI_HTX_PRX_P2 DMI1RXP FDI_RXN7
BA20 DMI2RXP
1 2 PM_CLKRUN# DMI_HTX_PRX_P3 BG20 BB18 H_FDI_TXP0
R657 8.2K_0402_5% DMI3RXP FDI_RXP0 H_FDI_TXP1
FDI_RXP1 BF17
DMI_PTX_HRX_N0 BE22 BC16 H_FDI_TXP2
DMI_PTX_HRX_N1 DMI0TXN FDI_RXP2 H_FDI_TXP3
BF21 DMI1TXN FDI_RXP3 BG16
DMI_PTX_HRX_N2 BD20 AW16 H_FDI_TXP4
DMI_PTX_HRX_N3 DMI2TXN FDI_RXP4 H_FDI_TXP5
BE18 DMI3TXN FDI_RXP5 BD14
BB14 H_FDI_TXP6
DMI_PTX_HRX_P0 FDI_RXP6 H_FDI_TXP7
BD22 DMI0TXP FDI_RXP7 BD12
DMI_PTX_HRX_P1 BH21
+3V DMI_PTX_HRX_P2 DMI1TXP
BC20 DMI2TXP
DMI_PTX_HRX_P3 BD18 BJ14 H_FDI_INT 4
+1.05VS_PCH DMI3TXP FDI_INT

DMI
FDI
1 2 SUS_PW R_DN_ACK BF13 H_FDI_FSYNC0 4
R648 10K_0402_5% R600 FDI_FSYNC0
BH25 DMI_ZCOMP
1 2 PCH_GPIO72 49.9_0402_1% BH13 H_FDI_FSYNC1 4
R628 8.2K_0402_5% DMI_COMP FDI_FSYNC1
1 2 BF25 DMI_IRCOMP
1 2 EC_SW I# BJ12 H_FDI_LSYNC0 4
R198 10K_0402_5% FDI_LSYNC0
1 2 PCH_PCIE_W AKE# 09/09/14 WW37 PCH WAKE# PU 10K BG14 H_FDI_LSYNC1 4
C R641 10K_0402_5% FDI_LSYNC1 C
1 @ 2 PM_SLP_LAN#
R248 10K_0402_5%

XDP_DBRESET# T6 J12 PCH_PCIE_W AKE#


5,21 XDP_DBRESET# SYS_RESET# WAKE# PCH_PCIE_W AKE# 32,34

SYS_PW ROK R620 2 1 0_0402_5% SYS_PW ROK_R M6 Y1 PM_CLKRUN#


SYS_PWROK CLKRUN# / GPIO32 PM_CLKRUN# 36
VGATE R631 2 @ 1 0_0402_5%

System Power Management


SYS_PW ROK B17 PWROK

K5 P8 PCH_GPIO61 @ PAD
MEPWROK SUS_STAT# / GPIO61 T10

LAN_RST# A10 F3 SUSCLK SUSCLK 36


LAN_RST# SUSCLK / GPIO62

5 PM_DRAM_PW RGD D9 DRAMPWROK SLP_S5# / GPIO63 E4 PM_SLP_S5# 36

PCH_RSMRST# C16 H7 PM_SLP_S4# 36


RSMRST# SLP_S4#

SUS_PW R_DN_ACK M1 P12 PM_SLP_S3# 36


B 36 SUS_PW R_DN_ACK SUS_PWR_DN_ACK / GPIO30 SLP_S3# B

PBTN_OUT# P5 K8 PM_SLP_M# @ PAD @


5,21,36 PBTN_OUT# PWRBTN# SLP_M# T11
+3V 1 2 R605 2 1 0_0402_5%
R240 10K_0402_5% Q41
1 2 PCH_ACIN P7 N2 PM_SLP_DSW # @ PAD MMBT3906_SOT23-3
36 EC_ACIN ACPRESENT / GPIO31 TP23 T22
D6 PCH_RSMRST# 1 3

C
EC_RSMRST# 36
CH751H-40PT_SOD323-2

E
PCH_GPIO72 A6 BJ10
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5

B
2
R604 1 2 +3V
EC_SW I# F14 F6 PM_SLP_LAN# 10K_0402_5% R598 4.7K_0402_5%
36 EC_SW I# RI# SLP_LAN# / GPIO29
D20A

2
IBEXPEAK-M_FCBGA107 1
6
2
+3VS BAV99DW -7_SOT363

D20B
5

U44 4
2 EC_PW ROK 3
P

B EC_PW ROK 36,38


SYS_PW ROK 4 5
21 SYS_PW ROK Y

1
1 VGATE
A VGATE 12,53
G

BAV99DW -7_SOT363 R591


MC74VHC1G08DFT2G_SC70-5 2.2K_0402_5%
3

2
A A

SYS_PW ROK 1 2
R606 10K_0402_5%

EC_PW ROK 1
R632
2
10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
LAN_RST# 1
R617
2
10K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI, FDI, PM
No used Integrated LAN, Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
connecting LAN_RST# to GND DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 15 of 56
5 4 3 2 1
5 4 3 2 1

U41D
IGPU_BKLT_EN T48 BJ46
L_BKLTEN SDVO_TVCLKINN
28 PCH_ENVDD T47 L_VDD_EN SDVO_TVCLKINP BG46

D 28 DPST_PW M Y48 L_BKLTCTL SDVO_STALLN BJ48 D


SDVO_STALLP BG48
28 PCH_LCD_CLK PCH_LCD_CLK AB48
PCH_LCD_DATA L_DDC_CLK
28 PCH_LCD_DATA Y45 L_DDC_DATA SDVO_INTN BF45
SDVO_INTP BH45
LCTLA_CLK AB46
LCTLB_DATA L_CTRL_CLK
V48 L_CTRL_DATA SDVO_CTRLDATA strap Pull High at Level Shift Page
R166 1 UMA@ 2 LVDS_IBG AP39 T51
LVD_IBG SDVO_CTRLCLK SDVO_SCLK 30
2.37K_0402_1% AP41 T53
LVD_VBG SDVO_CTRLDATA SDVO_SDATA 30
R162 1 UMA@ 2 LVD_VREF AT43
0_0402_5% LVD_VREFH R171 1
AT42 LVD_VREFL DDPB_AUXN BG44 2 100K_0402_5%
DDPB_AUXP BJ44
AU38 PCH_DPB_HPD
DDPB_HPD PCH_DPB_HPD 30

LVDS
PCH_TXCLK- AV53
28 PCH_TXCLK- LVDSA_CLK#
PCH_TXCLK+ AV51 BD42 PCH_DPB_N0 C313 2 1 UMA ONLY@ 0.1U_0402_16V7K PCH_TMDS_D2# 30
+3VS 28 PCH_TXCLK+ LVDSA_CLK DDPB_0N
BC42 PCH_DPB_P0 C305 2 1 UMA ONLY@ 0.1U_0402_16V7K PCH_TMDS_D2 30 HDMI D2
PCH_TXOUT0- DDPB_0P PCH_DPB_N1 C320 UMA ONLY@ 0.1U_0402_16V7K
11/21 intel JIM suggest Pull high at LVDS Conn 28 PCH_TXOUT0- BB47 LVDSA_DATA#0 DDPB_1N BJ42 2 1 PCH_TMDS_D1# 30
PCH_TXOUT1- BA52 BG42 PCH_DPB_P1 C323 2 1 UMA ONLY@ 0.1U_0402_16V7K PCH_TMDS_D1 30 HDMI D1

Digital Display Interface


28 PCH_TXOUT1- LVDSA_DATA#1 DDPB_1P
PCH_TXOUT2- AY48 BB40 PCH_DPB_N2 C317 2 1 UMA ONLY@ 0.1U_0402_16V7K PCH_TMDS_D0# 30
28 PCH_TXOUT2- LVDSA_DATA#2 DDPB_2N
R130 1 @ 2 2.2K_0402_5% PCH_LCD_CLK AV47 BA40 PCH_DPB_P2 C314 2 1 UMA ONLY@ 0.1U_0402_16V7K PCH_TMDS_D0 30 HDMI D0
LVDSA_DATA#3 DDPB_2P PCH_DPB_N3 C327 UMA ONLY@ 0.1U_0402_16V7K
DDPB_3N AW38 2 1 PCH_TMDS_CK# 30
R131 1 @ 2 2.2K_0402_5% PCH_LCD_DATA PCH_TXOUT0+ BB48 BA38 PCH_DPB_P3 C325 2 1 UMA ONLY@ 0.1U_0402_16V7K PCH_TMDS_CK 30 HDMI CLK
28 PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P
PCH_TXOUT1+ BA50
28 PCH_TXOUT1+ LVDSA_DATA1
R132 1 2 10K_0402_5% LCTLA_CLK PCH_TXOUT2+ AY49
28 PCH_TXOUT2+ LVDSA_DATA2
AV48 LVDSA_DATA3 DDPC_CTRLCLK Y49
R133 1 2 10K_0402_5% LCTLB_DATA AB49
DDPC_CTRLDATA
C R546 1 2 2.2K_0402_5% PCH_CRT_CLK AP48 C
LVDSB_CLK#
AP47 LVDSB_CLK DDPC_AUXN BE44
R545 1 2 2.2K_0402_5% PCH_CRT_DATA BD44
DDPC_AUXP
AY53 LVDSB_DATA#0 DDPC_HPD AV40
AT49 LVDSB_DATA#1
AU52 LVDSB_DATA#2 DDPC_0N BE40
AT53 LVDSB_DATA#3 DDPC_0P BD40
DDPC_1N BF41
AY51 LVDSB_DATA0 DDPC_1P BH41
AT48 LVDSB_DATA1 DDPC_2N BD38
AU50 LVDSB_DATA2 DDPC_2P BC38
AT51 LVDSB_DATA3 DDPC_3N BB36
DDPC_3P BA36

08/20 add UMA@


1 2 PCH_CRT_B PCH_CRT_B AA52 U50
29 PCH_CRT_B CRT_BLUE DDPD_CTRLCLK
R551 UMA@ 150_0402_1% PCH_CRT_G AB53 U52
29 PCH_CRT_G CRT_GREEN DDPD_CTRLDATA
1 2 PCH_CRT_G PCH_CRT_R AD53
29 PCH_CRT_R CRT_RED
R552 UMA@ 150_0402_1%
1 2 PCH_CRT_R BC46
R553 UMA@ 150_0402_1% PCH_CRT_CLK DDPD_AUXN
29 PCH_CRT_CLK V51 CRT_DDC_CLK DDPD_AUXP BD46
PCH_CRT_DATA V53 AT38
29 PCH_CRT_DATA CRT_DDC_DATA DDPD_HPD

DDPD_0N BJ40
29 PCH_CRT_HSYNC Y53 CRT_HSYNC DDPD_0P BG40
29 PCH_CRT_VSYNC Y51 CRT_VSYNC DDPD_1N BJ38
DDPD_1P BG38

CRT
DDPD_2N BF37
CRT_IREF AD48 BH37
B ENBKL R135 1 UMA ONLY@ 0_0402_5% IGPU_BKLT_EN DAC_IREF DDPD_2P B
2 AB51 CRT_IRTN DDPD_3N BE36

UMA ONLY USE


REV1.0 DDPD_3P BD36
1

IBEXPEAK-M_FCBGA107
R134
1

100K_0402_5%
R143
1K_0402_0.5%
2

2/3 Change to 1K_0402_0.5% from Intel


2

Suggestion. (EDS 1.0 is incorrect)


ENBKL R103 1 DIS ONLY@
2 0_0402_5% VGA_BKL_EN

DIS ONLY USE

+5VS C472 SG@


U25 0.1U_0402_16V4Z
22 VGA_BKL_EN 2 1A VCC 8 1 2
A
IGPU_BKLT_EN 5 3 A
2A 1B ENBKL
17,28,29 DGPU_SELECT# 1 1OE# 2B 6 ENBKL 36
28 IGPU_SELECT# 7 2OE# GND 4

SN74CBTD3306CPW R_TSSOP8
SG@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS, CRT, DPI
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 16 of 56
5 4 3 2 1
5 4 3 2 1

U41E
+3VS +3VS
H40
N34
AD0 REV1.0 NV_CE#0 AY9
BD1
AD1 NV_CE#1 MC74VHC1G08DFT2G_SC70-5
C44 AD2 NV_CE#2 AP15

5
R160 1 2 8.2K_0402_5% PCI_PIRQA# A38 BD8 U42
R588 8.2K_0402_5% PCI_PIRQG# AD3 NV_CE#3 PLT_RST#
1 2 C36 2

P
R585 8.2K_0402_5% PCI_PIRQC# AD4 B
1 2 J34 AD5 NV_DQS0 AV9 Y 4 PLT_RST_BUF# 34
R158 1 2 8.2K_0402_5% PCI_SERR# A40 BG8 1 1
AD6 NV_DQS1 A

1
D45 C443
AD7 @ R621
E36 AP7

3
AD8 NV_DQ0 / NV_IO0 0.1U_0402_16V7K 100K_0402_5%
H48 AD9 NV_DQ1 / NV_IO1 AP6
2
E40 AD10 NV_DQ2 / NV_IO2 AT6
D C40 AT9 D

2
R554 8.2K_0402_5% PCI_PLOCK# AD11 NV_DQ3 / NV_IO3 +3VSDGPU
1 2 M48 AD12 NV_DQ4 / NV_IO4 BB1
R555 1 2 8.2K_0402_5% PCI_PERR# M45 AV6
R581 8.2K_0402_5% PCI_PIRQE# AD13 NV_DQ5 / NV_IO5
1 2 F53 AD14 NV_DQ6 / NV_IO6 BB3

5
R579 1 2 8.2K_0402_5% PCI_STOP# M40 BA4 U43
AD15 NV_DQ7 / NV_IO7

NVRAM
M43 BE4 2

P
AD16 NV_DQ8 / NV_IO8 B R619 1 DIS@
J36 AD17 NV_DQ9 / NV_IO9 BB6 Y 4 2 PLTRST_VGA# 22
K48 BD6 1 100_0402_5%
AD18 NV_DQ10 / NV_IO10 18,21 DGPU_HOLD_RST# A

1
F40 AD19 NV_DQ11 / NV_IO11 BB7
C42 BC8 MC74VHC1G08DFT2G_SC70-5 R622

3
R556 8.2K_0402_5% PCI_REQ0# AD20 NV_DQ12 / NV_IO12 DIS@ 100K_0402_5%
1 2 K46 AD21 NV_DQ13 / NV_IO13 BJ8
R557 1 2 8.2K_0402_5% PCI_PIRQB# M51 BJ6 DIS@
R559 8.2K_0402_5% PCI_PIRQF# AD22 NV_DQ14 / NV_IO14
1 2 J52 BG6

2
R560 8.2K_0402_5% PCI_REQ3# AD23 NV_DQ15 / NV_IO15
1 2 K51 AD24
L34 BD3 NV_ALE NV_ALE,NV_CLE
AD25 NV_ALE NV_CLE
F42 AY6
J40
AD26 NV_CLE has a weak internal pull-down
AD27
G46 AD28
R577 1 2 8.2K_0402_5% PCI_IRDY# F44 AU2 NV_RCOMP R660 1 @ 2 32.4_0402_1% +1.8VS
R574 8.2K_0402_5% PCI_PIRQD# AD29 NV_RCOMP
1 2 M47 AD30
Design Guide 1.5 Ver:

PCI
R572 1 2 8.2K_0402_5% DGPU_SELECT# H36 AV7
R153 8.2K_0402_5% PCI_DEVSEL# AD31 NV_RB# NV_ALE R233 1 @
1 2 3.26.13 Terminating Unused Braidwood Interface 2 1K_0402_5%
J50 C/BE0# NV_WR#0_RE# AY8
G42 C/BE1# NV_WR#1_RE# AY5 If not implemented, the dual channel NAND interface signals,
H47 NV_CLE R225 1 @ 2 1K_0402_5%
C/BE2# including NV_RCOMP, can be left as No Connect.
G34 C/BE3# NV_WE#_CK0 AV11
R568 1 2 8.2K_0402_5% PCI_FRAME# BF5
R570 8.2K_0402_5% PCI_REQ1# PCI_PIRQA# NV_WE#_CK1 Intel Anti-Theft Techonlogy
1 2 G38 PIRQA#
R565 1 2 8.2K_0402_5% PCI_PIRQH# PCI_PIRQB# H51 PIRQB#
C R566 1 2 8.2K_0402_5% PCI_TRDY# PCI_PIRQC# B37 PIRQC# USBP0N H18 USB20_N0
USB20_N0 35 High=Endabled C
PCI_PIRQD# A44 PIRQD# USBP0P J18 USB20_P0
USB20_P0 35 USB/B (Right Side) NV_ALE
PCI_GNT0#,PCI_GNT1#,PCI_GNT2#,PCI_GNT3# USB20_N1 Low=Disable(floating)
has a weak internal pull-up
PCI_REQ0# F51 REQ0#
USBP1N
USBP1P
A18
C18 USB20_P1
USB20_N1
USB20_P1
35
35 USB Port (Left Side) *
PCI_REQ1# A46 N20 USB20_N2
REQ1# / GPIO50 USBP2N USB20_N2 35
16,28,29 DGPU_SELECT#
DGPU_SELECT# B45 REQ2# / GPIO52 USBP2P P20 USB20_P2
USB20_P2 35 USB/B (Right Side) DMI Termination Voltage
PCI_REQ3# M53 J20
REQ3# / GPIO54 USBP3N
USBP3P L20 EHCI 1 Set to Vcc when HIGH
PCI_GNT0# F48 GNT0# USBP4N F20 NV_CLE
PCI_GNT1# K45 GNT1# / GPIO51 USBP4P G20 Set to Vss when LOW
DGPU_PW MSEL# F36 A20
28 DGPU_PW MSEL# GNT2# / GPIO53 USBP5N
PCI_GNT3# H53 C20
GNT3# / GPIO55 USBP5P
PCI_GNT2# ESI Strap (Server Only) USBP6N M22
PCI_PIRQE# B41 N22 2/10 USB6, USB7 not NV_ALE

this signal should not be pulled low PCI_PIRQF# K53
PIRQE# / GPIO2 USBP6P
B21 Enable Intel Anti-Theft
PCI_PIRQG# PIRQF# / GPIO3 USBP7N support on HM55
A36 PIRQG# / GPIO4 USBP7P D21 Technology 8.2K PU to +3VS
PCI_PIRQH# A48 H22 USB20_N8


PIRQH# / GPIO5 USBP8N USB20_N8 28
J22 USB20_P8
USB20_P8 28 CMOS Camera (LVDS) Disable Intel Anti-Theft
USBP8P

USB
@ TP_PCI_RST# K6 E22 USB20_N9 Technology floating(internal PD)
T12 PAD PCIRST# USBP9N USB20_N9 35
F22 USB20_P9 Card Reader
USBP9P USB20_P9 35
PCI_SERR# E44 A22 USB20_N10
USB20_N10 34
NV_CLE
PCI_PERR# SERR# USBP10N USB20_P10
E50 PERR# USBP10P C22 USB20_P10 34 Mini Card(SIM Card)
USBP11N G24 USB20_N11
USB20_N11 35
DMI termination voltage.
H24 USB20_P11 Bluetooth EHCI 2 weak internal PU, don't PD
USBP11P USB20_P11 35
PCI_IRDY# A42 L24 USB20_N12
IRDY# USBP12N USB20_N12 34
H44 M24 USB20_P12 Mini Card(WLAN)
PAR USBP12P USB20_P12 34
PCI_DEVSEL# F46 A24 USB20_N13
DEVSEL# USBP13N USB20_N13 34
PCI_FRAME# C46 C24 USB20_P13 Mini Card(WWAN)
FRAME# USBP13P USB20_P13 34
B PCI_PLOCK# B
D49 PLOCK#
B25 USB_BIAS 1 2
PCI_STOP# USBRBIAS# R191
D41 STOP#
PCI_TRDY# C48 D25 22.6_0402_1% USB_OC#0_R
TRDY# USBRBIAS USB_OC#0_R 21
M7 USB_OC#2_R
PME# USB_OC#2_R 21
N16 USB_OC#0_R R216 1 2 0_0402_5% (For USB Port0, 2)
OC0# / GPIO59 USB_OC#0 35
PLT_RST# D5 J16 USB_OC#1_R
5,21,32,36 PLT_RST# PLTRST# OC1# / GPIO40 USB_OC#1_R 21
F16 USB_OC#2_R R210 1 2 0_0402_5% (For USB Port1)
OC2# / GPIO41 USB_OC#2 35
N52 L16 USB_OC#3_R
CLKOUT_PCI0 OC3# / GPIO42 USB_OC#3_R 21
2008/1/6 2009MOW01 change to 22 ohm P53 E14 USB_OC#4_R
CLKOUT_PCI1 OC4# / GPIO43 USB_OC#4_R 21
P46 G16 USB_OC#5_R
CLKOUT_PCI2 OC5# / GPIO9 USB_OC#5_R 21
36 CLK_PCI_LPC R561 1 2 22_0402_5% CLK_PCI_LPC_R P51 F12 USB_OC#6_R RP1
CLKOUT_PCI3 OC6# / GPIO10 USB_OC#6_R 21
R142 1 2 22_0402_5% CLK_PCI_FB_R P48 T15 USB_OC#7_R USB_OC#3_R 1 8 +3V
14 CLK_PCI_FB CLKOUT_PCI4 OC7# / GPIO14 USB_OC#7_R 21
USB_OC#5_R 2 7
USB_OC#6_R 3 6
IBEXPEAK-M_FCBGA107 USB_OC#7_R 4 5
OC[0..3] use for EHCI 1
Boot BIOS Strap 10K_1206_8P4R_5%
OC[4..7] use for EHCI 2
PCI_GNT#0 PCI_GNT#1 Boot BIOS Location
0 0 LPC PCI_GNT0# R137 1 @ 2 1K_0402_5%
Have internal PU USB_OC#1_R R601 1 2 10K_0402_5%
0 1 Reserved (NAND)
PCI_GNT1# R159 1 @ 2 1K_0402_5% USB_OC#4_R R603 1 2 10K_0402_5%
1 0 PCI Have internal PU
1 1 SPI PCI_GNT3# R558 1 @ 2 1K_0402_5%
A * Have internal PU
A

A16 swap overide Strap/Top-Block


Swap Override jumper Security Classification Compal Secret Data Compal Electronics, Inc.
Low=A16 swap Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
override/Top-Block PCH (5/9) PCI, USB, VRAM
PCI_GNT3# Swap Override enabled THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
High=Default * Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 17 of 56
5 4 3 2 1
5 4 3 2 1

+3VS +3VS

R582 1 2 10K_0402_5% DGPU_EDIDSEL#


R583 1 2 10K_0402_5% DGPU_HPD_INT# EC_GA20 R654 1 2 10K_0402_5%
U41F
R655 1 2 10K_0402_5% VGA_PRSNT_R# EC_KBRST# R653 1 2 10K_0402_5%
R261 1 2 10K_0402_5% VGA_PRSNT_L# CRT_DET Y3 AH45
21 CRT_DET BMBUSY# / GPIO0 CLKOUT_PCIE6N
UMA ONLY@ AH46
DGPU_EDIDSEL# CLKOUT_PCIE6P
28 DGPU_EDIDSEL# C38 TACH1 / GPIO1
R238 1 2 10K_0402_5% PCH_GPIO22 DGPU_HPD_INT# D37
30 DGPU_HPD_INT# TACH2 / GPIO6
D
CLKOUT_PCIE7N AF48 D

MISC
R651 1 2 10K_0402_5% PCH_GPIO39 EC_SCI# J32 AF47
36 EC_SCI# TACH3 / GPIO7 CLKOUT_PCIE7P
DGPU_PWR_EN Pull Low at Page 43 EC_SMI# F10
36 EC_SMI# GPIO8
R264 1 @ 2 10K_0402_5% DGPU_PW R_EN
PCH_GPIO12 K9
(GPIO8 Have Internal Pull High,Should not be Pull-Low) U2 EC_GA20
LAN_PHY_PWR_CTRL / GPIO12 A20GATE EC_GA20 36
(GPIO15 Have Internal Pull Down) PCH_GPIO15 T7
R236 1 GPIO15
2 10K_0402_5% PCH_GPIO48
R658 1 2 10K_0402_5% PCH_TEMP_ALERT# 17,21 DGPU_HOLD_RST# DGPU_HOLD_RST# AA2 AM3
R155 1 SATA4GP / GPIO16 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLK_CPU_BCLK# 5
2 10K_0402_5% VGA_PW ROK
R161 1 2 DGPU_PW ROK_1 F38 AM1
50 VGA_PW ROK TACH0 / GPIO17 CLKOUT_BCLK0_P / CLKOUT_PCIE8P CLK_CPU_BCLK 5
0_0402_5%
R243 1 2 10K_0402_5% PCH_GPIO34 PCH_GPIO22 Y7 BG10
SCLOCK / GPIO22 PECI H_PECI 5

GPIO
R178 1 2 10K_0402_5% EC_SCI#
2009/09/07 GPIO24 pull high +3V PCH_GPIO24 H10 T1 EC_KBRST#
GPIO24 RCIN# EC_KBRST# 36
+3V (GPIO27 Have Internal Pull High) PCH_GPIO27 AB12 BE10
GPIO27 PROCPWRGD H_CPUPW RGD 5

CPU
R245 1 2 10K_0402_5% PCH_GPIO12 PCH_GPIO28 V13 BD10 THRMTRIP_PCH# 2 1 H_THERMTRIP#
21 PCH_GPIO28 GPIO28 THRMTRIP# H_THERMTRIP# 5
R246 1 2 10K_0402_5% EC_SMI# R221 56_0402_5%
PCH_GPIO34 M11 2 1 +1.05VS_PCH
R239 1 STP_PCI# / GPIO34
2 1K_0402_5% PCH_GPIO15 R220 56_0402_5%
10/7 Not Use PCH_GPIO15 PU 1K to +3V PCH_GPIO35 V6 2009/08/23
R242 1 @ SATACLKREQ# / GPIO35
2 10K_0402_5% PCH_GPIO24 Series resistor of 56±5%
14,21,38,42 DGPU_PW R_EN DGPU_PW R_EN AB7 BA22
R642 10K_0402_5% PCH_GPIO28 SATA2GP / GPIO36 TP1 Pull-up of 56±5% to VTT
1 2
R640 1 2 10K_0402_5% PCH_GPIO57
21 VGA_PRSNT_L#
VGA_PRSNT_L# AB13 AW22 (both these should be close to PCH)
R633 10K_0402_5% PCH_GPIO45 SATA3GP / GPIO37 TP2
1 2
C R630 1 2 10K_0402_5% RST_GATE VGA_PRSNT_R# V3 BB22 C
SLOAD / GPIO38 TP3
PCH_GPIO39 P3 AY45
SDATAOUT0 / GPIO39 TP4
R262 1 DIS@ 2 10K_0402_5% VGA_PRSNT_L# PCH_GPIO45 H3 AY46
PCIECLKRQ6# / GPIO45 TP5 MAINPW ON 44,45,47
R659 1 2 10K_0402_5% DGPU_HOLD_RST# 10 RST_GATE RST_GATE F1 AV43
PCIECLKRQ7# / GPIO46 TP6 R224

1
PCH_GPIO48 AB6 AV45 @ 330_0402_5% C
R154 1 @ SDATAOUT1 / GPIO48 TP7
2 10K_0402_5% DGPU_PW ROK_1 +1.05VS_PCH 1 2 2 Q14
PCH_TEMP_ALERT# AA4 AF13 B 2SC2411K_SOT23-3
21,36 PCH_TEMP_ALERT# SATA5GP / GPIO49 TP8
R229 1 2 10K_0402_5% PCH_GPIO35 E
@

3
PCH_GPIO57 F8 M18
R263 1 @ GPIO57 TP9
2 10K_0402_5% PCH_GPIO27
GPIO27 (Have internal Pull-High) N18 H_THERMTRIP#
TP10
High: VCCVRM VR Enable A4 AJ24
VSS_NCTF_1 TP11
Low: VCCVRM VR Disable GPIO19 GPIO37 A49

NCTF
VSS_NCTF_2

RSVD
A5 VSS_NCTF_3 TP12 AK41
+3VS PCH_GPIO19 VGA_PRSNT_L# A50 VSS_NCTF_4
A52 VSS_NCTF_5 TP13 AK42
dGPU 0 0 A53 VSS_NCTF_6
2

B2 VSS_NCTF_7 TP14 M32


R656
10K_0402_5%
iGPU 0 1 B4
B52
VSS_NCTF_8
N32
VSS_NCTF_9 TP15
High: CRT Plugged * SG 1 0 B53 VSS_NCTF_10
BE1 M30
1

CRT_DET VSS_NCTF_11 TP16


BE53 VSS_NCTF_12
D BF1 VSS_NCTF_13 TP17 N30
1

B B
BF53 VSS_NCTF_14
2 Q20 BH1 H12
29 CRT_DET# VSS_NCTF_15 TP18
G @ BH2
2N7002E-T1-GE3_SOT23-3 VSS_NCTF_16
S BH52 AA23
3

VSS_NCTF_17 TP19
BH53 VSS_NCTF_18
BJ1 VSS_NCTF_19 NC_1 AB45
BJ2 VSS_NCTF_20
GPIO8 BJ4 AB38
VSS_NCTF_21 NC_2
This signal has a weak internal pull up BJ49 VSS_NCTF_22
can't Pull low BJ5 VSS_NCTF_23 NC_3 AB42
BJ50 VSS_NCTF_24
BJ52 VSS_NCTF_25 NC_4 AB41
GPIO27 BJ53 VSS_NCTF_26
On-Die PLL Voltage Regulator D1 VSS_NCTF_27 NC_5 T39
This signal has a weak internal pull up D2 INIT3_3V
::On-Die
VSS_NCTF_28
D53 VSS_NCTF_29 2009/08/23
H voltage regulator enable This signal has weak internal
* L On-Die PLL Voltage Regulator disable
E1
E53
VSS_NCTF_30
VSS_NCTF_31
INIT3_3V# P6 (Have internal PH,Do not pull down)
PH, can't pull low
TP24_SST @
REV1.0 TP24 C10 PAD T21
Note: the internal pull-up is disabled IBEXPEAK-M_FCBGA107
after RSMRST# de-asserts.
The On-Die PLL voltage regulator is enabled
when sampled high. When sampled low the
On-Die PLL Voltage Regulator is disabled.


A A
GPIO15
L Intel ME Crypto Transport
* Layer Security(TLS) chiper suite


with no confidentiality
H Intel ME Crypto Transport
Layer Security(TLS) chiper suite
Security Classification Compal Secret Data Compal Electronics, Inc.
with confidentiality Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
CRB has a 1-k pull-up on this signal AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
to +3.3VA rail. DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 18 of 56
5 4 3 2 1
5 4 3 2 1
Need Modify
180 ohm @
100MHz Bead

+1.05VS_VTT
+1.05VS_PCH +3VS
60mA
J1
10U_0805_10V4Z 1U_0402_6.3V4Z
U41G POWER +VCCADAC
15mil 0.01U_0402_16V7K 22U_0805_6.3V6M 22U_0805_6.3V6M
2 2 1 1 AB24 VCCCORE[1] VCCADAC[1] AE50 1 2
1 1 AB26 1 1 1 1 L19
VCCCORE[2]

1
D @ JUMP_43X118 AB28 69mA AE52 C296 C298 MBK1608221YZF_2P D
C718 C344 VCCCORE[3] VCCADAC[2] R136 C291 C476
AD26 VCCCORE[4]1524mA 220 ohm bead,350mA

CRT
AD28 AF53 0_0402_5% 0.1U_0402_16V4Z
2 2 VCCCORE[5] VSSA_DAC[1] @ 2 2 2 2
AF26 VCCCORE[6]

VCC CORE
Short J4 for PCH VCCCORE AF28 AF51 Near AE50

2
VCCCORE[7] VSSA_DAC[2] +3VS
Near AB24 Near AB24 AF30 VCCCORE[8] CRB 0.9 is 180 ohm @ 100MHz
AF31 VCCCORE[9] DG0.8 is 600 ohm FB (Page 290)
Top Side AH26 20mil
VCCCORE[10] +VCCA_LVDS R138 1 UMA@ 2 0_0805_5%
AH28 VCCCORE[11]
AH30 VCCCORE[12] 300mA

1
Intel suggest follow CRB 8/21 AH31 VCCCORE[13] VCCALVDS AH38
AJ30 R172
VCCCORE[14] 0_0402_5%
AJ31 VCCCORE[15] VSSA_LVDS AH39
All Ibex Peak-M Power rails with netnames +1.1VS and DIS ONLY@
59mA

2
+1.1V rails are actually +1.05VS and +1.05V rails +1.05VS_PCH AP43 +1.8VS
VCCTX_LVDS[1]
VCCTX_LVDS[2] AP45 15mil L20 UMA@
AT46 Near AP43

LVDS
VCCTX_LVDS[3] +VCCTX_LVDS C300
AK24 VCCIO[24] VCCTX_LVDS[4] AT45 2 1
C316 1 1 UMA@ 1 0.1UH_MLF1608DR10KT_10%_1608
42mA 0.01U_0402_16V7K 22U_0805_6.3V6M 0.1uH inductor, 200mA
10mil @ +VCCAPLL_EXP BJ24 C304
T20 PAD VCCAPLLEXP
AB34 UMA@ 0.01U_0402_16V7K 1 2
VCC3_3[2] 2 UMA@ 2 2 R145 DIS ONLY@
DG 1.6 (Page 329)
Have Internal VRM AN20 AB35 0_0402_5%
VCCIO[25] VCC3_3[3]
AN22

HVCMOS
VCCIO[26]
AN23 VCCIO[27] VCC3_3[4] AD35 +3VS
AN24 VCCIO[28]
AN26 VCCIO[29] 1
C AN28 C331 C
VCCIO[30]
BJ26 VCCIO[31]
BJ28 0.1U_0402_16V4Z Near AB34
VCCIO[32] 2
AT26 VCCIO[33]
AT28 R186 1 @ 2 0_0805_5% +1.05VS_PCH
VCCIO[34]
AU26 VCCIO[35]
+1.05VS_PCH +VCCVRM
AU28 VCCIO[36] 40mil
AV26 VCCIO[37] 35mA R192 1
Near AN20 AV28 VCCIO[38] VCCVRM[2] AT24 2 0_0805_5% +1.8VS
10U_0805_10V4Z 1U_0402_6.3V4Z 1U_0402_6.3V4Z AW26 3208mA
VCCIO[39]
1 1 1 1 1 AW28 VCCIO[40] 61mA +1.05VS_PCH

DMI
C719 C321 C342 C345 C348
BA26 VCCIO[41] VCCDMI[1] AT16 10mil
BA28 VCCIO[42]
BB26 AU16 +VCC_DMI R204 1 2 0_0805_5%
2 2 2 2 2 VCCIO[43] VCCDMI[2]
BB28 VCCIO[44] 1
Top Side BC26 VCCIO[45]

PCI E*
1U_0402_6.3V4Z 1U_0402_6.3V4Z BC28 C368
VCCIO[46] 1U_0402_6.3V4Z
BD26 VCCIO[47] 2
BD28 VCCIO[48] 156mA
BE26 VCCIO[49] VCCPNAND[1] AM16 Near AT16
BE28 VCCIO[50] VCCPNAND[2] AK16
BG26 VCCIO[51] VCCPNAND[3] AK20
BG28 VCCIO[52] VCCPNAND[4] AK19
BH27 VCCIO[53] VCCPNAND[5] AK15
AK13 +1.8VS
+3VS VCCPNAND[6]
Follow Intel suggestion 8/21 AN30 VCCIO[54] VCCPNAND[7] AM12
Near AN35
NAND / SPI
AN31 VCCIO[55] VCCPNAND[8] AM13
VCCPNAND[9] AM15
0.1U_0402_16V4Z 1
B C329 2 C372 B
1 AN35 VCC3_3[1]
0.1U_0402_16V4Z
2
+VCCVRM AT22 VCCVRM[1]
@ +VCCAPLL_FDI
85mA Near AK13
10mil DG 1.6 (Page 329) T9 PAD BJ18 VCCFDIPLL 6mA VCCME3_3[1] AM8
Have Internal VRM AM9 +3VS
VCCME3_3[2]
FDI

+1.05VS_PCH AM23 VCCIO[1] VCCME3_3[3] AP11


VCCME3_3[4] AP9
1
C387
REV1.0
IBEXPEAK-M_FCBGA107 0.1U_0402_16V4Z
2
Near AM8

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Friday, December 18, 2009 Sheet 19 of 56
5 4 3 2 1
5 4 3 2 1

U41J POWER
@ +1.1VS_VCCACLK
10mil
AP51
52mA REV1.0 V24
T17 PAD VCCACLK[1] VCCIO[5] +1.05VS_PCH
VCCIO[6] V26 1 09/09/14 WW37 remove
DG 1.6 (Page 329) AP53 Y24 +1.05VS_PCH +VCCADPLLA
VCCACLK[2] VCCIO[7] C340
+VCCADPLLA,+VCCADPLLB external 1U
Have Internal VRM VCCIO[8] Y26
344mA 1U_0402_6.3V4Z
+1.05VS_PCH 2
AF23 VCCLAN[1] VCCSUS3_3[1] V28
+3V L60
Near BB51
R187 1 @
15mil +VCCLAN VCCSUS3_3[2] U28 Near V24 1 2
10UH_LB2012T100MR_20%
2 AF24 VCCLAN[2] VCCSUS3_3[3] U26
0_0603_5% 1 U24 10uH inductor, 120mA 1 1
VCCSUS3_3[4]

1
P28 1 1 R562
VCCSUS3_3[5]

1
R199 C352 +PCH_VCCD6W C350 C347 + C691 0_0402_5%
D
0_0402_5% 1U_0402_6.3V4Z
10mil Y20 DCPSUSBYP VCCSUS3_3[6] P26
C688 @ @
D
1 VCCSUS3_3[7] N28
@ 2 C367 0.1U_0402_16V4Z 0.1U_0402_16V4Z 220U_B2_2.5VM_R35 2
1998mA VCCSUS3_3[8] N26
2 2 2 1U_0402_6.3V4Z
Near AF23 AD38 M28

2
0.1U_0402_16V4Z VCCME[1] VCCSUS3_3[9]
M26 Near A26 Near U23

2
2 VCCSUS3_3[10] +VCCADPLLB
AD39 L28

USB
VCCME[2] VCCSUS3_3[11]
Near Y20 VCCSUS3_3[12] L26
DG2.0 Table162 Note2 (C295 unpop) AD41 VCCME[3] VCCSUS3_3[13] J28
J26 L61 1 2
+1.05VS_PCH VCCSUS3_3[14] 10UH_LB2012T100MR_20%
Follow Intel suggestion AF43 VCCME[4] VCCSUS3_3[15] H28
VCCSUS3_3[16] H26 10uH inductor, 120mA 1 1
22U_0805_6.3V6M AF41 163mA G28 C692
VCCME[5] VCCSUS3_3[17] + 1U_0402_6.3V4Z
1 1 1 1 1 VCCSUS3_3[18] G26
@ AF42 F28 C689 @
C293 C294 C341 C295 C324 VCCME[6] VCCSUS3_3[19] 220U_B2_2.5VM_R35 2
VCCSUS3_3[20] F26
22U_0805_6.3V6M 1U_0402_6.3V4Z +3V 2
2 2 2 2 2
V39 VCCME[7] VCCSUS3_3[21] E28 Near BD51
E26

Clock and Miscellaneous


VCCSUS3_3[22] D5
V41 VCCME[8] VCCSUS3_3[23] C28

2
22U_0805_6.3V6M Near AD38 1U_0402_6.3V4Z Near V39 C26 CH751H-40PT_SOD323-2
VCCSUS3_3[24]
V42 VCCME[9] VCCSUS3_3[25] B27
VCCSUS3_3[26] A28
Y39 VCCME[10] VCCSUS3_3[27] A26
+1.05VS_PCH
All Ibex Peak-M Power rails with netnames +1.1VS and

1
Y41 U23 2/12 Follow EDS1.11 +3VS
+1.1V rails are actually +1.05VS and +1.05V rails VCCME[11] VCCSUS3_3[28]
Change to 100 ohm +5V
Y42 VCCME[12] VCCIO[56] V23 10mil

2
10mil R189 D4
Near V9 C390 10mil >1mA F24 +VCC5REFSUS 1 2 100_0402_5% CH751H-40PT_SOD323-2
0.1U_0402_16V4Z V5REF_SUS
C 1 2 +VCCRTCEXT V9 2 1 C349 2/12 Follow EDS1.11 C
DCPRTC 1U_0402_6.3V6K R141
10mil Change to 100 ohm

1
>1mA Near F24 100_0402_5%
K49 +VCC5REF 1 2 +5VS
V5REF
+VCCVRM AU24 VCCVRM[3] Change to 1U for power

PCI/GPIO/LPC
357mA 2 1 C299
sequence issue on ICH9 1U_0402_6.3V6K
20mil 72mA VCC3_3[8] J38
+VCCADPLLA BB51 VCCADPLLA[1] Near K49
BB53 VCCADPLLA[2] VCC3_3[9] L38
+3VS
20mil 73mA VCC3_3[10] M36
+VCCADPLLB BD51 VCCADPLLB[1]
+1.05VS_PCH BD53 N36
VCCADPLLB[2] VCC3_3[11]
Near AH23 C337
1
AH23 VCCIO[21] VCC3_3[12] P36 Near J38
AJ35 VCCIO[22]
1 1 Near AF32 AH35 U35 0.1U_0402_16V4Z
C351 VCCIO[23] VCC3_3[13] 2 +3VS
C330 1 2 +PCH_VCCIO AF34
1U_0402_6.3V4Z 1U_0402_6.3V4Z R139 0_0603_5% VCCIO[2]
2 2 VCC3_3[14] AD13 Near AD13
2 1 AH34 VCCIO[3]
Near AH35 C336 1 2 C376
1U_0402_6.3V4Z AF32 32mA 10mil 0.1U_0402_16V4Z
VCCIO[4]
VCCSATAPLL[1] AK3
10mil 1 2 +VCCSST V12 AK1 +VCCSATAPLL @ PAD T23
C375 DCPSST VCCSATAPLL[2]
0.1U_0402_16V4Z
Near V12
DG 1.6 (Page 329)
+1.05VS_PCH Have Internal VRM
10mil 1 2 +VCCSUS Y22
B C353 DCPSUS B
+3V 0.1U_0402_16V4Z
Near Y22 VCCIO[9] AH22

P18 VCCSUS3_3[29] VCCVRM[4] AT20 +VCCVRM


1
C369 U19
SATA

VCCSUS3_3[30] +1.05VS_PCH
PCI/GPIO/LPC

VCCIO[10] AH19
0.1U_0402_16V4Z U20
2 VCCSUS3_3[31]
VCCIO[11] AD20
Near P18 U22 VCCSUS3_3[32] +5VALW
VCCIO[12] AF22 1
+3VS
AD19 C371
VCCIO[13] 1U_0402_6.3V4Z R176
V15 VCC3_3[5] VCCIO[14] AF20

1
2 0_0402_5% S Q8
1 VCCIO[15] AF19
C370 V16 AH20 Near AB19 42 SBPW R_EN# 2 @ 1 2 R169
VCC3_3[6] VCCIO[16] G @ 0_0402_5%
0.1U_0402_16V4Z Y16 AB19 1 D

1
2 VCC3_3[7] VCCIO[17] C343 AO3413L_SOT23-3
AB20

2
+1.05VS_PCH VCCIO[18] +1.05VS_PCH @
Near V15 VCCIO[19] AB22
0.1U_0402_16V4Z
> 1mA VCCIO[20] AD22 15mil 2
AT18 V_CPU_IO[1]
1 1 1 AA34 PCH_VCCME13 R179 1 2 0_0603_5% +5V
CPU

C364 C359 C360 VCCME[13] PCH_VCCME14 R164 0_0603_5%


VCCME[14] Y34 1 2
AU18 Y35 PCH_VCCME15 R165 1 2 0_0603_5%
4.7U_0805_10V4Z 0.1U_0402_16V4Z V_CPU_IO[2] VCCME[15] PCH_VCCME16 R173 0_0603_5%
VCCME[16] AA35 1 2
2 2 2
0.1U_0402_16V4Z Near AT18 2mA 6mA
RTC

A A12 VCCRTC VCCSUSHDA L30 +3V A


HDA

C357 1 2 1U_0402_6.3V4Z
20mil IBEXPEAK-M_FCBGA107
+RTCVCC Near L30
1 1 1
C386 C377
C373 Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2009/08/01 2010/08/01 Title
2 2 2 Issued Date Deciphered Date
1U_0402_6.3V4Z
Near A12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (8/9) PWR
0.1U_0402_16V4Z Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 20 of 56
5 4 3 2 1
5 4 3 2 1

U41I U41H
AY7
B11
VSS[159] VSS[259] H49
H5
AB16 VSS[0] PCH XDP Port
VSS[160] VSS[260]
B15 VSS[161] VSS[261] J24 AA19 VSS[1] VSS[80] AK30
B19 VSS[162] VSS[262] K11 AA20 VSS[2] VSS[81] AK31
B23 VSS[163] VSS[263] K43 AA22 VSS[3] VSS[82] AK32
B31 K47 AM19 AK34 R314 1 @ 2 33_0402_5% XDP_FN0
VSS[164] VSS[264] VSS[4] VSS[83] 17 USB_OC#0_R
B35 VSS[165] VSS[265] K7 AA24 VSS[5] VSS[84] AK35
B39 L14 AA26 AK38 R311 1 @ 2 33_0402_5% XDP_FN2
VSS[166] VSS[266] VSS[6] VSS[85] 17 USB_OC#2_R
B43 VSS[167] VSS[267] L18 AA28 VSS[7] VSS[86] AK43
B47 L2 AA30 AK46 R306 1 @ 2 33_0402_5% XDP_FN4
VSS[168] VSS[268] VSS[8] VSS[87] 17 USB_OC#4_R
B7 VSS[169] VSS[269] L22 AA31 VSS[9] VSS[88] AK49
D BG12 VSS[170] VSS[270] L32 AA32 VSS[10] VSS[89] AK5 D
BB12 VSS[171] VSS[271] L36 AB11 VSS[11] VSS[90] AK8
BB16 L40 AB15 AL2 R312 1 @ 2 33_0402_5% XDP_FN8
VSS[172] VSS[272] VSS[12] VSS[91] 14 PCH_GPIO20
BB20 L52 AB23 AL52 R310 1 @ 2 33_0402_5% XDP_FN9
VSS[173] VSS[273] VSS[13] VSS[92] 14 PCH_GPIO18
BB24 M12 AB30 AM11 R309 1 @ 2 33_0402_5% XDP_FN10
VSS[174] VSS[274] VSS[14] VSS[93] 13 PCH_GPIO21
BB30 M16 AB31 BB44 R307 1 @ 2 33_0402_5% XDP_FN11
VSS[175] VSS[275] VSS[15] VSS[94] 13 PCH_GPIO19
BB34 M20 AB32 AD24 R305 1 @ 2 33_0402_5% XDP_FN12
VSS[176] VSS[276] VSS[16] VSS[95] 14,18,38,42 DGPU_PW R_EN
BB38 N38 AB39 AM20 R304 1 @ 2 33_0402_5% XDP_FN13
VSS[177] VSS[277] VSS[17] VSS[96] 18 VGA_PRSNT_L#
BB42 M34 AB43 AM22 R300 1 @ 2 33_0402_5% XDP_FN14
VSS[178] VSS[278] VSS[18] VSS[97] 17,18 DGPU_HOLD_RST#
BB49 M38 AB47 AM24 R297 1 @ 2 33_0402_5% XDP_FN15
VSS[179] VSS[279] VSS[19] VSS[98] 18,36 PCH_TEMP_ALERT#
BB5 VSS[180] VSS[280] M42 AB5 VSS[20] VSS[99] AM26
BC10 M46 AB8 AM28 R313 1 @ 2 33_0402_5% XDP_FN17
VSS[181] VSS[281] VSS[21] VSS[100] 18 CRT_DET
BC14 VSS[182] VSS[282] M49 AC2 VSS[22] VSS[101] BA42
BC18 VSS[183] VSS[283] M5 AC52 VSS[23] VSS[102] AM30
BC2 M8 AD11 AM31 R287 1 2 0_0402_5% PCH_JTAG_TCK_R
VSS[184] VSS[284] VSS[24] VSS[103] 13 PCH_JTAG_TCK
BC22 N24 AD12 AM32 R284 1 2 0_0402_5% PCH_JTAG_TMS_R
VSS[185] VSS[285] VSS[25] VSS[104] 13 PCH_JTAG_TMS
BC32 P11 AD16 AM34 R286 1 2 0_0402_5% PCH_JTAG_TDI_R
VSS[186] VSS[286] VSS[26] VSS[105] 13 PCH_JTAG_TDI
BC36 AD15 AD23 AM35 13 PCH_JTAG_TDO R293 1 2 PCH_JTAG_TDO_R
VSS[187] VSS[287] VSS[27] VSS[106] 0_0402_5%
BC40 VSS[188] VSS[288] P22 AD30 VSS[28] VSS[107] AM38
BC44 P30 AD31 AM39 R289 1 @ 2 0_0402_5% PCH_JTAG_RST#_R
VSS[189] VSS[289] VSS[29] VSS[108] 13 PCH_JTAG_RST#
BC52 VSS[190] VSS[290] P32 AD32 VSS[30] VSS[109] AM42
BH9 VSS[191] VSS[291] P34 AD34 VSS[31] VSS[110] AU20
BD48 VSS[192] VSS[292] P42 AU22 VSS[32] VSS[111] AM46
BD49 VSS[193] VSS[293] P45 AD42 VSS[33] VSS[112] AV22
BD5 P47 AD46 AM49 JP3
VSS[194] VSS[294] VSS[34] VSS[113]
BE12 R2 AD49 AM7 1 2 (XDP_FN16)
VSS[195] VSS[295] VSS[35] VSS[114] GND0 GND1
BE16 VSS[196] VSS[296] R52 AD7 VSS[36] VSS[115] AA50 3 OBSFN_A0 OBSFN_C0 4 PCH_GPIO28 18
BE20 T12 AE2 BB10 5 6 XDP_FN17
VSS[197] VSS[297] VSS[37] VSS[116] OBSFN_A1 OBSFN_C1
BE24 VSS[198] VSS[298] T41 AE4 VSS[38] VSS[117] AN32 7 GND2 GND3 8
C BE30 T46 AF12 AN50 XDP_FN0 9 10 XDP_FN8 C
VSS[199] VSS[299] VSS[39] VSS[118] (XDP_FN1) 17 USB_OC#1_R OBSDATA_A0 OBSDATA_C0 XDP_FN9
BE34 VSS[200] VSS[300] T49 Y13 VSS[40] VSS[119] AN52 11 OBSDATA_A1 OBSDATA_C1 12
BE38 VSS[201] VSS[301] T5 AH49 VSS[41] VSS[120] AP12 13 GND4 GND5 14
BE42 T8 AU4 AP42 XDP_FN2 15 16 XDP_FN10
VSS[202] VSS[302] VSS[42] VSS[121] (XDP_FN3) 17 USB_OC#3_R OBSDATA_A2 OBSDATA_C2 XDP_FN11
BE46 VSS[203] VSS[303] U30 AF35 VSS[43] VSS[122] AP46 17 OBSDATA_A3 OBSDATA_C3 18
BE48 VSS[204] VSS[304] U31 AP13 VSS[44] VSS[123] AP49 19 GND6 GND7 20
BE50 VSS[205] VSS[305] U32 AN34 VSS[45] VSS[124] AP5 21 OBSFN_B0 OBSFN_D0 22
BE6 VSS[206] VSS[306] U34 AF45 VSS[46] VSS[125] AP8 23 OBSFN_B1 OBSFN_D1 24
BE8 VSS[207] VSS[307] P38 AF46 VSS[47] VSS[126] AR2 25 GND8 GND9 26
BF3 V11 AF49 AR52 XDP_FN4 27 28 XDP_FN12
VSS[208] VSS[308] VSS[48] VSS[127] (XDP_FN5) 17 USB_OC#5_R OBSDATA_B0 OBSDATA_D0 XDP_FN13
BF49 VSS[209] VSS[309] P16 AF5 VSS[49] VSS[128] AT11 29 OBSDATA_B1 OBSDATA_D1 30
BF51 VSS[210] VSS[310] V19 AF8 VSS[50] VSS[129] BA12 31 GND10 GND11 32
BG18 V20 AG2 AH48 (XDP_FN6) 17 USB_OC#6_R 33 34 XDP_FN14
VSS[211] VSS[311] VSS[51] VSS[130] (XDP_FN7) 17 USB_OC#7_R OBSDATA_B2 OBSDATA_D2 XDP_FN15
BG24 VSS[212] VSS[312] V22 AG52 VSS[52] VSS[131] AT32 35 OBSDATA_B3 OBSDATA_D3 36
BG4 VSS[213] VSS[313] V30 AH11 VSS[53] VSS[132] AT36 37 GND12 GND13 38
BG50 V31 AH15 AT41 39 40 +3VS
VSS[214] VSS[314] VSS[54] VSS[133] 15 SYS_PW ROK PWRGOOD/HOOK0 ITPCLK/HOOK4
BH11 VSS[215] VSS[315] V32 AH16 VSS[55] VSS[134] AT47 5,15,36 PBTN_OUT# 1 2 41 HOOK1 ITPCLK#/HOOK5 42
BH15 V34 AH24 AT7 +3VS R296 0_0402_5% 43 44
VSS[216] VSS[316] VSS[56] VSS[135] VCC_OBS_AB VCC_OBS_CD
BH19 VSS[217] VSS[317] V35 AH32 VSS[57] VSS[136] AV12 45 HOOK2 RESET#/HOOK6 46 2 1 PLT_RST# 5,17,32,36
BH23 V38 AV18 AV16 47 48 R295 XDP_DBRESET# 5,15
VSS[218] VSS[318] VSS[58] VSS[137] HOOK3 DBR#/HOOK7 1K_0402_5%
BH31 VSS[219] VSS[319] V43 AH43 VSS[59] VSS[138] AV20 49 GND14 GND15 50
BH35 V45 AH47 AV24 51 52 PCH_JTAG_TDO_R
VSS[220] VSS[320] VSS[60] VSS[139] 5 SMB_DATA_S3 SDA TD0
BH39 V46 AH7 AV30 53 54 PCH_JTAG_RST#_R
VSS[221] VSS[321] VSS[61] VSS[140] 5 SMB_CLK_S3 SCL TRST#
BH43 V47 AJ19 AV34 55 56 PCH_JTAG_TDI_R
VSS[222] VSS[322] VSS[62] VSS[141] PCH_JTAG_TCK_R TCK1 TDI PCH_JTAG_TMS_R
BH47 VSS[223] VSS[323] V49 AJ2 VSS[63] VSS[142] AV38 57 TCK0 TMS 58
BH7 VSS[224] VSS[324] V5 AJ20 VSS[64] VSS[143] AV42 59 GND16 GND17 60
C12 VSS[225] VSS[325] V7 AJ22 VSS[65] VSS[144] AV46
C50 V8 AJ23 AV49 CONN@ SAMTE_BSH-030-01-L-D-A
VSS[226] VSS[326] VSS[66] VSS[145]
D51 VSS[227] VSS[327] W2 AJ26 VSS[67] VSS[146] AV5
B B
E12 VSS[228] VSS[328] W52 AJ28 VSS[68] VSS[147] AV8
E16 VSS[229] VSS[329] Y11 AJ32 VSS[69] VSS[148] AW14
E20 VSS[230] VSS[330] Y12 AJ34 VSS[70] VSS[149] AW18
E24 VSS[231] VSS[331] Y15 AT5 VSS[71] VSS[150] AW2
E30 VSS[232] VSS[332] Y19 AJ4 VSS[72] VSS[151] BF9
E34 VSS[233] VSS[333] Y23 AK12 VSS[73] VSS[152] AW32
E38 Y28 AM41 AW36 +3VS R294
VSS[234] VSS[334] VSS[74] VSS[153] @
E42 VSS[235] VSS[335] Y30 AN19 VSS[75] VSS[154] AW40
E46 Y31 AK26 AW52 4.7K_0402_5%
VSS[236] VSS[336] VSS[76] VSS[155]

2
E48 VSS[237] VSS[337] Y32 AK22 VSS[77] VSS[156] AY11 1 2 +3VS
E6 VSS[238] VSS[338] Y38 AK23 VSS[78] VSS[157] AY43
SMB_DATA_S3
E8
F49
VSS[239] VSS[339] Y43
Y46
AK28 VSS[79] REV1.0 VSS[158] AY47 12,14,34 PCH_SMBDATA 6 1
VSS[240] VSS[340] IBEXPEAK-M_FCBGA107 Q21A
F5 VSS[241] VSS[341] P49
G10 Y5 2N7002DW H_SOT363-6
VSS[242] VSS[342] @
G14 VSS[243] VSS[343] Y6
G18 Y8 +3VS R290
VSS[244] VSS[344] @
G2 VSS[245] VSS[345] P24
G22 T43 4.7K_0402_5%
VSS[246] VSS[346]

5
G32 VSS[247] VSS[347] AD51 1 2 +3VS
G36 VSS[248] VSS[348] AT8
G40 AD47 12,14,34 PCH_SMBCLK 3 4 SMB_CLK_S3
VSS[249] VSS[349]
G44 VSS[250] VSS[350] Y47
G52 AT12 Q21B
VSS[251] VSS[351] 2N7002DW H_SOT363-6
AF39 VSS[252] VSS[352] AM6
H16 AT13 @
VSS[253] VSS[353]
H20 VSS[254] VSS[354] AM5
H30 VSS[255] VSS[355] AK45
A H34 VSS[256] VSS[356] AK39 A
H38 VSS[257] VSS[366] AV14
H42 VSS[258]

REV1.0
IBEXPEAK-M_FCBGA107 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS & PCH XDP Port
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 21 of 56
5 4 3 2 1
A B C D E

U51A

4 PEG_HTX_C_GRX_P0 AP17 Part 1 of 7 K1 GPIO I/O ACTIVE USAGE


PEX_RX0 GPIO0 @
4 PEG_HTX_C_GRX_N0 AN17 K2 VGA_HDMI_DET 30 2 1 +3VSDGPU
PEX_RX0_N GPIO1 R741 2.2K_0402_5%
4 PEG_HTX_C_GRX_P1 AN19 K3 VGA_PNL_PWM 28
PEX_RX1 GPIO2
4 PEG_HTX_C_GRX_N1 AP19 PEX_RX1_N GPIO3 H3 ENVDD 28 GPIO0 IN N/A N/A
4 PEG_HTX_C_GRX_P2 AR19 H2 VGA_BKL_EN 16
PEX_RX2 GPIO4
4 PEG_HTX_C_GRX_N2 AR20 H1 GPU_VID0 50
PEX_RX2_N GPIO5 @
4 PEG_HTX_C_GRX_P3 AP20 PEX_RX3 GPIO6 H4 GPU_VID1 50 2
R742
1
2.2K_0402_5%
+3VSDGPU GPIO1 IN H HDMI Hot-plug
4 PEG_HTX_C_GRX_N3 AN20 H5
PEX_RX3_N GPIO7
4 PEG_HTX_C_GRX_P4 AN22 PEX_RX4 GPIO8 H6 1 DIS@ 2 +3VSDGPU
4 PEG_HTX_C_GRX_N4 AP22 J7 R7431 DIS@ 10K_0402_5%
2 GPIO2 OUT H VGA_PNL_PWM
PEX_RX4_N GPIO9 R744 10K_0402_5%
4 PEG_HTX_C_GRX_P5 AR22 K4
PEX_RX5 GPIO10
4 PEG_HTX_C_GRX_N5 AR23 PEX_RX5_N GPIO11 K5 1 DIS@ 2
AP23 H7 R745 10K_0402_5% GPIO3 OUT H ENVDD

GPIO
4 PEG_HTX_C_GRX_P6 PEX_RX6 GPIO12
1 4 PEG_HTX_C_GRX_N6 AN23 J4 1
PEX_RX6_N GPIO13
4 PEG_HTX_C_GRX_P7 AN25 PEX_RX7 GPIO14 J6 1 DIS@ 2
4 PEG_HTX_C_GRX_N7 AP25 L1 R746 10K_0402_5% GPIO4 OUT H VGA_BKL_EN
PEX_RX7_N GPIO15
4 PEG_HTX_C_GRX_P8 AR25 L2
PEX_RX8 GPIO16 Q54 2N7002_SOT23
4 PEG_HTX_C_GRX_N8 AR26 PEX_RX8_N GPIO17 L4

D
4 PEG_HTX_C_GRX_P9 AP26
PEX_RX9 GPIO18
M4 3 1 VGA_idle 36 GPIO5 OUT N/A NVVDD VID0
4 PEG_HTX_C_GRX_N9 AN26 PEX_RX9_N GPIO19 L7
4 PEG_HTX_C_GRX_P10 AN28 L5 DIS@
PEX_RX10 GPIO20
GPIO6 OUT N/A NVVDD VID1

G
4 PEG_HTX_C_GRX_N10 AP28 K6

2
PEX_RX10_N GPIO21
4 PEG_HTX_C_GRX_P11 AR28 L6 +3VSDGPU
PEX_RX11 GPIO22
4 PEG_HTX_C_GRX_N11 AR29 M6
PEX_RX11_N GPIO23
4 PEG_HTX_C_GRX_P12 AP29
PEX_RX12 GPIO7 OUT N/A N/A
4 PEG_HTX_C_GRX_N12 AN29 PEX_RX12_N 1 2 +3VSDGPU
4 PEG_HTX_C_GRX_P13 AN31 N1 R747 DIS@ 10K_0402_5%
PEX_RX13 MIOA_D0
4 PEG_HTX_C_GRX_N13 AP31
PEX_RX13_N MIOA_D1
P4 GPIO8 IN L N/A
4 PEG_HTX_C_GRX_P14 AR31 P1
PEX_RX14 MIOA_D2
4 PEG_HTX_C_GRX_N14 AR32 P2
PEX_RX14_N MIOA_D3
4 PEG_HTX_C_GRX_P15 AR34
PEX_RX15 MIOA_D4
P3 GPIO9 OUT L N/A
4 PEG_HTX_C_GRX_N15 AP34 T3 1 @ 2
PEX_RX15_N MIOA_D5 12 27M_CLK R860 0_0402_5%
MIOA_D6 T2

DIS@ C807 0.1U_0402_16V7K PEX_TXP0 MIOA_D7


T1 GPIO10 OUT N/A N/A
4 PEG_GTX_C_HRX_P0 1 2 AL17 PEX_TX0 MIOA_D8 U4
DIS@ C808 1 2 0.1U_0402_16V7K PEX_TXN0 AM17 U1
4 PEG_GTX_C_HRX_N0 PEX_TX0_N MIOA_D9
DIS@ C810 1 2 0.1U_0402_16V7K PEX_TXP1 AM18 U2 GPIO11 OUT N/A N/A
4 PEG_GTX_C_HRX_P1 PEX_TX1 MIOA_D10
DIS@ C811 0.1U_0402_16V7K PEX_TXN1 XTALOUT XTALIN

PCI EXPRESS
4 PEG_GTX_C_HRX_N1 1 2 AM19 PEX_TX1_N MIOA_D11 U3 2 1
DIS@ C812 1 2 0.1U_0402_16V7K PEX_TXP2 AL19 R6 R754 1M_0402_5%
4 PEG_GTX_C_HRX_P2 PEX_TX2 MIOA_D12
DIS@ C813 1 2 0.1U_0402_16V7K PEX_TXN2 AK19 T6 @ GPIO12 IN N/A N/A

DVO
4 PEG_GTX_C_HRX_N2 PEX_TX2_N MIOA_D13
DIS@ C814 1 2 0.1U_0402_16V7K PEX_TXP3 AL20 N6
4 PEG_GTX_C_HRX_P3 PEX_TX3 MIOA_D14
DIS@ C815 1 2 0.1U_0402_16V7K PEX_TXN3 AM20 N2
4 PEG_GTX_C_HRX_N3 PEX_TX3_N MIOA_DE
DIS@ C816 1 2 0.1U_0402_16V7K PEX_TXP4 AM21 N3 Y5 GPIO13 OUT N/A N/A
4 PEG_GTX_C_HRX_P4 PEX_TX4 MIOA_HSYNC
DIS@ C817 1 2 0.1U_0402_16V7K PEX_TXN4 AM22 L3 2 1
4 PEG_GTX_C_HRX_N4 PEX_TX4_N MIOA_VSYNC
DIS@ C818 1 2 0.1U_0402_16V7K PEX_TXP5 AL22 P5
4 PEG_GTX_C_HRX_P5 PEX_TX5 MIOA_CTL3
DIS@ C819 1 2 0.1U_0402_16V7K PEX_TXN5 AK22 N5 27MHZ_16PF_X5H027000FG1H GPIO14 OUT N/A N/A
2 4 PEG_GTX_C_HRX_N5 PEX_TX5_N MIOA_VREF 2
DIS@ C820 1 2 0.1U_0402_16V7K PEX_TXP6 AL23 N4 1 DIS@ 2 DIS@
4 PEG_GTX_C_HRX_P6 PEX_TX6 MIOA_CLKIN
DIS@ C821 1 2 0.1U_0402_16V7K PEX_TXN6 AM23 R4 R753 10K_0402_5% C836 C838
4 PEG_GTX_C_HRX_N6 PEX_TX6_N MIOA_CLKOUT
DIS@ C822 1 2 0.1U_0402_16V7K PEX_TXP7 AM24 U5 DIS@ DIS@
4 PEG_GTX_C_HRX_P7 PEX_TX7 MIOA_CAL_PD_VDDQ
DIS@ C823 1 2 0.1U_0402_16V7K PEX_TXN7 AM25 T5 18P_0402_50V8J 18P_0402_50V8J
4 PEG_GTX_C_HRX_N7 PEX_TX7_N MIOA_CAL_PD_VDDGND
DIS@ C824 1 2 0.1U_0402_16V7K PEX_TXP8 AL25 T4
4 PEG_GTX_C_HRX_P8 PEX_TX8 MIOA_CLKOUT_N
DIS@ C825 1 2 0.1U_0402_16V7K PEX_TXN8 AK25
4 PEG_GTX_C_HRX_N8
DIS@ C826 1 2 0.1U_0402_16V7K PEX_TXP9 AL26
PEX_TX8_N Unused MIO interface
4 PEG_GTX_C_HRX_P9 PEX_TX9
DIS@ C827 1 2 0.1U_0402_16V7K PEX_TXN9 AM26 Y1 When the MIOx interface is unused,
4 PEG_GTX_C_HRX_N9 PEX_TX9_N MIOB_D0
DIS@ C828 1 2 0.1U_0402_16V7K PEX_TXP10 AM27 Y2 the interface must still be powered by 3.3V,
4 PEG_GTX_C_HRX_P10 PEX_TX10 MIOB_D1
DIS@ C829 1 2 0.1U_0402_16V7K PEX_TXN10 AM28 Y3
4 PEG_GTX_C_HRX_N10 PEX_TX10_N MIOB_D2 a decoupling capacitor of 0.1uF
DIS@ C830 1 2 0.1U_0402_16V7K PEX_TXP11 AL28 AB3
4 PEG_GTX_C_HRX_P11 PEX_TX11 MIOB_D3 should still be placed on thx MIOx_VDDQ power rail
DIS@ C831 1 2 0.1U_0402_16V7K PEX_TXN11 AK28 AB2
4 PEG_GTX_C_HRX_N11 PEX_TX11_N MIOB_D4
DIS@ C832 1 2 0.1U_0402_16V7K PEX_TXP12 AK29 AB1 and 10k pull down should be used on MIOx_CLKIN
4 PEG_GTX_C_HRX_P12 PEX_TX12 MIOB_D5
DIS@ C833 1 2 0.1U_0402_16V7K PEX_TXN12 AL29 AC4
4 PEG_GTX_C_HRX_N12 PEX_TX12_N MIOB_D6
DIS@ C834 1 2 0.1U_0402_16V7K PEX_TXP13 AM29 AC1
4 PEG_GTX_C_HRX_P13 PEX_TX13 MIOB_D7
DIS@ C835 1 2 0.1U_0402_16V7K PEX_TXN13 AM30 AC2
4 PEG_GTX_C_HRX_N13 PEX_TX13_N MIOB_D8
DIS@ C837 1 2 0.1U_0402_16V7K PEX_TXP14 AM31 AC3
4 PEG_GTX_C_HRX_P14 PEX_TX14 MIOB_D9
DIS@ C839 1 2 0.1U_0402_16V7K PEX_TXN14 AM32 AE3
4 PEG_GTX_C_HRX_N14 PEX_TX14_N MIOBD_10
DIS@ C840 1 2 0.1U_0402_16V7K PEX_TXP15 AN32 AE2
4 PEG_GTX_C_HRX_P15 PEX_TX15 MIOB_D11
DIS@ C841 1 2 0.1U_0402_16V7K PEX_TXN15 AP32 U6
4 PEG_GTX_C_HRX_N15 PEX_TX15_N MIOB_D12
+3VSDGPU MIOB_D13 W6
2

Y6
R755 MIOB_D14 VGA_CRT_R
10K_0402_5% AR16
DIS@
14 CLK_PEG_VGA
AR17
PEX_REFCLK
W1 VGA_CRT_G External Spread Spectrum OSC_OUT R759 1 2 @ 22_0402_5% XTAL_OUTBUFF
14 CLK_PEG_VGA# PEX_REFCLK_N MIOB_HSYNC
14 PEG_CLKREQ# AR13 W2
1

PEX_CLKREQ_N MIOB_VSYNC

1
R760@ AJ17 VGA_CRT_B U53 R761
PEX_TSTCLK_OUT 10K_0402_5%
2 1 AJ18 PEX_TSTCLK_OUT_N MIOB_DE Y5 1 REFOUT VSS 6
200_0402_1% W3 DIS@
MIOB_CTL3 OSC_SPREAD
AF1 2 5

2
MIOB_VREF XOUT MODOUT

1
17 PLTRST_VGA# AM16
PEX_RST_N

150_0402_1%

150_0402_1%

150_0402_1%
3 2 @ 1 AG21 OSC_OUT 3 4 +3VSDGPU 3
R762 2.49K_0402_1% PEX_TERMP XIN/CLKIN VDD OSC_SPREAD R763 1
1 2 @ 22_0402_5% XTAL_SSIN
AE1 1 DIS@ 2 @
MIOB_CLKIN

1
BLM18PG181SN1D_0603 36 mA V4 R764 10K_0402_5% @ ASM3P2872AF-06OR_TSOT-23-6 C842

2
GPU_PLLVDD
MIOB_CLKOUT 0.1U_0402_16V4Z XTAL_SSIN
+1.05VSDGPU 2 1 AE9
DIS@ L79 PLLVDD 2 12 27M_SSC R765
4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
22U_0805_6.3V6M

1U_0402_6.3V6K

SP_PLLVDD R756 R757 R758 10K_0402_5%


0.1U_0402_16V4Z

1 1 1 1 1 1 AF9 W4
C843 C844 SP_PLLVDD MIOB_CLKOUT_N DIS@ DIS@ DIS@ DIS@

2
DIS@ C845 C846 C847 C848 AD9
DIS@ DIS@ DIS@ DIS@ DIS@ VID_PLLVDD
AA7
CLK

2 2 2 2 2 2 XTALIN MIOB_CAL_PD_VDDQ
B1 AA6
XTALOUT B2
XTAL_IN MIOB_CAL_PU_GND If External Spread Spectrum not stuff then stuff resistor
XTAL_OUT
AM15 VGA_CRT_R 29
XTAL_OUTBUFF DACA_RED
D1 XTAL_OUTBUFF DACA_GREEN AM14 VGA_CRT_G 29
+3VSDGPU XTAL_SSIN D2 AL14
XTAL_SSIN DACA_BLUE VGA_CRT_B 29

DACA_HSYNC AM13 VGA_CRT_HSYNC 29


R766 2 DIS@ 1 2K_0402_5% VGA_DDC_CLK AL13
DACA_VSYNC VGA_CRT_VSYNC 29
R767 2 DIS@ 1 2K_0402_5% VGA_DDC_DATA I2CS_SCL E2 150 mA BLM18PG181SN1D_0603
I2CS_SDA I2CS_SCL DACA_VDD
E1 AJ12 1 2 +3VSDGPU
R768 2 DIS@ 1 2K_0402_5% VGA_LCD_CLK I2CS_SDA DACA_VDD
2 0.1U_0402_16V4Z DIS@ L80

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
LVDS DACA_VREF AK12 1

470P_0402_50V7K

4700P_0402_25V7K

1U_0402_6.3V6K
R769 2 DIS@ 1 2K_0402_5% VGA_LCD_DATA VGA_LCD_CLK E3 AK13 1 2 C849 DIS@
28 VGA_LCD_CLK VGA_LCD_DATA I2CC_SCL DACA_RSET 124_0402_1% R770 DIS@
E4 1 1 1 1 2 2 2
R771 1 DIS@ 22.2K_0402_5% I2CS_SCL 28 VGA_LCD_DATA I2CC_SDA C852 C858 C857 C859
DACB_RED AK4
DACs

R772 1 DIS@ 22.2K_0402_5% I2CS_SDA I2CB_SCL G3 AL4 C850 C853 C851


I2CB_SDA I2CB_SCL DACB_GREEN DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
G2 AJ4
I2C

R773 DIS@ I2CB_SDA DACB_BLUE 2 2 2 2 1 1 1


1 22.2K_0402_5% I2CB_SCL
R774 1 DIS@ 22.2K_0402_5% I2CB_SDA VGA_DDC_CLK G1 AM1
R864 DIS@ 29 VGA_DDC_CLK I2CA_SCL DACB_HSYNC
22.2K_0402_5% HDCP_SCL VGA_DDC_DATA G4
R863
1
1 DIS@ 22.2K_0402_5% HDCP_SDA CRT 29 VGA_DDC_DATA I2CA_SDA DACB_VSYNC
AM2

HDCP_SCL F6 AG7 2 R775 1 0.1U_0402_16V4Z


HDCP_SDA I2CH_SCL DACB_VDD
G6 I2CH_SDA DACB_VREF AK6 10K_0402_5% DIS@ 1 2
AH7 1 R776 2 DIS@ C854
4 Q60A DACB_RSET 124_0402_1% DIS@ 4
2N7002DWH_SOT363-6
I2CS_SCL 1 6 DIS@ N11P-GE1-B-A2_BGA969
EC_SMB_CK2 14,36
BLM18PG181SN1D_0603
+1.05VSDGPU 2 1 SP_PLLVDD
+3VSDGPU DIS@ L81
2

4.7U_0603_6.3V6M

1U_0402_6.3V6K

2N7002DWH_SOT363-6 DIS@
Q60B 1
C855
C856
1 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title
I2CS_SDA 4 3 DIS@ DIS@
EC_SMB_DA2 14,36 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11P-GV2H PEG I2C
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
+3VSDGPU DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NEW71/91 M/B LA-5893P Schematic 0.1
5

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, December 23, 2009 Sheet 22 of 56
A B C D E
5 4 3 2 1

U51D
Straps MULTI LEVEL STRAPS
Part 4 of 7 STRAP0
28 VGA_TXCLK+ AM11 A2 STRAP1
IFPA_TXC NC STRAP2
28 VGA_TXCLK- AM12 IFPA_TXC_N NC C5
28 VGA_TXOUT0+ AM8 D5 ROM_SI
IFPA_TXD0 NC ROM_SO
28 VGA_TXOUT0- AL8 IFPA_TXD0_N NC E5
28 VGA_TXOUT1+ AM10 E7 ROM_SCLK
IFPA_TXD1 NC +3VSDGPU
28 VGA_TXOUT1- AM9 IFPA_TXD1_N NC F4
28 VGA_TXOUT2+ AK10 IFPA_TXD2 NC G5
28 VGA_TXOUT2- AL10 IFPA_TXD2_N NC G11
AK11 G12 1 @ 2 1 DIS@ 2 strap0
IFPA_TXD3 NC R777 5.1K_0402_5% R778 45.3K_0402_1%
AL11 IFPA_TXD3_N NC G14
D
NC G15 D
G27 1 @ 2 DIS@ strap1
NC R779 10K_0402_1% R780 34.8K_0402_1%
AP13 IFPB_TXC NC G28
AN13 IFPB_TXC_N NC G24
AN8 G25 1 @ 2 1 DIS@ 2 strap2
IFPB_TXD4 NC R781 30K_0402_5% R782 30K_0402_5%
Mode E Command Mapping Mode C Command Mapping AP8 IFPB_TXD4_N NC H32
GB2-128 Package Femi GB1-128 Package AP10 IFPB_TXD5 NC J18
AN10 IFPB_TXD5_N NC J19 1 X76@ 2 1 @ 2 ROM_SI
Data Bit 0..31 32..63 AR11 IFPB_TXD6 NC J25 R783 20K_0402_5% R784 5.1K_0402_5%
AR10 IFPB_TXD6_N NC J26
FBx_CMD3 FBx_CMD0 CKE_L AN11 IFPB_TXD7 NC L29 1 DIS@ 2 1 @ 2 ROM_SO
AP11 M7 R785 10K_0402_1% R786 5.1K_0402_5%
IFPB_TXD7_N NC
FBx_CMD8 FBx_CMD1 A8 A8 NC M29

NC
P6 DIS@ 1 @ 2 ROM_SCLK
NC
FBx_CMD2 FBx_CMD2 CS0_L* 30 VGA_HDMI_TXD2+ AM7 IFPC_L0 NC P29 R787 15K_0402_5% R788 5.1K_0402_5%
30 VGA_HDMI_TXD2- AM6 IFPC_L0_N NC R29
FBx_CMD21 FBx_CMD3 A7 A6 30 VGA_HDMI_TXD1+ AL5 IFPC_L1 NC U7
30 VGA_HDMI_TXD1- AM5 IFPC_L1_N NC V6
FBx_CMD24 FBx_CMD4 A2 A1 30 VGA_HDMI_TXD0+ AM3 Y4 20091214
IFPC_L2 NC
30 VGA_HDMI_TXD0- AM4 IFPC_L2_N NC AA4 Modify
FBx_CMD23 FBx_CMD5 A11 A9 30 VGA_HDMI_TXC+ AP1 IFPC_L3 NC AB4 strap0 strap1 strap2 ROM_SI ROM_SO ROM_SCLK
AR2 AB7

LVDS/TMDS
30 VGA_HDMI_TXC- IFPC_L3_N NC
FBx_CMD26 FBx_CMD6 A5 A4 NC AC5 64MX16 H H H L L L
AD6 Samsung 45K 35K 30K 20K 10K 15K
NC
FBx_CMD7 FBx_CMD7 A0 A12 AR8 IFPD_L0 NC AD29 SA000035720
AR7 IFPD_L0_N NC AE29
FBx_CMD15 FBx_CMD8 CAS* CAS* AP7 IFPD_L1 NC AF6 64MX16 H H H L L L
AN7 AG6 Hynix 45K 35K 30K 15K 10K 15K
IFPD_L1_N NC
FBx_CMD13 FBx_CMD9 BA1 A3 AN5 IFPD_L2 NC AG20 SA000032420
C AP5 AG29 C
IFPD_L2_N NC
FBx_CMD4 FBx_CMD10 A9 A11 AR5 AH29
IFPD_L3 NC
AR4 IFPD_L3_N NC AJ5
FBx_CMD18 FBx_CMD11 CS0_H NC AK15
NC AL7
FBx_CMD29 FBx_CMD12 BA0 BA0 AH6 IFPE_L0
AH5 IFPE_L0_N
FBx_CMD27 FBx_CMD13 BA2 A15 AH4 IFPE_L1
AG4 IFPE_L1_N
FBx_CMD6 FBx_CMD14 A3 BA1 AF4 IFPE_L2
AF5 IFPE_L2_N 20091217
FBx_CMD17 FBx_CMD15 CS1_H AE6
+3VSDGPU AE5
IFPE_L3 For layout convenient del R789 and R795
IFPE_L3_N
FBx_CMD19 FBx_CMD16 ODT_H
VDD_SENSE_0 D35 +NVVDD_SENSE 50
FBx_CMD22 FBx_CMD17 A4 A5 AL2 IFPF_L0 VDD_SENSE_1 P7 R790 1 DIS@ 2 0_0402_5%

1
AL3 AD20 R793 1 DIS@ 2 0_0402_5%
IFPF_L0_N VDD_SENSE_2
FBx_CMD12 FBx_CMD18 A13 A14 R791 R792 AJ3 IFPF_L1
4.7K_0402_5% 4.7K_0402_5% AJ2
IFPF_L1_N
FBx_CMD28 FBx_CMD19 WE* A10 DIS@ DIS@ AJ1 IFPF_L2
AH1 AD19 R794 1 DIS@ 2 0_0402_5%

2
IFPF_L2_N GND_SENSE_0
FBx_CMD10 FBx_CMD20 A1 A2 AH2 IFPF_L3 GND_SENSE_1 E35
AH3 R7 R796 1 DIS@ 2 0_0402_5%
IFPF_L3_N GND_SENSE_2
FBx_CMD25 FBx_CMD21 A10 WE*
30 VGA_HDMI_SCLK AP2 IFPC_AUX_I2CW_SCL
FBx_CMD9 FBx_CMD22 A12 A0 30 VGA_HDMI_SDATA AN3 IFPC_AUX_I2CW_SDA_N
FBx_CMD1 FBx_CMD23 CS1_L* AP4
AN4
IFPD_AUX_I2CX_SCL TEST
B IFPD_AUX_I2CX_SDA_N B
FBx_CMD11 FBx_CMD24 RAS* RAS*
AE4 AP35 DIS@ 1 R797 2
IFPE_AUX_I2CY_SCL TESTMODE
FBx_CMD0 FBx_CMD25 ODT_L AD4 IFPE_AUX_I2CY_SDA_N JTAG_TCK AP14 10K_0402_5% JTAG_TCK PAD T25
@
AN14 JTAG_TDI PAD @
JTAG_TDI T26
FBx_CMD5 FBx_CMD26 A6 A7 JTAG_TDO AN16 JTAG_TDO PAD T27
@
AF3 AR14 JTAG_TMS PAD @
IFPF_AUX_I2CZ_SCL JTAG_TMS T28
FBx_CMD16 FBx_CMD27 CKE_H AF2 IFPF_AUX_I2CZ_SDA_N JTAG_TRST_N AP16 JTAG_TRST PAD T29
@

FBx_CMD20 FBx_CMD28 RST RST 2 R798 1


A7 10K_0402_5%
NC
FBx_CMD14 FBx_CMD29 A14 A13 B7 NC NC SERIAL DIS@
C7 R799
NC
FBx_CMD30 FBx_CMD30 A15 BA2 D6 NC ROM_CS_N C3 ROM_CS# 10K_0402_5%1 2 @ +3VSDGPU
D7 D3 ROM_SI
NC ROM_SI ROM_SO
ROM_SO C4
FBx_CMD31 ROM_SCLK D4 ROM_SCLK

LOW HIGH GENERAL


NC A5
A4 DIS@ R801
10K_0402_5% BUFRST_N
MULTI_STRAP_REF0_GND N9 2 1
+3VSDGPU 2 R800 1 AB5 CEC
40.2K_0402_1%
MULTI_STRAP_REF1_GND M9 2 1
DIS@ STRAP0 W5 40.2K_0402_1%
STRAP1 STRAP0 DIS@ R802
W7 STRAP1 THERMDP B5
STRAP2 V7 B4
STRAP2 THERMDN

A A

N11P-GE1-B-A2_BGA969

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11P-GV2H LVDS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic
Date: Tuesday, December 22, 2009 Sheet 23 of 56
5 4 3 2 1
5 4 3 2 1

U51E

Part 5 of 7 +1.05VSDGPU
+1.5VSDGPU FBVDDQ J23 AG11 PEX_IOVDDQ PEX_IOVDDQ

10U_0805_6.3V6M

22U_0805_6.3V6M
4.7U_0603_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z
FBVDDQ_0 PEX_IOVDDQ_0
J24 AG12

1U_0603_10V4Z

1U_0603_10V4Z
FBVDDQ_1 PEX_IOVDDQ_1
J29 AG13 1 1 2 2 1 1 1
22U_0805_6.3V6M

22U_0805_6.3V6M

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

0.1U_0402_16V4Z
FBVDDQ FBVDDQ_2 PEX_IOVDDQ_2 C1044 C1045 C1047 C1043 C1042 C1046 C1041
AA27 FBVDDQ_3 PEX_IOVDDQ_3 AG15
AA29 AG16 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
FBVDDQ_4 PEX_IOVDDQ_4

C863

C864

C865

C866

C867

C868
DIS@ C1039

DIS@ C1040

DIS@ C1051
1 1 1 1 1 AA31 FBVDDQ_5 PEX_IOVDDQ_5 AG17
2 2 1 1 2 2 2
AB27 FBVDDQ_6 PEX_IOVDDQ_6 AG18
AB29 FBVDDQ_7 PEX_IOVDDQ_7 AG22

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
AC27 FBVDDQ_8 PEX_IOVDDQ_8 AG23
2 2 2 2 2 AD27 AG24
FBVDDQ_9 PEX_IOVDDQ_9 +1.05VSDGPU
AE27 FBVDDQ_10 PEX_IOVDDQ_10 AG25
D AJ28 FBVDDQ_11 PEX_IOVDDQ_11 AG26 D
B18 AJ14 PEX_IOVDD

10U_0805_6.3V6M

22U_0805_6.3V6M
4.7U_0603_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z
FBVDDQ FBVDDQ_12 PEX_IOVDDQ_12
E21 AJ15

1U_0603_10V4Z

1U_0603_10V4Z
FBVDDQ_13 PEX_IOVDDQ_13
C869 G17 FBVDDQ_14 PEX_IOVDDQ_14 AJ19 1 1 2 2 1 1 1

DIS@ C870

C872

C873

C874

C884
1 1 1 G18 AJ21 C875 C876 C1033 C877 C878 C879 C880
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0.047U_0402_16V7K

0.047U_0402_16V7K

0.047U_0402_16V7K
FBVDDQ_15 PEX_IOVDDQ_15 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
G22 FBVDDQ_16 PEX_IOVDDQ_16 AJ22
G8 FBVDDQ_17 PEX_IOVDDQ_17 AJ24
2 2 1 1 2 2 2
DIS@

DIS@

DIS@

DIS@

DIS@
G9 FBVDDQ_18 PEX_IOVDDQ_18 AJ25
2 2 2 H29 AJ27
FBVDDQ_19 PEX_IOVDDQ_19

POWER
J14 FBVDDQ_20 PEX_IOVDDQ_20 AK18
J15 FBVDDQ_21 PEX_IOVDDQ_21 AK20
J16 AK23

0.01U_0402_25V7K
4.7U_0603_6.3V6M
FBVDDQ_22 PEX_IOVDDQ_22 PEX_PLLDVDD
J17 AK26 2 1

1U_0402_6.3V6K
+1.05VSDGPU

0.1U_0402_16V4Z
FBVDDQ_23 PEX_IOVDDQ_23 L82 DIS@
J20 FBVDDQ_24 PEX_IOVDDQ_24 AL16
J21 1 1 1 1 BLM18PG181SN1D_0603
FBVDDQ_25
J22 FBVDDQ_26
N27 C887 C888 C889 C890 PEX_IOVDDQ
FBVDDQ_27 PEX_IOVDD DIS@ DIS@ DIS@ DIS@
P27 FBVDDQ_28 PEX_IOVDD_0 AK16
2 2 2 2 2200mA
R27 FBVDDQ_29 PEX_IOVDD_1 AK17 PEX_IOVDD
T27 FBVDDQ_30 PEX_IOVDD_2 AK21
U27 FBVDDQ_31 PEX_IOVDD_3 AK24 PEX_PLLVDD 120mA
U29 FBVDDQ_32 PEX_IOVDD_4 AK27
V27 PEX_SVDD_3V3 120mA

4.7U_0603_6.3V6M
FBVDDQ_33 R803
V29

0.1U_0402_16V4Z
+1.05VSDGPU FBVDDQ_34 PEX_SVDD_3V3
100mA V34 1 1 2 1 +3VSDGPU

1U_0603_10V4Z
BLM18PG181SN1D_0603 FBVDDQ_35 PEX_PLLDVDD 0_0603_5%
follow the DS04644 W27 FBVDDQ_36 PEX_PLLVDD AG14
C892
2 1 IFPAB_PLLVDD Y27 C891 1 DIS@
L83 DIS@ FBVDDQ_37 DIS@ DIS@ C1032
2 2 DIS@
0.1U_0402_16V4Z

1 2 1 C895 1 C896 1 IFPAB_PLLVDD AK9 AG19 PEX_SVDD_3V3


1U_0402_6.3V6K
4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C893 C894 C1053 1K_0402_1% 2 IFPAB_RSET AJ11 IFPAB_PLLVDD PEX_SVDD_3V3_0 2


1 IFPAB_RSET PEX_SVDD_3V3_1 F7
R804 @
DIS@ DIS@ DIS@ DIS@ DIS@ +3VSDGPU
2 1 2 2 2 IFPA_IOVDD AG9

4.7U_0603_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
IFPB_IOVDD IFPA_IOVDD
AG10 J10

1U_0603_10V4Z
IFPB_IOVDD VDD33_0
C VDD33_1 J11 C
VDD33_2 J12 1 1 1 1 1
IFPC_PLLVDD AJ9 J13 C1031
IFPC_PLLVDD VDD33_3 C899
2 1 IFPC_RSET AK7 IFPC_RSET VDD33_4 J9 C1026 C897 C898 DIS@
DIS@ R805 1K_0402_1% DIS@ DIS@ DIS@ DIS@
IFPC_IOVDD 2 2 2 2 2
AJ8 IFPC_IOVDD
+1.8VSDGPU 0.1U_0402_16V4Z
100 mA #SI Change to +VDDMEM18 MIOA_VDDQ P9 1 +3VSDGPU
2 1 IFPA_IOVDD IFPC_PLLVDD AC6 R9
IFPD_PLLVDD MIOA_VDDQ
L84 DIS@ 1K_0402_1% 2 DIS@ 1 R806 IFPD_RSET AB6 T9 C900
1U_0402_6.3V6K

0.1U_0402_16V4Z

0.1U_0402_16V4Z

BLM18PG181SN1D_0603 IFPB_IOVDD IFPD_RSET MIOA_VDDQ DIS@


1 1 2 2 U9
4.7U_0603_6.3V6M

C901 C902 C903 C1048 IFPC_IOVDD MIOA_VDDQ 2 +VGA_CORE


AK8 IFPD_IOVDD +VGA_CORE
DIS@ DIS@ DIS@ DIS@ AA9 U51G
2 2 1 1 1K_0402_5% 1 DIS@ MIOB_VDDQ_0
2 R807 AJ6 AB9

4700P_0402_16V7K

4700P_0402_16V7K
0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K
1K_0402_1% 2 DIS@ IFPEF_PLLVDD MIOB_VDDQ_1
1 R808 IFPE_RSET AL1 IFPEF_RSET MIOB_VDDQ_2 W9 AB11 VDD_0 VDD_56 P21
Y9 +3VSDGPU AB13 Part 7 of 7 P23
R809 1 DIS@ AE7 MIOB_VDDQ_3 VDD_1 VDD_57
2 AB15 P25

0.1U_0402_16V4Z
+1.8VSDGPU 1K_0402_1% IFPE_IOVDD C904 C908 C909 C905 C910 C911 VDD_2 VDD_58
1 AB17 VDD_3 VDD_59 R11
2 R861 1 DIS@ AD7 AB19 R12
1K_0402_1% IFPF_IOVDD C907 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ VDD_4 VDD_60
2 1 AB21 VDD_5 VDD_61 R13
L88 DIS@ DIS@ AB23 R14
0.1U_0402_16V4Z

0.1U_0402_16V4Z

BLM18PG181SN1D_0603 2 VDD_6 VDD_62


1 1 2 2 AB25 R15
1U_0402_6.3V6K
4.7U_0603_6.3V6M

C912 C913 C1049 C1050 N11P-GE1-B-A2_BGA969 VDD_7 VDD_63


AC11 VDD_8 VDD_64 R16
AC12 VDD_9 VDD_65 R17
DIS@ DIS@ DIS@ DIS@ AC13 R18

0.01U_0402_16V7K

0.01U_0402_16V7K
0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K

0.022U_0402_16V7K
2 2 1 1 VDD_10 VDD_66
AC14 VDD_11 VDD_67 R19
AC15 VDD_12 VDD_68 R20
AC16 VDD_13 VDD_69 R21
C914 C915 C906 C916 C917 C918 AC17 R22
VDD_14 VDD_70
AC18 R23
PWR Sequence DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ AC19
VDD_15
VDD_16
VDD_71
VDD_72 R24
AC20 VDD_17 VDD_73 R25
AC21 VDD_18 VDD_74 T12
+3VS_DELAY AC22 VDD_19 VDD_75 T14
B AC23 VDD_20 VDD_76 T16 B

POWER
follow the DS04644 +VGA_CORE AC24 VDD_21 VDD_77 T18
AC25 VDD_22 VDD_78 T20
+1.8VS AD12 VDD_23 VDD_79 T22
+3VSDGPU BLM18PG181SN1D_0603 +VGA_CORE
160 mA AD14
AD16
VDD_24 VDD_80 T24
V11

0.047U_0402_16V7K

0.047U_0402_16V7K

0.047U_0402_16V7K
IFPC_PLLVDD VDD_25 VDD_81
2 1 AD18 V13

0.22U_0603_16V7K

0.22U_0603_16V7K
L85 DIS@ VDD_26 VDD_82
AD22 VDD_27 VDD_83 V15
AD24 V17
1U_0402_6.3V6K

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

VDD_28 VDD_84
1 1 2 2 2 L11 VDD_29 VDD_85 V19
C919 C920 C921 C922 C1052 +3VS C1037 C1034 C1035 C1036 C1038 L12 V21
VDD_30 VDD_86
L13 VDD_31 VDD_87 V23
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ L14 V25
2 2 1 1 1 +3VSDGPU VDD_32 VDD_88
L15 VDD_33 VDD_89 W11
L16 VDD_34 VDD_90 W12
1 L17 VDD_35 VDD_91 W13
C929 R810 1 @ 2 0_0805_5% L18 W14
DIS@ VDD_36 VDD_92
L19 VDD_37 VDD_93 W15
10U_0805_10V4Z L20 W16
2 +VGA_CORE VDD_38 VDD_94
L21 VDD_39 VDD_95 W17
AO3413_SOT23-3 L22 W18
+3VALW Q56 VDD_40 VDD_96
100mil(1.5A) L23 W19

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

4.7U_0603_6.3V6M
VDD_41 VDD_97
S

3 1 DIS@ L24 W20

1U_0402_6.3V6K
330U_D2_2V_Y
VDD_42 VDD_98
1

385 mA 1 L25 VDD_43 VDD_99 W21


2

+1.05VSDGPU BLM18PG181SN1D_0603 1 1 1 1 1 1 M12 W22


IFPC_IOVDD R811 DIS@ C930 R812 C923 + C924 C925 C926 C927 C928 VDD_44 VDD_100
2 1
G

M14 W23
2

L86 DIS@ 100K_0402_5% DIS@ 470_0603_5% VDD_45 VDD_101


3VSdelay_gate

M16 W24
1U_0402_6.3V6K

4.7U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ VDD_46 VDD_102


1 1 2 2 M18 W25
2

C931 C932 C933 C934 2 2 2 2 2 2 2 VDD_47 VDD_103


M20 Y12
3 1

VDD_48 VDD_104
1 2 M22 Y14
2N7002DWH_SOT363-6

DIS@ DIS@ DIS@ DIS@ R813 DIS@ 1K_0402_5% VDD_49 VDD_105


M24 VDD_50 VDD_106 Y16
2 2 1 1 DIS@ P11 VDD_51 VDD_107 Y18
6

DIS@ Q57B P13 Y20


R814 DIS@ 2N7002DWH_SOT363-6 3VSdelay_gate VDD_52 VDD_108
1 5 P15 VDD_53 VDD_109 Y22
1K_0402_5% Q57A C935 P17 Y24
0.1U_0603_25V7K VDD_54 VDD_110
A 38,42,50 VGA_ON 2 1 2 P19 A
4

DIS@ VDD_55
1 2
C936
1

0.1U_0603_25V7K DIS@
2
N11P-GE1-B-A2_BGA969

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/5/12 Deciphered Date 2009/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11P-GV2H POWER & GND
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom NEW71/91 M/B LA-5893P Schematic 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 22, 2009 Sheet 24 of 56
5 4 3 2 1
A

VRAM Interface
MDC[15..0] U51F
27 MDC[15..0]
MDC[31..16] B3 Part 6 of 7
MDA[15..0] 27 MDC[31..16] GND_0
26 MDA[15..0] B6 GND_1 GND_97 V18
MDC[47..32] B9 V20
MDA[31..16] 27 MDC[47..32] GND_2 GND_98
26 MDA[31..16] B12 GND_3 GND_99 V22
MDC[63..48] B15 V24
MDA[47..32] 27 MDC[63..48] GND_4 GND_100
26 MDA[47..32] B21 GND_5 GND_101 V31
B24 GND_6 GND_102 Y11
MDA[63..48] U51C B27 Y13
26 MDA[63..48] GND_7 GND_103
CMDC[30..0] 27 B30 GND_8 GND_104 Y15
U51B Part 3 of 7 B33 Y17
CMDA[30..0] 26 GND_9 GND_105
MDC0 B13 C17 CMDC0 C2 Y19
Part 2 of 7 CMDA0 MDC1 FBC_D00 FBC_CMD0 CMDC1 GND_10 GND_106
FBA_CMD0 V32 D13 FBC_D01 FBC_CMD1 B19 C34 GND_11 GND_107 Y21
MDA0 L32 W31 CMDA1 MDC2 A13 D18 CMDC2 E6 Y23
MDA1 N33 FBA_D0 FBA_CMD1 CMDA2 MDC3 FBC_D02 FBC_CMD2 CMDC3 GND_12 GND_108
FBA_D1 FBA_CMD2 U31 A14 FBC_D03 FBC_CMD3 F21 E9 GND_13 GND_109 Y25
MDA2 L33 Y32 CMDA3 MDC4 C16 A23 CMDC4 E12 AA2
MDA3 N34 FBA_D2 FBA_CMD3 CMDA4 MDC5 FBC_D04 FBC_CMD4 CMDC5 GND_14 GND_110
FBA_D3 FBA_CMD4 AB35 B16 FBC_D05 FBC_CMD5 D21 E15 GND_15 GND_111 AA5
MDA4 N35 AB34 CMDA5 MDC6 A17 B23 CMDC6 E18 AA11
MDA5 P35 FBA_D4 FBA_CMD5 CMDA6 MDC7 FBC_D06 FBC_CMD6 CMDC7 GND_16 GND_112
FBA_D5 FBA_CMD6 W35 D16 FBC_D07 FBC_CMD7 E20 E24 GND_17 GND_113 AA12
MDA6 P33 W33 CMDA7 MDC8 C13 G21 CMDC8 E27 AA13
MDA7 P34 FBA_D6 FBA_CMD7 CMDA8 MDC9 FBC_D08 FBC_CMD8 CMDC9 GND_18 GND_114
FBA_D7 FBA_CMD8 W30 B11 FBC_D09 FBC_CMD9 F20 E30 GND_19 GND_115 AA14
MDA8 K35 T34 CMDA9 MDC10 C11 F19 CMDC10 F2 AA15
MDA9 K33 FBA_D8 FBA_CMD9 CMDA10 MDC11 FBC_D10 FBC_CMD10 CMDC11 GND_20 GND_116
FBA_D9 FBA_CMD10 T35 A11 FBC_D11 FBC_CMD11 F23 F31 GND_21 GND_117 AA16
MDA10 K34 AB31 CMDA11 MDC12 C10 A22 CMDC12 F34 AA17
MDA11 H33 FBA_D10 FBA_CMD11 CMDA12 MDC13 FBC_D12 FBC_CMD12 CMDC13 GND_22 GND_118
FBA_D11 FBA_CMD12 Y30 C8 FBC_D13 FBC_CMD13 C22 F5 GND_23 GND_119 AA18
MDA12 G34 Y34 CMDA13 MDC14 B8 B17 CMDC14 J2 AA19
MDA13 G33 FBA_D12 FBA_CMD13 CMDA14 MDC15 FBC_D14 FBC_CMD14 CMDC15 GND_24 GND_120
FBA_D13 FBA_CMD14 W32 A8 FBC_D15 FBC_CMD15 F24 J5 GND_25 GND_121 AA20
MDA14 E34 AA30 CMDA15 MDC16 E8 C25 CMDC16 J31 AA21
MDA15 E33 FBA_D14 FBA_CMD15 CMDA16 MDC17 FBC_D16 FBC_CMD16 CMDC17 GND_26 GND_122
FBA_D15 FBA_CMD16 AA32 F8 FBC_D17 FBC_CMD17 E22 J34 GND_27 GND_123 AA22
MDA16 G31 Y33 CMDA17 MDC18 F10 C20 CMDC18 K9 AA23
MDA17 F30 FBA_D16 FBA_CMD17 CMDA18 MDC19 FBC_D18 FBC_CMD18 CMDC19 GND_28 GND_124
FBA_D17 FBA_CMD18 U32 F9 FBC_D19 FBC_CMD19 B22 L9 GND_29 GND_125 AA24
MDA18 G30 Y31 CMDA19 MDC20 F12 A19 CMDC20 M2 AA25
MDA19 G32 FBA_D18 FBA_CMD19 CMDA20 MDC21 FBC_D20 FBC_CMD20 CMDC21 GND_30 GND_126
FBA_D19 FBA_CMD20 U34 D8 FBC_D21 FBC_CMD21 D22 M5 GND_31 GND_127 AA34
MDA20 K30 Y35 CMDA21 MDC22 D11 D20 CMDC22 M11 AB12
MDA21 K32 FBA_D20 FBA_CMD21 CMDA22 MDC23 FBC_D22 FBC_CMD22 CMDC23 GND_32 GND_128
FBA_D21 FBA_CMD22 W34 E11 FBC_D23 FBC_CMD23 E19 M13 GND_33 GND_129 AB14
MDA22 H30 V30 CMDA23 MDC24 D12 D19 CMDC24 M15 AB16
MDA23 K31 FBA_D22 FBA_CMD23 CMDA24 MDC25 FBC_D24 FBC_CMD24 CMDC25 GND_34 GND_130
FBA_D23 FBA_CMD24 U35 E13 FBC_D25 FBC_CMD25 F18 M17 GND_35 GND_131 AB18
MDA24 L31 U30 CMDA25 MDC26 F13 C19 CMDC26 M19 AB20

MEMORY INTERFACE C
MDA25 L30 FBA_D24 FBA_CMD25 CMDA26 MDC27 FBC_D26 FBC_CMD26 CMDC27 GND_36 GND_132
FBA_D25 FBA_CMD26 U33 F14 FBC_D27 FBC_CMD27 F22 M21 GND_37 GND_133 AB22
MDA26 M32 AB30 CMDA27 MDC28 F15 C23 CMDC28 M23 AB24
MEMORY INTERFACE

MDA27 N30 FBA_D26 FBA_CMD27 CMDA28 MDC29 FBC_D28 FBC_CMD28 CMDC29 GND_38 GND_134
FBA_D27 FBA_CMD28 AB33 E16 FBC_D29 FBC_CMD29 B20 M25 GND_39 GND_135 AC9
MDA28 M30 T33 CMDA29 MDC30 F16 A20 CMDC30 M31 AD2
MDA29 P31 FBA_D28 FBA_CMD29 CMDA30 MDC31 FBC_D30 FBC_CMD30 GND_40 GND_136
FBA_D29 FBA_CMD30 W29 F17 FBC_D31 M34 GND_41 GND_137 AD5
MDA30 R32 MDC32

GND
FBA_D30 D29 FBC_D32 N11 GND_42 GND_138 AD11
MDA31 R30 MDC33 F27 N12 AD13
FBA_D31 FBC_D33 DQMC[3..0] 27 GND_43 GND_139
MDA32AG30 MDC34 F28 A16 DQMC0 N13 AD15
FBA_D32 DQMA[3..0] 26 FBC_D34 FBC_DQM0 GND_44 GND_140
MDA33AG32 P32 DQMA0 MDC35 E28 D10 DQMC1 N14 AD17
MDA34AH31 FBA_D33 FBA_DQM0 DQMA1 MDC36 FBC_D35 FBC_DQM1 DQMC2 GND_45 GND_141
FBA_D34 FBA_DQM1 H34 D26 FBC_D36 FBC_DQM2 F11 N15 GND_46 GND_142 AD21
MDA35AF31 J30 DQMA2 MDC37 F25 D15 DQMC3 N16 AD23
FBA_D35 FBA_DQM2 FBC_D37 FBC_DQM3 DQMC[7..4] 27 GND_47 GND_143
MDA36AF30 P30 DQMA3 MDC38 D24 D27 DQMC4 N17 AD25
FBA_D36 FBA_DQM3 DQMA[7..4] 26 FBC_D38 FBC_DQM4 GND_48 GND_144
MDA37AE30 AF32 DQMA4 MDC39 E25 D34 DQMC5 N18 AD31
MDA38AC32 FBA_D37 FBA_DQM4 DQMA5 MDC40 FBC_D39 FBC_DQM5 DQMC6 GND_49 GND_145
FBA_D38 FBA_DQM5 AL32 E32 FBC_D40 FBC_DQM6 A34 N19 GND_50 GND_146 AD34
MDA39AD30 AL34 DQMA6 MDC41 F32 D28 DQMC7 N20 AE11
MDA40AN33 FBA_D39 FBA_DQM6 DQMA7 MDC42 FBC_D41 FBC_DQM7 GND_51 GND_147
FBA_D40 FBA_DQM7 AF35 D33 FBC_D42 N21 GND_52 GND_148 AE12
MDA41 AL31 MDC43 E31 N22 AE13
FBA_D41 FBC_D43 DQSC#[3..0] 27 GND_53 GND_149
A

1 1
MDA42AM33 MDC44 C33 B14 DQSC#0 N23 AE14
MDA43 AL33 FBA_D42 MDC45 FBC_D44 FBC_DQS_RN0 DQSC#1 GND_54 GND_150
FBA_D43 DQSA#[3..0] 26 F29 FBC_D45 FBC_DQS_RN1 B10 N24 GND_55 GND_151 AE15
MDA44AK30 L35 DQSA#0 MDC46 D30 D9 DQSC#2 N25 AE16
MDA45AK32 FBA_D44 FBA_DQS_RN0 FBC_D46 FBC_DQS_RN2 GND_56 GND_152
FBA_D45 FBA_DQS_RN1 G35 DQSA#1 MDC47 E29 FBC_D47 FBC_DQS_RN3 E14 DQSC#3
DQSC#[7..4] 27 P12 GND_57 GND_153 AE17
MDA46 AJ30 H31 DQSA#2 MDC48 B29 F26 DQSC#4 P14 AE18
MDA47AH30 FBA_D46 FBA_DQS_RN2 FBC_D48 FBC_DQS_RN4 GND_58 GND_154
FBA_D47 FBA_DQS_RN3 N32 DQSA#3 DQSA#[7..4] 26
MDC49 C31 FBC_D49 FBC_DQS_RN5 D31 DQSC#5 P16 GND_59 GND_155 AE19
MDA48AH33 AD32 DQSA#4 MDC50 C29 A31 DQSC#6 P18 AE20
MDA49AH35 FBA_D48 FBA_DQS_RN4 FBC_D50 FBC_DQS_RN6 GND_60 GND_156
FBA_D49 FBA_DQS_RN5 AJ31 DQSA#5 MDC51 B31 FBC_D51 FBC_DQS_RN7 A26 DQSC#7 P20 GND_61 GND_157 AE21
MDA50AH34 AJ35 DQSA#6 MDC52 C32 P22 AE22
MDA51AH32 FBA_D50 FBA_DQS_RN6 FBC_D52 GND_62 GND_158
FBA_D51 FBA_DQS_RN7 AC34 DQSA#7 MDC53 B32 FBC_D53 P24 GND_63 GND_159 AE23
MDA52 AJ33 MDC54 B35 R2 AE24
FBA_D52 FBC_D54 DQSC[3..0] 27 GND_64 GND_160
MDA53 AL35 MDC55 B34 C14 DQSC0 R5 AE25
MDA54AM34 FBA_D53 MDC56 FBC_D55 FBC_DQS_WP0 DQSC1 GND_65 GND_161
FBA_D54 DQSA[3..0] 26 A29 FBC_D56 FBC_DQS_WP1 A10 R31 GND_66 GND_162 AG2
MDA55AM35 L34 DQSA0 MDC57 B28 E10 DQSC2 R34 AG5
MDA56AF33 FBA_D55 FBA_DQS_WP0 FBC_D57 FBC_DQS_WP2 GND_67 GND_163
FBA_D56 FBA_DQS_WP1 H35 DQSA1 MDC58 A28 FBC_D58 FBC_DQS_WP3 D14 DQSC3
DQSC[7..4] 27 T11 GND_68 GND_164 AG31
MDA57AE32 J32 DQSA2 MDC59 C28 E26 DQSC4 T13 AG34
MDA58AF34 FBA_D57 FBA_DQS_WP2 FBC_D59 FBC_DQS_WP4 GND_69 GND_165
FBA_D58 FBA_DQS_WP3 N31 DQSA3 DQSA[7..4] 26
MDC60 C26 FBC_D60 FBC_DQS_WP5 D32 DQSC5 T15 GND_70 GND_166 AK2
MDA59AE35 AE31 DQSA4 MDC61 D25 A32 DQSC6 T17 AK5
MDA60AE34 FBA_D59 FBA_DQS_WP4 FBC_D61 FBC_DQS_WP6 GND_71 GND_167
FBA_D60 FBA_DQS_WP5 AJ32 DQSA5 MDC62 B25 FBC_D62 FBC_DQS_WP7 B26 DQSC7 T19 GND_72 GND_168 AK14
MDA61AE33 AJ34 DQSA6 MDC63 A25 T21 AK31
MDA62AB32 FBA_D61 FBA_DQS_WP6 FBC_D63 GND_73 GND_169
FBA_D62 FBA_DQS_WP7 AC33 DQSA7 T23 GND_74 GND_170 AK34
MDA63AC35 40.2_0402_1% T25 AL6
FBA_D63 GND_75 GND_171
+1.5VSDGPU 2 DIS@ 1 R815 K27 FBCAL_PD_VDDQ FBC_CLK0 E17 CLKC0 27 U11 GND_76 GND_172 AL9
FBC_CLK0_N D17 CLKC0# 27 U12 GND_77 GND_173 AL12
FB_PLLAVDD AG27 40.2_0402_1%2 DIS@ 1 R816 L27 U13 AL15
FB_DLLAVDD FBCAL_PU_GND GND_78 GND_174
AF27 FB_PLLAVDD FBA_CLK0 T32 CLKA0 26 FBC_CLK1 D23 CLKC1 27 U14 GND_79 GND_175 AL18
T31 CLKA0# 26 40.2_0402_1%2 DIS@ 1 R817 M27 E23 CLKC1# 27 U15 AL21
FBA_CLK0_N FBCAL_TERM_GND FBC_CLK1_N GND_80 GND_176
U16 GND_81 GND_177 AL24
FB_VREF J27 FB_VREF G19 1 2 +1.5VSDGPU U17 AL27
FBC_DEBUG @ 10K_0402_5% GND_82 GND_178
+1.5VSDGPU FBA_CLK1 AC31 CLKA1 26 U18 GND_83 GND_179 AL30
2 1 T30 AC30 CLKA1# 26 R818 U19 AN2
R819 10K_0402_5% @ FBA_DEBUG FBA_CLK1_N
U20
GND_84 GND_180
AN34
GND_85 GND_181
U21 GND_86 GND_182 AP3
N11P-GE1-B-A2_BGA969 U22 AP6
GND_87 GND_183
U23 GND_88 GND_184 AP9
N11P-GE1-B-A2_BGA969 +1.5VSDGPU U24 AP12
GND_89 GND_185
U25 GND_90 GND_186 AP15
V2 GND_91 GND_187 AP18
1

V5 GND_92 GND_188 AP21


V9 GND_93 GND_189 AP24
R820 @ Rt V12 AP27
1K_0402_1% GND_94 GND_190
V14 GND_95 GND_191 AP30
V16 AP33
2

FB_VREF GND_96 GND_192


FB_PLLAVDD 2 1 +1.05VSDGPU
1

L87 DIS@ 1
1 1 1 1 BLM18PG181SN1D_0603
0.1U_0402_16V4Z

0.1U_0402_16V4Z
DIS@ C938

C939

C940

R821 @ Rb C941 N11P-GE1-B-A2_BGA969


1U_0402_6.3V6K

4.7U_0603_6.3V6M

C937 1K_0402_1% @
0.01U_0402_25V7K

DIS@ 2
Security Classification Compal Secret Data Compal Electronics, Inc.
2

2 2 2 2
DIS@

DIS@

2009/5/12 2009/12/31 Title


Issued Date Deciphered Date N11P-GV2H VRAM
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom NEW71/91 M/B LA-5893P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 22, 2009 Sheet 25 of 56
A
5 4 3 2 1

DQSA[7..0]
25 DQSA[7..0] DQMA[7..0]
CMDA0 R822 1 2 10K_0402_5%
DQSA#[7..0] 25 DQMA[7..0]
CMDA25 R823 1 DIS@ 2 10K_0402_5%
25 DQSA#[7..0] CMDA[30..0]
CMDA28 R824 1 DIS@ 2 10K_0402_5%
DQMA[7..0] 25 CMDA[30..0]
CMDA16 R825 1 DIS@ 2 10K_0402_5%
25 DQMA[7..0] DQSA#[7..0]
CMDA27 R826 1 DIS@ 2 10K_0402_5%
25 DQSA#[7..0]

, ,ODT
MDA[63..0] DIS@
25 MDA[63..0] DQSA[7..0]
CMDA[30..0]
MODE C PULL DOWN SIGNAL:RST CKE 25 DQSA[7..0]
25 CMDA[30..0] MDA[63..0]
25 MDA[63..0]
U54 X76@ U55 X76@
U56 X76@ U57 X76@
MEM_VREFA0 M8 E3 MDA21 MEM_VREFA1 M8 E3 MDA0
VREFCA DQL0 MDA18 VREFCA DQL0 MDA7 MEM_VREFA2 M8 MDA57 MEM_VREFA3 M8 MDA43
D H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 VREFCA DQL0 E3 VREFCA DQL0 E3 D
F2 MDA23 F2 MDA1 H1 F7 MDA63 H1 F7 MDA45
CMDA7 DQL2 MDA16 CMDA7 DQL2 MDA4 +1.5VSDGPU +1.5VSDGPU VREFDQ DQL1 MDA62 VREFDQ DQL1 MDA40
N3 A0 DQL3 F8 N3 A0 DQL3 F8 DQL2 F2 DQL2 F2
CMDA20 P7 H3 MDA22 CMDA20 P7 H3 MDA3 CMDA22 N3 F8 MDA61 CMDA22 N3 F8 MDA44
CMDA4 A1 DQL4 MDA19 CMDA4 A1 DQL4 MDA6 CMDA4 A0 DQL3 MDA59 CMDA4 A0 DQL3 MDA41
P3 A2 DQL5 H8 P3 A2 DQL5 H8 P7 A1 DQL4 H3 P7 A1 DQL4 H3

1
CMDA14 N2 G2 MDA20 CMDA14 N2 G2 MDA2 CMDA20 P3 H8 MDA56 CMDA20 P3 H8 MDA47
CMDA17 A3 DQL6 MDA17 CMDA17 A3 DQL6 MDA5 R828 CMDA9 A2 DQL5 MDA60 CMDA9 A2 DQL5 MDA42
P8 A4 DQL7 H7 P8 A4 DQL7 H7 N2 A3 DQL6 G2 N2 A3 DQL6 G2
CMDA6 P2 CMDA6 P2 R827 DIS@ 1K_0402_1% DIS@ CMDA6 P8 H7 MDA58 CMDA6 P8 H7 MDA46
CMDA26 A5 CMDA26 A5 1K_0402_1% CMDA17 A4 DQL7 CMDA17 A4 DQL7
R8 A6 R8 A6 P2 A5 P2 A5
CMDA3 R2 D7 MDA13 CMDA3 R2 D7 MDA27 CMDA3 R8 CMDA3 R8

2
CMDA1 A7 DQU0 MDA11 CMDA1 A7 DQU0 MDA26 CMDA26 A6 MDA33 CMDA26 A6 MDA51
T8 A8 DQU1 C3 T8 A8 DQU1 C3 R2 A7 DQU0 D7 R2 A7 DQU0 D7
CMDA10 R3 C8 MDA14 CMDA10 R3 C8 MDA31 MEM_VREFA0 MEM_VREFA1 CMDA1 T8 C3 MDA38 CMDA1 T8 C3 MDA52
CMDA21 A9 DQU2 MDA10 CMDA21 A9 DQU2 MDA28 CMDA5 A8 DQU1 MDA32 CMDA5 A8 DQU1 MDA48
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 1 1 R3 A9 DQU2 C8 R3 A9 DQU2 C8

1
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D
CMDA5 R7 A7 MDA12 CMDA5 R7 A7 MDA29 DIS@ DIS@ CMDA19 L7 C2 MDA37 CMDA19 L7 C2 MDA54
CMDA22 A11 DQU4 MDA8 CMDA22 A11 DQU4 MDA25 R829 C942 R830 C943 CMDA10 A10/AP DQU3 MDA34 CMDA10 A10/AP DQU3 MDA49
N7 A12 DQU5 A2 N7 A12 DQU5 A2 R7 A11 DQU4 A7 R7 A11 DQU4 A7
CMDA18 T3 B8 MDA15 CMDA18 T3 B8 MDA30 1K_0402_1% DIS@ 1K_0402_1% DIS@ CMDA7 N7 A2 MDA39 CMDA7 N7 A2 MDA55
CMDA29 A13 DQU6 MDA9 CMDA29 A13 DQU6 MDA24 2 2 CMDA29 A12 DQU5 MDA35 CMDA29 A12 DQU5 MDA50
T7 A14 DQU7 A3 T7 A14 DQU7 A3 T3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDA30 M7 CMDA30 M7 CMDA18 T7 A3 MDA36 CMDA18 T7 A3 MDA53

2
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU CMDA13 A14 DQU7 CMDA13 A14 DQU7
M7 A15/BA3 M7 A15/BA3 +1.5VSDGPU
CMDA12 M2 B2 CMDA12 M2 B2 +1.5VSDGPU
CMDA9 BA0 VDD CMDA9 BA0 VDD CMDA12 M2 CMDA12 M2
N8 BA1 VDD D9 N8 BA1 VDD D9 BA0 VDD B2 BA0 VDD B2
CMDA13 M3 G7 CMDA13 M3 G7 CMDA14 N8 D9 CMDA14 N8 D9
BA2 VDD BA2 VDD +1.5VSDGPU +1.5VSDGPU CMDA30 M3 BA1 VDD CMDA30 M3 BA1 VDD
VDD K2 VDD K2 BA2 VDD G7 BA2 VDD G7
VDD K8 VDD K8 VDD K2 VDD K2
VDD N1 VDD N1 VDD K8 VDD K8

1
CLKA0 J7 N9 CLKA0 J7 N9 N1 N1
CLKA0# CK VDD CLKA0# CK VDD R831 R832 CLKA1 VDD CLKA1 VDD
K7 CK VDD R1 K7 CK VDD R1 J7 CK VDD N9 J7 CK VDD N9
CMDA0 K9 R9 CMDA0 K9 R9 1K_0402_1% DIS@ 1K_0402_1% DIS@ CLKA1# K7 R1 CLKA1# K7 R1
C CKE/CKE0 VDD CKE/CKE0 VDD CMDA27 K9 CK VDD CMDA27 K9 CK VDD C
CKE/CKE0 VDD R9 CKE/CKE0 VDD R9
+1.5VSDGPU +1.5VSDGPU

2
CMDA25 K1 A1 CMDA25 K1 A1 +1.5VSDGPU +1.5VSDGPU
CMDA2 ODT/ODT0 VDDQ CMDA2 ODT/ODT0 VDDQ MEM_VREFA3 MEM_VREFA2 CMDA16 CMDA16
L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8 K1 ODT/ODT0 VDDQ A1 K1 ODT/ODT0 VDDQ A1

0.1U_0402_10V6K~D
CMDA24 J3 C1 CMDA24 J3 C1 1 1 CMDA11 L2 A8 CMDA11 L2 A8
RAS VDDQ RAS VDDQ CS/CS0 VDDQ CS/CS0 VDDQ

0.1U_0402_10V6K~D
CMDA8 K3 C9 CMDA8 K3 C9 DIS@ DIS@ CMDA24 J3 C1 CMDA24 J3 C1
CMDA19 CAS VDDQ CMDA19 CAS VDDQ R833 C944 R834 C945 CMDA8 RAS VDDQ CMDA8 RAS VDDQ
L3 WE VDDQ D2 L3 WE VDDQ D2 K3 CAS VDDQ C9 K3 CAS VDDQ C9
310mAVDDQ E9 E9 1K_0402_1% DIS@ 1K_0402_1% DIS@ CMDA21 L3 D2 CMDA21 L3 D2
VDDQ 2 2 WE VDDQ WE VDDQ
DQSA2 VDDQ F1
DQSA0
310mAVDDQ F1 310mAVDDQ E9 310mAVDDQ E9
F3 H2 F3 H2 F1 F1

2
DQSA1 DQSL VDDQ DQSA3 DQSL VDDQ DQSA7 VDDQ DQSA5 VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
DQSA4 C7 H9 DQSA6 C7 H9
DQSU VDDQ DQSU VDDQ
DQMA2 E7 A9 DQMA0 E7 A9
DQMA1 DML VSS DQMA3 DML VSS DQMA7 E7 DQMA5 E7
D3 DMU VSS B3 D3 DMU VSS B3 DML VSS A9 DML VSS A9
E1 E1 DQMA4 D3 B3 DQMA6 D3 B3
VSS VSS DMU VSS DMU VSS
VSS G8 VSS G8 VSS E1 VSS E1
DQSA#2 G3 J2 DQSA#0 G3 J2 G8 G8
DQSA#1 DQSL VSS DQSA#3 DQSL VSS DQSA#7 G3 VSS DQSA#5 G3 VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 DQSL VSS J2 DQSL VSS J2
M1 M1 DQSA#4 B7 J8 DQSA#6 B7 J8
VSS VSS CLKA0 CLKA1 DQSU VSS DQSU VSS
VSS M9 VSS M9 25 CLKA0 25 CLKA1 VSS M1 VSS M1
VSS P1 VSS P1 VSS M9 VSS M9
CMDA28 T2 P9 CMDA28 T2 P9 R835 R836 P1 P1
RESET VSS RESET VSS DIS@ 240_0402_1% DIS@ 240_0402_1% CMDA28 T2 VSS CMDA28 T2 VSS
VSS T1 VSS T1 RESET VSS P9 RESET VSS P9
L8 T9 ZQA1 L8 T9 T1 T1
ZQ/ZQ0 VSS ZQ/ZQ0 VSS CLKA0# CLKA1# ZQA2 VSS ZQA3 VSS
ZQA0 25 CLKA0# 25 CLKA1# L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
243_0402_1%

243_0402_1%

J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1


R837

R838

L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1

1
B B

243_0402_1%

243_0402_1%
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1 L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9

R839

R840
DIS@
DIS@

L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1


E2 E2 L9 D8 L9 D8
2

VSSQ VSSQ DIS@ NCZQ1 VSSQ NCZQ1 VSSQ


VSSQ E8 VSSQ E8 VSSQ E2 VSSQ E2
F9 F9 E8 DIS@ E8

2
VSSQ VSSQ VSSQ VSSQ
VSSQ G1 VSSQ G1 VSSQ F9 VSSQ F9
VSSQ G9 VSSQ G9 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 96-BALL 96-BALL
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

+1.5VSDGPU
+1.5VSDGPU

+1.5VSDGPU

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
C946

1U_0402_6.3V6K
C947

1U_0402_6.3V6K
C948

1U_0402_6.3V6K
C949

1U_0402_6.3V6K
C950

0.1U_0402_16V7K
C951

0.1U_0402_16V7K
C952

0.1U_0402_16V7K
C953

0.1U_0402_16V7K
C954

0.1U_0402_16V7K
C955

0.1U_0402_16V7K

C956

C957

C958

C959

C960

C961

C962

C963

C964
1 1 1 1 1 1 1 1 1
+1.5VSDGPU
1 1 1 1 1 1 1 1 1 1
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2
1000P_0402_50V7K

1 1 1 1 1 1 1 1 1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C975

C976

C977

C978

C979

C980

C981

C982

C983
C970

C971

C972

C973

C974

1 1 1 1 1 1 1 1 1 1
C965

C966

C967

C968

C969

A
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ A
2 2 2 2 2 2 2 2 2

2 2 2 2 2 2 2 2 2 2 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

DIS@
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11P-GV2H gDDR3
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic
Date: Tuesday, December 22, 2009 Sheet 26 of 56
5 4 3 2 1
5 4 3 2 1

DQSC[7..0] DQMC[7..0]
25 DQSC[7..0] 25 DQMC[7..0]
CMDC0 R841 1 2 10K_0402_5% U60 RAM BIT SWAP 20091211
DQSC#[7..0] CMDC25 R842 1 DIS@ 2 10K_0402_5% CMDC[30..0] 60->60
25 DQSC#[7..0] 25 CMDC[30..0]
CMDC28 R843 1 DIS@ 2 10K_0402_5% 62->58
DQMC[7..0] CMDC27 R844 1 DIS@ 2 10K_0402_5% DQSC#[7..0] 58->63
25 DQMC[7..0] 25 DQSC#[7..0]
CMDC16 R847 1 DIS@ 2 10K_0402_5% 63->57

, ,ODT
MDC[63..0] DIS@ DQSC[7..0]
25 MDC[63..0] 25 DQSC[7..0] 59->56
CMDC[30..0]
MODE C PULL DOWN SIGNAL:RST CKE MDC[63..0] 56->62
25 CMDC[30..0] 25 MDC[63..0] 57->61
U58 X76@ U59 X76@ 61->59
U60 X76@ U61 X76@
D MEM_VREFC0 M8 E3 MDC22 MEM_VREFC1 M8 E3 MDC3 D
VREFCA DQL0 MDC16 VREFCA DQL0 MDC7 MEM_VREFC2 M8 MDC60 MEM_VREFC3 M8 MDC44
H1 VREFDQ DQL1 F7 H1 VREFDQ DQL1 F7 VREFCA DQL0 E3 VREFCA DQL0 E3
F2 MDC23 F2 MDC0 H1 F7 MDC58 H1 F7 MDC43
CMDC7 DQL2 MDC19 CMDC7 DQL2 MDC5 +1.5VSDGPU +1.5VSDGPU VREFDQ DQL1 MDC63 VREFDQ DQL1 MDC42
N3 A0 DQL3 F8 N3 A0 DQL3 F8 DQL2 F2 DQL2 F2
CMDC20 P7 H3 MDC18 CMDC20 P7 H3 MDC2 CMDC22 N3 F8 MDC57 CMDC22 N3 F8 MDC47
CMDC4 A1 DQL4 MDC17 CMDC4 A1 DQL4 MDC6 CMDC4 P7 A0 DQL3 MDC56 CMDC4 A0 DQL3 MDC41
P3 A2 DQL5 H8 P3 A2 DQL5 H8 A1 DQL4 H3 P7 A1 DQL4 H3

1
CMDC14 N2 G2 MDC20 CMDC14 N2 G2 MDC1 CMDC20 P3 H8 MDC62 CMDC20 P3 H8 MDC45
CMDC17 A3 DQL6 MDC21 CMDC17 A3 DQL6 MDC4 R845 CMDC9 N2 A2 DQL5 MDC61 CMDC9 A2 DQL5 MDC40
P8 A4 DQL7 H7 P8 A4 DQL7 H7 A3 DQL6 G2 N2 A3 DQL6 G2
CMDC6 P2 CMDC6 P2 R848 DIS@ 1K_0402_1% DIS@ CMDC6 P8 H7 MDC59 CMDC6 P8 H7 MDC46
CMDC26 A5 CMDC26 A5 1K_0402_1% CMDC17 P2 A4 DQL7 CMDC17 A4 DQL7
R8 A6 R8 A6 A5 P2 A5
CMDC3 R2 D7 MDC15 CMDC3 R2 D7 MDC29 CMDC3 R8 CMDC3 R8

2
CMDC1 A7 DQU0 MDC11 CMDC1 A7 DQU0 MDC26 CMDC26 R2 A6 MDC35 CMDC26 A6 MDC48
T8 A8 DQU1 C3 T8 A8 DQU1 C3 A7 DQU0 D7 R2 A7 DQU0 D7
CMDC10 R3 C8 MDC13 CMDC10 R3 C8 MDC31 MEM_VREFC0 MEM_VREFC1 CMDC1 T8 C3 MDC39 CMDC1 T8 C3 MDC53
CMDC21 A9 DQU2 MDC9 CMDC21 A9 DQU2 MDC25 CMDC5 R3 A8 DQU1 MDC32 CMDC5 A8 DQU1 MDC51
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2 1 1 A9 DQU2 C8 R3 A9 DQU2 C8

1
0.1U_0402_10V6K~D

0.1U_0402_10V6K~D
CMDC5 R7 A7 MDC12 CMDC5 R7 A7 MDC30 DIS@ DIS@ CMDC19 L7 C2 MDC36 CMDC19 L7 C2 MDC54
CMDC22 A11 DQU4 MDC8 CMDC22 A11 DQU4 MDC27 R846 C984 R849 C985 CMDC10 R7 A10/AP DQU3 MDC33 CMDC10 A10/AP DQU3 MDC49
N7 A12 DQU5 A2 N7 A12 DQU5 A2 A11 DQU4 A7 R7 A11 DQU4 A7
CMDC18 T3 B8 MDC14 CMDC18 T3 B8 MDC28 1K_0402_1% DIS@ 1K_0402_1% DIS@ CMDC7 N7 A2 MDC38 CMDC7 N7 A2 MDC55
CMDC29 A13 DQU6 MDC10 CMDC29 A13 DQU6 MDC24 2 2 CMDC29 T3 A12 DQU5 MDC34 CMDC29 A12 DQU5 MDC50
T7 A14 DQU7 A3 T7 A14 DQU7 A3 A13 DQU6 B8 T3 A13 DQU6 B8
CMDC30 M7 CMDC30 M7 CMDC18 T7 A3 MDC37 CMDC18 T7 A3 MDC52

2
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU CMDC13 M7 A14 DQU7 CMDC13 A14 DQU7
A15/BA3 M7 A15/BA3 +1.5VSDGPU
CMDC12 M2 B2 CMDC12 M2 B2 +1.5VSDGPU
CMDC9 BA0 VDD CMDC9 BA0 VDD CMDC12 M2 CMDC12
N8 BA1 VDD D9 N8 BA1 VDD D9 BA0 VDD B2 M2 BA0 VDD B2
CMDC13 M3 G7 CMDC13 M3 G7 CMDC14 N8 D9 CMDC14 N8 D9
BA2 VDD BA2 VDD CMDC30 M3 BA1 VDD CMDC30 BA1 VDD
VDD K2 VDD K2 BA2 VDD G7 M3 BA2 VDD G7
VDD K8 VDD K8 VDD K2 VDD K2
N1 N1 +1.5VSDGPU +1.5VSDGPU K8 K8
CLKC0 VDD CLKC0 VDD VDD VDD
J7 CK VDD N9 J7 CK VDD N9 VDD N1 VDD N1
CLKC0# K7 R1 CLKC0# K7 R1 CLKC1 J7 N9 CLKC1 J7 N9
CK VDD CK VDD CK VDD CK VDD

1
C CMDC0 K9 R9 CMDC0 K9 R9 CLKC1# K7 R1 CLKC1# K7 R1 C
CKE/CKE0 VDD CKE/CKE0 VDD R850 R851 CMDC27 K9 CK VDD CMDC27 CK VDD
CKE/CKE0 VDD R9 K9 CKE/CKE0 VDD R9
+1.5VSDGPU +1.5VSDGPU 1K_0402_1% DIS@ 1K_0402_1% DIS@
CMDC25 K1 A1 CMDC25 K1 A1 +1.5VSDGPU +1.5VSDGPU
CMDC2 ODT/ODT0 VDDQ CMDC2 ODT/ODT0 VDDQ CMDC16 CMDC16
L2 A8 L2 A8 K1 A1 K1 A1

2
CMDC24 CS/CS0 VDDQ CMDC24 CS/CS0 VDDQ CMDC11 ODT/ODT0 VDDQ CMDC11 ODT/ODT0 VDDQ
J3 RAS VDDQ C1 J3 RAS VDDQ C1 L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
CMDC8 K3 C9 CMDC8 K3 C9 MEM_VREFC2 MEM_VREFC3 CMDC24 J3 C1 CMDC24 J3 C1
CAS VDDQ CAS VDDQ RAS VDDQ RAS VDDQ

0.1U_0402_10V6K~D
CMDC19 L3 D2 CMDC19 L3 D2 1 1 CMDC8 K3 C9 CMDC8 K3 C9
WE VDDQ WE VDDQ CAS VDDQ CAS VDDQ

1
0.1U_0402_10V6K~D
310mAVDDQ E9 E9 DIS@ DIS@ CMDC21 L3 D2 CMDC21 L3 D2
VDDQ R852 C986 R853 C987 WE VDDQ WE VDDQ
DQSC2 VDDQ F1
DQSC0
310mAVDDQ F1
1K_0402_1% DIS@ 1K_0402_1% DIS@
310mAVDDQ E9 310mAVDDQ E9
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2 VDDQ F1 VDDQ F1
DQSC1 DQSC3 2 2 DQSC7 DQSC5
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9 F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
DQSC4 C7 H9 DQSC6 C7 H9

2
DQSU VDDQ DQSU VDDQ
DQMC2 E7 A9 DQMC0 E7 A9
DQMC1 DML VSS DQMC3 DML VSS DQMC7 E7 DQMC5
D3 DMU VSS B3 D3 DMU VSS B3 DML VSS A9 E7 DML VSS A9
E1 E1 DQMC4 D3 B3 DQMC6 D3 B3
VSS VSS DMU VSS DMU VSS
VSS G8 VSS G8 VSS E1 VSS E1
DQSC#2 G3 J2 DQSC#0 G3 J2 G8 G8
DQSC#1 DQSL VSS DQSC#3 DQSL VSS DQSC#7 G3 VSS DQSC#5 VSS
B7 DQSU VSS J8 B7 DQSU VSS J8 DQSL VSS J2 G3 DQSL VSS J2
M1 M1 DQSC#4 B7 J8 DQSC#6 B7 J8
VSS VSS CLKC0 CLKC1 DQSU VSS DQSU VSS
VSS M9 VSS M9 25 CLKC0 25 CLKC1 VSS M1 VSS M1
VSS P1 VSS P1 VSS M9 VSS M9
CMDC28 T2 P9 CMDC28 T2 P9 R854 R855 P1 P1
RESET VSS RESET VSS DIS@ 240_0402_1% DIS@ 240_0402_1% CMDC28 T2 VSS CMDC28 VSS
VSS T1 VSS T1 RESET VSS P9 T2 RESET VSS P9
L8 T9 ZQC1 L8 T9 T1 T1
ZQ/ZQ0 VSS ZQ/ZQ0 VSS CLKC0# CLKC1# ZQC2 VSS ZQC3 VSS
ZQC0 25 CLKC0# 25 CLKC1# L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
243_0402_1%

243_0402_1%

J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1


B B
R856

R857

L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9 J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1

1
243_0402_1%

243_0402_1%
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1 L1 NC/CS1 VSSQ B9 L1 NC/CS1 VSSQ B9

R858

R859
DIS@
DIS@

L9 NCZQ1 VSSQ D8 L9 NCZQ1 VSSQ D8 J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1


E2 E2 L9 D8 L9 D8
2

VSSQ VSSQ DIS@ NCZQ1 VSSQ NCZQ1 VSSQ


VSSQ E8 VSSQ E8 VSSQ E2 VSSQ E2
F9 F9 E8 DIS@ E8

2
VSSQ VSSQ VSSQ VSSQ
VSSQ G1 VSSQ G1 VSSQ F9 VSSQ F9
VSSQ G9 VSSQ G9 VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9
96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 96-BALL 96-BALL
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96 SDRAM DDR3 SDRAM DDR3
K4B1G1646E-HC12_FBGA96 K4B1G1646E-HC12_FBGA96

+1.5VSDGPU
+1.5VSDGPU +1.5VSDGPU

+1.5VSDGPU

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
1000P_0402_50V7K

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M

4.7U_0603_6.3V6M
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1017

C1018

C1019

C1020

C1021

C1022

C1023

C1024

C1025
1 1 1 1 1 1 1 1 1

C1007

1U_0402_6.3V6K
C1008

1U_0402_6.3V6K
C1009

1U_0402_6.3V6K
C1010

1U_0402_6.3V6K
C1011

0.1U_0402_16V7K
C1012

0.1U_0402_16V7K
C1013

0.1U_0402_16V7K
C1014

0.1U_0402_16V7K
C1015

0.1U_0402_16V7K
C1016

0.1U_0402_16V7K
C993

C994

C995

C996

C997

1 1 1 1 1 1 1 1 1 1
C988

C989

C990

C991

C992

C1004

C1005

C1006

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C998

C999

C1000

C1001

C1002

C1003

2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 DIS@
A
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ A
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N11P-GV2H gDDR3
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 27 of 56
5 4 3 2 1
5 4 3 2 1

+3VS C475 SG@


0.1U_0402_16V4Z

+LCDVDD
LCD POWER CIRCUIT 1 2
+3V +3VS

1
W=60mils

NC
+5VS DGPU_SELECT# 2 4 IGPU_SELECT#
16,17,29 DGPU_SELECT# A Y IGPU_SELECT# 16

1
R349 1 U23

G
300_0603_5% R357 C463 INVT_PWM 2 8 U27
DPST_PWM_1 1A VCC INVTPWM SG@ SG@ 2
100K_0402_5% 5 3 1

3
4.7U_0805_10V4Z PWMSEL_1# 2A 1B R365 100K_0402_5%
1 1OE# 2B 6
2 IGPU_PWM_SELECT# 7 4 74AHC1G14GW_SOT3535

2
R353 2OE# GND

3
D D 1K_0402_5% S Q30 SN74CBTD3306CPWR_TSSOP8 +3VS C474 @ D
Q28 2 2 1 2 SG@ 0.1U_0402_16V4Z
G G 1 2
S 1 D AO3413L_SOT23-3

1
2N7002E-T1-GE3_SOT23-3 C466 +LCDVDD

1
W=60mils

1
D 0.047U_0402_16V7K

NC
PCH_ENVDD 2 Q29 2 1 SG@ 2 DGPU_EDIDSEL_R# 2 4 IGPU_EDIDSEL#
16 PCH_ENVDD 18 DGPU_EDIDSEL# A Y
G UMA@ 1 1 R366 0_0402_5%

G
1
S 2N7002E-T1-GE3_SOT23-3 C462 C459 U26

3
@ 1 @ 2
29 DGPU_EDIDSEL_R#

3
R351 4.7U_0805_10V4Z 0.1U_0402_16V4Z R364 100K_0402_5%
100K_0402_5% 2 2 74AHC1G14GW_SOT3535
2

+3VS C469 SG@


0.1U_0402_16V4Z
1 +5VS 1 2
D 0_0402_5% 091211 ADD R371 Fix CPT 4sec shut down flash issue

1
ENVDD 2 Q31
22 ENVDD
1

UMA@
G 2N7002E-T1-GE3_SOT23-3 R417

NC
DIS@ S DIS@ R371 1 SG@ 2 PWMSEL_1# 2 4 IGPU_PWM_SELECT#
17 DGPU_PWMSEL#
3

R367 100K_0402_5% R361 0_0402_5% A Y

G
100K_0402_5% 1 2 U22

2
UMA@ SG@
2

3
74AHC1G14GW_SOT3535

1
UMA ONLY@

OE#
P
2 4 DPST_PWM_1 1 2 INVTPWM
16 DPST_PWM A Y R358 0_0402_5%

G
U24 Reserved for UMA Only
C UMA@ C

3
74AHCT1G125GW_SOT353-5

DIS ONLY@
INVT_PWM 1 2
36 INVT_PWM
R356 0_0402_5%

VGA_PNL_PWM 1 @ 2
22 VGA_PNL_PWM
R360 0_0402_5%

1
SM010014520 3000ma 220ohm@100mhz DCR 0.04 R355
10K_0402_5%
+INVPWR_B+
W=60mils D1
UMA ONLY

2
L31 2 1 6 3 USB20_CMOS_N8
B+ CH3 CH2
FBMA-L11-201209-221LMA30T_0805

L30 2 1 2009/8/27 ADD SWITCHABLE


FBMA-L11-201209-221LMA30T_0805 +3VS 5
Vp Vn
2 SWITCHABLE +3VS
1 1
C471 C470 L B1 DIS

1
680P_0402_50V7K 68P_0402_50V8J SEL1 TXOUT0+ 0_0402_5% 2 UMA ONLY@
1 R416 PCH_TXOUT0+
USB20_CMOS_P8 TXOUT0- PCH_TXOUT0- PCH_TXOUT0+ 16
4 1 R15 0_0402_5% 2 UMA ONLY@
1 R412
2 2 CH4 CH1 SEL2 PCH_TXOUT0- 16
H B2 UMA 0_0603_5%
CM1293-04SO_SOT23-6 SG@ TXOUT1+ 0_0402_5% 2 UMA ONLY@
1 R405 PCH_TXOUT1+
TXOUT1- PCH_TXOUT1- PCH_TXOUT1+ 16
@ 0_0402_5% 2 UMA ONLY@
1 R410
PCH_TXOUT1- 16

0.1U_0402_16V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6K
TS3DV520ERHUR with 1 SEL pin U3
LCD/LED PANEL Conn. VCC
4
10
+3VS_SWITCH
1 1 1
TXOUT2+
TXOUT2-
0_0402_5% 2 UMA ONLY@
1
0_0402_5% 2 UMA ONLY@
1
R401
R399
PCH_TXOUT2+
PCH_TXOUT2- PCH_TXOUT2+ 16
B VCC PCH_TXOUT2- 16 B
W=60mils VGA_TXCLK+ 48 18
JLVDS1 VGA_TXCLK- 0B1 VCC TXCLK+ 0_0402_5% 2 UMA ONLY@ R393 PCH_TXCLK+
+LCDVDD
Place closed to JLVDS1 VGA_TXOUT2-
47 1B1 VCC 27
TXCLK-
1
PCH_TXCLK- PCH_TXCLK+ 16
1 +INVPWR_B+ 43 38 SG@ SG@ SG@ 0_0402_5% 2 UMA ONLY@
1 R396
1 +3VS VGA_TXOUT2+ 2B1 VCC 2 2 2 PCH_TXCLK- 16
41 G1 2 2 42 3B1 VCC 50
42 3 VGA_TXOUT1+ 37 56
G2 3 +LVDD_R @ VGA_TXOUT1- 4B1 VCC C63 C54 C66 I2CC_SCL 0_0402_5% 2 UMA ONLY@ R418 PCH_LCD_CLK
43 4 2 1 +LCDVDD 36 1 PCH_LCD_CLK 16
G3 4 R679 0_0603_5% VGA_TXOUT0- 5B1 TXCLK+ I2CC_SDA 0_0402_5% 2 UMA ONLY@ R420 PCH_LCD_DATA
44 5 1 1 1 32 2 1 PCH_LCD_DATA 16
G4 5 C464 C461 C458 VGA_TXOUT0+ 6B1 A0 TXCLK-
45 6 +LCDVDD 31 3
G5 6 VGA_LCD_CLK 7B1 A1 TXOUT2-
46
G6 7
7 +3VS 22
8B1 A2
7 5/4 PCH_LCD_CLK& PCH_LCD_DATA
INVTPWM 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z VGA_LCD_DATA TXOUT2+ +3VS
8 8
DISPOFF#
W=60mils 2 2 2
23 9B1 A3 8
TXOUT1+
Pull high 2.2K change to 4.7K
9 9 A4 11
10 I2CC_SCL 12 TXOUT1- R29 1 UMA@ 2 4.7K_0402_5% PCH_LCD_CLK
10 I2CC_SDA A5 TXOUT0-
11 11 A6 14
12 15 TXOUT0+ R32 1 UMA@ 2 4.7K_0402_5% PCH_LCD_DATA
12 DAC_BRIG 36 A7
13 TXOUT0- PCH_TXCLK+ 46 19 I2CC_SCL
13 TXOUT0+ DAC_BRIG PCH_TXCLK- 0B2 A8 I2CC_SDA
14 1 2 45 20
14 C467 220P_0402_50V7K PCH_TXOUT2- 1B2 A9
15 41
15 TXOUT1- INVTPWM PCH_TXOUT2+ 2B2 DGPU_SELECT#
16 1 2 40 17
16
17
18
17
18
19
TXOUT1+

TXOUT2-
DISPOFF#
C468
1
C473
2
220P_0402_50V7K

220P_0402_50V7K
PCH_TXOUT1+
PCH_TXOUT1-
PCH_TXOUT0-
35
34
30
3B2
4B2
5B2
SEL

GND
1
6 TXOUT0+
Discrete ONLY
0_0402_5% 2 DIS ONLY@
1 R26 VGA_TXOUT0+
19 6B2 GND VGA_TXOUT0+ 23
20 TXOUT2+ PCH_TXOUT0+ 29 9 TXOUT0- 0_0402_5% 2 DIS ONLY@
1 R24 VGA_TXOUT0-
20 PCH_LCD_CLK 7B2 GND VGA_TXOUT0- 23
21 25 13
21 TXCLK- PCH_LCD_DATA 8B2 GND TXOUT1+ 0_0402_5% 2 DIS ONLY@ R22 VGA_TXOUT1+
22 22 26 9B2 GND 16 1 VGA_TXOUT1+ 23
23 TXCLK+ DISPOFF# 0_0402_5% 2 1 R363 21 TXOUT1- 0_0402_5% 2 DIS ONLY@
1 R23 VGA_TXOUT1-
23 BKOFF# 36 GND VGA_TXOUT1- 23
24 DGPU_EDIDSEL_R# 54 24
24 10K_0402_5% 2 SEL2 GND TXOUT2+ VGA_TXOUT2+
25 25 1 R362 GND 28 0_0402_5% 2 DIS ONLY@
1 R21
VGA_TXOUT2+ 23
26 33 TXOUT2- 0_0402_5% 2 DIS ONLY@
1 R20 VGA_TXOUT2-
26 GND VGA_TXOUT2- 23
27 0_0402_5% 2 @ 1 R368 52 39
27 LOCAL_DIM 36 NC GND
28 5 44 TXCLK+ 0_0402_5% 2 DIS ONLY@
1 R18 VGA_TXCLK+
28 NC GND VGA_TXCLK+ 23
29 51 49 TXCLK- 0_0402_5% 2 DIS ONLY@
1 R19 VGA_TXCLK-
29 NC GND VGA_TXCLK- 23
30 0_0402_5% 2 @ 1 R369 53
A 30 COLOR_ENG_EN 36 GND A
31 57 55
31 Thermal_GND GND I2CC_SCL 0_0402_5% 2 DIS ONLY@ R419 VGA_LCD_CLK
32 32 1 VGA_LCD_CLK 22
33 PI3LVD400ZFEX_TQFN56_11X5 I2CC_SDA 0_0402_5% 2 DIS ONLY@
1 R421 VGA_LCD_DATA
33 VGA_LCD_DATA 22
34 SG@
34
35 35 1109 RF request
36
36 PI3LVD400ZFE with 2 SEL pin
37 37 +3VS
38 USB20_CMOS_N8 R1 2 1 0_0402_5%
38
39 39 USB20_CMOS_P8 R2 2 1 0_0402_5%
USB20_N8 17
USB20_P8 17
Security Classification Compal Secret Data Compal Electronics, Inc.
40 40 1 1 Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

IPEX_20143-040E-20F C805 C806


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LVDS Connector
CONN@ 22P_0402_50V8J 22P_0402_50V8J Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
@ 2 2 Custom
@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 28 of 56
5 4 3 2 1
A B C D E

CRT Connector D17 D16 D14


W=40mils
+5VS +R_CRT_VCC +CRT_VCC
BAV99_SOT-23 BAV99_SOT-23 BAV99_SOT-23
D2 F1 W=40mils

1
2 1 1 2

CH491DPT_SOT23-3 1.1A_6V_SMD1812P110TF
1
C171

3
0.1U_0402_16V4Z
2
SM010005220 600ma 80ohm@100mhz DCR 0.25 +3VS
1 1

Change to 0 ohm for Discrete

CRT_R L47 1 2 CRT_R_1 L48 1 2 FCM2012CF-800T06_2P CRT_R_2 JCRT1


FCM2012CF-800T06_2P 6
11
CRT_G L40 1 2 CRT_G_1 L41 1 2 FCM2012CF-800T06_2P CRT_G_2 1
FCM2012CF-800T06_2P 7
12
CRT_B L38 1 2 CRT_B_1 L39 1 2 FCM2012CF-800T06_2P CRT_B_2 2
FCM2012CF-800T06_2P 8
13

1
1 1 1 1 1 1 1 1 1 3
R466 R464 R446 C607 C592 C567 C618 C598 C590 9
C603 C593 C569 14 G 16
150_0402_1% 150_0402_1% 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J 4 17
2 2 2 2 2 2 2 2 2 G
10

2
10P_0402_50V8J 10P_0402_50V8J 22P_0402_50V8J 15
22P_0402_50V8J 1 5
150_0402_1% 10P_0402_50V8J 22P_0402_50V8J Change to 12pf for Discrete C110
C-H_13-12201513CP
100P_0402_50V8J CONN@
2
Change to 15pf for Discrete SM010012010 300ma 120ohm@100mhz DCR 0.4 CRT_DET# 18
1 2 CRT_HSYNC_2
+CRT_VCC L2 MBC1608121YZF_0603 DSUB_12

2
C194 1 2 0.1U_0402_16V4Z R67 2 1 10K_0402_5% 1 2 CRT_VSYNC_2 1 R41
L1 MBC1608121YZF_0603 1 1 100K_0402_5%
@

1
U7 C178 C164 DSUB_15

1
2 10P_0402_50V8J 10P_0402_50V8J C208 2 2

OE#
P
CRT_HSYNC 2 4 CRT_HSYNC_1 2 2 68P_0402_50V8J 1
A Y

G
C126 +CRT_VCC
74AHCT1G125GW_SOT353-5 68P_0402_50V8J

3
2
+CRT_VCC

C111 1 2 0.1U_0402_16V4Z

1
U5

OE#
P
CRT_VSYNC 2 4 CRT_VSYNC_1
A Y

G
D33 D25
74AHCT1G125GW_SOT353-5 +CRT_VCC

3
DAN217_SC59 DAN217_SC59

1
+3VS

1
R48 R78
4.7K_0402_5% 4.7K_0402_5%

2
2
G
+3VS
SWITCHABLE CRT_DDC_DATA 3 1 DSUB_12
+CRT_VCC
0.1U_0402_16V4Z

D
Q3
2009/08/27 1 1 1 1

2
G
C273 C290 C271 C280 2N7002E-T1-GE3_SOT23-3
SG@ SG@ SG@ SG@
0.1U_0402_16V4Z CRT_DDC_CLK 3 1 DSUB_15
3 2 2 2 2 3

D
0.1U_0402_16V4Z 0.1U_0402_16V4Z Q2
20091214 For NV Recommand 2N7002E-T1-GE3_SOT23-3

+3VS

U10
4 1 CRT_R
VDD A0 CRT_G
16 VDD A1 2
CRT_B
23
VDD A2
5
CRT_HSYNC UMA only
29
32
VDD A3 6
7 CRT_VSYNC Discrete only
VDD A4
VGA_CRT_R 27 8 VGA_CRT_R R537 2 DIS ONLY@
1 0_0402_5% CRT_R PCH_CRT_R R536 2 UMA ONLY@
1 0_0402_5% CRT_R
0B1 SEL1 DGPU_SELECT# 16,17,28 22 VGA_CRT_R 16 PCH_CRT_R
VGA_CRT_G 25
VGA_CRT_B 1B1 VGA_CRT_G R535 2 DIS ONLY@ 0_0402_5% CRT_G PCH_CRT_G R534 2 UMA ONLY@ 0_0402_5% CRT_G
22 22 VGA_CRT_G 1 16 PCH_CRT_G 1
VGA_CRT_HSYNC 2B1 CRT_DDC_CLK
20 9
VGA_CRT_VSYNC 3B1 A5 CRT_DDC_DATA VGA_CRT_B R533 2 DIS ONLY@ 0_0402_5% CRT_B PCH_CRT_B R532 2 UMA ONLY@ 0_0402_5% CRT_B
18 10 22 VGA_CRT_B 1 16 PCH_CRT_B 1
VGA_DDC_CLK 4B1 A6
12
VGA_DDC_DATA 5B1 VGA_CRT_HSYNC R531 2 DIS ONLY@ 0_0402_5% CRT_HSYNC PCH_CRT_HSYNC R530 2 UMA ONLY@ 0_0402_5% CRT_HSYNC
14 6B1 SEL2 30 DGPU_EDIDSEL_R# 28 22 VGA_CRT_HSYNC 1 16 PCH_CRT_HSYNC 1
VGA_CRT_VSYNC R529 2 DIS ONLY@
1 0_0402_5% CRT_VSYNC PCH_CRT_VSYNC R528 2 UMA ONLY@
1 0_0402_5% CRT_VSYNC
PCH_CRT_R 22 VGA_CRT_VSYNC 16 PCH_CRT_VSYNC
26
PCH_CRT_G 0B2 VGA_DDC_CLK R527 2 DIS ONLY@ 0_0402_5% CRT_DDC_CLK PCH_CRT_CLK R544 2 UMA ONLY@ 0_0402_5% CRT_DDC_CLK
24 22 VGA_DDC_CLK 1 16 PCH_CRT_CLK 1
PCH_CRT_B 1B2
21 2B2 GND 3
PCH_CRT_HSYNC 19 11 VGA_DDC_DATA R526 2 DIS ONLY@
1 0_0402_5% CRT_DDC_DATA PCH_CRT_DATA R543 2 UMA ONLY@
1 0_0402_5% CRT_DDC_DATA
PCH_CRT_VSYNC 3B2 GND 22 VGA_DDC_DATA 16 PCH_CRT_DATA
17
4B2 GND
28 PCH DDC PU 2.2K on Page 17
PCH_CRT_CLK 13 31
PCH_CRT_DATA 5B2 GND
15 33
6B2 GPAD
4 PI3V712-AZLEX_TQFN32_6X3~D VGA_DDC_DATA and VGA_DDC_CLK Pull high at Page22 4
SG@

L B1 DIS
Security Classification Compal Secret Data Compal Electronics, Inc.
H B2 UMA Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 29 of 56
A B C D E
5 4 3 2 1

+3VS
+3VS

HDMI connector

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R590 1 2 0_0603_5% W=40mils R616
1 1 1 1 1 1 1 10K_0402_5% JHDMI1
C727 C725 C730 C731 C720 C721 C409 +HDMI_5V_OUT HDMI_HPD 19
UMA ONLY@ HP_DET
D21 F2 +HDMI_5V_OUT 18

2
UMA ONLY@ UMA ONLY@ UMA ONLY@ UMA ONLY@ UMA ONLY@ UMA ONLY@ UMA ONLY@ +5V
+5VS 2 1 +HDMI_5V 1 2 OE# 17 DDC/CEC_GND
2
0.1U_0402_16V4Z 2 2 2 2 2 2 @ HDMI_SDATA
1 D 16 SDA

1
CH491DPT_SOT23-3 1.1A_6V_SMD1812P110TF HDMI_SCLK 15
0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C707 Q43 HDMI_HPD SCL
2 14 Reserved
D UMA ONLY@ G 1 13 D
CEC

1
0.1U_0402_16V4Z 2 S C410 HDMI_R_CK- 12 20

3
R256 CK- GND
11 CK_shield GND 21
2N7002E-T1-GE3_SOT23-3 0.1U_0402_16V4Z HDMI_R_CK+ 10 22
100K_0402_5% 2 HDMI_R_D0- CK+ GND
9 D0- GND 23
U45 8

2
HDMI_R_D0+ D0_shield
7 D0+
HDMI_R_D1- 6
+3VS OE# @ D1-
OE# 25 1 2 5 D1_shield
R618 0_0402_5% HDMI_R_D1+ 4
D23 CH751H-40PT_SOD323-2 HDMI_R_D2- D1+
2 VCC3V 3 D2-
11 28 HDMI_SCLK R625 1 2 2.2K_0402_5%1 2 +HDMI_5V_OUT 2
VCC3V SCL_SINK HDMI_R_D2+ D2_shield
15 VCC3V 1 D2+
21 29 HDMI_SDATA R627 1 2 2.2K_0402_5%1 2
VCC3V SDA_SINK SUYIN_100042MR019S153ZL
26 VCC3V
33 D24 CH751H-40PT_SOD323-2 CONN@
VCC3V HDMI_HPD
40 VCC3V HPD_SINK 30
46 VCC3V
32 R629 1 UMA ONLY@
2 2.2K_0402_5% +3VS
R269 @ DDC_EN
+3VS 1 2 2.2K_0402_5% R637 1 UMA ONLY@
2 2.2K_0402_5% +3VS
R253 1 @ 2 2.2K_0402_5% R638 1 UMA ONLY@
2 2.2K_0402_5%
R273 1 UMA ONLY@
2 2.2K_0402_5% CG_0 3 34 EQ_S0 R635 1 @ 2 2.2K_0402_5% SM070001310 400ma 90ohm@100mhz DCR 0.3
R252 CG_0 EQ_0
1 UMA ONLY@
2 2.2K_0402_5% CG_1 4 CG_1 EQ_1 35 EQ_S1 R666 1 @ 2 2.2K_0402_5%

Connection to 3.4K HDMI_CLK+ R180 1 2 0_0402_5% HDMI_R_CK+


R235 UMA ONLY@ 1 2 3.3K_0402_5% REXT 6
external resistor. REXT
1 1 2 2
HPD_SOURCE 7 EQ0 EQ1 Equalization L24
R223 UMA ONLY@ HPD#
+3VS 1 2 2.2K_0402_5% W CM-2012-900T_0805
C SDVO_SDATA 8 @ 4 3 C
16 SDVO_SDATA
R219 UMA ONLY@ SDA 0 0 12dB 4 3
1 2 2.2K_0402_5%
SDVO_SCLK 9 0 1 9dB HDMI_CLK- R177 1 2 0_0402_5% HDMI_R_CK-
16 SDVO_SCLK SCL 1 0 6dB
+3VS R211 1 @ 2 2.2K_0402_5% 1 1 3dB (default)
R209 UMA ONLY@
1 2 2.2K_0402_5% CG_2 10 CG_2 HDMI_TX0+ R174 1 0_0402_5% HDMI_R_D0+
2

HDMI_TX2+ 13 48 1 2
OUT_D4+ IN_D4+ PCH_TMDS_D2 16 1 2
CG0 CG1 CG2 Swing Pre-amp Slew-rate HDMI_TX2- 14 47 L23
OUT_D4- IN_D4- PCH_TMDS_D2# 16
W CM-2012-900T_0805
0 0 0 450 0 0 HDMI_TX1+ 16 45 @ 4 3
OUT_D3+ IN_D3+ PCH_TMDS_D1 16 4 3
HDMI_TX1- 17 44
0 0 1 420 0 -3db OUT_D3- IN_D3- PCH_TMDS_D1# 16
HDMI_TX0- R168 1 2 0_0402_5% HDMI_R_D0-
0 1 0 450 0 -3db (default) HDMI_CLK+ 19 OUT_D2+ IN_D2+ 42 PCH_TMDS_CK 16
HDMI_CLK- 20 41
0 1 1 460 0 -4db OUT_D2- IN_D2- PCH_TMDS_CK# 16
HDMI_TX1+ R183 1 0_0402_5% HDMI_R_D1+
2
1 0 0 340 0 0 HDMI_TX0+ 22 39
OUT_D1+ IN_D1+ PCH_TMDS_D0 16
0 HDMI_TX0- 23 38 1 2
1 0 1 400 2db OUT_D1- IN_D1- PCH_TMDS_D0# 16
L25 1 2
1 1 0 400 2db 0 W CM-2012-900T_0805
@ 4 3
1 1 1 420 0 0 4 3

2
1

2.2K_0402_5%

2.2K_0402_5%
GND @ @ 20091216 HDMI_TX1- R182 0_0402_5% HDMI_R_D1-
5 GND 1 2
12 49
18
GND GND For ASMEDIA AOC
GND
Panel Bug

R719

R718
+3VS R228 1 @ 2 10K_0402_5% 24 HDMI_TX2+ R190 1 2 0_0402_5% HDMI_R_D2+

1
GND
27 GND
16 PCH_DPB_HPD 1 UMA ONLY@
2 HPD_SOURCE 31 GND 1 1 2 2
B R230 0_0402_5% L26 B
36 GND
37 W CM-2012-900T_0805
@ GND @
1 2 43 GND 4 4 3 3
R234 10K_0402_5% ASM1442 PN: SA00003GT00
HDMI_TX2- R188 1 2 0_0402_5% HDMI_R_D2-
ASM1442T_QFN48_7X7 UMA ONLY@
C379 DIS@ 2 1 0.1U_0402_16V7K HDMI_TX2- R613 1 DIS@ 2 499_0402_1%
23 VGA_HDMI_TXD2-
C378 DIS@ 2 1 0.1U_0402_16V7K HDMI_TX2+ R614 1 DIS@ 2 499_0402_1%
23 VGA_HDMI_TXD2+
C381 DIS@ 2 1 0.1U_0402_16V7K HDMI_TX1- R611 1 DIS@ 2 499_0402_1%
23 VGA_HDMI_TXD1-
C380 DIS@ 2 1 0.1U_0402_16V7K HDMI_TX1+ R612 1 DIS@ 2 499_0402_1%
23 VGA_HDMI_TXD1+
C385 DIS@ 2 1 0.1U_0402_16V7K HDMI_TX0- R607 1 DIS@ 2 499_0402_1%
23 VGA_HDMI_TXD0-
C384 DIS@ 2 1 0.1U_0402_16V7K HDMI_TX0+ R608 1 DIS@ 2 499_0402_1%
23 VGA_HDMI_TXD0+
C383 DIS@ 2 1 0.1U_0402_16V7K HDMI_CLK- R609 1 DIS@ 2 499_0402_1%
+3VSDGPU +3VSDGPU 23 VGA_HDMI_TXC-
C382 DIS@ 2 1 0.1U_0402_16V7K HDMI_CLK+ R610 1 DIS@ 2 499_0402_1%
23 VGA_HDMI_TXC+
1

C
D

1
Pull high at VGA side Q52 2 1 DIS@ 2 HDMI_HPD
MMBT3904_G_SOT23-3 B R634 150K_0402_5% 2
+3VSDGPU
2

1
1109 RF request DIS@ E G
G
3
2
G

22 VGA_HDMI_DET 1 2 Q42 S

3
R714 18 DGPU_HPD_INT# 1 3 @ R370 DIS@
1

3 1 HDMI_SCLK 0_0402_5%
D

23 VGA_HDMI_SCLK
DIS@ DIS@ R715 Q44 100K_0402_5%
S

2
2
G

A
Q12 2N7002E-T1-GE3_SOT23-3 10K_0402_5% 2N7002E-T1-GE3_SOT23-3 2N7002E-T1-GE3_SOT23-3 A
C804 DIS@ SG@
23 VGA_HDMI_SDATA 3 1 HDMI_SDATA 12P_0402_50V8J
2

DIS@ 2 @
S

1
Q13 2N7002E-T1-GE3_SOT23-3
C803
Place closed to JHDMI1 12P_0402_50V8J
2 @ Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/08/01 Deciphered Date 2010/08/01 Title
DDC to HDMI CONN HDMI Level Shift & Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic
Date: Tuesday, December 22, 2009 Sheet 30 of 56
5 4 3 2 1
5 4 3 2 1

D D

SATA HDD1 Conn.


CL 4.0 mm
JHDD1

1 GND
13 SATA_PTX_DRX_P0 SATA_PTX_DRX_P0 C753 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 2
SATA_PTX_DRX_N0 C751 1 SATA_PTX_C_DRX_N0 A+
13 SATA_PTX_DRX_N0 2 0.01U_0402_16V7K 3 A-
4
SATA_DTX_C_PRX_N0 C749 1 SATA_DTX_PRX_N0 GND
2 0.01U_0402_16V7K 5 B-
13 SATA_DTX_C_PRX_N0 SATA_DTX_C_PRX_P0 C747 1 SATA_DTX_PRX_P0
2 0.01U_0402_16V7K 6
13 SATA_DTX_C_PRX_P0 B+
7
+3VS GND

1 +3VS 8
C745 V33
9 V33
10
0.1U_0402_16V4Z V33
11
2 GND
12
GND
13 GND
R669 1 2 0_0805_5% +5VS_HDD1 14
+5VS V5
100mils 15
V5
16 V5
17
10U_0805_10V4Z 0.1U_0402_16V4Z GND
18
Reserved
19 GND
1 1 1 1 20 V12
C735 C734 C733 C732 21 24
V12 GND
22 23
C V12 GND C
2 2 2 2
SANTA_192301-1
1U_0402_6.3V4Z 1000P_0402_50V7K CONN@

SATA ODD Conn.


JODD1

1
C687 1 SATA_PTX_C_DRX_P1 GND
13 SATA_PTX_DRX_P1 2 0.01U_0402_16V7K 2
C685 1 SATA_PTX_C_DRX_N1 A+
13 SATA_PTX_DRX_N1 2 0.01U_0402_16V7K 3
B A- B
4 GND
C680 1 2 0.01U_0402_16V7K SATA_DTX_PRX_N1 5
13 SATA_DTX_C_PRX_N1 SATA_DTX_PRX_P1 B-
C678 1 2 0.01U_0402_16V7K 6
13 SATA_DTX_C_PRX_P1 B+
7 GND

R516 1 @ 2 1K_0402_1% 8
DP
9
R105 1 +5VS_ODD +5V
+5VS 2 0_0805_5% 10 17
+5V GND
80mils 11 MD GND 16
12 GND GND 15
13 14
GND GND
10U_0805_10V4Z 0.1U_0402_16V4Z
OCTEK_SLS-13SB1G_RV
1 1 1 1 CONN@
C642 C654 C653 C643

2 2 2 2
Place caps. near ODD CONN.
1U_0402_6.3V4Z 1000P_0402_50V7K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD & ODD Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 31 of 56
5 4 3 2 1
5 4 3 2 1

+3V_LAN
60mil
+3VALW R599 1 2

0_1206_5%
1 1
C716 C715

4.7U_0603_6.3V6K
D U39 2 2 D
0.1U_0402_16V4Z
+1.2V_LAN +LAN_BIASVDDH
091211 EMI add 1000P +3V_LAN 42 VDDC BIASVDDH 25

6 14 +LAN_XTALVDDH
VDDC XTALVDDH

1000P_0402_50V7K
4.7U_0603_6.3V6K

1 1 1 1 2 2 15
VDDC
1000P_0402_50V7K
0.1U_0402_16V4Z

0.1U_0402_16V4Z

C697 C701 C333 C705 C492 C493 41 VDDC +LAN_AVDDH


AVDDH 30
0.1U_0402_16V4Z

2 2 2 2 1 1 SPROM_CLK SPROM_DOUT
AVDDH 36
(EECLK) (EEDATA)
+LAN_AVDDL 27
AVDDL LAN_MIDI3- On chip 1 0
33 37 LAN_MIDI3- 33
AVDDL TRD3_N
39
AVDDL LAN_MIDI3+
38 LAN_MIDI3+ 33
TRD3_P AT24C02 1 1

35 LAN_MIDI2-
TRD2_N LAN_MIDI2- 33 +3V_LAN
34 LAN_MIDI2+
+LAN_GPHYPLLVDDL TRD2_P LAN_MIDI2+ 33
24 C322 1 2 0.1U_0402_16V4Z
GPHY_PLLVDDL
31 LAN_MIDI1- @
TRD1_N LAN_MIDI1- 33

2
32 LAN_MIDI1+ R195 R193
TRD1_P LAN_MIDI1+ 33
1K_0402_1% 1K_0402_1%
+LAN_PCIEPLLVDD 18
PCIE_PLLVDDL @
29 LAN_MIDI0- U12 @
LAN_MIDI0- 33

1
TRD0_N
21 PCIE_PLLVDDL 8 VCC A0 1
28 LAN_MIDI0+ 7 2
TRD0_P LAN_MIDI0+ 33 SPROM_CLK WP A1
6 3
C SPROM_DOUT SCL NC C
5 SDA GND 4

AT24C02_SO8

2
LINKLED# 48 2 1 LAN_LINK# 33
R595 R196 R194
0.1U_0402_16V7K 47 0_0402_5% 1K_0402_1% 1K_0402_1%
PCIE_DTX_PRX_P1 SPD100LED#
14 PCIE_DTX_C_PRX_P1 1 2 C699 17 PCIE_TXD_P @
1 2 C700 PCIE_DTX_PRX_N1 16 46
14 PCIE_DTX_C_PRX_N1

1
PCIE_TXD_N SPD1000LED#
22 PCIE_RXD_P
0.1U_0402_16V7K 23 45 2 1
LAN_PME# PCIE_RXD_N TRAFFICLED# R594 LAN_ACTIVITY# 33
14 PCIE_PTX_C_DRX_P1 4 WAKE# SM010005500 500ma 600ohm@100mhz DCR 0.38
LAN_RESET# 2 0_0402_5% 20mil
14 PCIE_PTX_C_DRX_N1 REST#
20 L22
R592 1 @ PCIE_REFCLK_P +LAN_XTALVDDH
15,34 PCH_PCIE_WAKE# 2 0_0402_5% 19 1 2 +3V_LAN
R589 1 PCIE_REFCLK_N
36 EC_PME# 2 0_0402_5% 1 BLM18AG601SN1D_2P
+3V_LAN R587 1 2 4.7K_0402_5% C301
0.1U_0402_16V4Z
R597 1 2 0_0402_5% 20mil
5,17,21,36 PLT_RST# 2
5 L64
MODE +LAN_BIASVDDH
14 CLK_PCIE_LAN 1 2
1 BLM18AG601SN1D_2P
14 CLK_PCIE_LAN#
C703
0.1U_0402_16V4Z

SPROM_DOUT
20mil 2
43
EEDATA L66
44 SPROM_CLK +LAN_AVDDH 1 2
R175 1 EECLK
+3VS 2 1K_0402_5% 40 1 1 BLM18AG601SN1D_2P
VMAIN_PRSINT C712 C706
R596 1 2 10K_0402_5% 1
LOW_PWR 0.1U_0402_16V4Z 0.1U_0402_16V4Z
40mil L65 2 2
B +1.2V_LAN_OUT B
SR_LX 11 1 2 +1.2V_LAN
4.7UH_PG031B-4R7MS_1.1A_20% SM010005500 500ma 600ohm@100mhz DCR 0.38
LAN_XTALO_R 13 8 1 1 20mil
XTALO SR_VFB C708 L63
LAN_XTALI 12 C710 +LAN_PCIEPLLVDD 1 2 +1.2V_LAN
XTALI 0.1U_0402_16V4Z 10U_0805_10V4Z BLM18AG601SN1D_2P
2 2
1 1
C302 C695
R575
1 2 LAN_RDAC 26 0.1U_0402_16V4Z 4.7U_0603_6.3V6K
RDAC 2 2
SR_VDDP 10 +3V_LAN
1.24K_0402_1% 1 1
9 C318 C311
SR_VDD
20mil
L62
3 2 2 +LAN_GPHYPLLVDDL 1 2
14 LAN_CLKREQ# CLKREQ# +1.2V_LAN
4.7U_0603_6.3V6K 0.1U_0402_16V4Z BLM18AG601SN1D_2P
7 1 1
NC C698 C696
PAD

0.1U_0402_16V4Z 4.7U_0603_6.3V6K
2 2
49

BCM57780A0KMLG_QFN48_7X7
20mil
L21
+LAN_AVDDL 1 2 +1.2V_LAN
BLM18AG601SN1D_2P
1 1
LAN_XTALI C709 C312

LAN_XTALO_R 0.1U_0402_16V4Z 4.7U_0603_6.3V6K


A 2 2 A
1

R571
200_0402_1%
2

Y3
1 2 LAN_XTALO Security Classification Compal Secret Data Compal Electronics, Inc.
1 1 Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title
25MHZ_20PF_7A25000012
C704 C702
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Broadcom BCM57780
27P_0402_50V8J 27P_0402_50V8J Size Document Number Rev
2 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 32 of 56
5 4 3 2 1
5 4 3 2 1

LAN Connector

D D

T16

1 TCT1 MCT1 24
32 LAN_MIDI0+ LAN_MIDI0+ 2 23 RJ45_MIDI0+
LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0-
32 LAN_MIDI0- 3 TD1- MX1- 22 +3V_LAN 2 1
R518 1K_0402_5% 1
4 TCT2 MCT2 21
32 LAN_MIDI1+ LAN_MIDI1+ 5 20 RJ45_MIDI1+ 220P_0402_50V7K
LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1- LAN_ACTIVITY# C663
32 LAN_MIDI1- 6 TD2- MX2- 19
LAN_LINK# 2 C656 68P_0402_50V8J
JRJ45
7 18 @
LAN_MIDI2+ TCT3 MCT3 RJ45_MIDI2+
32 LAN_MIDI2+ 8 TD3+ MX3+ 17 2 1 9 Green LED+
32 LAN_MIDI2- LAN_MIDI2- 9 16 RJ45_MIDI2-
TD3- MX3- LAN_LINK#
32 LAN_LINK# 10 Green LED-

2
10 TCT4 MCT4 15
32 LAN_MIDI3+ LAN_MIDI3+ 11 14 RJ45_MIDI3+ D22 RJ45_MIDI0+ 1 14
LAN_MIDI3- TD4+ MX4+ RJ45_MIDI3- PR1+ SHLD1
32 LAN_MIDI3- 12 TD4- MX4- 13 PJDLC05C_SOT23-3 SHLD2 13
@ RJ45_MIDI0- 2 PR1-
RJ45_MIDI1+ 3 PR2+

1
350UH_IH-037-2
RJ45_MIDI2+ 4
C R549 R541 PR3+ C
1 1 1 1

1
C671 C681 C686 C690 75_0402_1% 75_0402_1% RJ45_MIDI2- 5 PR3-

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z RJ45_MIDI1- 6
2 2 2 2 PR2-
R525 R522 RJ45_MIDI3+ 7
0.1U_0402_16V4Z 0.1U_0402_16V4Z 75_0402_1% 75_0402_1% PR4+
RJ45_MIDI3- 8

2
PR4-
RJ45_GND 2 1 11
+3V_LAN Yellow LED+
Place close to TCT pin R140 1K_0402_5% 1
40mil LAN_ACTIVITY# 12
220P_0402_50V7K 32 LAN_ACTIVITY# Yellow LED-
C297 68P_0402_50V8J
BOTHHAND: S X'FORM_ GST5009-D LF LAN, SP050006B00 2 SANTA_130451-K
2 1
TIMAG:S X'FORM_ IH-160 LAN , SP050006F00 @ CONN@
C292

RJ45_GND 1 2 LANGND 40mil


1 1
C661
1000P_1206_2KV7K C660 C659
4.7U_0603_6.3V6K
2 2

0.1U_0402_16V4Z

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN Magnetic & RJ45
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 33 of 56
5 4 3 2 1
A B C D E

+3VS 2
R302
1
0_1206_5%
+3VS_W LAN For Wireless LAN
60mil
+3VS_W LAN +1.5VS +3VS_W LAN

1 1 1 1 1 1
C440 C423 C452 C441 C434 C442

4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z


Mini Card Power Rating
2 2 2 2 2 2
1 Power Primary Power (mA) Auxiliary Power (mA) 1

Peak Normal Normal


JMINI1 +3VS 1000 750
PCH_PCIE_W AKE# R323 1 @ 2 0_0402_5% 1 2 +3VS_W LAN
15,32 PCH_PCIE_W AKE# 1 2
(WLAN_BT_DATA) 3 4 +3V 330 250 250 (wake enable)
(WLAN_BT_CLK) 3 4
5 5 6 6 +1.5VS
14 MINI1_CLKREQ# 7 7 8 8 +1.5VS 500 375 5 (Not wake enable)
9 9 10 10
14 CLK_PCIE_MINI1# 11 11 12 12
14 CLK_PCIE_MINI1 13 13 14 14
15 15 16 16

17 17 18 18
19 20 W L_OFF#
19 20 W L_OFF# 36
21 22 PLT_RST_BUF#
21 22 PLT_RST_BUF# 17
14 PCIE_DTX_C_PRX_N2 23 24 R303 1 2 0_0603_5% +3VS
23 24 R299 1 @
14 PCIE_DTX_C_PRX_P2 25 25 26 26 2 0_0603_5% +3V
27 28 0_0402_5%
27 28 MINI1_SMBCLK R292 1 @
29 29 30 30 2 PCH_SMBCLK 12,14,21
31 32 MINI1_SMBDATA 1 @ 2 PCH_SMBDATA 12,14,21
14 PCIE_PTX_C_DRX_N2 31 32
33 34 R288 0_0402_5%
14 PCIE_PTX_C_DRX_P2 33 34
35 35 36 36 USB20_N12 17
37 37 38 38 USB20_P12 17
+3VS_W LAN 39 39 40 40
41 42 (WWAN_LED#) R291 1 2 0_0402_5%
41 42
43 43 44 44 (WLAN_LED#) MINI1_LED# 36
2 45 46 2
0_0402_5% 45 46
47 47 48 48 (9~16mA)

1
R280 1 2 E51TXD_P80DATA1_R 49 50
36 E51TXD_P80DATA 49 50
E51RXD_P80CLK 51 52 R285
36 E51RXD_P80CLK 51 52
100K_0402_5%
G1
G2
G3
G3

2
ACES_88910-5204
53
54
55
56
CONN@
+3VS_W LAN
4 mm High

+3VS_W W AN

1
C460
3G@
2
0.1U_0402_16V4Z For 3G / GPS
3 +3VS_W W AN 3

To 3G Module Connect LS-5895

2
+3VS_W W AN R350
+3VS +3VS_W W AN (Port 9) 100K_0402_5%
Peak: 2.75A JP4 @
1
Normal: 1.1A 1
1
2 2
3 W W AN_OFF#
3 W W AN_OFF# 36
1 3G@ 2 4 4 W W AN_LED# 36
R352 0_1206_5% 5
5
1 1 1 6 6 USB20_N13 17
7 7 USB20_P13 17
C465 + C801 C173 8
@ 3G@ 3G@ 8
9 9 USB20_N10 17
150U_B2_6.3VM_R35M 2 2 10U_0603_6.3V6M
10 10 USB20_P10 17
2
GND 11
47P_0402_50V8J 12
GND
1109 RF request ACES_87036-1001-CP
Close to WWAN CONN CONN@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN & TV-Tuner)
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 34 of 56
A B C D E
A B C D E

+3V
+3V

+5VALW

1
+USB_VCCB
+5VALW

1
+USB_VCCA U46
U17 1 8 R681
R250 GND VOUT 100K_0402_5%
1 GND VOUT 8 2 VIN VOUT 7
2 7 100K_0402_5% 3 6

2
VIN VOUT VIN VOUT
3 6 1 4 5 1 2 USB_OC#0 17

2
VIN VOUT C736 EN FLG R680
1 4 EN FLG 5 1 2 USB_OC#2 17
C424 R251 RT9715BGS_SO8 10K_0402_5% 1
RT9715BGS_SO8 10K_0402_5% 1 4.7U_0805_10V4Z C744
4.7U_0805_10V4Z C408 2
1 1
2 0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
2 SYSON#

SYSON#
42 SYSON#

2009/08/14 CHANGE cap


D26
USB20_N1_1 +USB_VCCA
6 3 W=100mils
CH3 CH2
+USB_VCCA
USB/B Conn. LS-5891
(Port 0,2)

1
5 2 +USB_VCCB
+USB_VCCA Vp Vn 1
C726 + C728
JUSB2
220U_6.3V_M_R17
2009/08/25 Update Footprint(follow NAL00)
1 W=100mils

2
USB20_P1_1 2 1
4 CH4 CH1 1 2 2
470P_0402_50V7K 3
CM1293-04SO_SOT23-6 USB Conn. 3
4 4
5
R667 1 @ 5
2 0_0402_5% (Port 1) 6 6 USB20_N0
USB20_N0 17
7 USB20_P0
7 USB20_P0 17
JUSB1 8
USB20_N1 8 USB20_N2
17 USB20_N1 1 1 2 2 1 VBUS 9 9 USB20_N2 17
L68 USB20_N1_1 2 10 USB20_P2
2 USB20_P1_1 D- 10 USB20_P2 17 2
3 D+ 13 GND 11 11
USB20_P1 4 3 4 14 12
17 USB20_P1 4 3 GND GND 12
5 GND
W CM-2012-900T_0805 6 GND ACES_85201-1205N
1 2 7 GND
R668 @ 0_0402_5% 8 CONN@
GND
SUYIN_020133GB004M51PZR
CONN@

3 3

2009/08/24 CHANGE Conn to FFC Type +3VALW +3VS

2 1
BT Conn. +BT_VCC
C789 C790
BT@ BT@ (Port 11) JBT1
Card Reader Conn. LS-5896 0.1U_0402_16V4Z 1U_0603_10V4Z 10 GND 8 8

3
1 S 2
7 7
BT_ON# 1 BT@ 2 2 Q51 6
36 BT_ON# G 6 USB20_P11 17
R706 BT@ 5
+3VS D 5 USB20_N11 17
10K_0402_5% AO3413L_SOT23-3 4 (WLAN_BT_DATA)

1
C445 4 (WLAN_BT_CLK)
GND 10 2 3 3
9 4.7U_0805_10V4Z C788 W=40mils 2
GND BT@ 2
8 8 1 2 +BT_VCC 9 GND 1 1
0.1U_0402_16V4Z
7 7 BT Wire Cable Note:

1
1 ACES_87213-0800G
6 6 5IN1_LED# 37 1
5 5 C796
BT@
C795
BT@
R713
300_0603_5%
CONN@ Pin 3, Pin 4 NC
4 4
3 USB20_N9 4.7U_0805_10V4Z BT@
3 USB20_N9 17 2
2 USB20_P9
USB20_P9 17

2
2 0.1U_0402_16V4Z
1 1

JCR1
D

1
ACES_85201-08051
CONN@ 2 Q50
G 2N7002E-T1-GE3_SOT23-3
S BT@

3
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB / BT / USBB
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Thursday, December 24, 2009 Sheet 35 of 56
A B C D E
5 4 3 2 1

SM010015410 300ma 80ohm@100mhz DCR 0.3


For EC Tools
+3VALW L32
FBMA-L11-160808-800LMT_0603 KSI[0..7]
0.1U_0402_16V4Z 0.1U_0402_16V4Z
40mil +3VALW _EC
20mil KSI[0..7] 37 +3VALW
2 +EC_VCCA
R385
1 2
1 1 1 1 2 2
1
KSO[0..17] JP6 Place on RAM door
KSO[0..17] 37
0_0805_5% C512 C519 C533 C538 C524 C488 1 1
1 E51RXD_P80CLK
2 2 E51RXD_P80CLK 34
1000P_0402_50V7K C505 3 E51TXD_P80DATA
2 2 2 2 1 1 3 E51TXD_P80DATA 34
4 4
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K 2 0.1U_0402_16V4Z

ECAGND
ACES_85205-0400
@
D
+3VALW Place on MiniCard D
JP5

111
125
22
33
96

67
U32 1 1

9
2 E51RXD_P80CLK
2 E51TXD_P80DATA
3

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
3
4 4

ACES_85205-0400
EC_GA20 1 21 @
18 EC_GA20 EC_KBRST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F BEEP# +3VALW
18 EC_KBRST#
SERIRQ
2 KBRST#/GPIO01 BEEP#/PWM2/GPIO10 23 BEEP# 39 Board ID definition,
1109 RF request 13 SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26 ME_OVERRIDE 13
13 LPC_FRAME#
LPC_FRAME# 4 27 ACOFF
ACOFF 46,47
Please see page 3.
LFRAME# ACOFF/FANPWM2/GPIO13

2
C516 LPC_AD3 5 2 1 ECAGND
13 LPC_AD3 LAD3
22P_0402_50V8J LPC_AD2 7 PWM Output C491 0.01U_0402_16V7K R389
13 LPC_AD2 LAD2
2 1 R403 2 1 47_0402_5% 13 LPC_AD1
LPC_AD1 8 LAD1 BATT_TEMP/AD0/GPIO38 63 BATT_TEMP
BATT_TEMP 44 Ra 100K_0402_5%
LPC_AD0 BATT_OVP @
13 LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64
ADP_I
BATT_OVP 46
65 ADP_I 46

1
ADP_I/AD2/GPIO3A AD_BID0 AD_BID0
17 CLK_PCI_LPC 12 PCICLK AD Input AD3/GPIO3B 66
13 75 EC_PROJECTID
5,17,21,32 PLT_RST# PCIRST#/GPIO05 AD4/GPIO42

2
+3VALW R375 2 1 47K_0402_5% EC_RST# 37 76 1
EC_SCI# ECRST# SELIO2#/AD5/GPIO43 R382 C496
18 EC_SCI# 20 SCI#/GPIO0E
C487 2 1 0.1U_0402_16V4Z
15 PM_CLKRUN# 38 CLKRUN#/GPIO1D Rb 0_0402_5%
68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C DAC_BRIG 28 2
70 EN_DFAN1
EN_DFAN1 41

1
EN_DFAN1/DA1/GPIO3D IREF 0.1U_0402_16V4Z
+3VALW
DA Output IREF/DA2/GPIO3E 71 IREF 46
KSI0 55 72 CALIBRATE#
KSI0/GPIO30 DA3/GPIO3F CALIBRATE# 46
KSI1 56 KSI1/GPIO31
1 2 EC_SMB_CK1 KSI2 57 KSI2/GPIO32
+5VS
R392 2.2K_0402_5% KSI3 58 83 EC_MUTE#
KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# 40
C 1 2 EC_SMB_DA1 KSI4 59 KSI4/GPIO34 PSDAT1/GPIO4B 84 GFX_CORE_PW RGD
GFX_CORE_PW RGD 52
TP_CLK 2 1 C
R395 2.2K_0402_5% KSI5 60 85 W W AN_LED# R404 4.7K_0402_5%
KSI5/GPIO35 PSCLK2/GPIO4C W W AN_LED# 34
KSI6 61 PS2 Interface 86 VGA_idle TP_DATA 2 1
KSI6/GPIO36 PSDAT2/GPIO4D VGA_idle 22
1 2 LID_SW # KSI7 62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK
TP_CLK 37
R408 4.7K_0402_5%
R422 100K_0402_5% KSO0 39 88 TP_DATA +3VALW
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 37
KSO1 40 KSO1/GPIO21
1 2 KSO1 KSO2 41 KSO2/GPIO22
3S/4S# 2 1
R374 47K_0402_5% KSO3 42 97 3S/4S# R423 100K_0402_5%
KSO3/GPIO23 SDICS#/GPXOA00 3S/4S# 46
1 2 KSO2 KSO4 43 KSO4/GPIO24 SDICLK/GPXOA01 98 65W /90W #
65W /90W # 46
65W /90W # 2 1
R373 47K_0402_5% KSO5 SBPW R_EN R424 100K_0402_5%
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW #
SBPW R_EN 42
VGA_idle
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW # 37 2 1
1 @ 2 EC_PME# KSO7 46 SPI Device Interface R428 DIS@ 100K_0402_5%
R426 10K_0402_5% KSO8 KSO7/GPIO27
47 KSO8/GPIO28 PCH_TEMP_ALERT# Pull high at Page 18 (PCH side)
KSO9 48 119 EC_SI_SPI_SO
KSO9/GPIO29 SPIDI/RD# EC_SI_SPI_SO 37 +3VALW
KSO10 49 120 EC_SO_SPI_SI
KSO10/GPIO2A SPIDO/WR# EC_SO_SPI_SI 37
KSO11 50 SPI Flash ROM 126 EC_SPICLK
KSO11/GPIO2B SPICLK/GPIO58 EC_SPICLK 37
KSO12 51 128 EC_SPICS#/FSEL#
KSO12/GPIO2C SPICS# EC_SPICS#/FSEL# 37

1
KSO13 52
KSO14 KSO13/GPIO2D R394
53 KSO14/GPIO2E
KSO15 54 KSO15/GPIO2F CIR_RX/GPIO40 73 W W AN_OFF#
W W AN_OFF# 34 Ra 100K_0402_5%
KSO16 81 74 PCH_TEMP_ALERT# @
KSO16/GPIO48 CIR_RLC_TX/GPIO41 PCH_TEMP_ALERT# 18,21
KSO17 82 89 FSTCHG
FSTCHG 46

2
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 BATT_GRN_LED# (CAPS_LED#) EC_PROJECTID
BATT_CHGI_LED#/GPIO52 90 BATT_GRN_LED# 37
91 3G_LED#
CAPS_LED#/GPIO53 3G_LED# 37

1
EC_SMB_CK1 77 GPIO 92 BATT_AMB_LED# 1
44 EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_AMB_LED# 37
EC_SMB_DA1 78 93 PW R_LED R397
44 EC_SMB_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 PW R_LED 37
14,22 EC_SMB_CK2
EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON
SYSON 42,49 Rb 0_0402_5% C511
EC_SMB_DA2 80 121 VR_ON 0.1U_0402_16V4Z
14,22 EC_SMB_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 38,53 2
127 ACIN @
ACIN 37,42,43

2
B AC_IN/GPIO59 B

PM_SLP_S3# 6 100 EC_RSMRST#


15 PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 15
PM_SLP_S5# 14 101 EC_LID_OUT# Project ID definition,
15 PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# 14
EC_SMI# 15 102 EC_ON
18 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON 38 Please see page 3.
EC_ACIN 16 103 EC_SW I#
15 EC_ACIN LID_SW#/GPIO0A EC_SWI#/GPXO06 EC_SW I# 15
MINI1_LED# 17 104 EC_PW ROK
34 MINI1_LED# SUSP#/GPIO0B ICH_PWROK/GPXO06 EC_PW ROK 15,38
LOCAL_DIM 18 GPO 105 BKOFF#
+3VS 28 LOCAL_DIM PBTN_OUT#/GPIO0C BKOFF#/GPXO08 BKOFF# 28
COLOR_ENG_EN 19 GPIO 106 W L_OFF# EC_CRY1 EC_CRY2
28 COLOR_ENG_EN EC_PME#/GPIO0D WL_OFF#/GPXO09 W L_OFF# 34
INVT_PW M 25 107
28 INVT_PW M EC_THERM#/GPIO11 GPXO10
R398 2 1 EC_SMB_CK2 FAN_SPEED1 28 108 1 1
2.2K_0402_5% 41 FAN_SPEED1 BT_ON# FAN_SPEED1/FANFB1/GPIO14 GPXO11 C536 C537
35 BT_ON# 29 FANFB2/GPIO15

4
R400 2 1 EC_SMB_DA2 (NUM_LED#) E51TXD_P80DATA 30
2.2K_0402_5% E51RXD_P80CLK EC_TX/GPIO16 15P_0402_50V8J X1 15P_0402_50V8J
31 110

OSC

OSC
EC_RX/GPIO17 PM_SLP_S4#/GPXID1 PM_SLP_S4# 15 2 2
ON/OFF 32 112 ENBKL
38 ON/OFF ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL 16
37 PW R_SUSP_LED PW R_SUSP_LED 34 114 EAPD
PWR_LED#/GPIO19 GPXID3 EAPD 39
R402 1 2 GFX_CORE_PW RGD W LAN_LED# 36 GPI 115 SUS_PW R_DN_ACK
37 W LAN_LED# NUMLED#/GPIO1A GPXID4 SUS_PW R_DN_ACK 15
10K_0402_5% SUSP#

NC

NC
GPXID5 116 SUSP# 38,42,46,48
117 PBTN_OUT#
GPXID6 PBTN_OUT# 5,15,21
118 EC_PME#
EC_PME# 32

3
EC_CRY1 GPXID7
122 XCLK1
2 1 E51TXD_P80DATA 15 SUSCLK 1 @ 2 EC_CRY2 123 XCLK0 V18R 124 32.768KHZ_12.5PF_Q13MC14610002
100K_0402_5% R508 R740 0_0402_5% 1
AGND

C539
GND
GND
GND
GND
GND

2 1 LOCAL_DIM
100K_0402_5% R509 4.7U_0805_10V4Z C490 100P_0402_50V8J
KB926QFD3_LQFP128_14X14 2 BATT_TEMP 2 1
11
24
35
94
113

69

2 1 COLOR_ENG_EN <BOM Structure> 20mil C489 100P_0402_50V8J


A
100K_0402_5% R511 L33 BATT_OVP 2 1 A
ECAGND 2 1 C534 100P_0402_50V8J
FBMA-L11-160808-800LMT_0603 ENBKL 1 2 ACIN 2 1
R425 100K_0402_5%
For Low PWR Pannel use SM010015410 300ma 80ohm@100mhz DCR 0.3

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE KB926
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 36 of 56
5 4 3 2 1
C506
+3VALW 1 2 1 2 0.1U_0402_16V4Z
R391 0_0603_5%
20mil To TP/B Conn.
+5VS

36 EC_SPICS#/FSEL# 150mils
JTP1
U31 1
R406 4.7K_0402_5% +SPI_VCC 1
1 8 2 TP_CLK 36
CE# VDD 2
1 2 SPI_WP# 3 WP# SCK 6 EC_SPICLK 36 3 3 TP_DATA 36
+3VALW 1 2 SPI_HOLD# 7 5 EC_SO_SPI_SI 36 4 LEFT_BTN#
R390 4.7K_0402_5% HOLD# SI 4 RIGHT_BTN#
4 VSS SO 2 EC_SI_SPI_SO 36 5 5
6
MX25L1005AMC-12G_SOP8 6
7 GND 1 1

2
8
GND C683 C682
Reserved for BIOS simulator.
Footprint SO8 @ ACES_85201-0605N @ @
0_0402_5% R386 CONN@ 2 2
(Left) JKB1 100P_0402_50V8J 100P_0402_50V8J

1
KSO0
KSO1
26
25
KSO0 G2
28
27
INT_KBD Conn. @
C497 TP_CLK LEFT_BTN#
KSO2 KSO1 G1 33P_0402_50V8K
24 KSO2
KSO3 23 TP_DATA RIGHT_BTN#
KSO4 KSO3
22
KSO4

3
KSO5 21 KSI[0..7]
KSO5 KSI[0..7] 36 +5VS
KSO6 20 D19 D18
KSO7 KSO6 KSO[0..17]
19 KSO[0..17] 36 PJDLC05C_SOT23-3 PJDLC05C_SOT23-3
KSO8 KSO7
18 1
KSO9 KSO8 C684
17 KSO9
KSO10 16 0.1U_0402_16V4Z
KSO11 KSO10
15
KSO12 KSO11 2
14 KSO12
KSO13 13

1
KSO14 KSO13
12
KSO15
KSO16
11
10
KSO14
KSO15 LS-5893+LS-5894(Lid Board)
KSO17 KSO16 SW2 SW3
9
LED/B RIGHT (90) LED/B LEFT (70)
KSI0 KSO17 SMT1-05-A_4P SMT1-05-A_4P
8
KSI1 KSI0 LEFT_BTN# RIGHT_BTN#
7 KSI1 3 1 3 1
KSI2 6
KSI3 KSI2 JLED1 JLED2
5 4 2 4 2
KSI4 KSI3
4 KSI4 1 1 +3VALW 1 1 +3VALW
KSI5 3 2 LID_SW# 2 LID_SW#
LID_SW# 36

5
6

5
6
KSI6 KSI5 2 ACIN_LED# 2 ACIN_LED#
2 KSI6 3 3 3 3
KSI7 1 4 3G_LED# 4 3G_LED#
KSI7 4 3G_LED# 36 4
5 WLAN_LED# 5 WLAN_LED#
5 WLAN_LED# 36 5
(Right) 6 MEDIA_LED# 6 MEDIA_LED#
ACES_88747-2601 6 6
7 +3VS 7 +3VS
7 PWR_LED# 7 PWR_LED#
CONN@ 8 8
8 ON/OFFBTN# 8 ON/OFFBTN#
9 9 ON/OFFBTN# 38 9 9
10 10
KSO16 C35 100P_0402_50V8J 10 10
1 2 GND 11 GND 11
12 12
KSO17 C36 100P_0402_50V8J GND GND
1 2
ACES_85201-1005N ACES_85201-1005N
KSO15 C34 1 2 100P_0402_50V8J KSO7 C26 1 2 100P_0402_50V8J CONN@ CONN@ +3VS +3VS

KSO14 C33 1 2 100P_0402_50V8J KSO6 C25 1 2 100P_0402_50V8J

2
KSO13 C32 1 2 100P_0402_50V8J KSO5 C24 1 2 100P_0402_50V8J R272
@

2
KSO12 C31 1 2 100P_0402_50V8J KSO4 C23 1 2 100P_0402_50V8J Q4A 100K_0402_5%

1
6 1 5IN1_LED# 35
KSI0 C37 1 2 100P_0402_50V8J KSO3 C22 1 2 100P_0402_50V8J
2N7002DWH_SOT363-6
KSO11 C30 1 2 100P_0402_50V8J KSI4 C41 1 2 100P_0402_50V8J
MEDIA_LED#
KSO10 C29 1 2 100P_0402_50V8J KSO2 C21 1 2 100P_0402_50V8J

KSI1 C38 1 2 100P_0402_50V8J KSO1 C20 1 2 100P_0402_50V8J 3 4 PCH_SATALED# 13


Q4B 2N7002DWH_SOT363-6
KSI2 C39 1 2 100P_0402_50V8J KSO0 C19 1 2 100P_0402_50V8J

5
KSO9 C28 1 2 100P_0402_50V8J KSI5 C42 1 2 100P_0402_50V8J Power/SUS Battery 3G/WLAN BlueTooth ACIN
LED Status
KSI3 C40 1 2 100P_0402_50V8J KSI6 C43 1 2 100P_0402_50V8J ON SUS Full Charge 3G WLAN
KSO8 C27 1 2 100P_0402_50V8J KSI7 C44 1 2 100P_0402_50V8J +3VS
NEW70/80/90 Blue Amber Blue Amber Blue Amber

LED3 ACIN_LED#

1
PWR_LED# D
+3VS 1 71@ 2 2 1
R343 2.2K_0402_5% B 2 91@ 1 36,42,43 ACIN 2 Q53
R343 680_0402_5% G @
HT-191NB5_BLUE S

3
2N7002E-T1-GE3_SOT23-3
LED1

1 71@ 2 2 1 PWR_SUSP_LED#
+3VALW
R344 3.9K_0402_5% A 2 91@ 1
R344 680_0402_5%
HT-191UD5_AMBER

PWR_LED# PWR_SUSP_LED#
6

3
LED4
Q26A Q26B
1 71@ 2 2 1 BATT_GRN_LED# 2 91@ 1 2 5 2N7002DWH_SOT363-6
+3VALW BATT_GRN_LED# 36 36 PWR_LED 36 PWR_SUSP_LED
R341 2.2K_0402_5% B R341 680_0402_5% 2N7002DWH_SOT363-6
2

2
1

4
HT-191NB5_BLUE R340 R335
100K_0402_5% 100K_0402_5%
LED2
1

1
1 71@ 2 2 1 BATT_AMB_LED# BATT_AMB_LED# 36
R342 3.9K_0402_5% A 2 91@ 1
R342 680_0402_5%
HT-191UD5_AMBER

Bom option Security Classification Compal Secret Data Compal Electronics, Inc.
For 71 and 91 2008/08/10 2010/08/01 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS, I/O Port & K/B Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 37 of 56
A B C D E

Power Button

ON/OFF switch
+3VALW

2
1 1
R409
37 ON/OFFBTN#
100K_0402_5%
TOP Side

1
SW1 2 ON/OFF 36
SMT1-05-A_4P
1 3 ON/OFFBTN# 1

2 4 3 51ON#
51ON# 43
@ D12
6
5

CHN202UPT_SC70-3

1
D
EC_ON 2 Q32
36 EC_ON
G 2N7002E-T1-GE3_SOT23-3

2
S

3
R413
Bottom Side 10K_0402_5%
SW4
SMT1-05-A_4P 1
1 3

2 4
6
5

2 2

Test Only

Power ON Circuit
+3VS

+3VALW +3VALW
1

U21A U21B
R331 SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14
For South Bridge
14

14

180K_0402_5%
D7
P

P
2

1 2 1 2 3 4 SYS_PWROK_1 1 @ 2
36,53 VR_ON I O I O EC_PWROK 15,36
R332 0_0402_5%
G

CH751H-40PT_SOD323-2 2
@
7

C455
1U_0603_10V6K
@ 1

3 3

+3VS

+3VALW +3VALW
1

R333
10K_0402_1% U21C U21D
14

14

R334 @ SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14


249K_0402_1%
P

P
2

SUSP# 1 2 5 6 9 8 1 2
36,42,46,48 SUSP# I O I O VS_ON 51
2 R320 0_0402_5%
G

G
1

D
SUSP 2 Q25 C456
For VTT
42,48 SUSP
7

G 0.1U_0402_16V7K
1 SUSP# @
S 1 2
3

2N7002E-T1-GE3_SOT23-3 R321 0_0402_5%

+3VS
+3VALW +3VALW
C448
1

1 2 0.1U_0402_16V4Z
R319
31.6K_0402_1% U21E U21F
14

14

R318 @ SN74LVC14APWLE_TSSOP14 SN74LVC14APWLE_TSSOP14


10K_0402_1%
P

P
2

14,18,21,42 DGPU_PWR_EN 1 DIS@ 2 11 10 13 12 1 DIS@ 2


VGA_ON 24,42,50
I O I O R317 0_0402_5%
G

G
1

4 D 4
2
2 Q23 C447
42 DGPU_PWR_EN#
7

G DIS@ DIS@
S 1U_0603_10V6K
3

2N7002E-T1-GE3_SOT23-3 1 DGPU_PWR_EN @
1 2
R316 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power OK
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 38 of 56
A B C D E
5 4 3 2 1

+5VAMP

1 2

1
1 2 R339 0_0805_5%
R298 0_0805_5% R698
SM010014520 3000ma 220ohm@100mhz DCR 0.04 +3VS 10K_0402_5%
1 2
+5VAMP R329 0_0805_5%

2
U19
1 2
60mil 40mil

1
+5VS L28 1 2 0.1U_0402_16V4Z 1 C783 1U_0402_6.3V4Z
IN

1
FBMA-L11-201209-221LMA30T_0805
OUT 5 +VDDA 4.75V D32 R704 1 2
@ 1 1 2 CH751H-40PT_SOD323-2 R696 R283 0_0805_5%
L27 1 C444 C438 GND 10K_0402_5% 10K_0402_5%
2
FBMA-L11-201209-221LMA30T_0805 3 4 1 2

2
0.1U_0402_16V4Z SHDN BYP C439 C773

2
D 2 2 G9191-475T1U_SOT23-5 0.01U_0402_16V7K 1 2 MONO_IN D
@ @ 1U_0402_6.3V4Z GND GNDA

1
C
C780 1 R699
(output = 300 mA) 36 BEEP# 2 1 2 2
B Q49
1
R694
2
2.4K_0402_1%
1U_0402_6.3V4Z 560_0402_5% E 1 2

3
2SC2411K_SOT23-3 R670 0_0805_5%
C785 1 R701
2 1 2
13 PCH_SPKR

1
1U_0402_6.3V4Z 560_0402_5% 1 2
D31 R308 0_0805_5%
CH751H-40PT_SOD323-2

1 2

2
R707 0_0805_5%

GND GNDA
HD Audio Codec
+AVDD_HDA
SM010015410 300ma 80ohm@100mhz DCR 0.3 Place near Codec
40mil SM010032020 600ma 120ohm@100mhz DCR 0.25
L70 1 2 0.1U_0402_16V4Z
10mil 0.1U_0402_16V4Z +3VS_DVDD L71 1 2
+VDDA +3VS
FBMA-L11-160808-800LMT_0603 1 1 1 MBK1608121YZF_0603
C739 C772 1 1 1
C738 C760 C748 C746
C 10U_0805_10V4Z 10U_0805_10V4Z C
2 2 2
0.1U_0402_16V4Z 2 2 2

25

38

9
U48
Place near Codec 0.1U_0402_16V4Z

DVDD_IO
AVDD1

AVDD2

DVDD
14 35 AMP_LEFT
LINE2_L LOUT1_L AMP_LEFT 40
272@amp
15 36 AMP_RIGHT
LINE2_R LOUT_R AMP_RIGHT 40
1K_0402_1% C775 1 2 MIC2_C_L 16 39
INT_MIC_R R702 2 INT_MIC 4.7U_0603_6.3V6K MIC2_L LOUT2_L
External MIC 1
C776 1 2 MIC2_C_R 17 41
4.7U_0603_6.3V6K MIC2_R LOUT2_R
23 45
LINE1_L SPDIFO2
24 46
LINE1_R DMIC_CLK1/2
18 43
LINE1_VREFO NC
20 44 1 2 1 2 C752
LINE2_VREFO DMIC_CLK3/4 R686 0_0402_5% 22P_0402_50V8J
Internal MIC REF For EMI
272@ MIC2_VREFO 19
MIC2_VREFO
6 HDA_BITCLK_AUDIO 13
MIC1_L C777 1 MIC1_C_L BITCLK
40 MIC1_L 2 21 MIC1_L
4.7U_0603_6.3V6K
MIC1_R C778 1 2 MIC1_C_R 22 8 HDA_SDIN0_AUDIO 1 2
40 MIC1_R MIC1_R SDATA_IN HDA_SDIN0 13
4.7U_0603_6.3V6K R687 33_0402_5%
MONO_IN 12 37
PCBEEP_IN MONO_OUT
B B
CBP 29
11 C754 2.2U_0402_6.3V6M
13 HDA_RST_AUDIO# RESET#
31
CPVEE
13 HDA_SYNC_AUDIO 10 SYNC 10mil External MIC REF 1
28 MIC1_VREFO 272@
MIC1_VREFO C758
13 HDA_SDOUT_AUDIO 5
SDATA_OUT HP_RIGHT
32 HP_RIGHT 40
HPOUT_R 2 2.2U_0402_6.3V6M MIC2_VREFO
2
GPIO0/DMIC_DATA1/2
3 30
R695 2 SENSE_A GPIO1/DMIC_DATA3/4 CBN
40 MIC_PLUG# 1 20K_0402_1% 13 SENSE A 10mil
R685 2 1 5.11K_0402_1% SENSE_B 34 27 CODEC_VREF C764 1 2 0.1U_0402_16V4Z
40 HP_PLUG# SENSE B VREF

1
C765 1 2 10U_0805_10V4Z For EMI
36 EAPD
1
R672
2
0_0402_5%
47 EAPD JDREF 40 R673 1 2 20K_0402_1%
Place next pin27
Int. MIC R703
2.2K_0402_5%
48 33 HP_LEFT 15mil 15mil
SPDIFO1 HPOUT_L HP_LEFT 40
JP1

2
4 26 1 INT_MIC_L 1 2 INT_MIC_R
DVSS1 AVSS1 1 L29 FBMA-L11-160808-700LMT_2P
7 42 2
DVSS2 AVSS2 2
1
ALC272X-GR_LQFP48_7X7 C786
3
G1 220P_0402_50V7K
G2 4
2
DGND AGND ACES_88266-02001
CONN@

3
D10 SM010004010 300ma 70ohm@100mhz DCR 0.3
PJDLC05C_SOT23-3

A A

1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC272X
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 39 of 56
5 4 3 2 1
A B C D E

GAIN0 GAIN1 AV(inv) Ri +5VAMP


0 0 6dB 90k
0 0.1U_0402_16V4Z
1 10dB 70k
1 1
1 0 15.6dB 45k C453 C457 10 dB
1 1 21.6dB 25k 10U_0805_10V4Z
2 2 +5VAMP

1
16
15
6
U50 R710 @ R709
100K_0402_5% 100K_0402_5%

PVDD1
PVDD2
VDD
1 1

2
C792 1 2 0.47U_0603_10V7K 7 2 GAIN0
RIN+ GAIN0
3 GAIN1
GAIN1

1
1 2 1 2 AMP_C_RIGHT 17
39 AMP_RIGHT C779 0.47U_0603_10V7K R697 0_0603_5% RIN- SPKR+ @ R711 R708
ROUT+ 18
100K_0402_5% 100K_0402_5%

14 SPKR-

2
C793 1 ROUT-
2 0.47U_0603_10V7K 9 LIN+
4 SPKL+
LOUT+
1 2 1 2 AMP_C_LEFT 5
39 AMP_LEFT C791 0.47U_0603_10V7K R712 0_0603_5% LIN- SPKL-
8
LOUT-

NC 12

EC_MUTE# BYPASS
10 Keep 10 mil width
36 EC_MUTE# 19 SHUTDOWN
2

GND5
GND1
GND2
GND3
GND4
C794
0.47U_0603_10V7K
1

21
20
13
11
1
2 2
TPA6017A2PWPR_TSSOP20

(Use NAL00 PCB Footprint)


2 2
C787 C784
Headphone Out
330P_0402_50V7K 330P_0402_50V7K
1 1 JHP1
1
39 HP_LEFT R705 1 2 56.2_0603_1% HPOUT_L_1 1 2 HPOUT_L_2 2
L78 FBMA-L11-160808-700LMT_2P
39 HP_RIGHT R700 1 2 56.2_0603_1% HPOUT_R_1 1 2 HPOUT_R_2 3
L77 FBMA-L11-160808-700LMT_2P
4
SM010004010 300ma 70ohm@100mhz DCR 0.3
HP_PLUG# 5
39 HP_PLUG#

3 3
6
MIC1_VREFO
SINGA_2SJ-0960-C01
MIC_PLUG# CONN@

HP_PLUG#
Headphone Out

2
D27 D29

2
CH751H-40PT_SOD323-2 CH751H-40PT_SOD323-2
Int. Speaker Conn. D30
PJDLC05C_SOT23-3

1
Left Side
JSPK2

1
SPKL+ R354 1 2 0_0603_5% SPK_L+ 1
SPKL- R359 1 2 0_0603_5% SPK_L- 2
1 R676 R688 MIC JACK

1
2 4.7K_0402_5%
20mil 4.7K_0402_5% JMIC1

2
3 1
G1
2

4 R689 1 2 MIC1_L_1 L73 1 2 MIC1_L_R 2


G2 39 MIC1_L
D11 1K_0603_1% FBMA-L11-160808-700LMT_2P
PJDLC05C_SOT23-3 ACES_88266-02001 R674 1 2 MIC1_R_1 L72 1 2 MIC1_R_R 3
39 MIC1_R
CONN@ 1K_0603_1% FBMA-L11-160808-700LMT_2P

3
1 1 4
SM010004010 300ma 70ohm@100mhz DCR 0.3 D28
C743 C759
PJDLC05C_SOT23-3 MIC_PLUG# 5
39 MIC_PLUG#
220P_0402_50V7K 220P_0402_50V7K
2 2
Right Side
1

JSPK1 6
4 4
SPKR+ R348 1 2 0_0603_5% SPK_R+ 1 SINGA_2SJ-A960-C01

1
SPKR- R347 1 SPK_R- 1
2 0_0603_5% 2 2
CONN@
2

D9 3
G1
PJDLC05C_SOT23-3 4 G2
ACES_88266-02001 Security Classification Compal Secret Data Compal Electronics, Inc.
CONN@ Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Amplifier & Audio Jack
Size Document Number Rev
1

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 40 of 56
A B C D E
H10 H15 H6 H17 H21 H20 H2 H1 H5 H3 H16 H22
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0

@ @ @ @ @ @ @ @ @ @ @ @

1
GNDA
H11
H_3P0
H14 H9 H13 H8
FAN1 Conn H_4P2 H_4P2 H_4P2 H_4P2
@

1
+5VS @ @ @ @

1
C542 10U_0805_10V4Z +5VS
1 2

1
U35 D13
1 8 1SS355_SOD323-2 H12 H4
EN GND @ H_4P0 H_4P0
2 VIN GND 7
+VCC_FAN1 3 6

2
VOUT GND D15
36 EN_DFAN1 2 1 4 5
R461 300_0402_5% VSET GND @ @
1 2

1
1 APL5607KI-TRG_SO8 @
BAS16_SOT23-3
C570 C568
0.1U_0402_16V4Z 10U_0805_10V4Z
2 1 2
H18 H19 H7
+3VS C563 H_3P4 H_3P0X3P5N H_3P0N
1000P_0402_50V7K
1 2

1
@ @ @

1
R445
10K_0402_5%
40mil
JFAN1
2

+VCC_FAN1
1 FD4 FD2 FD1 FD3
36 FAN_SPEED1 2
3
1
C562 ACES_85205-03001 @ @ @ @

1
1000P_0402_50V7K CONN@
FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FAN & Screw Hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 41 of 56
A B C D E

+3VALW TO +3V(PCH AUX Power)


+1.05VS_VTT to +1.05VSDGPU for GPU
+5VALW TO +5VS +3VALW Short J5 for PCH VCCSUS3.3 +1.05VS_VTT +1.05VSDGPU
J5 @ U63 DIS@
+5VALW +5VS SI4800BDY-T1-GE3_SO8
1 1 2 2 4A
U49 +3V 8 1
SI4800BDY-T1-GE3_SO8 JUMP_43X79 40mil 7 2 1 1

2
8 1 U14 @ 6 3 C1028
7 2 SI4800BDY-T1-GE3_SO8 5 @ + DIS@ R865
1

2
6 3 1 1 8 1 C1029 C1027 470_0603_5%
5 C761 C767 R692 7 2 2
330U_D2_2V_Y 1U_0603_10V4Z DIS@
1 1

4
2
C763 C766 470_0603_5% 6 3 DIS@ 2
1 1

1
10U_0805_10V4Z 5 C393 C392 R226 2
1

4
10U_0805_10V4Z 2 2
1U_0603_10V4Z C407 @ 10U_0805_10V4Z

6
1 2 2 10U_0805_10V4Z 470_0603_5% 1

4
10U_0805_10V4Z 10U_0805_10V4Z 2 2
1U_0603_10V4Z 20mil 10mil

3 1
3
2 R866 Q58A
Q47B +VSB 1 2 +1.05VSDGPU_GATE 2N7002DWH_SOT363-6 2 VGA_ON#
20mil 10mil DIS@
+VSB 2 1 5VS_GATE 5 SUSP 20mil 10mil 10K_0402_5% 1

1
3

1
R684 5 SBPWR_EN# Q58B C1030
@ DIS@
200K_0402_5% 1 R255 2 @ 1 3V_GATE DIS@ R867 DIS@
+VSB

4
6

C756 2N7002DWH_SOT363-6 Q16B @ 0.1U_0603_25V7K

4
6
200K_0402_5% 2N7002DWH_SOT363-6 VGA_ON# 2
1 5
Q47A 0.1U_0603_25V7K C421 2N7002DWH_SOT363-6 510K_0402_5%

1 2
SUSP 2 2 Q16A @

4
SBPWR_EN# 0.1U_0603_25V7K D
2 @ 2 ACIN 2 Q59
1

2N7002DWH_SOT363-6 G @

1
2N7002DWH_SOT363-6 S 2N7002E-T1-GE3_SOT23-3

3
+3VALW TO +3VS
+3VALW
+1.8VS to +1.8VSDGPU
+1.8VS +1.8VSDGPU
for GPU +5VALW
+5VALW
+3VS
U20 U37 DIS@

2
SI4800BDY-T1-GE3_SO8 SI4800BDY-T1-GE3_SO8

2
8 1 8 1 R337
7 2 7 2 1 1 100K_0402_5% R346

2
6 3 1 1 6 3 C648 C664 100K_0402_5%
1 1 5 C449 C446 R315 1 5 DIS@ DIS@ R502

1
C454 C451 470_0603_5% C670 470_0603_5% SYSON#
35 SYSON#

1
10U_0805_10V4Z 2 2
1U_0603_10V4Z DIS@
4

6
10U_0805_10V4Z 2 2
1U_0603_10V4Z DIS@ 10U_0805_10V4Z SUSP
38,48 SUSP
3 1

1
2 2 2
10U_0805_10V4Z 2
10U_0805_10V4Z 2

3
2N7002DWH_SOT363-6

Q27A

3
SYSON 2
36,49 SYSON
20mil 10mil 20mil 10mil 2N7002DWH_SOT363-6 Q27B

1
2 1 3VS_GATE 5 SUSP Q35B 5 2N7002DWH_SOT363-6
+VSB 36,38,46,48 SUSP#

1
R322 2 1 1.8VSDGPU_GATE 2N7002DWH_SOT363-6 5 VGA_ON# R345
+VSB

1
200K_0402_5% 1 Q22B R505 DIS@ 100K_0402_5%
4

4
6

C450 510K_0402_5% 1 R338

4
6

1
DIS@ C650 10K_0402_5%

2
Q22A 0.1U_0603_25V7K R472 DIS@
SUSP 2 2 Q35A @ 0.1U_0603_25V7K

2
VGA_ON# DIS@ 2
2
1

2
2N7002DWH_SOT363-6 2N7002DWH_SOT363-6 510K_0402_5%

1
D
ACIN 2 Q34
G @
+1.5V to +1.5VS S 2N7002E-T1-GE3_SOT23-3

3
+1.5V +1.5VS
1211 EMI ADD 0.1U close PJ5
U13
SI4800BDY-T1-GE3_SO8
8 1
7 2 1 1
+1.5V to +1.5VSDGPU for GPU
2

+5VALW
C374
10U_0805_10V4Z

10U_0805_10V4Z

6 3 C328 C338
0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 1 1 1 5 R181
+1.5V +1.5VSDGPU
C588

C587

C389

10U_0805_10V4Z 470_0603_5%

2
2 2
1U_0603_10V4Z +5VALW
4

2
U40 R31
1

2 2 2 2 8 1 100K_0402_5% R326
D S @ 100K_0402_5%
7 2 1 1
D S
3

2
3 C717 C713 DIS@ 3
6 3

1
D S DIS@ DIS@ R593
1 5 4

1
Q9B C714 D G 470_0603_5% SBPWR_EN# DGPU_PWR_EN#
10mil 1.5VS_GATE 2N7002DWH_SOT363-6 SUSP SI4856ADY_SO8 2 2
1U_0603_10V4Z DIS@
20 SBPWR_EN# 38 DGPU_PWR_EN#
+VSB 2 1 5
R184 DIS@ DIS@ 10U_0805_10V4Z

1
2 D
510K_0402_5%

20mil 510K_0402_5% 1
4
1

1
C346 10U_0805_10V4Z Q1 D
36 SBPWR_EN 2
6

3
G @ 14,18,21,38 DGPU_PWR_EN 2 Q24

1
R185 0.1U_0603_25V7K 20mil S G DIS@

3
2 Q40B R30 2N7002E-T1-GE3_SOT23-3 S

3
1
SUSP 2 @ 2N7002DWH_SOT363-6 5 VGA_ON# 100K_0402_5%
2

DIS@ @ R325 2N7002E-T1-GE3_SOT23-3


Q9A 100K_0402_5%
1

2
2N7002DWH_SOT363-6 2 1 1.5VSDGPU_GATE DIS@
+VSB
R586

2
1

D 510K_0402_5% +5VALW
1
6

36,37,43 ACIN ACIN 2 Q10 DIS@ Q40A C711


G @ DIS@ R584 DIS@

2
S 2N7002E-T1-GE3_SOT23-3 @ 0.1U_0603_25V7K
3

VGA_ON# 2 R232
2
510K_0402_5% 100K_0402_5%
2

2009/08/17 add VGA_ON# DIS@


1

2N7002DWH_SOT363-6

1
1

D VGA_ON#
+0.75VS +1.05VS_VTT +1.8VS +1.5V ACIN VGA_ON#
2 Q38
G @
S 2N7002E-T1-GE3_SOT23-3
3
1

1
D
R200 R427 R524 R569 2 Q15
24,38,50 VGA_ON
22_0603_5% 470_0603_5% 470_0603_5% 470_0603_5% G DIS@

1
@ S

3
R231
2

4 DIS@ 4
22K_0402_5%
1

D D D D 2N7002E-T1-GE3_SOT23-3

2
Q11 2 SUSP Q33 2 SUSP Q36 2 SUSP Q37 2 SYSON#
G G G @ G
S S S S
3

2N7002E-T1-GE3_SOT23-3 2N7002E-T1-GE3_SOT23-3 2N7002E-T1-GE3_SOT23-3 2N7002E-T1-GE3_SOT23-3


Security Classification Compal Secret Data Compal Electronics, Inc.
2009/08/14 Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title
CP_S3PowerReduction THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
WhitePaper_Rev0.9 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
0.75VS speed up discharge DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic 0.1
Date: Tuesday, December 22, 2009 Sheet 42 of 56
A B C D E
A B C D

VIN
1 1

VIN PR295
1M_0402_1%
1 2

1
PL24 VIN
PJP1 SMB3025500YA_2P PR296 VS
DC_IN_S1 1 2DC_IN_S2 10K_0402_5%
1

1
2 PR297

2
3 84.5K_0402_1%
4 46,47 PACIN PR298
GND

8
PC208 PR299 22K_0402_5%

2
GND PC206 PC207 100P_0402_50V8J PC209 10K_0402_5% 3 1 2

P
ACES_50305-00441-001 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K +
1 2 1

2
36,37,42 ACIN O

20K_0402_1%
- 2

1
PR301
PU18A

1
PC210
LM393DG_SO8 PC211

0.1U_0603_25V7K
4
PR302 PD1 1000P_0402_50V7K

2
10K_0402_1% GLZ4.3B_LL34-2

2
2

2
PR303
10K_0402_1%
1 2
RTCVREF

2
Vin Dectector 2

Min. Typ Max.


H-->L 16.976V 17.525V 17.728V
L-->H 17.430V 17.901V 18.384V

VIN
PJ6
2

+3VALWP 2 2 1 1 +3VALW
PD2 PJ2
LL4148_LL34-2 JUMP_43X118 2 1
+VGFX_COREP 2 1 +VGFX_CORE
PD3 JUMP_43X118
1

3
LL4148_LL34-2 PJ4 3

BATT+ 2 1 2 2 1 1
1

PJ8
PR304 PR305 2 1 JUMP_43X118
PQ42 68_1206_5% 68_1206_5% +5VALWP 2 1 +5VALW
TP0610K-T1-E3_SOT23-3 JUMP_43X118
PR306
2

200_0603_5% PJ5
CHGRTCP 1 2 N1 3 1 +1.5VP 2 1 +1.5V
VS PJ11
2 1
JUMP_43X118
1

2 1 PJ7
+VSBP 2 1 +VSB
1

PR307 PC213 2 2
100K_0402_1% PC212 0.1U_0603_25V7K JUMP_43X39 1 1
0.22U_0603_25V7K JUMP_43X118
2

PR308
2

22K_0402_1%
1 2 PJ9
38 51ON# +1.05VS_VTTP 2 1
2 1 +1.05VS_VTT
PJ14 JUMP_43X118
2 1 PJ10
+1.8VSP 2 1 +1.8VS
2 2 1 1
RTCVREF JUMP_43X118
1

JUMP_43X118
PR309
PU14 200_0603_5% PJ15
PR310 PR311 G920AT24U_SOT89-3 2 1
560_0603_5% 560_0603_5% 3.3V PJ17 +VGA_COREP 2 1 +VGA_CORE
2

1 2 1 2 3 2 N2 2 1 JUMP_43X118
OUT IN +0.75VSP 2 1 +0.75VS
+CHGRTC PJ16
JUMP_43X39 2 2 1 1
1

4 GND PC215 4

PC214
10U_0805_10V4Z 1
1U_0805_25V4Z - PBJ1 + +RTCBATT
JUMP_43X118
2

2 1
+RTCBATT

ML1220T13RE
<BOM Structure>
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN & DETECTOR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71
Date: Tuesday, December 22, 2009 Sheet 43 of 56
A B C D
A B C D

GND 10
GND 9
8 8
7
PH1 under CPU botten side :
7 EC_SMDA
6 6 CPU thermal protection at 92 degree C

2
5 EC_SMCA
5 TH PR542
4 4
3 PI 100_0402_1%
3
2 2
1

1
1
1 1

2
PJP2
SUYIN_200275GR008G13GZR PR543
100_0402_1% VL
CONN@ <40,41> EC_SMB_DA1 36

VMB

1
VL

1
PL44
<40,41> EC_SMB_CK1 36

1
SMB3025500YA_2P
BATT+

2
BATT_S1 1 2 PR544 PC381 PR545 PR546
1K_0402_5% 0.1U_0603_25V7K 10K_0402_1% 21K_0402_1% @ PR547

2
PR548 100K_0402_1%
1

1
6.49K_0402_1%

2
PC379 PC380 2 1 PU30
+3VALW P

1
1000P_0402_50V7K 0.01U_0402_25V7K 1 8
2

2
VCC TMSNS1

2
2 7 PR549
GND RHYST1

1
9.53K_0402_1%

2
PR550 3 6
1K_0402_1% OT1 TMSNS2 @ PR551

1
1
4 5 47K_0402_1%
OT2 RHYST2

2
G718TM1U_SOT23-8 PH1

1
100K_0402_1%_NCP15W F104F03RC
BATT_TEMP 36

2
MAINPW ON 18,45,47

1
2 2

@ PH2
100K_0402_1%_NCP15W F104F03RC

2
PQ44
TP0610K-T1-E3_SOT23-3

B+ 3 1 +VSBP
0.22U_0603_25V7K

0.1U_0603_25V7K
1

1
PC221

PC222

PR325
3
100K_0402_1% 3
2

PR327
2

VL 22K_0402_1%
1 2
2

PR329
100K_0402_1%

PR330
1

1K_0402_5% PQ45 D
1 2 2
45 SPOK G 2N7002W -T/R7_SOT323-3
S
3
1

@ PC224
1U_0402_6.3V6K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/09/20 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71
Date: Tuesday, December 22, 2009 Sheet 44 of 56
A B C D
5 4 3 2 1

ISL6237_B+
ISL6237_B+
B+
PR331
PJ19 0_0805_5%
2 2 1 1 1 2

JUMP_43X118

10U_1206_25V6M

2200P_0402_50V7K

10U_1206_25V6M

2200P_0402_50V7K
D D
VL

5
6
7
8

1
PC225

PC226

PC228
8
7
6
5

PC227
1U_0603_10V6K
2

2
2
2

PC230
PQ46 PC229
AO4466_SO8 0.1U_0603_25V7K 4

4.7U_0603_6.3V6K
3/5V_VCC
1

1
3/5V_VIN
4

PC231
PQ47 +5VALWP

2
AO4466_SO8

3
2
1
PL27

1
2
3
PL28 4.7UH_SIL104R-4R7PF_5.7A_30%

7
4.7UH_SIL104R-4R7PF_5.7A_30% PU16 PC232 2 1
1 2 1U_0603_10V6K

VIN

V5FILT

LDO
+3VALWP 33 19 1 2
TP V5DRV

5
6
7
8

1
PQ49

8
7
6
5
UG3 26 15 HG5 AO4712_SO8
PR332 DRVH2 DRVH1 PR336
0_0402_5%

4.7_1206_5% PQ48 BST3A-1 1 2 BST3A 24 17 BST5A1 2BST5A-1 4.7_1206_5% 1


VBST2 VBST1
2

1 AO4712_SO8 0_0603_5% PR333 0_0603_5% PR334

2
2

2
+
PR335

PC233 PC237

61.9K_0402_1%
4

13V_SNB
2
220U_6.3VM_R15 + 4 PC234 220U_6.3VM_R15

2
0.1U_0603_25V7K

1
2

@ PR337
SW 3 25 16 SW 5
1

2 PC235 LL2 LL1 PC236

3
2
1
680P_0603_50V7K 0.1U_0603_25V7K PC238

1
2
3

2
2 LG3 23 18 LG5 680P_0603_50V7K

1
DRVL2 DRVL1
@ 10K_0402_1%
2

PGND 22

2
C C
PR338

FB3 30 VOUT2

PR339
0_0402_5%
VOUT1 10
VL 32
1

REFIN2

1
11 FB5
2VREF_ISL6237 FB1

1 2 1 VREF2
PC239
0.22U_0603_25V7K 9
VSW
8 LDOREFIN
29 5V_SKIP 2 1
SKIPSEL @ PR340
VL
0_0402_5%
1 2
20 28 PR341
PD7 PR342 NC PGOOD2 0_0402_5%
VS RLZ5.1B_LL34 100K_0402_1%
1 2 EN_LDO-1 1 2 EN_LDO 4 13 SPOK 44
EN_LDO PGOOD1 PR344 For +5VALWP
2

402K_0402_1%
200K_0402_5%

Power Budget=8.8A, Ipeak=7A, I max=4.9A


2
PR343

PC240 3/5V_EN1 14 12 ILM1 2 1


0.22U_0603_25V7K EN1 TRIP1 Fsw=300KHz by RT8206 setting.
VL VS
∆I=2.61A, 1/2∆I=1.306A

TONSE
VREF3
1

27 31 ILIM2 2 1

GND
5uA*PR344=10*Iocpmin*18mΩ*1.3
1

EN2 TRIP2
PR345 =>PR344=397KΩ~402KΩ
2

2
RT8206BGQW QFN 32P 267K_0402_1%

21
1

B @ PR346 B
PD8 0_0402_5% 5uA*402K=10*ILIMTmin*18mΩ*1.3

13/5V_NC
PR561 1SS355_SOD323-2 PR347 ILIMTmin=8.589A

13/5V_TON
806K_0603_1% 0_0402_5% 5uA*402K=10*ILIMTmax*15mΩ*1.1
1

1
@

PR349
P R349 1U_0603_10V6K
2

ILMIT=12.181A
PC241

PR348 47K_0402_5%
2VREF_ISL6237

0_0402_5% Iocp=9.89A~13.48A
18,44,47 MAINPWON 2 1 1 2
2

PR350 For +3VALWP


0.047U_0402_16V7K

@ 0.047U_0402_16V7K

0_0402_5% Power Budget=4.72A, Ipeak=4.72A, Imax=4A


1

080414:PQ23 ,Del @
Iocpmin=4.72*1.2=5.664~5.7A
2
PC242

PC243

PQ50
3

Fsw=375KHz, ∆I=1.547A, 1/2∆I=0.773A


2

5uA*PR345=10*Iocpmin*Rdsonmax*1.3
5uA*PR345=10*5.7A*18mΩ*1.3
2VREF_ISL6237

2 PR345=266.76K~267K
TP0610K-T1-E3_SOT23-3

5uA*267KΩ=10*ILIMTmin*18mΩ*1.3
ILIMTmin=5.705A
5uA*267KΩ=10*ILIMTmax*15mΩ*1.1
1

ILIMTmax=8.09A
Iocp=6.47A~8.86A

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/02/04 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71
Date: Tuesday, December 22, 2009 Sheet 45 of 56
5 4 3 2 1
A B C D

Iada=0~4.74A(90W/19V=4.736A)
ADP_I = 19.9*Iadapter*Rsense
CP = 85%*Iada ; CP = 4.07A B+
Iada=0~3.42A(90W/19V=3.421A) CP = 85%*Iada ; CP = 2.91A

P2 P3 B+ CHG_B+
PQ51 AO4407A_SO8 PQ52 AO4407A_SO8 PR351 0.02_2512_1% PQ53 AO4407A_SO8
PJ18
VIN 8 1 1 8 1 4 2 2 1 1 1 8
7 2 2 7 2 7
6 3 3 6 2 3 JUMP_43X118 CSIN 3 6
5 5 5

10U_1206_25V6M

10U_1206_25V6M

2200P_0402_25V7K
0.1U_0603_25V7K
1 1
CSIP PR352

5600P_0402_25V7K
4

4
1

1
PC244

PC245
47K_0402_1%
VIN

PC246

PC247
PQ54 TP0610K-T1-E3_SOT23-3 1 2

PC248

2
1

3 1 DCIN

1
P3

2
PR353 PD9

1
47K_0402_1% PR356 ACOFF

100K_0402_1%
0.1U_0603_25V7K
1 2

1
PR354 PQ55 10K_0402_1%

1
PC249

PR355
200K_0402_1% PDTC115EU_SOT323 1SS355_SOD323-2
2

PR357

1 1
PD10 200K_0402_1%

2
PR358 2 FSTCHG 1 2 VIN

2
3

2 1 2 1
47K PQ56 PD11 1SS355_SOD323-2 3 SUSP#
PDTA144EU_SOT323-3 1 2 6251VDD 100K_0402_1% SUSP# 36,38,42,48 PQ57 PD12
2 BAS40CW _SOT323-3 PDTC115EU_SOT323 2 1 2

2.2U_0603_6.3V6K
47K

PC250
PR359

3
1
10K_0402_5% wrong Value 1SS355_SOD323-2
FSTCHG 2 1 PU17 PC252
36 FSTCHG
1

0.1U_0603_25V7K

0.1U_0603_25V7K
2

1
PQ58 1 2 1 24 DCIN 2 1 PQ61D
1

VDD DCIN
1

1
PC253
PDTC115EU_SOT323 PR360 47K_0402_5% PC251 2 PACIN

100K_0402_1%
6251VDD 1 2 0.1U_0402_16V7K 2N7002W
G -T/R7_SOT323-3

PR362
2 PR361 2 23 S

3
ACSET ACPRN

1
150K_0402_1% PR363
PQ60 20_0402_5%
2

2
1

PQ59 D PDTC115EU_SOT323 6251_EN CSON


3 EN CSON 22 1 2

2
2 PC254
3

5
6
7
8
G 2N7002W -T/R7_SOT323-3 2 0.047U_0402_16V7K
36 3S/4S#
S 4 21 1 2 CSOP PQ62
3

1
CELLS CSOP PR364 AO4466_SO8
2
PC255 6800P_0402_25V7K 20_0402_5% 2

3 1 2 5 ICOMP CSIN 20 2 1
1

2
PQ63 D PR365 4
PC257 20_0402_5%
2
G 2N7002W -T/R7_SOT323-3 1 2 1 PR366 2 10K_0402_1% 6 19 0.1U_0603_25V7K
1 2 TCR=50ppm / C
<40,41>

1
PR368 VCOMP CSIP PR367 PL29
S
3

PC256 1 2 100_0402_1% 2_0402_5% 10UH_MMD-10DZ-100M-X1_6A_20% PR369 BATT+

3
2
1
ACON 0.01U_0402_25V7K PC258 1 2 7 18 LX_CHG 1 2 CHG 1 4
47 ACON ICM PHASE
@ 100P_0402_50V8J 0.02_1206_1%

4.7_1206_5%
5
6
7
8

1
36 ADP_I 2 3

PR370
PR371 PC259 6251VREF 8 17 DH_CHG
22K_0402_5% PR372 VREF UGATE PR373 PC260
1 2
PACIN 80.6K_0402_1% 0_0603_5% 0.1U_0603_25V7K

10U_1206_25V6M

10U_1206_25V6M
43,47 PACIN 1 2
2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1 PQ64

2
36 IREF CHLIM BOOT

1
PD13 4
0.01U_0402_25V7K

AO4466_SO8
1

1
PC263

PC264
PQ65 PR375

1
PC261

PDTC115EU_SOT323 PR374 6251VREF 1 6251ACLIM 6251VDDP

680P_0402_50V7K
2 10 ACLIM VDDP 15

PC262
100K_0402_1% RB751V-40_SOD323-2
2

2
1
2.55K_0402_1%
PR377
12.1K_0402_1% 20K_0402_1% 1 26251VDD

3
2
1

2
ACOFF 2 PR378 11 14 DL_CHG
36,47 ACOFF
2

1 VADJ LGATE

2
PR376
4.7_0603_5%
12 13 PC265
2

1
GND PGND 4.7U_0603_6.3V6K
3

2
1

PQ66 D ISL6251AHAZ-T_QSOP24
2
36 65W/90W# G 2N7002W -T/R7_SOT323-3
S
3

3
CP mode 3

VMB
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) <40,41>
where Vaclm=1.502V, Iinput=4.07A PR379
15.4K_0402_1%

1
1 2
36 CALIBRATE#
2

Ki VS PR380
Vchlim=Iref*(PR374/(PR372+PR374)) PR381 LI-3S :13.5V----BATT-OVP=1.5012V 340K_0402_1%
CC=0.6~4.48A =Iref*(100K/(80.6K+100K)) 31.6K_0402_1%

2
=Iref*0.5537 BATT-OVP=0.1112*VMB
Iref=0.7224*Ichanrge

0.01U_0402_25V7K
Ichanrge=(165mV/PR369)*(Vchlim/3.3V)
1

kI=0.7224 =(165m/20m)*(1/3.3V)*Iref*0.5537 Per cell=4.5V

PC266
=1.3842*Iref

1
Iref=0.7224*Ichanrge =>Ki=0.7224
IREF=0.43V~3.24V PR382

2
Kv 499K_0402_1%
Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K
R=514K//31.6K//(15.4K+3k)=11.372K

2
8
r=514K//514K//31.6K=28.14K PR383 PU13B
Vcell=0.175*Vadj+3.99v 10K_0402_1% LM358DT_SO8 5

P
4.2V=0.175*Vadj+3.99V =>Vadj=1.2V +
1 2 7 0
Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 36 BATT_OVP 6
-

G
1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899

1
1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv

0.01U_0402_25V7K
4

1
A=Vref*(R/(R+514K))=0.052 PR384

PC267
Kv=9.451 105K_0402_1%
Charging Voltage
BATT Type CV mode

2
(0x15)

2
4 4

Normal 3S LI-ON Cells


12600mV 12.60V

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/09/20 Deciphered Date 2010/08/01 Title
-
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71
Date: Tuesday, December 22, 2009 Sheet 46 of 56
A B C D
5 4 3 2 1

D D

PR385 B+
VL 2.2M_0402_5% PR386
2 1 1K_1206_5%
1 2

TP0610K-T1-E3_SOT23-3
PR388 PQ67
PD14

1
VIN 1K_1206_5%
PR387 2 1 1 2 3 1
B+
VS 499K_0402_1%
1

PR390
PR389 LL4148_LL34-2 1K_1206_5%

2
100K_0402_1% 1 2

100K_0402_5%

100K_0402_5%
1

1
PR392
PU18B PR391
2

PR393
18,44,45 MAINPWON PD15 LM393DG_SO8 1K_1206_5%

2
2 5 1 2
P

C + C
1 7 O
46 ACON 3 6

0.01U_0402_25V7K

2
-
G

1
32.4

PC270
BAS40CW _SOT323-3 PR394

1000P_0402_50V7K
4
1

PC269 191K_0402_1%
PC268 PR395

2
0.1U_0603_25V7K
2

PRG++ 2

1
499K_0402_1%
PR396

1
100K_0402_5%
PQ68
PDTC115EU_SOT323

1 2
PR397 1 PR398
34K_0402_1% PQ69D 47K_0402_5% 36,46 ACOFF 2
2 1 2 2 1 PQ70
RTCVREF 2N7002W
G -T/R7_SOT323-3 PACIN 43,46 PDTC115EU_SOT323

1
S
3

PQ71 2

3
1

PDTC115EU_SOT323
@ PR399
66.5K_0402_1% 2 +5VALW

3
2

ACIN
Precharge detector
Min. typ. Max.
B B
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V
BATT ONLY
Precharge detector
Min. typ. Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/09/20 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PRECHARGE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71
Date: Tuesday, December 22, 2009 Sheet 47 of 56
5 4 3 2 1
5 4 3 2 1

D D

C C

PL30
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% +1.8VSP
LX_1.8V 1 2
2

VFB=0.8V PR405

2
309K_0402_1%

1
PR563
PU20 4.7_1206_5% PC278 PC279
1

PR407 MP2121DQ-LF-Z_QFN10_3X3 22U_0805_6.3V6M 22U_0805_6.3V6M

2
402K_0402_1%

1
1 2 1 10 1.8V_EN
FB EN/SYNC

1
2 GND GND 9
PC281 PC382
1 2 3 8 680P_0402_50V7K
2
SW SW

+5VALW 0.01U_0402_16V7K PR566 4 7


0_0402_5% IN IN
1

B 1 2 5 6 B
BS POK
1

@ PD16
PC282
10U_0805_10V4Z
PC283
10U_0805_10V4Z TP 11
B340A_SMA2
+1.5V +1.5VS
2

OP1 PR409 PC287 PQ78 OP1 Short


2

OP2 PR409 OP2 Short

1
PJ20 PJ25

1
JUMP_43X79 JUMP_43X79

2
PU21

2
1 VIN VCNTL 6 +3VALW
2 GND NC 5

1
1
PC284 3 7 PC285
4.7U_0603_6.3V6K PR408 REFEN NC 1U_0402_6.3V6K

2
PR401 OP2@ 1K_0402_1% 4 8
22K_0402_5% PR409 VOUT NC

36,38,42,46 SUSP# 1 2 1.8V_EN 0_0402_5% 9

2
1 2 GND
APL5336KAI-TRL SO8
PR409

0.1U_0402_16V7K
+0.75VSP
1

1
24.9K_0402_1% PQ72 D PQ78 D

38,42 SUSP susp 2

PC286
PC274 1 2 2

1
0.47U_0603_16V7K G 2N7002W -T/R7_SOT323-3 G 2N7002W -T/R7_SOT323-3 PR410
2

2
1

S S 1K_0402_1% PC288
3

A PC287 10U_0805_6.3V6M A

2
1U_0402_6.3V6K
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/09/20 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VSP/+0.75VSP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71
Date: Tuesday, December 22, 2009 Sheet 48 of 56
5 4 3 2 1
A B C D

PJ21 B+
51117_1.5V_B+ 2 1
2 1
EN_PSV
JUMP_43X118

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1. GND=>Disable SMPS
2. FLOAT=>PWM_only mode

1
3. HIGH=>Auto_skip mode

PC289

PC290
5
6
7
8
Because +1.5VSP has 17.74A power budget, it includes

2
PQ73
1
DDR3, VGA chip, VRAM, so must use molding choke. AO4466_SO8 1

PR411 4
280K_0402_1%
1 2
PR412
0_0402_5%

3
2
1
1 2 1.5V_EN BST_1.5V

1
36,42 SYSON

1
@ PR413 PR414 PL32

15

14
PC292
+1.5VP

1
47K_0402_5% @ PC291 PU22 0_0603_5% 1UH_FDUE1040D-1R0M-P3_21.3A_20%
0.1U_0402_16V7K 1 2BST_1.5V-1 1 2 1 2

EN/DEM

NC

BOOT
2
2

2 13 UG_1.5V 0.1U_0603_25V7K
TON UGATE

1
3 12 LX_1.5V
VOUT PHASE

5
6
7
8
PR415 1
4 11 +5VALW PQ74 4.7_1206_5%
VDD CS AO4456_SO8 + PC293

2
5 10 330U_6.3V_M
PR416 FB VDDP

1
100_0603_1% LG_1.5V 2
6 9 4
open-drain PGOOD LGATE

PGND
1 2 PC294

GND
+5VALW
680P_0603_50V7K

2
1
11K_0402_1%
1
@ PC297 RT8209BGQW _W QFN14_3P5X3P5 PC295

3
2
1
1

4.7U_0805_10V6K

PR417
47P_0402_50V8J

2
PC296 1 2
4.7U_0603_6.3V6K
2

2
2
Rds=4.5mΩ(Typ) 2

PR418 5.6mΩ(Max)
5.9K_0402_1% VFB=0.75V
1 2 VFB=0.75V
Vo=VFB*(1+PR418/PR419)=1.52V
1

Freq=282KHz(min) , 300KHz(typ)
PR419
5.76K_0402_1% Cesr=15m ohm
Ipeak=13.61A
2

Iocpmin=18.98A
∆I=((19-1.5)*(1.5/19))/(L*Freq)=4.899A
1/2∆I=2.449A

Iocp=18.09A~29.13A

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71
Date: Tuesday, December 22, 2009 Sheet 49 of 56
A B C D
5 4 3 2 1

PJ22
VGA_CORE
B+ 2 1 B+_CORE Ipeak=27.82A
2 1
JUMP_43X118 Imax=19.47A

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
Delta I / 2 = 3.97A , Freq=1/ 75E-12*PR134=300K Hz

VGA@ PC98

VGA@ PC99

VGA@ PC100
LX_VCORE Iocp(min)=1.2*Ipeak+Delta I / 2 = 37.354A

0.1U_0805_50V7K
1

1
VGA@ PC171
VGA@ PR161 0_0603_5%
DH_VCORE 1 2 DH_VCORE-1 Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=6.49K ohm
VGA@ PR124 0_0603_5% VGA@ PC101
ISEN(min)=19uA , Rds(on)=5.6m ohm(max) ,4.5m ohm(typ)

2
1 2 1 2
D BST_VCORE
0.1U_0603_25V7K
Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=45.67A D

18 VGA_PWROK +5VS Iocp=37.35~45.67A

5
VGA@ PR125
0_0603_5%

VGA@ PR126

16

15
8

1
VGA@ PU998 4.7_0603_5% VGA@ PQ34

2
1 2 7138_VCORE 4 TPCA8030-H_SOP-ADV8-5

UG

BOOT
PHASE
GND

PGOOD
VGA@ PC102 Layout Note: DCR=1.6mΩ(typ)
3 14 1 2
+3VSDGPU VIN PVCC Close IC 1.8mΩ(max)

3
2
1
2.2U_0603_6.3V6K
VGA@ PL9
7138_VCORE 4 13 DL_VCORE 0.36UH_PCMC104T-R36MN1R17_30A_20%
VCC LG
2

1 4
+VGA_COREP
1
@ PR128 APW7138NITRL_SSOP16

5
6
7
8

5
6
7
8
10K_0402_5% VGA@ PC103 12 2 3
PGND

1
2 2.2U_0603_6.3V6K 1
VGA@ PR130 VGA@ PQ35 VGA@ PQ36 VGA@ PC104
1

30K_0402_1% VGA@ PR131 AO4456_SO8 AO4456_SO8 390U_2.5V_M +


24,38,42 VGA_ON VGA_ON 1 2 5 11 1 2 VGA@ PR129
EN ISEN

2
4.7_1206_5%
4 4 ESR=10 mΩ

1 2
6.49K_0402_1% 2

FSET
1

VGA@ PR127

NC

VO
FB
VGA@ PC105 VGA@ PC106 0_0402_5%
C .1U_0402_16V7K 470P_0603_50V8J C
2

10

3
2
1

3
2
1

1
VGA@ PR132
10_0402_5%
2 1 +NVVDD_SENSE
+NVVDD_SENSE 23

44.2K_0402_1%
Layout Note:

1
單單單單單單Pin15
VGA@ PC107

VGA@ PR134
22P_0402_50V8J

Close IC Rds=4.5mΩ(typ)
1

1
VGA@ PR133
5.6mΩ(max)
2200P_0402_25V7K
33K_0402_1% @ PC998 VGA@ PR135
0.01U_0402_25V7K 4.99K_0402_1%
2

2
VGA@ PC109

2
@PC998 for IC APW7138
1
2

Layout Note: VFB=0.6V


Close IC

1
VGA@ PR136
B 49.9K_0402_1% @ PR137 B
1

43.2K_0402_1% +3VSDGPU

2
VGA@ PR138 +3VSDGPU

1
11.8K_0402_1%
2

N11P-GV2H @ PR139
VGA@ PR140 10K_0402_5%
10K_0402_5% @ PR141

2
1
GPU_VID0 GPU_VID1 Core Voltage Level D 10K_0402_5%
VGA@ PR142 @ PQ38 2 1 2
2

1
10K_0402_5% D VGA@ PQ75 2N7002W-T/R7_SOT323-3 G

1
1 1 reserve 2 1 2 2N7002W-T/R7_SOT323-3 S +3VSDGPU

1
+3VSDGPU G
S @ PC110 @ PR143

3
1

1
0 1 reserve 4700P_0402_25V7K 10K_0402_1%

2
VGA@ PC111 @ PR145

2
4700P_0402_25V7K 10K_0402_5%
2
1

1 0 0.85V
@ PR146 @ PR144
2

2
10K_0402_5% 10K_0402_1% @ PR147

1
D
0 0 0.9V 10K_0402_5%
@ PQ76 2 2 1
GPU_VID1 22
2

1
VGA@ PR148 2N7002W-T/R7_SOT323-3 G
1

10K_0402_5% D
S

3
1 2 2 VGA@ PQ77 @ PR149
22 GPU_VID0
1

G 2N7002W-T/R7_SOT323-3 10K_0402_5%
S
3

2
VGA@ PR150
A A
10K_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/08/25 Deciphered Date 2010/08/25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NEW71
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 22, 2009 Sheet 50 of 56
5 4 3 2 1
5 4 3 2 1

PJ23
2 1 6268_B+
B+ 2 1
JUMP_43X118 PR458 +3VS
0_0402_5%

10U_1206_25V6M

10U_1206_25V6M
1 2
LX_1.05VS_VTT

1
H_VTTPWRGD 5

2K_0402_1%
PC326

PC327
DH_1.05VS_VTT

PR459
PGOOD=1V PR461

2
BST_1.05VS_VTT
1 2 1 2
@ PR462 0_0603_5%

2
D 1K_0402_1% PC328 D
1 2 +5VS 0.1U_0603_25V7K

5
PR463
0_0603_5%

PR464 PQ82

16

15
8

1
PU999 4.7_0603_5% TPCA8030-H_SOP-ADV8-5

2
1 2 6268_VCORE_1.05VS_VTT 4

UG

BOOT
PHASE
GND

PGOOD
Layout Note: DCR=2.7mΩ(Typ)
3 14 1 2
VIN PVCC Close IC 3.0mΩ(Max)

3
2
1
PC329
2.2U_0603_6.3V6K
6268_VCORE_1.05VS_VTT
4 VCC LG 13 DL_1.05VS_VTT PL38 +1.05VS_VTTP
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1 2

1
APW7138NITRL_SSOP16

1
TPCA8028-H_SOP-ADVANCE8-5

TPCA8028-H_SOP-ADVANCE8-5
PC330 12
2.2U_0603_6.3V6K PGND @

PQ83

PQ95
PR466 PR465
57.6K_0402_1% Change PU999 to APW7138 in PVT. 4.7_1206_5%
38 VS_ON 1 2 5 11 1 2

1 2
EN ISEN
4 4 1

1
PR467

FSET
1
5.23K_0402_1% PC332 + PC333

NC

VO
FB
@ PR468 PC331 680P_0603_50V7K 390U_2.5V_M

2
10K_0402_5% 0.1U_0402_16V7K

10

3
2
1

3
2
1
C 2 C
2

90.9K_0402_1%
1

57.6K_0402_1%
Rdson=2.3mΩ/3.2mΩ Material Note:

1
22P_0402_50V8J
Layout Note: 330uF/9 mΩ, number

1
單單單單單單Pin15

PR469
PC334 Close IC are 3, Power 1, HW 2

PR470
6800P_0402_25V7K
@ PC999
0.01U_0402_25V7K
2

2
2
1
PC336
@ PR471
@PC999 for IC APW7138 0_0402_5%
1 2 +1.05VS_VTTP

2
+1.05VS_VTT
Ipeak=20.14A PR472
5.11K_0402_1%
@ PR473
10_0402_5%
Imax=14.10A 1 2 1 2 VTT_SENSE 7
Delta I / 2 = 2.176A , Freq=230K Hz VFB=0.6V
Iocp(min)=1.2*Ipeak + Delta I / 2 = 26.34A
Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=5.23K ohm PR564
0_0402_5%
ISEN(min)=19uA , Rds(on)=3.2m ohm(max) ,2.3m ohm(typ) 1 2 +1.05VS_VTT
B Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=36A B
1

Iocp=26.34~36A
Vref=(Rb/(Rtop+Rbot))*Vo PR476
6.65K_0402_1%
=>0.6=(6.65/(5.11+6.65))*Vo
2

Vo=1.061V

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/4/15 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS_VTTP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NEW71
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 22, 2009 Sheet 51 of 56
5 4 3 2 1
5 4 3 2 1

Intel Auburndale CPU(Integrate Graphics) Ipeak=22A Imax=15A


OCP calculation : Assume DCR=1.1m ohm
G1=Rn/(Rn+Rsum)=0.617
where Rn=PR277 // (PR274+PH3)=5.875k ohm
Rsum=PR269=3.65k ohm
LL=2*Rdroop*G1*DCR/Ri= 6.96m V/A
D D
where Rdroop=PR271=8.66k ohm, Ri=PR283=1.69k ohm
Iocp=OCP Threshold*Rdroop/LL=24.89A

B+ PJ24
2 1 GFX_B+
2 1

2
JUMP_43X118

10U_1206_25V6M

10U_1206_25V6M
2200P_0402_50V7K
UMA@ PR263
@ PC188 UMA@ PR264 0_0603_5% VSS_AXG_SENSE
UMA@ PC187

UMA@ PC125

UMA@ PC126

0.22U_0603_25V7K
1

1
0.1U_0402_25V6 1_0603_5%

UMA@ PC190
+5VALW 2 1

1 1

2
2

2
UMA@ PC189
1U_0402_6.3V6K UMA@ PR265 UMA@ PC191
22.6K_0402_1% 0.22U_0402_6.3V6K

1
1
UMA@ PR292
GFXVR_IMON 8
2 1 ISUM+

5
10_0402_1% UMA@ PC192
1000P_0402_50V7K ISUM- UMA@ PQ39
1 2 BST_GFX 1 2 1 2 TPCA8030-H_SOP-ADV8-5
8 VSS_AXG_SENSE
1

C UMA@ PR266 UMA@ PC193 C


UMA@ PC194 0_0603_5% 0.22U_0603_25V7K 4
8 VCC_AXG_SENSE 330P_0402_50V7K

29

10

11

12

13

14
1 2
2

9
+VGFX_COREP UMA@ PC195
DCR=1.1 mOHM

AGND

RTN

ISUM+

VDD

VIN

IMON

BOOT
ISUM
2 1 330P_0402_50V7K

3
2
1
UMA@ PR293
10_0402_1% 7 15 DH_GFX UMA@ PL10 +VGFX_COREP
VSEN UGATE 0.45UH_PCMB104T-R45MN_25A_20%
6 UMA@ PU12 16 LX_GFX 4 1
FB ISL62881HRZ-T_QFN28_4X4 PHASE

5
6
7
8

5
6
7
8
5 17 3 2
COMP VSSP

1
4 18 DL_GFX UMA@ PQ40 UMA@ PR268 1
VW LGATE

1
UMA@ PR294 AO4456_SO8 4.7_1206_5% UMA@
2 1 3 19 UMA@ UMA@ PR269 PR270 + UMA@ PC130
UMA@ PR271 UMA@ PR272 UMA@ PC197 RBIAS VCCP PQ41 3.65K_0805_1% 330U_X_2VM_R6M
47K_0402_1% 4 4 0_0402_5%

2
8.66K_0402_1% 825K_0402_1% 1000P_0402_50V7K 2 20 UMA@ PR273 AO4456_SO8
PGOOD VID0 UMA@ PR274 2
2 1 1 2 1 2 2 1 1 2 +5VALW

2
147K for CPU 1 21 0_0603_5% 2.61K_0402_1% UMA@ PH3

DPRSLPVR
CLK_EN# VID1

2
UMA@ PC196 1 2 1 2
47K for GPU

3
2
1

3
2
1
1
100P_0402_50V8J +VGFX_COREP UMA@ PC199

VR_ON
680P_0603_50V7K 10K +-5% TSM0A103J4302RE 0402

VID6

VID5

VID4

VID3

VID2

1
UMA@ PR275 UMA@ PC201 UMA@ PR276 UMA@ PC198

2
17.8K_0402_1% 22P_0402_50V8J 8.06K_0402_1% 2.2U_0603_6.3V6K
2 1 2 1 1 2 2 1

28

27

26

25

24

23

22
1 2
UMA@ PC200 UMA@ PR277
Rds=4.5mOHM(typ)
1

150P_0402_50V8J 11K_0402_1% Material Note:


Rds=5.6mOHM(max) Layout Note: 330uF/6 mΩ, number are 3, PW
@ PR279
10K_0402_1% Place near Choke 1 2 1, HW 1, 1 of HW is backup
2

UMA@ PC202
0.1U_0402_16V7K

B 36 GFX_CORE_PWRGD B
1 2

2
0_0402_5% 2 UMA@
1 PR280 UMA@ PC203
0_0402_5% UMA@ PR281 GFXVR_VID_0 8 0.1U_0402_16V7K @ PR284
2 1
0_0402_5% UMA@ PR282 GFXVR_VID_1 8 UMA@ PR283
2 1 100_0402_1%
0_0402_5% UMA@ PR285 GFXVR_VID_2 8 UMA@ PR288 1.69K_0402_1%
2 1
0_0402_5% UMA@ PR286 GFXVR_VID_3 8 82.5_0402_1%
2 1

1
0_0402_5% UMA@ PR287 GFXVR_VID_4 8
2 1 1 2 1 2
0_0402_5% UMA@ PR289 GFXVR_VID_5 8
2 1
GFXVR_VID_6 8

2
0_0402_5% 2 UMA@
1 PR290 UMA@ PC204
0_0402_5% UMA@ PR291 GFXVR_EN 8 0.01U_0402_16V7K @ PC205
2 1
GFXVR_DPRSLPVR 8
180P 50V J NPO 0402

1
ISUM+
1

@ PR300 ISUM-
1K_0402_1%
reduce system idle power
2

+1.05VS_VTTP

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2009/4/15 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GFX_COREP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71
Date: Tuesday, December 22, 2009 Sheet 52 of 56
5 4 3 2 1
8 7 6 5 4 3 2 1

+5VS

HFM_VID HFM_Icc LL Icc_TDC Icc_Dyn

H PH0 PH1 # of PH Auburndale 45W 1.075 50 1.9m 37 35 H

1
7 H_DPRSLPVR
PR565
7 H_PSI# 0_0805_5% 0 1 2 Auburndale 35W 0.975 38 1.9m 29 27

2
7 CPU_VID6 1 1 3 Clarksfield SV 0.95 51 1.9m 38 39
7 CPU_VID5
7 CPU_VID4
7 CPU_VID3
+5VS_3212 Clarksfield XE 0.95 65 TBD 48 TBD
+5VS_3212
7 CPU_VID2
7 CPU_VID1
7 CPU_VID0

1
+CPU_B+ PL39
PR481 FBMA-L18-453215-900LMA90T_1812
10_0603_5%
36,38 VR_ON 2 1 B+

2
G G

10U_1206_25V6M

10U_1206_25V6M
2200P_0402_50V7K
0.1U_0603_25V7K

220U_25V_M
1

499_0402_1%

PC339

PC341
0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%
1

1
PC344 +

PC345

PC343
2

2
2
+3VS 1U_0603_16V6K

PC342
5

2
+3VS PR491 PQ87 @ 2

1
0_0603_5% TPCA8030-H_SOP-ADV8-5

2
2

PR482

PR483

PR484

PR485

PR486

PR487

PR488

PR489

PR490
2 1
PR492
2

3K_0402_5% 3212_DRVH1 4 3212_DRVH1 4


3K_0402_5%

0_0402_5%
1 PU27 @ PQ86
PR493

PGND
1

PR495 0_0402_5% TPCA8030-H_SOP-ADV8-5 PL40


AGND

48

47

46

45

44

43

42

41

40

39

38

37
0.36UH +-20% ETQP4LR36WFC 24A
1

3
2
1

3
2
1
1 2 CLK_EN# 3212_SW1 1 4

VID0

VID1

VID2

VID3

VID4

VID5

VID6

PH0

PH1
PSI

VCC
DPRSLP
12 CLK_ENABLE# +CPU_CORE
PR497 0_0402_5%
2

+1.05VS_VTT PR498 PC346


PR494

2 3

5
12,15 VGATE 1 2 0_0603_5% 0.1U_0603_25V7K DCR=1.1m OHM

1
F F
1 36 2 1 2 1
EN BST1
1

1
PR499
4.7_1206_5% PR500
@ PR496 2 35 3212_DRVH1 @ 10_0402_5%
0_0402_5% PWRGD DRVH1 3212_DRVL1 3212_DRVL1
4 4

1 2
2

2
IMVP_IMON 3 34 3212_SW1
7 IMVP_IMON IMON SW1
2

PR502 PC347
1

100_0402_1% 680P_0603_50V7K

3
2
1

3
2
1

3212_CS_PH1
PR501 PC348 CLK_EN# 4 33 1 2 3212_CS_PH1 @
5.49K_0402_1% CLKEN SWFB1
0.068U_0402_16V7K
2

CSREF
PQ88
1

1 2 3212_FBRTN 5 32 +5VS TPCA8028-H_SOP-ADVANCE8-5


FBRTN PVCC VGA@ PQ89
PC349 PC351 150P_0402_50V8J 12P_0402_50V8J TPCA8028-H_SOP-ADVANCE8-5

1
1000P_0402_50V7K 1 2 3212_FB PC352 6 31 3212_DRVL1 +CPU_B+
FB DRVL1 PC350
ADP3212MNR2G_QFN48_7X7
1

PC353 4.7U_0603_6.3V6K

2
150P_0402_50V8J PR504 7 30
E PR503 COMP PGND E
1.65K_0402_1% 39.2K_0402_1%

10U_1206_25V6M
2

1 2 1 2 1 2

1
2 1 8 29 3212_DRVL2 PC355 @ PC356
5.11K_0402_1% TRDET DRVL2

5
PR505 PR506 10U_1206_25V6M 0.1U_0603_25V7K

PC354
100_0402_1% PQ90

2
+5VS_3212 9 28 1 2 3212_CS_PH2 TPCA8030-H_SOP-ADV8-5
VARFR SWFB2

3212_VRTT 10 27 3212_SW2 3212_DRVH2 4 3212_DRVH2 4


VRTT SW2
2

+3VS @ PQ91 PL41


PR507 PR508 TTSENSE 11 26 3212_DRVH2 TPCA8030-H_SOP-ADV8-5 0.36UH +-20% ETQP4LR36WFC 24A
0_0402_5% 0_0402_5% TTSNS DRVH2 PR509 PC358

3
2
1

3
2
1
0_0603_5% 0.1U_0603_25V7K 3212_SW2 4 1
2

12 25 2 1 2 1
1

PR510 GND BST2


3 2
CSCOMP

5
@ 499_0402_1%
CSSUM

SWFB3
CSREF

PWM3

1
RAMP

LLINE

PR511 0_0402_5% 49
IREF

RPM

OD3
ILIM

AGND PR512
RT

D D
1

2
1 2 4.7_1206_5%
5 H_PROCHOT#
@ PR513
13

14

15

16

17

18

19

20

21

22

23

24

3212_DRVL2 4 3212_DRVL2 4 10_0402_5%

1 2
2N7002W-T/R7_SOT323-3

D
PQ94

162K_0402_1%

1
1

2 3212_VRTT PC359
3212_CSCOMP

3212_CSCOMP

680P_0603_50V7K

3212_CS_PH2
PR514
PR516

3
2
1

3
2
1

2
S 80.6K_0402_1% @
3

Avoid high dV/dt

CSREF
+5VS_3212 2.05K VGA@ PQ93 PQ92
2

TPCA8028-H_SOP-ADVANCE8-5 TPCA8028-H_SOP-ADVANCE8-5
1
1

PR515 PR517 PR519


2

PR518 69.8K_0402_1% 649K_0402_1% 2.05K_0402_1% Place PH1 close to


7.32K_0402_1% Connect to input caps PHASE 1 inductor on
2

the same layer


2

C TTSense +CPU_B+ 2 PR520 1 C


1200P_0402_50V7K
1

1K_0402_1%
73.2K_0402_1%
680P_0402_50V7K

PC360
1

PR522

0.01U_0402_50V7K
2

PR521 PC361 PH6


PC362

PC363

0_0402_5% 1000P_0402_50V7K 100K_0402_1%_NCP15WF104F03RC


2

PR523
2

165K_0402_1%
2

CSREF 1 2
2
2

PC364 PR524 130K_0603_1%


PH7 1U_0603_16V6K 2 1 3212_CS_PH1
1

100K_0402_1%_NCP15WF104F03RC

2 1 3212_CS_PH2
1

B PR525 130K_0603_1% B

@ PR526
100_0402_1%
2 1 +CPU_CORE

VCCSENSE
VCCSENSE 7

VSSSENSE
VSSSENSE 7

2 1

PR527 100_0402_1%
A @ A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/04 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5893P Schematic
Date: Tuesday, December 22, 2009 Sheet 53 of 56
8 7 6 5 4 3 2 1
5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 3


for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
Change PD8 from SC1SS355003(S DIO 1SS355)
D For BOM unique. For BOM unique. to SC100001K00( DIO 1SS355 SOD323 T/R-5K) 2009-1021 to DVT D
0.1 46
1
Delete PQ86/PQ91 SB00000HL00(S TR TPCA8030-H 1N SOP).
For BOM unique. For BOM unique. 0.1 54 2009-1021 to DVT
Add PQ87/PQ90 SB00000HL00(S TR TPCA8030-H 1N SOP).
2
For UMA Arrandale CPU For UMA Arrandale CPU, we just only pop 1 HS MOS
commond design. and 1 LS MOS. Delete PQ89/PQ93 SB00000GL00(S TR TPCA8028-H 1N SOP) 2009-1021 to DVT
0.1 54
3
For VTT Power rail commond design, we pop 1 HS MOS
For VTT Power rail commond design. and 1LS MOS. Delete PQ95 SB00000GL00(S TR TPCA8028-H 1N SOP) 2009-1021 to DVT
0.1 52
4
Change PR500 from SD028100A00(S RES 1/16W 10 +-5% 0402)
CIS link error. CIS link error. 0.1 54 to SD028100A80(S RES 1/16W 10 +-5% 0402) 2009-1021 to DVT
5
Chnage PC265 from SE107475M80(S CER CAP 4.7U 6.3V M X5R
BOM unique. BOM unique. 0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603) 2009-1021 to DVT
0.1 47
6
Chnage PC284 from SE107475M80(S CER CAP 4.7U 6.3V M X5R
BOM unique. BOM unique. 0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603) 2009-1021 to DVT
0.1 49
7
Chnage PC350 from SE107475M80(S CER CAP 4.7U 6.3V M X5R
BOM unique. BOM unique. 0.1 54 0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603) 2009-1021 to DVT
C 8 C

Chnage PC367 from SE107475M80(S CER CAP 4.7U 6.3V M X5R


BOM unique.(For Madison/Park SKU) BOM unique.(For Madison/Park SKU) 0.1 52 0603 to SE107475K80(S CER CAP 4.7U 6.3V K X5R 0603) 2009-1021 to DVT
9
Change PC225/PC227 from SE153106K80(S CER CAP 10U 25V K
BOM unique. BOM unique. 0.1 46 X6S 1206) to SE142106M80 (S CER CAP 10U 25V M X5R 1206) 2009-1021 to DVT
10
Change PC339/PC341 from SE153106K80(S CER CAP 10U 25V K
11 BOM unique. BOM unique. 0.1 54 X6S 1206) to SE142106M80 (S CER CAP 10U 25V M X5R 1206) 2009-1021 to DVT
Change PC354/PC355 from SE153106K80(S CER CAP 10U 25V K
X6S 1206) to SE142106M80 (S CER CAP 10U 25V M X5R 1206)
12 Delete PQ95 SB00000GL00(S TR TPCA8028-H 1N SOP )
+1.05VS_VTTP Cost down 1 LS MOS. +1.05VS_VTTP Cost down 1 LS MOS. Delete PR471 SD028000080(S RES 0 0402 5%)
HW request. Because +1.05VS_VTT has voltage drop issue, 0.2 52 Delete PR473 from SD034100A80(S RES 10 0402 5%) 2009-1029 to DVT
13 HW request, remote sense to close to PCH. Add PR564 SD028000080(S RES 1/16W 0 0402 5%)

Adjust +1.05VS_VTTP OCP. Because we remove a LS MOS, so OCP must adjust. 0.2 52 Change PR467 from SD000004O80(S RES 1/16W 2.2K +-1% 0402) 2009-1029 to DVT
14 to SD034499180(S RES 1/16W 4.99K 0402 1%)
+1.8VSP2, Using MP2121 for 1.8V No need to use LDO for +1.8V.
0.2 49 Delete PU19 SA00001NC00 (S IC APL5913-KAC-TRL SO 8P) 2009-1029 to DVT
15 only. Delete all PU19 circiut.
B +1.8VSP2, Using MP2121 for 1.8V No need to use LDO for +1.8V. Delete PR402 SD034150280, PR404 SD034120280. B

only. Delete all PU19 circiut. 0.2 49


Delete PC273 SE075103K80 PC275 SE000000I10 2009-1029 to DVT
16
+1.8VSP2, Using MP2121 for 1.8V No need to use LDO for +1.8V. Delete PC272 SE107475K80, PC271 SE107105M80
only. Delete all PU19 circiut. 49 2009-1029 to DVT
0.2 Delete PR401 and PR403 SD028220280, PC274 SE026474K80
17
Change PR196 from SD034442280 to SD034365280.
+VGA_COREP, efficiency issue. Increase Freq, decrease choke, to improve efficiency. 0.2 51 2009-1029 to DVT
Change PL14 from SL200000V00 to SH000005680
18
Becasue if PR199/PR202 pop 0ohm, it will cause OVP Change PR199/PR202 from SD028000080 to SD028100280
+VGA_COREP, OVP issue. when VID change from 00 to 11) 0.2 51 (S RES 1/16W 10K 0402 5%) 2009-1029 to DVT
19
Change PQ75/PQ78 from SB00000GL00(S TR TPCA8028-H 1N SOP)
+VGA_COREP, cost issue. Cost down. 0.2 51 to SB000009F80(S TR AO4456 1N SO8) 2009-1029 to DVT
20
+VGA_COREP, satndard design, pop 1HS MOS and 2LS MOS, Delete PQ79 SB000008L80 (S TR SI7686DP-T1-E3 1N
+VGA_COREP, satndard design. so remove one HS MOS PQ79. 0.2 51 POWERPAK SO8 ) 2009-1029 to DVT
21
Because +GFX_COREP has spike voltage issue, add
+GFX_COREP, spike issue. schottky diode across GFXVR_EN and VS_ON to solve it. 0.2 51 Add PD17 SCS00000Z00 (S SCH DIO RB751V-40 SOD-323 ) 2009-1029 to DVT
22
A +VGA_COREP, OCP caaculation erroe Because VGA_CORE has 2 LS MOS, APW7138 detect LS Rdson, 0.2 51 Change PR190 from SD034649180 to SD034511180 2009-1029 to DVT A

23 issue. so when caculate OCP, Rdson must reduce 1/2. (S RES 1/16W 5.11K 0402 1%)

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/09/20 Deciphered Date 2010/08/01 Title
PIR (PWR)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS NEW70 M/B LA-5891P Schematic
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 22, 2009 Sheet 54 of 56
5 4 3 2 1
5 4 3 2 1

A -->Modify item

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2007/09/20 Deciphered Date 2010/08/01 Title
PIR (HW)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW71/91 M/B LA-5891P Schematic
Date: Friday, December 18, 2009 Sheet 55 of 56
5 4 3 2 1
A B C D E

1 1

2 2

PCB
ZZZ

LA-5893P REV0 M/B

ZZZ1

X7621@ ALT. GROUP PARTS 1G SAM

X76198BOL21

ZZZ2
3 3

X7622@
ALT. GROUP PARTS 1G HYN
X76198BOL22

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2008/08/10 Deciphered Date 2010/08/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Option Component
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NEW70 M/B LA-5891P Schematic
Date: Monday, December 21, 2009 Sheet 56 of 56
A B C D E
www.s-manuals.com

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