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H.D.L – LAB
For IV Semester B.E
By
HDL
LABORATORY MANUAL
(06ESL48)
DEPARTMENT
OF
ELECTRONICS & COMMUNICATION ENGINEERING
INDEX
Opcode(3:0)
Enable
ALU should use the combinational logic to calculate an output based on the four
bit op-code input.
ALU should pass the result to the out bus when enable line in high, and tri-state
the out bus when the enable line is low.
ALU should decode the 4 bit op-code according to the given in example below.
5. Develop the HDL code for the following flip-flop, SR, D, JK, T.
6. Design 4 bit binary , BCD counters (Synchronous reset and asynchronous reset) and
“any sequence” counters
INTERFACING (at least four of the following must be covered using VHDL/Verilog)
1. Write HDL code display messenger on the given seven segment display and LCD
and accepting Hex key pad input data.
2. Write HDL code to control speed, direction of DC and stepper motor.
3. Write HDL code to accept 8 channel analog signal, Temperature sensors and
display the data on LC panel or seven segment display
4. Write HDL code to generate different waveforms (Sine, Square, Triangle,
Ramp etc.,)using DAC change the frequency and amplitude.
5. Write H DL code to simulate Elevator operation
6. Write HDL code to control external light using relays.
*******************
HDL MANUAL
It is one of most popular software tool used to synthesize VHDL code. This tool
Includes many steps. To make user feel comfortable with the tool the steps are
given below:-
HDLnavigator.
Double click on Project MANUAL (Assumed icon is present on desktop).
Select NEW PROJECT in FILE MENU.
Enter following details as per your convenience
Project name : sample
Project location : C:\example
Top level module : HDL
In NEW PROJECT dropdown Dialog box, Choose your appropriate device
specification. Example is given below:
Device family : Spartan2
Device : xc2s200
Package : PQ208
TOP Level Module : HDL
Synthesis Tool : XST
Simulation : Modelsim / others
Generate sim lang : VHDL
In source window right click on specification, select new source
Enter the following details
Entity: sample
Architecture : Behavioral
Enter the input and output port and modes.
This will create sample.VHDL source file. Click Next and finish the initial Project
preparation.
Double click on synthesis. If error occurs edit and correct VHDL code.
Double click on Lunch modelsim (or any equivalent simulator if you are using) for
functional simulation of your design.
Right click on sample.VHDL in source window, select new source
Select source : Implementation constraints file.
File name : sample
This will create sample. UCF constraints file.
Double click on Edit constraint (Text) in process window.
Edit and enter pin constraints with syntax:
NET “NETNAME” LOC = “PIN NAME”
Double click on Implement, which will carry out translate, mapping, place and route
of your design. Also generate program file by double clicking on it, intern which
will create .bit file.
Connect JTAG cable between your kit and parallel pot of your computer.
Double click on configure device and select mode in which you want to configure
your device. For ex: select slave serial mode in configuration window and finish
your configuration.
Right click on device and select „program‟. Verify your design giving appropriate
inputs and check for the output.
Also verify the actual working of the circuit using pattern generator & logic
analyzer.
EXPERIMENT NO. 1
Black Box
c
a d
LOGIC e
GATES f
b g
h
i
begin
c<= a and b;
d<= a or b;
e<= not a;
f<= a nand b;
g<= a nor b;
h<= a xor b;
i<= a xnor b;
end dataflw;
Output (c to i)
RESULT: The logic gates design have been realized and simulated using HDL codes.
EXPERIMENT NO.2
AIM: Write a HDL code to describe the functions of Half adder, Half Subtractor and Full
Subtractor.
INPUTS OUTPUTS
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
BOOLEAN EXPRESSIONS:
S=A B
C=A B
architecture dataflow of HA is
begin
s<= a xor b;
c<= a and b;
end dataflow;
(b)HALF SUBTRACTOR
BASIC GATES
architecture dataflow of hs is
begin
d<= a xor b;
br<= (not a) and b;
end dataflow;
(C)FULL SUBTRACTOR
architecture dataflw of fs is
begin
d<= a xor b xor c;
br<= ((not a) and (b xor c)) or (b and c);
end datafolw;
RESULT: The half adder, half subtractor and full subtractor designs have been realized and
simulated using HDL codes.
EXPERIMENT NO.3
AIM: Write HDL codes for the following combinational circuits.
3.a) 2 TO 4 DECODER
BLACK BOX
Y0
Sel 0 2 to 4
Sel 1 Y1
Decoder Y2
E Y4
E Sel1 Sel0 Y3 Y2 Y1 Y0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
0 X X 0 0 0 0
DATA FLOW
VHDL CODE VERILOG CODE
Output
Black Box
i7 Z3
8:3 Z1
Parity Z0
Encoder
enx
i0 V
en
Truth table
En I7 I6 I5 I4 I3 I2 I1 I0 Z2 Z1 Z0 enx V
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 1 1 1 1 1 1 0 1 1 1 0 1
0 1 1 1 1 1 1 0 X 1 1 0 0 1
0 1 1 1 1 1 0 X X 1 0 1 0 1
0 1 1 1 1 0 X X X 1 0 0 0 1
0 1 1 1 0 x X X X 0 1 1 0 1
0 1 1 0 X X X X X 0 1 0 0 1
0 1 0 X X X X X X 0 0 1 0 1
0 0 X X X X X X X 0 0 0 0 1
Output
3.c) 8 TO 1 MULTIPLEXER
Black Box
b
c
d 8:1Mux Z
e
f
g
h
sel (2 to 0)
Truth table
Sel2 Sel1 Sel0 Z
0 0 0 A
0 0 1 B
0 1 0 C
0 1 1 D
1 0 0 E
1 0 1 F
1 1 0 G
1 1 1 H
Output
Black Box
clk 4 bit
en Binary to q(3 downto 0)
rst gray
Truth table
Rst Clk En B3 B2 B1 B0 G3 G2 G1 G0
1 X 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 1
0 1 1 0 0 1 0 0 0 1 1
0 1 1 0 0 1 1 0 0 1 0
0 1 1 0 1 0 0 0 1 1 0
0 1 1 0 1 0 1 0 1 1 1
0 1 1 0 1 1 0 0 1 0 1
0 1 1 0 1 1 1 0 1 0 0
0 1 1 1 0 0 0 1 1 0 0
0 1 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 0 1 1 1 1
0 1 1 1 0 1 1 1 1 1 0
0 1 1 1 1 0 0 1 0 1 0
0 1 1 1 1 0 1 1 0 1 1
0 1 1 1 1 1 0 1 0 0 1
0 1 1 1 1 1 1 1 0 0 0
3.e)MULTIPLEXER(4 TO 1)
Black Box
a
b 4:1 Z
c Mux
d
sel (1 to 0)
Truth Table
Sel1 Sel0 Z
0 0 a
0 1 b
1 0 c
1 1 d
end dataflow;
( 4:1)Multiplexer Output
3.f) DE-MULTIPLEXER ( 1 TO 4)
Black Box
a
en 1:4 Y(3 downto 0)
Demux
sel(1 downto 1)
Truth table
a en Sel1 Sel0 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0 1
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 1 0 0 0
0 1 X X 0 0 0 0
output
Outp
Black Box
a L
1bit E
b Comparat
or G
Truth table
a b L E G
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
component and_2 is
port( a, b: in std_logic;
c: out std_logic);
end component;
component xnor_2 is
port( a, b: in std_logic;
c: out std_logic);
end component;
signal s1,s2: std_logic;
begin
X1: not_2 port map (a, s1);
X2: not_2 port map (a, s2);
X3: and_2 port map (s1, b, L);
X4: and_2 port map (s2, a, G);
X5: xnor_2 port map (a, b, E);
end structural;
output
NET "a" LOC = "p74" ;
NET "b" LOC = "p75" ;
NET "E" LOC = "p86" ;
3.h)4-BIT COMPARATOR
Black Box
a(3 to 0) x
4bit y
Comparato
b(3 to 0) r z
output
Greater than Equal to Less than
RESULT: Combinational designs have been realized and simulated using HDL codes.
EXPERIMENT NO.4
AIM: Write HDL code to describe the functions of a full Adder Using three modeling styles.
a
FULL Sum
b ADDER
Cout
c
Truth table
INPUTS OUTPUTS
a b cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
BEHAVIORAL STYLE
STRUCTURAL STYLE
component and_2
port(l,m:in std_logic;
n:out std_logic);
end component;
component or_3
port(p,q,r:in std_logic;
s:out std_logic);
end component;
begin
X1: xor_3 port map ( a, b, cin,sum);
A1: and_2 port map (a, b, c1);
A2: and_2 port map (b,cin,c2);
A3: and_2 port map (a,cin,c3);
O1: or_3 port map (c1,c2,c3,carry);
end structural;
//and gate//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and2 is
Port ( l,m : in std_logic;
n : out std_logic);
end and2;
architecture dataf of and2 is
begin
n<=l and m;
end dataf;
//or gate//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or3 is
Port ( p,q,r : in std_logic;
s : out std_logic);
end or3;
architecture dat of or3 is
begin
s<= p or q or r;
end dat;
//xor gate//
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor3 is
Port ( x,y,z : in std_logic;
u : out std_logic);
end xor3;
EXPERIMENT NO. 5
AIM: Write a model for 32 bit ALU using the schematic diagram shown below.
Black box
A1(3 to 0)
B1(3 to 0)
ALU Zout (7 downto 0)
opcode (2 to 0)
Truth table
Operation Opcode A B Zout
A+B 000 1111 0000 00001111
A-B 001 1110 0010 00001100
A or B 010 1111 1000 00001111
A and B 011 1001 1000 00001000
Not A 100 1111 0000 11110000
A1*B1 101 1111 1111 11100001
A nand B 110 1111 0010 11111101
A xor B 111 0000 0100 00000100
RESULT: 32 bit ALU operations have been realized and simulated using HDL codes.
EXPERIMENT NO.6
AIM: Develop the HDL code for the following flipflop: T, D, SR, JK.
T FLIPFLOP
Black Box
t
clk q
T ff
rst qb
Truth table
Rst T Clk q
1 0 1 q
1 1 1 qb
1 X No +ve edge Previous state
0 X X 0
Rising edge
Output
D FLIPFLOP
Black Box
d
q
D FF
clk qb
Truth table
clk d q qb
X 1 1 0
1 1 1 0
1 0 0 1
SR FLIPFLOP
Black Box
clk
s q
r SR FF
rst qb
pr
Truth table
rst pr Clk s r q qb
1 X X X X 0 1
0 1 X X X 1 0
0 0 1 0 0 Qb Qbprevious
0 0 1 0 1 0 1
0 0 1 1 0 1 0
0 0 1 1 1 1 1
S R
output
JK FLIPFLOP
Black Box
j
k q
JK FF
clk qb
rst
end Behavioral;
Truth table
Rst Clk J K Q Qb
1 1 0 0 Previous state
1 1 0 1 0 1
1 1 1 0 1 0
1 1 1 1 Qb Q
1 No+ve egde - - Previous state
0 - - - 0 1
RESULT: Flip-flop operations have been realized and simulated using HDL codes
EXPERIMENT NO.7
AIM: Design 4 bit Binary, BCD counter ( Synchronous reset and Asynchronous reset and
any sequence counters.
a)BCD COUNTER
Black Box
clk
q(3 downto 0)
Bcd
rst counter
Truth table
Rst Clk Q
1 X 0000
0 1 0001
0 1 0010
0 1 0011
0 1 0100
0 1 0101
0 1 0110
0 1 0111
0 1 1000
0 1 1001
end Behavioral;
b)GRAY COUNTER
Black Box
clk 4 bit
en Binary to q(3 downto 0)
rst gray
Truth table
Rst Clk En B3 B2 B1 B0 G3 G2 G1 G0
1 X 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 1
0 1 1 0 0 1 0 0 0 1 1
0 1 1 0 0 1 1 0 0 1 0
0 1 1 0 1 0 0 0 1 1 0
0 1 1 0 1 0 1 0 1 1 1
0 1 1 0 1 1 0 0 1 0 1
0 1 1 0 1 1 1 0 1 0 0
0 1 1 1 0 0 0 1 1 0 0
0 1 1 1 0 0 1 1 1 0 1
0 1 1 1 0 1 0 1 1 1 1
0 1 1 1 0 1 1 1 1 1 0
0 1 1 1 1 0 0 1 0 1 0
0 1 1 1 1 0 1 1 0 1 1
0 1 1 1 1 1 0 1 0 0 1
0 1 1 1 1 1 1 1 0 0 0
BINARY COUNTER(UP/DOWN)
Black Box
clk
Binary qout(3 dt 0)
rst counter
Truth table
Clk Rst Qout
X 1 0000
1 0 0001
1 0 0010
1 0 0011
1 0 0100
1 0 0101
1 0 0110
1 0 0111
1 0 1000
1 0 1001
1 0 1010
1 0 1011
1 0 1100
1 0 1101
1 0 1110
1 0 1111
HDL MANUAL 44 EC Dept, BGSIT
HDL LAB IVth Sem EC
process(clkd)
variable temp:std_logic_vector(3 downto
0):="0010";
begin
if rising_edge(clkd(21)) then
if (clr='0') then
if (dir='1') then
temp:=temp+'1';
else
temp:=temp-'1';
end if;
else temp:="0000";
end if;
end if;
q<=temp;
end process;
end Behavioral;
RESULT: Asynchronous and Synchronous counters have been realized and simulated using
HDL codes.
ADDITIONAL EXPERIMENTS
EXPERIMENT NO.8
RING COUNTER
INTERFACING PROGRAMS
1.WRITE A HDL CODE TO CONTROL THE SPEED, DIRECTION
OF DC & STEPPER MOTOR
DC MOTOR
VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dcmotr is
Port ( dir,clk,rst : in std_logic;
pwm : out std_logic_vector(1 downto 0);
rly : out std_logic;
row : in std_logic_vector(0 to 3));
end dcmotr;
begin
process(clk,div_reg)
begin
if(clk'event and clk='1') then
div_reg<=div_reg+'1';
end if;
end process;
ddclk<=div_reg(12);
tick<= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then
case row is
when"1110"=> duty_cycle<=255;
when"1101"=> duty_cycle<=200;
when"1011"=> duty_cycle<=150;
when"0111"=> duty_cycle<=100;
when others => duty_cycle<=100;
end case;
end if;
end process;
end Behavioral;
2. DC MOTOR
NET "CLK" LOC="p18";
NET "RESET" LOC="p74";
NET "dir" LOC="p75";
NET "pwm<0>" LOC="p5";
NET "pwm<1>" LOC="p141";
NET "rly" LOC="p3";
NET "ROW<0>" LOC="p64";
NET "ROW<1>" LOC="p63";
NET "ROW<2>" LOC="p60";
NET "ROW<3>" LOC="p58";
PRODEDURE:1) Make connection between FRC 9 and FPGA board to the dc motor
connector of VTU card 2
2) Make the connection between FRC 7 of FPGA board to the K/B connector of VTU card 2
3) Make the connection between FRC 1 of FPGA board to the DIP switch connector of VTV
card 2.
4) Connect the down loading cable and power supply to FPGA board.
5) Then open xilinx impact s/w, select slave serial mode and select the respective bit file and
click program.
6) Make the reset switch on.
7) Press the Hex keys and analyze speed changes for dc motor.
RESULT: The DC motor runs when reset switch is on and with pressing of different keys
variation of DC motor speed was noticed.
STEPPER MOTOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
HDL MANUAL 50 EC Dept, BGSIT
HDL LAB IVth Sem EC
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity steppermt is
Port ( clk,dir,rst : in std_logic;
dout : out std_logic_vector(3 downto 0));
end steppermt;
end Behavioral;
PROCEDURE:1) Make connection between FRC 9 and FPGA board to the stepper motor
connector of
VTU card 1
2) Make the connection between FRC 1 of FPGA board to the DIP switch connector of
VTU card 1.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
4) Make the reset switch on.
5) Visualize the speed variation of stepper motor by changing counter value in the
program.
RESULT: The stepper motor runs with varying speed by changing the counter value
HDL MANUAL 51 EC Dept, BGSIT
HDL LAB IVth Sem EC
entity externallc is
Port ( cnt : in std_logic;
light : out std_logic);
end externallc;
begin
light<=cnt;
end Behavioral;
PROCEDURE:
1.Make the connections b/w FRC9 of fpga board to external light connector of vtu card 2
2.Make connection b/w FRC1 of fpga board to the dip switch connector of vtucard2
3.Connect the Downloading cable and power supply to fpga board.
1. Then open the xilinx impact software select the slave serial mode and select
respective bit file and click program
2. Make the reset switch on and listen to the tick sound.
RESULT: Once the pin p74 (reset) is switched on the tick sound is heard at the external light
junction.
SAWTOOTH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sawtooth is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end sawtooth;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
begin
if rst='1' then cnt<="00000000";
elsif rising_edge(temp(3)) then
cnt<= cnt+1;
end if;
end process;
dac<=cnt;
end Behavioral;
SQUARE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity squarewg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end squarewg;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process(temp(3))
begin
if rst='1' then cnt<="00000000";
elsif rising_edge (temp(3)) then
if cnt< 255 and en='0' then
cnt<=cnt+1;
en<='0';
dac<="00000000";
elsif cnt=0 then en<='0';
else en<='1';
cnt<=cnt-1;
dac<="11111111";
end if;
end if;
end process;
end Behavioral;
TRIANGLE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end triangwg;
end Behavioral;
RAMP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rampwg is
Port ( clk,rst : in std_logic;
dac : out std_logic_vector(0 to 7));
end rampwg;
begin
process(clk)
begin
if rising_edge(clk) then
temp<= temp+'1';
end if;
end process;
process (temp(3),cnt)
end Behavioral;
SINE WAVE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sinewave is
Port ( clk,rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end sinewave;
architecture Behavioral of sinewave is
signal temp: std_logic_vector(3 downto 0);
signal counter: std_logic_vector(0 to 7);
signal en: std_logic; 4.DAC
begin NET "CLK" LOC="p18";
process(clk) is NET "dac_out<0>" LOC="p27";
begin NET "dac_out<1>" LOC="p26";
if rising_edge (clk) then NET "dac_out<2>" LOC="p22";
temp<= temp+'1'; NET "dac_out<3>" LOC="p23";
end if; NET "dac_out<4>" LOC="p21";
end process; NET "dac_out<5>" LOC="p19";
process(temp(3)) is NET "dac_out<6>" LOC="p20";
begin NET "dac_out<7>" LOC="p4";
if rst='1' then counter<="00000000";
NET "rst" LOC="p74";
elsif rising_edge(temp(3)) then
if counter<255 and en='0' then
counter<= counter+31; en<='0';
elsif counter=0 then en<='0';
else en<='1';
counter<= counter-31;
end if;
end if;
end process;
dac_out<= counter;
end Behavioral;
PROCEDURE:
1) Make connection between FRC 5 and FPGA and DAC connector of VTU card 2.
RESULT:The waveform obtained Ramp, Saw tooth, Triangular, Sine and Square waves are
as per the graph.
PROCEDURE:
1) Make connection between FRC 5 and FPGA board to the seven segment connector of
VTU card 1.
2) Make the connection between FRC 4 to FPGA board to K/B connector of VTU card1.
3) Then open xilinx impact s/w, select slave serial mode and select the respective bit file
and click program.
4) Make the reset switch on.
5) Change the pressing of Hex Keys to watch the display on LCD‟s ranging from 0000 to
FFFF.
RESULT:The values from 0 to F were displayed on all 4 LCD‟s with the respective Hex
Key being pressed.
Constrints file
1. External Light Controller
NET "cntrl" LOC="p74"; => FRC1
NET "light" LOC="p7"; => FRC9
2. DC MOTOR
NET "CLK" LOC="p18";
NET "RESET" LOC="p74";
FRC1
NET "dir" LOC="p75";
HDL MANUAL 59 EC Dept, BGSIT
HDL LAB IVth Sem EC
NET "pwm<0>" LOC="p5";
NET "pwm<1>" LOC="p141"; FRC9
NET "rly" LOC="p3";
NET "ROW<0>" LOC="p64";
NET "ROW<1>" LOC="p63";
FRC7
NET "ROW<2>" LOC="p60";
NET "ROW<3>" LOC="p58";
3. STEPPER MOTOR
NET "CLK" LOC="p18";
NET "dout<0>" LOC="p7";
NET "dout<1>" LOC="p5";
FRC9
NET "dout<2>" LOC="p3";
NET "dout<3>" LOC="p141";
NET "RESET" LOC="p74";
FRC1
NET "dir" LOC="p75";
4.DAC
NET "CLK" LOC="p18";
NET "dac_out<0>" LOC="p27";
NET "dac_out<1>" LOC="p26";
NET "dac_out<2>" LOC="p22";
NET "dac_out<3>" LOC="p23"; FRC5
NET "dac_out<4>" LOC="p21";
NET "dac_out<5>" LOC="p19";
NET "dac_out<6>" LOC="p20";
NET "dac_out<7>" LOC="p4";
NET "rst" LOC="p74"; FRC1
Implement design
entity bcd is
Port ( clr,clk,dir : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0);
tc : out STD_LOGIC);
end bcd;
architecture Behavioral of bcd is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
variable temp:std_logic_vector(3 downto 0);
begin
if(clr='1')then
temp:="0000";tc<='0';
elsif rising_edge(clkd(21)) then
if (dir='1') then
temp:=temp+1;
elsif(dir='0') then
temp:=temp-1;
end if;
if(dir='1' and temp="1010") then
temp:="0000"; tc<='1';
elsif(dir='0' and temp="1111") then
temp:="1001"; tc<='1';
else tc<='0';
end if;
end if;
q<=temp;
end process;
end Behavioral;
entity bin_as is
Port ( dir,clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end bin_as;
process(clkd)
variable temp:std_logic_vector(3 downto 0):="0010";
begin
if rising_edge(clkd(21)) then
if (clr='0') then
if (dir='1') then
temp:=temp+'1';
else
temp:=temp-'1';
end if;
else temp:="0000";
end if;
end if;
q<=temp;
end process;
end Behavioral;
entity binary is
Port ( dir,clk,clr : in STD_LOGIC;
q : out STD_LOGIC_vector(3 downto 0));
end binary;
end Behavioral;
entity gray is
Port ( clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end gray;
process(clr,clkd)
variable temp:std_logic_vector(2 downto 0);
begin
if(clr='0') then
if rising_edge(clkd(21)) then
case temp is
when "000"=> temp:="001";
when "001"=> temp:="011";
when "011"=> temp:="010";
when "010"=> temp:="110";
when "110"=> temp:="111";
when "111"=> temp:="101";
when "101"=> temp:="100";
when "100"=> temp:="000";
when others => null;
end case;
end if;
else temp:="000";
end if;
q<=temp;
end process;
end Behavioral;
entity johnc is
Port ( clk,clr : in STD_LOGIC;
HDL MANUAL 65 EC Dept, BGSIT
HDL LAB IVth Sem EC
process(clkd,clr)
begin
if (clr='1') then q<="0000";
elsif rising_edge(clkd(21)) then
end process;
end Behavioral;
entity ring is
Port ( clk,clr,l : in STD_LOGIC;
process(clkd,clr)
begin
if (clr='1') then q<="0000";
elsif rising_edge(clkd(21)) then
if (l='1') then
q<="1000";
HDL MANUAL 66 EC Dept, BGSIT
HDL LAB IVth Sem EC
else
q<=q(0) & q(3 downto 1);
end if;
end if;
end process;
end Behavioral;
module alu1(a,b,s,en,y);
input [3:0] s,a,b;
input en;
output reg [7:0] y;
always@(a,b,s,en,y)
begin
if(en==1)
begin
case(s)
4'd0:y=a+b;
4'd1:y=a-b;
4'd2:y=a*b;
4'd3:y={4'd0,~a};
4'd4:y={4'd0,(a&b)};
4'd5:y={4'd0,(a|b)};
4'd6:y={4'd0,(a^b)};
4'd7:y={4'd0,~(a&b)};
4'd8:y={4'd0,~(a|b)};
4'd9:y={4'd0,(~a^b)};
default:begin end
endcase
end
else
y=8'd0;
end
endmodule
module bcd(clr,clk,dir, tc, q);
input clr,clk,dir;
output reg tc;
output reg[3:0] q;
always@(posedge clk,posedge clr)
begin
if(clr==1)
q=4'd0;
else
begin
if (dir==1)
q=q+1;
else if(dir==0)
q=q-1;
if(dir==1 & q==4'd10)
begin
q=4'd0;tc=1'b1;
end
else if(dir==0 & q==4'd15)
endmodule
module bin_as(clk,clr,dir, temp);
input clk,clr,dir;
output reg[3:0] temp;
always@(posedge clk,posedge clr)
begin
if(clr==0)
begin
if(dir==0)
temp=temp+1;
else temp=temp-1;
end
else
temp=4'd0;
end
endmodule
endmodule
endmodule
endmodule
module ring(clk,clr,l, q);
input clk,clr,l;
output reg[3:0] q;
always@(posedge clk,posedge clr)
begin
if(clr==1)
q=4'd0;
else
begin
if (l==1)
q=4'd8;
else
q={q[0], q[3:1]};
end
end
endmodule
entity bcd is
Port ( clr,clk,dir : in STD_LOGIC;
q : inout STD_LOGIC_VECTOR (3 downto 0);
tc : out STD_LOGIC);
end bcd;
architecture Behavioral of bcd is
signal clkd:std_logic_vector(21 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clkd<= clkd + '1';
end if;
end process;
process(clkd,clr)
variable temp:std_logic_vector(3 downto 0);
begin
if(clr='1')then
temp:="0000";tc<='0';
elsif rising_edge(clkd(21)) then
if (dir='1') then
temp:=temp+1;
HDL MANUAL 69 EC Dept, BGSIT
HDL LAB IVth Sem EC
elsif(dir='0') then
temp:=temp-1;
end if;
if(dir='1' and temp="1010") then
temp:="0000"; tc<='1';
elsif(dir='0' and temp="1111") then
temp:="1001"; tc<='1';
else tc<='0';
end if;
end if;
q<=temp;
end process;
end Behavioral;
entity bin_as is
Port ( dir,clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end bin_as;
process(clkd)
variable temp:std_logic_vector(3 downto 0):="0010";
begin
if rising_edge(clkd(21)) then
if (clr='0') then
if (dir='1') then
temp:=temp+'1';
else
temp:=temp-'1';
end if;
else temp:="0000";
end if;
end if;
q<=temp;
end process;
end Behavioral;
ntity binary is
Port ( dir,clk,clr : in STD_LOGIC;
q : out STD_LOGIC_vector(3 downto 0));
end binary;
end Behavioral;
entity gray is
Port ( clr,clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (2 downto 0));
end gray;
process(clr,clkd)
variable temp:std_logic_vector(2 downto 0);
begin
if(clr='0') then
if rising_edge(clkd(21)) then
case temp is
when "000"=> temp:="001";
when "001"=> temp:="011";
when "011"=> temp:="010";
when "010"=> temp:="110";
when "110"=> temp:="111";
when "111"=> temp:="101";
when "101"=> temp:="100";
when "100"=> temp:="000";
when others => null;
end case;
end if;
else temp:="000";
end if;
q<=temp;
HDL MANUAL 71 EC Dept, BGSIT
HDL LAB IVth Sem EC
end process;
end Behavioral;
entity johnc is
Port ( clk,clr : in STD_LOGIC;
process(clkd,clr)
begin
if (clr='1') then q<="0000";
elsif rising_edge(clkd(21)) then
end process;
end Behavioral;
entity ring is
Port ( clk,clr,l : in STD_LOGIC;
process(clkd,clr)
begin
if (clr='1') then q<="0000";
elsif rising_edge(clkd(21)) then
if (l='1') then
q<="1000";
else
q<=q(0) & q(3 downto 1);
end if;
end if;
HDL MANUAL 72 EC Dept, BGSIT
HDL LAB IVth Sem EC
end process;
end Behavioral;
FLIP FLOPS
entity dff is
Port ( d,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end dff;
process (clk)
variable temp: std_logic;
begin
if rising_edge(clk) then
temp:=d;
end if;
q<=temp;qb<=not temp;
end process;
end Behavioral;
entity jkff is
Port ( j,k,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end jkff;
process(clk,rst)
variable jk:std_logic_vector(1 downto 0);
variable temp:std_logic:='0';
begin
jk:=j&k;
if (rst ='0')then
if rising_edge(clk) then
HDL MANUAL 73 EC Dept, BGSIT
HDL LAB IVth Sem EC
case jk is
when "01"=> temp:='0';
end Behavioral;
entity srff is
Port ( s,r,rst,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end srff;
process(clk,rst)
variable sr:std_logic_vector(1 downto 0);
variable temp1,temp2:std_logic:='0';
begin
sr:=s&r;
if (rst ='0')then
if rising_edge(clk) then
case sr is
when "01"=> temp1:='0'; temp2:='1';
entity tff is
Port ( t,clk : in STD_LOGIC;
q,qb : out STD_LOGIC);
end tff;
process (clk)
variable temp:std_logic:='0';
begin
if rising_edge(clk) then
if (t='1') then
temp:=not temp;
else
temp:=temp;
end if;
end if;
q<=temp;qb<=not temp;
end process;
end Behavioral;
VERILOG FP
module dff(d,clk,rst,q,qb);
input d,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;
q=1'b0;
end
endmodule
module srff(s,r,clk,rst, q,qb);
input s,r,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]sr;
always@(posedge clk,posedge rst)
begin
sr={s,r};
if(rst==0)
begin
case (sr)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=1'b1;
default: begin end
endcase
end
else
begin
q=1'b0;
end
qb=~q;
end
endmodule
module tff(t,clk,rst, q,qb);
input t,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;
always@(posedge clk,posedge rst)
begin
if (rst==0) begin
if(t==1) begin
temp=~ temp;
end
else
temp=temp;
end
q=temp;qb=~temp;
end
endmodule
module alu1(a,b,s,en,y);
input [3:0] s,a,b;
input en;
output reg [7:0] y;
always@(a,b,s,en,y)
HDL MANUAL 76 EC Dept, BGSIT
HDL LAB IVth Sem EC
begin
if(en==1)
begin
case(s)
4'd0:y=a+b;
4'd1:y=a-b;
4'd2:y=a*b;
4'd3:y={4'd0,~a};
4'd4:y={4'd0,(a&b)};
4'd5:y={4'd0,(a|b)};
4'd6:y={4'd0,(a^b)};
4'd7:y={4'd0,~(a&b)};
4'd8:y={4'd0,~(a|b)};
4'd9:y={4'd0,(~a^b)};
default:begin end
endcase
end
else
y=8'd0;
end
endmodule