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Digital Electronics
Number System Simplification

Digital Electronics
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Number Systems
 Binary, octal, hexadecimal and decimal number
systems are positional weighted, which means that
the values attached to the symbols depend on their
location with respect to the radix point.
 If the base or radix of a number system indicates the
number of unique symbols used in that system.
 The base or radix point separates the integer and
fraction parts.
 The extreme right digit in any number is the LSD and
the extreme left digit is the MSD.
 A decimal number can be converted to a number in
any other system with base b by using sum-of-
weights method or by repeated division by b. In
repeated division by b, the remainders are read from
bottom to top.
 A decimal fraction can be converted to a fraction in
any other number system with base b by using the
sum-of-weights method or by repeated
multiplication by b. In repeated multiplication by b,
the integers to the left of the radix point are read
from top to bottom.
 The binary system has two symbols 0 and 1. A binary
digit is also called a bit.
 Each 4-bit binary group is called a nibble. Binary
word lengths are multiples of four bits.
 Conversion of octal to hexadecimal and vice versa is
simpler via the binary system.
 The main advantage of octal and hexadecimal
systems is their ease of conversion to and from
binary.

rd
An octal number is 1/3 the length of the
corresponding binary number and a hex number is
th
1/4 the length of the corresponding binary number.
 To convert an octal number into binary, replace each
octal digit by its 3-bit binary equivalent.
 To convert a binary number into octal, starting from
the binary point make groups of 3-bits on either side
of the binary point and replace each 3-bit group by
an octal digit.
 To convert a binary number into hex, starting from
the binary point , make groups of 4-bits on either
side of binary point and replace each 4-bit group by a
hex digit.
 To convert a hex number into binary , replace each
hex digit by its 4-bit binary equivalent.
 The hex system is particularly useful for human
communication with computers.
Operations and Representation of Numbers
 The computer method of multiplication requires
repeated addition.
 The computer method of division requires successive
subtraction.
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 Subtraction in any number system with base b can
be done by the b’s complement method or (b – 1)’s
complement method.
 In b’s complement subtraction , the carry is ignored
and in (b – 1)’s complement method the carry is
added to the LSD.
 Negative numbers can be represented in sign
magnitude form , or in 1’s complement form, or in
2’s complement form.
 In signed magnitude form, the MSB represent the
sign bit (0 for positive and 1 for negative) and the
remaining bits represent the magnitude of the
number.
 If b is the base of a number system, (b -1)’s
complement of a number can be obtained by
subtracting each digit of number from (b-1) and b’s
complement of any number can be obtained by
adding 1 to its (b-1)’s complement.
 The complement of the complement gives the
original number.
 The 2’s complement system has a unique zero. But
the 1’s complement system has two zeros, a positive
0 (all 0s) and a negative 0 (all 1s).
 The 1’s complement of a binary number is obtained
by complementing each bit of the number.
 The 2’s complement of a binary number can be
obtained (a) by finding its 1’s complement and
adding 1 to it, or (b) by subtracting the given N-bit
N
binary number from 2 , or (c) by copying down,
starting from the LSB, all bits up to and including the
first 1 and then complementing the remaining bits.
 Large numbers can be represented using double
precision or triple precision.
 Double precision notation requires two storage
locations (registers) to represent each binary
number.
 In the floating point notation, both very large and
very small binary numbers can be represented very
conveniently.
BINARY CODES
 Binary codes may be numeric or alphanumeric
 Alphanumeric codes represent the letters of the
alphabet and decimal numbers sequence of 0s and
1s
 A sequence of binary digits such as that representing
a decimal digit, is called a word.
WEIGHTED CODE & NON WEIGHTEDCODE
 Numeric codes used to represent decimal numbers
are called BCD codes.
 The BCD codes may be weighted or non-weighted.
The weighted codes obey the position weighting
principle.
 In every positively weighted code, one of the weights
must be 1, the second must be either 1 or 2 and the
sum of all the weights must be equal to or greater
than 9.
 Positively weighted codes are those codes in which
all the weights assigned to the binary digits is
negative.
 There are 17 positively weighted codes, out of which
only four are self-complementing.
 There are 13 negatively-weighted self-
complementing codes.
 In a sequential code, each succeeding code word is
one binary number greater than its preceding code
word for N.
 For a code to be self-complementing , the sum of
positional weights must be 9.
 In a cyclic code each successive code word differs in
only one digit position from its preceding code word.
 The 8421 BCD is less efficient than pure binary, but
its main advantage is its ease of conversion to and
from decimal.
 Each one of the 4-bit BCD codes has 6 illegal states.
 The XS-3 BCD code is a non-weighted code, but is
used for mathematical operations because it is a
sequential code.
 In the XS-3 code, each binary code word is the
corresponding 8421 code word plus 0011.
 Where special additive requirements exist , the XS-3
code can be used, and where mechanical systems
must be used, binary coded Gray codes are helpful.
 The Grey code is a unit distance code and its main
advantage is its case of conversion to and from
binary.
 The Grey code is not a BCD code; it is not sequential ,
but cyclic and reflective.
 The Grey code cannot be used for mathematical
operations . It is used in instrumentation and data
aqusition (*) systems where lineary or angular
displacement is measured . It is used in shaft
encoders. I/O devices, A/D converters and other
peripheral devices.
ERROR DETECTION & CORRECTION CODES
 The simplest technique for detecting a single error is
that of adding an extra bit, known parity bit, to each
word being transmitted.
 For even parity, the parity bit should be set to a 0 or
a 1, so that the total number of 1s in the word to be
transmitted including the parity bit is even.
 For odd parity the parity bit should be set to a 0 or a
1, so that the total number of 1s in the word to be
transmitted including the parity bit is odd.
 Odd parity is used more often than even parity,
because even parity does not detect a situation
where all 0s are created by a short circuit or any
other fault condition.
 A code is said to be error detecting, if it possesses
the property such that the occurrence of a single
error transforms a valid code word into an invalid
one.
 Check sums provide a sort of two-dimensional parity.
 Block parity can correct any single error in a data
word and detect any two errors in a data word.
 A code is said to be error correcting, if the correct
code word can always be deduced from an
erroneous word.
 The minimum distance of a code is the smallest
number of bits by which any two code words differ.
 The minimum distance of both BCD and XS-3 codes is
1.
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 The number of digits that must change in a word to
get the other word is the distance between those
two words.
 For single-bit error detection, the minimum distance
between code words must be two or more, and for
single-bit error correction it must be three or more.
 Hamming codes can, not only detect errors but also
correct them.
 In the Hamming code, to each group of m data bits, k
k-1
parity bits located at positions 2 are added to form
an (m+k) – bit code word.
ALPHANUMERIC CODES
 The ASCII code and the EBCDIC code are the most
popular, modern alphanumeric codes.
 The EBCDIC code does not use a straight binary
sequence for representing characters, but uses BCD
as the basis of binary assignment.
LOGIC GATES
 Logic gates are the fundamental building blocks of
digital systems.
 AND, OR and NOT gates are the basic types of gates.
The interconnection of gates to perform a variety of
logical operations is called logic design.
 A truth table lists all possible combinations of inputs
and the corresponding outputs.
 In a positive logic system, the higher of the two
voltage levels represents logic 1 and the lower of the
two voltage levels represents logic 0.
 In a negative logic system, the higher of the two
voltage levels represents logic 0 and the lower of the
two voltage levels represents logic 1.
 An AND gate is an all or nothing gate; it produces a 1,
only in one case when all its inputs are a 1. In all
other cases, its output is a 0.
An OR gate is any or all gate; it produces a 1, even if
one of its inputs is a 1. It produces a 0, only when all
its inputs are a 0.
 A NOT gate complements its input. It produces a 1
when the input is a 0 and produces a 0 when the
input is a 1.
 A NAND gate is effectively an AND gate followed by
an inverter. The output of a NAND gate is a 0, only
when each one of its inputs is a 1. It produces a 1
when any of the inputsis a 0. It therefore also acts as
a negative OR gate.
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 A NAND gate can be used as an inverter by trying all
its input terminals together and feeding the signal to
be inverted to the common terminal or by trying all
but one input terminal to logic 1 and feeding the
signal to be inverted to the remaining terminal.
 A NOR gate is effectively an OR gate followed by an
inverter . It produces a 1 when all of its inputs are a
0. It produces a 0 when any of its inputs is a 1. It
therefore also acts as a negative AND gate.
 A NOR gate can be used as an inverter by trying all
its input terminals together and feeding the signal to
be inverted to the common terminal, or by trying all
but one input terminal to logic 0 and feeding the
signal to be inverted to the remaining terminal.
 NAND and NOR gates are called universal gates. Any
circuit of any complexity can be realized by using
only NAND gates or only NOR gates.
 AND, OR, NAND , and NOR gates can have any
number of inputs.
 An X-OR gate is an anti-coincidence gate. It is an
inequality detector. It produces a 1 , only when its
two inputs are not equal , i.e. when both inputs are
a 0 or a 1.
 Three or more input X-OR or X-NOR gates do not
exist.
 An X-NOR gate can be used as an inverter by
connecting one input terminal to logic 0 and feeding
the signal to be inverted to the other terminal. It is a
controlled inverter.
 When three or more variables are to be X-ORed or X-
NORed, a number of two-input X-OR or X-NO gates
may be used.
 All logic gates have only one output.
 AND , OR, NAND, and NOR gates can be used to
enable or inhibit the passage of an input signal.
 When AND and OR gates are enabled, the output
follows the input exactly.
 When NAND and NOR gates are enabled, the output
is the exact inverse of the input signal.
 AND and NOR gates produce a constant LOW output
when they are in the inhibited condition.
 NAND and OR gates produce a constant HIGH output
when they are in the inhibited condition.
 All logic gates obey their truth table operations
regardless of whether their inputs are constant
levels or pulsed levels.
BOOLEAN ALGEBRA
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 Boolean algebra is a system of mathematical logic,
which uses capital letters of English alphabet to
represent variables . Any single variable, or a
function of the variables can have a value of either a
0 or a 1.
 In Boolean algebra, there is no subtraction or
division. Only logical addition and logical
multiplication are performed. There are no fractions
or negative numbers in Boolean algebra.
 The AND operation is the same as logical
multiplication. The OR operation is the same as
logical multiplication. The OR operation is the same
as logical addition.
 The NOT operation is the same as inversion or
complementation. It is represented by a bar over the
variable.
 The NAND and NOR gates are universal gates, as all
three basic functions, ie. AND , OR and NOT can be
realized by using either only the NAND gates or only
the NOR gates.
 In universal logic, logic circuits are realized using
either only the NAND gates or only the NOR gates.
 The X-OR operation is called the module-2 addition
operation because it assigns each pair of elements its
modulo-2 sum.
 Axioms or postulates of Boolean algebra are a set of
logical expressions that we accept without proof and
upon which we can build a set of useful theorems.
 De Morgan’s theorem states that the complement of
a sum of variables is equal to the product of their
individual complements, and the complement of a
product of variables is equal to the sum of their
individual complements.
 De Morgan’s theorem allows removal of variables
from under a NOT sign. It allows transformation from
SOP form to POS form.
 The dual of an expression is obtained by changing
ANDs to ORs, , Ors to ANDs, 0s to 1s and 1s to 0s.The
variables are not complemented.
 Every logic operation in the Boolean expression
represents a corresponding element of hardware.
 For demorganization of an expression, complement
the entire function, change all the ANDs to ORs all
the ORs to ANDs and complement each of the
individual variables.
 In realization of Boolean expressions, both the
variables and their complement are assumed to be
variable.
 In AOI logic, the circuits area realized using AND , OR
and NOT gates only.
 There are two basic forms of Boolean expressions –
SOP form and POS form.
 The hybrid form of realization is a combination of
both SOP and POS forms.
 A/O gates in which an additional variable or a
combination of variables can be included in the logic
operation, are called expandable gates.
 A circuit having n AND gates feeding an OR gate is
called an n-wide A/O gate.
 Active-LOW gates and circuits are those in which the
action represented or initiated by a variable occurs
when it is equal to a 0.
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 Active-HIGH gates and circuits are those in which the  A standard or canonical or expanded POS form is
action represented or initiated by a variable occurs one in which each one of the sum terms contain all
when it is equal to a 1. the variables of the expression either in
 On logic diagrams, an inversion bubble at the point complemented or non-complemented form.
where the input is connected to a gate , indicates an  Each one of the product terms in the canonical SOP
active LOW input. form is called a minterm.
 An OR gate in the positive logic system becomes an  Each one of the sum terms in the canonical POS form
AND gate in the negative logic system and vice versa. is called a maxterm.
 Laws of Boolean Algebra at a glance  A standard SOP form can always be converted into a
 Laws of complementation standard POS form by treating the missing minterms
̅ =1 ; ̅ = 0; of the SOP form as the maxterms of the POS form.
If A = 0 , then = 1;  A standard POS form can always be converted to a
standard SOP form by treating the missing maxterms
if A = 1, then = 0
of the POS form as the minterms of the SOP form.
 AND laws
 Two squares are said to be adjacent to each other, if
A.0 = 0;
their min(max) terms differ in only one variable.
A . 1 = A;
 Two minterms or maxterms can be combined , only
A.A=A;
if they are adjacent to each other.
A. =0  A real minimal expression is the minimal of the SOP
 OR laws and POS minimals.
A+0 =A;  The binary number designations of the rows and
A + 1 = 1; columns of the K-map are in Gray code.
A + A= A;  The main criteria in the design of digital circuits is
A+ =1 the cost (indicated by the number of gate inputs)
 Commutative laws which must be kept to a minimum.
A+B=B+A;  The squares may also be formed by wrapping around
AB = BA the K-maps.
 Associative laws  2-squares, 4-squares, or 8-squares , etc form either
(A + B) + C = A + (B + C) ; geometric squares or rectangles.
(AB) . C =A (BC)  A 2-square eliminates one variable , a 4-square
 Distributive laws eliminates 2 variables, an 8-square eliminates 3
A(B + C) = AB +AC; variables, a 16-square eliminates 4 variables, and so
A + BC = (A+ B) (A + C) on.
 Idempotence laws  Combinations for which the value of an expression is
A . A = A; not specified are called “don’t care combinations.
A+A=A  Incompletely specified expressions are those which
 Negation laws are not specified for certain combinations.
 An SOP expression with don’t cares can be converted
A. =0;
to a POS form by keeping the don’t cares as they are
A+ =1 and writing the missing minterms of the SOP form as
 Absorption laws the maxterms of the POS form, and vice versa.
A + AB = A ;  In K-maps , don’t care terms are used only if they
A(A + B) =A help in reducing the expression. Otherwise , they
 Consensus theorem need not be considered.
AB + C + BC = AB + C  If each one of the input signals has to pass through
 Transportation theorem two gates to reach the output, it is called the two
AB + C = (A + C) ( + B) level logic . The SOP and POS forms of realization
 De Morgan’s theorem give two-level logic
= . ; = +  Two-level logic provides uniform propagation delay
BOOLEAN SIMPLIFICATION between the input and the output, but may not yield
 The K-map is a chart or a graph composed of an the real minimal.
arrangement of adjacent cells, each representing a  In hybrid logic, different input signals pass through
particular combination of variables in a sum or different number of gates to reach the output.
product term.  Hybrid logic does not produce uniform time delay
n and may suffer from the problem of ‘logic race’ , but
 An n-variable K-map will have 2 cells or squares.
results in a circuit with the least number of gate
 The use of K-maps is usually limited to six variables.
inputs.
 A standard or canonical or expanded SOP form is one
 Variable mapping (Variable entry mapping)
in which each one of the product terms contains all
technique can be used to minimize the given
the variables of the expression either in
Boolean expressions which involve infrequently used
complemented or non-complemented form.
variables.

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 Variable mapping technique allows us to reduce a b) LSB
large mapping problem to one that uses just a small c) Byte
map. d) Nibble
 The Quine-McClusky method , also known as the
2. The parameter through which 16 distinct values
tabular method, is a more systematic method than
the K-map for minimizing functions of a large can be represented is known as ________
number of variables. a) Bit
 In the tabular method the condition that the binary b) Byte
designations of two combinable terms must differ by c) Word
a power of 2, is necessary but not sufficient. d) Nibble
 Two terms whose codes differ by a power of 2 but 3. If the decimal number is a fraction then its binary
which have the same index cannot be combined
equivalent is obtained by ________ the number
because these terms differ in more than one
variable. continuously by 2.
 The ‘index’ of a term indicates the total number of 1s a) Dividing
present in that term. b) Multiplying
 A term with a smaller index but having a higher c) Adding
decimal value cannot be combined with a term d) Subtracting
whose index is higher even though they may differ 4. The representation of octal number (532.2)8 in
by a power of 2, because they would differ in more
decimal is ________
than one variable.
 The terms which cannot be combined further in the a) (346.25)10
tabular method are called prime implicants. These b) (532.864)10
terms may occur in the final expression. c) (340.67)10
 Essential prime implicants are the implicants which d) (531.668)10
will definitely occur in the final expression. 5. The decimal equivalent of the binary number
 Each essential prime implicant will cover at least one
(1011.011)2 is ________
minterm which is not covered by any other prime
implicant. a) (11.375)10
 The prime implicant chart is a pictorial b) (10.123)10
representation of the relations between the prime c) (11.175)10
implicants and the minterms of the expression. d) (9.23)10
 Don’t care minterms are used in the table, only to 6. An important drawback of binary system is
obtain the set of prime implicants . They are not ________
used in the prime implicant chart to obtain essential
a) It requires very large string of 1’s and 0’s to
prime implicants.
 Any row in a prime implicant chart is said to represent a decimal number
dominate any other row, if the first row has a x in b) It requires sparingly small string of 1’s and 0’s to
every column in which the second row has X. represent a decimal number
 Any column in a prime implicant chart is said to c) It requires large string of 1’s and small string of 0’s
dominate any other column, if the first column has a to represent a decimal number
x in every row in which the second column has an x. d) It requires small string of 1’s and large string of 0’s
 All dominating columns and dominated rows can be
to represent a decimal number
removed while drawing the reduced prime implicant
chart. 7. The decimal equivalent of the octal number (645)8
 If the prime implicant chart has no essential prime is ______
implicants and dominated rows and dominating a) (450)10
columns, the minimal expressions can be obtained b) (451)10
by the branching method. c) (421)10
 A minterm fills with 1s the minimum possible area of
d) (501)10
the K-map , short of filling no area at all. Hence , the
name minterm. 8. The largest two digit hexadecimal number is
 A maxterm fills with 1s the maximum possible area ________
of the K-map, short of filling the entire area. Hence, a) (FE)16
the name maxterm. b) (FD)16
c) (FF)16
OBJECTIVE QUESTIONS FOR PRACTICE d) (EF)16
A: Number System 1 9. Representation of hexadecimal number (6DE)H in
1. Any signed negative binary number is recognised decimal:
2 1 0
by its ________ a) 6 * 16 + 13 * 16 + 14 * 16
2 1 0
a) MSB b) 6 * 16 + 12 * 16 + 13 * 16
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 2 1 0
c) 6 * 16 + 11 * 16 + 14 * 16 In hexadecimal number D & E represents 13 & 14
2 1 0
d) 6 * 16 + 14 * 16 + 15 * 16 respectively.
10. The quantity of double word is ________ 10:B
a) 16 bits Explanation: One word means 16 bits, Thus, the
b) 32 bits quantity of double word is 32 bits.
c) 4 bits
d) 8 bits OBJECTIVE QUESTIONS FOR PRACTICE
ANSWERS WITH EXPLANATION B: K-MAP
1: A 1. Which statement below best describes a Karnaugh
Explanation: Any negative number is recognized by map?
its MSB (Most Significant Bit).If it’s 1, then ít’s a) It is simply a rearranged truth table
negative, else if it’s 0, then positive b) The Karnaugh map eliminates the need for using
2.C NAND and NOR gates
Explanation: It can be represented up to 16 different c) Variable complements can be eliminated by using
values with the help of a Word. Nibble is a Karnaugh maps
combination of four bits and Byte is a combination of d) A Karnaugh map can be used to replace Boolean
8 bits. It is “word” which is said to be a collection of rules
16-bits on most of the systems 2. Which of the examples below expresses the
3:B commutative law of multiplication?
Explanation: On multiplying the decimal number a) A + B = B + A
continuously by 2, the binary equivalent is obtained b) A • B = B + A
by the collection of the integer part. However, if it’s c) A • (B • C) = (A • B) • C
an integer, then it’s binary equivalent is determined d) A • B = B • A
by dividing the number by 2 and collecting the 3. The Boolean expression Y = (AB)’ is logically
remainders. equivalent to what single gate?
4: A a) NAND
Explanation: Octal to Decimal conversion is obtained b) NOR
by multiplying 8 to the power of base index along c) AND
with the value at that index position. d) OR
2 1 0 1
(532.2)8 = 5 * 8 + 3 * 8 + 2 * 8 + 2 * 8- = (346.25)10 4. The observation that a bubbled input OR gate is
5:A interchangeable with a bubbled output AND gate is
3 2 1 0 -1 -2 -3
1 * 2 + 0 * 2 + 1 * 2 +1*2 + 0 * 2 +1 * 2 + 1 * 2 referred to as:
= (11.375)10 a) A Karnaugh map
6:A b) DeMorgan’s second theorem
a c) The commutative law of addition
Explanation: The most vital drawback of binary d) The associative law of multiplication
system is that it requires very large string of 1’s and 5. The systematic reduction of logic circuits is
0’s to represent a decimal number. Hence, accomplished by:
Hexadecimal systems are used by processors for a) Symbolic reduction
calculation purposes as it compresses the long binary b) TTL logic
strings into small parts. c) Using Boolean algebra
7:C d) Using a truth table
The decimal equivalent of the octal number (645) 8 is 6. Each “1” entry in a K-map square represents:
2 1 0
6 * 8 + 4 * 8 + 5 * 8 = (421)10. a) A HIGH for each input truth table condition that
8:C produces a HIGH output
Explanation: (FE)16 is 254 in decimal system, while b) A HIGH output on the truth table for all LOW input
(FD)16 is 253. (EF)16 is 239 in decimal system. And, combinations
(FF)16 is 255. Thus, The largest two-digit hexadecimal c) A LOW output for all possible HIGH input
number is (FF)16. conditions
9:A d) A DON’T CARE condition for all possible input
Explanation: Hexadecimal to Decimal conversion is truth table combinations
obtained by multiplying 16 to the power of base 7. Each “0” entry in a K-map square represents:
index along with the value at that index position.

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 a) A HIGH for each input truth table condition that 5.C
produces a HIGH output Explanation: The systematic reduction of logic
b) A HIGH output on the truth table for all LOW input circuits is accomplished by using boolean algebra.
combinations 6.A
c) A LOW output for all possible HIGH input Explanation: Each “1” entry in a K-map square
conditions represents a HIGH for each input truth table
d) A DON’T CARE condition for all possible input condition that produces a HIGH output. Thus, it
truth table combinations represents a minterm.
8. Which of the following statements accurately 7.A
represents the two BEST methods of logic circuit Explanation: Each “0” entry in a K-map square
simplification? represents a LOW output for all possible HIGH input
a) Actual circuit trial and error evaluation and conditions. Thus, it represents a Maxterm.
waveform analysis 8.C
b) Karnaugh mapping and circuit waveform analysis Explanation: The two BEST methods of logic circuit
c) Boolean algebra and Karnaugh mapping simplification are Boolean algebra and Karnaugh
d) Boolean algebra and actual circuit trial and error mapping. Boolean Algebra uses the Laws of Boolean
evaluation Algebra for minimization of Boolean expressions
9. Looping on a K-map always results in the while Karnaugh Map is a pictorial representation and
elimination of __________ reduction of the Boolean expression.
a) Variables within the loop that appear only in their 9.C
complemented form Explanation: Looping on a K-map always results in
b) Variables that remain unchanged within the loop the elimination of variables within the loop that
c) Variables within the loop that appear in both appear in both complemented and uncomplemented
complemented and uncomplemented form form.
d) Variables within the loop that appear only in their 10.D
uncomplemented form Explanation: Sum of product means that it is the sum
10. Which of the following expressions is in the sum- of all product terms. Thus, the number is multiplied
of-products form? first and then it is added: A * B + C * D.
a) (A + B)(C + D) OBJECTIVE QUESTIONS FOR PRACTICE
b) (A * B)(C * D) C: SOP AND POS
c) A* B *(CD) 1. In boolean algebra, the OR operation is performed
d) A * B + C * D by which properties?
a) Associative properties
Answers with Explanations: b) Commutative properties
1.A c) Distributive properties
a d) All of the Mentioned
Explanation: K-map is simply a rearranged truth 2. The expression for Absorption law is given by
table. It is a pictorial representation of truth table _________
having a specific number of cells or squares, where a) A + AB = A
each cell represents a Maxterm or a Minterm. b) A + AB = B
2.D c) AB + AA’ = A
Explanation: The commutative law of multiplication d) A + B = B + A
is (A * B) = (B * A). 3. According to boolean law: A + 1 = ?
The commutative law of addition is (A + B) = (B + A). a) 1
3.A b) A
Explanation: If A and B are the input for AND gate c) 0
the output is obtained as AB and after inversion we d) A’
get (AB)’, which is the expression of NAND gate. 4. The involution of A is equal to _________
NAND gate produces high output when any of the a) A
input is 0 and produces low output when all inputs b) A’
are 1. c) 1
4.B d) 0
Explanation: DeMorgan’s Law: ~(P+Q) <=> (~P).(~Q) 5. A(A + B) = ?
Also, ~(P.Q) <=> (~P)+(~Q)
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 a) AB Property) = A(1 + B) = A*1 (1 + B = 1 by 1’s Property)
b) 1 = A.
c) (1 + AB) 6.A
d) A Explanation: The DeMorgan’s law states that (AB)’ =
6. DeMorgan’s theorem states that _________ A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.
a) (AB)’ = A’ + B’ 7.B
b) (A + B)’ = A’ * B Explanation: The DeMorgan’s law states that (AB)’ =
c) A’ + B’ = A’B’ A’ + B’ & (A + B)’ = A’ * B’, as per the Dual Property.
d) (AB)’ = A’ + B 8.D Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ (By
7. (A + B)(A’ * B’) = ? DeMorgan’s Theorem) = (A” + B’)(C’ + D”) (By
a) 1 DeMorgan’s Theorem) = (A + B’)(C’ + D).
b) 0 9. A
c) AB Explanation: Y = AB’ + (A’ + B)C = AB’ + (AB’)’C = (AB’
d) AB’ + C)( AB’ + AB’) = (AB’ + C).1 = (AB’ + C).
8. Complement of the expression A’B + CD’ is 10.B
_________ Explanation: (A + B)(A + C) = AA + AC + AB + BC = A +
a) (A’ + B)(C’ + D) AC + AB + BC (By Commutative Property) = A(1 + C +
b) (A + B’)(C’ + D) B) + BC = A + BC (1 + B + C =1 By 1’s Property).
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
9. Simplify Y = AB’ + (A’ + B)C.
a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
10. The boolean function A + BC is a reduced form of
____________
a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
Answers with Explanation:
1.D
Explanation: The expression for Associative property
is given by A+(B+C) = (A+B)+C & A*(B*C) = (A*B)*C.
The expression for Commutative property is given by
A+B = B+A & A*B = B*A.
The expression for Distributive property is given by
A+BC=(A+B)(A+C) & A(B+C) = AB+AC
2.A
Explanation: The expression for Absorption Law is
given by: A+AB = A.
Proof: A + AB = A(1+B) = A (Since 1 + B = 1 as per 1’s
Property).
3.A
Explanation: A + 1 = 1, as per 1’s Property.
4.A
Explanation: The involution of A means double
inversion of A (i.e. A”) and is equal to A.
Proof: ((A)’)’ = A
5.D
Explanation: A(A + B) = AA + AB (By Distributive
Property) = A + AB (A.A = A By Commutative

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