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245
multilevel inverter topologies is the reduction of voltage
stress on the semi conductor devices used in the inverter
and bridge and the generation of high quality output voltages.
These benefits have attracted a tremendous interest in the
(in balanced three phase AC loads) industries. For high voltage high power applications where
From above, high voltage rating semi conductors are not available the
multilevel VSI topologies are the good alternatives. The most
(1) popular multilevel inverter topology starts with 3-level
inverter. The number of voltage vectors in 3-level three
In equation (1), it is assumed that the load is balanced so phase inverter is 27 (mp where “m” is the level and “p” is the
that the sum of all three phase-to-neutral voltages is Zero no. of phases) and for 5- level inverter it is 125 and so on.
(∑Va,b,c-N=0).If the source voltage is assumed to be Presently there are three kinds of multilevel inverters: (1)
balanced and ideal, then the sum of all three phase-to-ground Neutral Point Clamped inverter (NPC) (2) Flying Capacitor
voltages is zero (∑Va,b,c-G=0).In that case, VN-G will be inverter and (3) Cascaded inverter. The proposed work
zero from equation (1).However, in the case of an investigates the experimental evaluation of 2-level,
inverter-driven AC machine, there exists a common-mode Multi-level (3-level , 5-level) inverters for the speed control
voltage because the voltage sources inverter does not of induction motor, identification, measurement of CM
constitute an ideal balanced source. Fig.1 shows a typical voltage, shaft voltage and the bearing current using Space
2-level voltage source inverter-fed AC machine. Vector Modulation (SVM) method. The inverter is built
In an inverter-driven system, the common mode voltage using the MOSFET devices, DC link capacitors and the
(VCOM or VN-G) can also be defined as the voltage across the clamping diodes. For the proposed work Neutral point
stator neutral (N) and the DC bus mid-point (M) because from clamped (NPC) multi level inverter structure is used. In
a high-frequency viewpoint, the DC bus mid-point (M) is multilevel voltage source inverters, SVM methodologies
same as the electrical ground (G) of the system. Using this have the advantages of increased inverter output voltage
definition, the common-mode voltage can be redefined as when compared to sine triangle pulse width modulation
shown in equation (2). This definition would then be valid for (SPWM) method. One of the most important advantages of
3-level inverters as well. the SVM is that the gating signal of the power devices can be
easily programmed using Microcontrollers/digital signal
(2) processor (DSP). Also, SVM offers improved dc bus
utilization, reduced commutation losses and lower total
harmonic distortion.
C. Space Vector Modulation
In 2- level and multilevel inverters using SVM
methodologies, identifies each switching state as a point in
complex (∝,β) plane. Then a reference vector rotating in
(∝,β) plane at the fundamental frequency is sampled within
each switching period, and the nearest three inverter
switching states are selected with duty cycles calculated to
achieve the same volt-second average as the sampled
reference vector. This directly controls the inverter
Fig. 1. Two level inverter driven AC motor. line-to-line voltages, and implicitly develops the phase leg
voltages.
In equation (2), it should be noted that the source voltage
nomenclature has been changed from Va,b,c-G to Vu,v,w-M to
reflect the fact that the source now is the voltage source III. EXPERIMENTAL RESULTS
inverter. The common mode current (icom) is defined as the
instantaneous sum-total of all the currents flowing through
the output conductors. Stray capacitances of the motor cable
and inside the motor are the paths of this current, and a source
of EMI noise problems.
Generally PWM inverter gives the two levels of output
voltages which are not closer to sinusoidal. In order to
minimize the CM voltage and to achieve the high quality
output voltage which is closer to sinusoidal and also to get
lower %THD, multilevel inverter topologies are preferred.
B. Multi-level Inverter
Several multilevel inverter topologies and modulation
technologies have been developed and applied to high power
and high voltage systems. The main motivation for Fig. 2. Micro-controller output for 2- level inverter
246
Fig. 3. Gating signal generation (switching pattern) for 3-level inverter
60
40
Ch 1: 200 : 1 Phase voltage to IM.
Ch 2: 200 : 1 Line voltage to IM.
20
Ch 3: 20 : 1 Vector sum of current in terms of voltage.
Ch 4: 1 : 1 One phase current in terms of voltage.
0
0 5 00 1 00 0 1 50 0 2 00 0 2 50 0
F re q u e n cy (H z )
Fig. 11. FFT of Common mode voltage of IM. (20msec/Div,2-level
inverter)
50
40
Amplitude in volts
30
20
10
247
50
40
40
Amplitude in volts
30
Amplitude in volts
30
20
20
10
10
0 0
0 400 800 1200 1600 2000 2400
0 50 100 150 200 250 300 350 400
Frequency (Hz) Frequency (Hz)
Fig. 13. Expanded view of FFT of CM voltage (3-level inverter) Fig. 19. FFT of im shaft voltage in Volts(5-level NPC inverter)
200 50
30
100
20
50 10
0
0
-1000 0 1000 2000 3000 4000 5000
0 500 1000 1500 2000 2500
Frequency (H z)
Frequency (Hz)
Fig. 20. FFT of IM shaft voltage (3-level inverter)
Fig. 14. FFT of CM voltage of IM in dB µV(3-level inverter)
200
100 40
50
20
0
0 50 100 150 200 250 300 350 400 450 500
F re q u e n c y (H z )
0
0 1000 2000 3000 4000 5000
Fig. 15. FFT of CM voltage of IM in dBµV (Expanded view, 3-level Frequency (Hz)
inverter)
Fig 21. FFT of I.M. shaft voltage (2-level inverter)
30 200
Amplitude in Volts
150
Amplitude in dB μV
20
100
10
50
0 0
0 500 1000 1500 2000 2500 0 400 800 1200 1600 2000 2400
Frequency (Hz) Frequency (Hz)
Fig. 16. FFT of Common mode voltage of IM in volts (5- level NPC inverter) Fig. 22. FFT of Shaft voltage in dB µV (5-level NPC inverter)
10
200
8
150
Amplitude in dB μ volts
Amplitude in Volts
100
4
50
2
0 0
-100 0 100 200 300 400 500 600 700 800 900 1000
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
F re q u e n c y (H z )
Fig. 17. FFT of cm voltage of IM (X-Y expanded, 5-level NPC inverter) Fig. 23. FFT of Shaft voltage in dB µV (3-level inverter)
200 250
200
150
Amplitude in dBμV
Amplitude in dB μ V
150
100 100
50
50
0
-100 0 100 200 300 400 500 600 700 800 900 1000
0
Frequency (Hz)
0 500 1000 1500 2000 2500
Frequency (Hz) Fig. 24. FFT of shaft voltage in dBμV (2-level inverter)
Fig. 18. FFT of common mode voltage of IM in DBµV(5-level NPC inverter)
248
250
Fundamental
200 frequency(40) 45 170
Amplitude in dB μA
3-Level 120 9 13
150
Inverter 200 8 10
100 280 6 5
2.
440 5 6
50
0 Fundamental
0 500 1000 1500 2000 2500 frequency(40) 38 155
Frequency (Hz)
5- Level 120 5 10
Inverter 200 7 9
Fig. 25. FFT of Bearing current in µA(5-level NPC Inverter) 3 280 4 7
440 1.5 2
150
Fundamental
145
frequency(40)
100 2.2
3-Level 120
2.1
Inverter 200
50
1.9
2. 280
1.9
0 440
0 1000 2000 3000 4000 5000
Frequency (Hz)
Fundamental
Fig. 27. FFT of bearing current in dBμA (2-level Inverter)
frequency(40) 135
120 1.2
TABLE I: THE FFT OF COMMON MODE VOLTAGE, SHAFT VOLTAGE AND 5- Level
200 0.9
THE BEARING CURRENT IN INVERTER FED INDUCTION MOTOR Inverter
3 280 0.8
440 0.6
FFT of CM Voltage
Sl
Inverter
No. Value Value in
Level Frequency in Hz
in volts dBµV
Fundamental 180
49
frequency(40) 14 IV. CONCLUSION
10
2- Level 120 12
8 This work proposes a simple and efficient SVM method
Inverter 200 11
1. 5
280
3
5 that uses only outermost active voltage vectors. Due to these
440
reasons the proposed SVM is computationally very simple
Fundamental
frequency(40)
42 170 and efficient. The research work presented in this paper is
3-Level 2 6 about the identification and the experimental measurement of
120
Inverter 4 5
200 the Common Mode Voltage in 2-level, 3-level and the 5-level
3 4
2. 280
440
2 3 (NPC) inverter fed induction motor drive and the technique
Fundamental of SVM scheme. This work also discusses identification as
frequency(40) 36 160 well as the experimental measurement of the rotor shaft
5- Level 120 1 1 voltage and the bearing current that is present in the modified
Inverter 200 2.5 1.5
3 280 3 2 squirrel cage three phase inverter fed induction motor drive.
440 1 0.8 Figures 2, 3 and 4 shows the gating signal generation to the
inverter circuits using micro-controller. Figures 5 to 10
FFT of Shaft Voltage with respect to gnd.
shows the DSO recorded wave forms of the 2-level and
Sl Inverter multilevel Inverters. Figures 11to 27 shows the FFT results
No. Level
Frequency in Hz
Value Value in of the DSO Recorded waveforms using signal analysis
in volts dBµV software. The table-1 shows the comparison of the FFT
Fundamental
frequency(40)
64 220 results of the various parameters. It is observed
2- Level 12 2
120
5 4
experimentally by measuring the CM voltage and analyzing
Inverter
200 the same with FFT analysis using the Signal Analysis
1. 6 5
280
440
14 2.5 software that the 5-level inverters generates less CM voltage,
249
Shaft voltage and the Bearing current when compared to 3- Mr.B.Muralidhara received the B E, M. E degree
from Bangalore University; Bangalore .He is working
level and 2- level inverter(Table-1). as an Assistant Professor, B.M.S.IT, Bangalore. India.
He has guided many Undergraduate students in Power
Electronics field. At present pursing for Ph.D Degree
ACKNOWLEDGMENT with JNTU/ Hyderabad, India. He has published the
papers in international journals. He is the life member
The authors are thankful to KRJS management, the for institution of Engineers and Fellow IETE.
Director and Principal of Vemana Institute of Technology, (email:muralimunny07@yahoo.co.in )
Koramangala, Bangalore-560034, India for providing the
facilities to carry out the experiments. The author 1 is thankful
to the Principal BMSIT and Dr. T.C. Balachandra, Professor.
Dr.A.Ramachandran obtained his Bachelor’s,
BMSIT for permitting to carry out the above work. And also Master’s and doctoral Degree in Electrical Engineering
to Prof. V. Keshavamurthy, Professor and former Chairman from Bangalore University, Bangalore, India. He was
UVCE, Bangalore University, Bangalore India for his with National Aerospace Laboratories Bangalore, India,
as scientist in various capacities, and was working in
constant support.
the areas of Power Electronics & drives for the past 35
years. He was heading the Instrumentation & controls
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