designfeature By S Meiyappan, K Jaramillo, and P Chambers, VLSI Technology Inc

YOUR ABILITY TO REUSE BLOCKS EXPRESSED IN AN HDL IS

CRITICAL TO DESIGNING SYSTEMS ON CHIPS. HERE ARE
SOME TIPS YOU CAN USE TO GENERATE VHDL-BASED
BLOCKS THAT YOU—AND OTHERS—CAN REUSE
IN SUBSEQUENT CHIP DESIGNS.

10 tips for generating

reusable VHDL
“D esign reuse” is the process of mi-
grating high-quality intellectual proper-
ty (IP) from one ASIC design to anoth-
er. With the tremendous advances in semiconductor
technology, it is increasingly difficult to bridge the
productivity gap between what technology offers and
what silicon productivity allows. Designing full-cus-
tom ASICs to occupy as much silicon area as possi-
ble is becoming increasingly challenging. To achieve
the highest level of silicon efficiency, designing semi-
custom ASICs with highly reusable design entities
has become today’s challenge.
The use of predesigned and preverified design
blocks to achieve a high level of design reuse is the
most promising technique for bridging the gap be-
tween available gate count and designer productiv-
ity. Designing a complex chip requires an HDL-
based design. Effective HDL generation with design
reuse in mind will help you create
IP cores that are usable in
multiple chip designs. Figure 1 EN
confidence; and independent of technology, design
tools, and applications.
Because of mounting time-to-market pressures,
designers often bypass some or all of these guide-
lines, rendering a design virtually nonreusable. How-
ever, following these guidelines speeds designing,
verifying, and debugging a project by reducing iter-
ations throughout the coding and verification loops.
The efficient use and reuse of designs play a vital role
in the creation of large ASICs with aggressive design
schedules.
Although chip designers have used HDLs for
some time, most designs today do not use the built-
in “design-reuse” features of the languages. In other
words, designers do not thoroughly understand the
purpose of the HDLs and misuse or underuse their
features. On an average, only 20% of the designs in
the industry are reusable. With an increasing need

THE DESIGN-REUSE CHALLENGE D

Designing for reuse poses new D

CLK COUNT (1:8)
and innovative challenges to a de-
signer. Before being reusable, a
design must be usable, which RESET_N
means design using good design
practices. A reusable design must
be designed with the mindset of
solving a general problem; well-
coded, commented, and docu-
mented; verified to a high level of In this up-counter, count is disabled, and bit width equals 2.

www.ednmag.com August 19, 1999 | edn 49

designfeature Generating reusable VHDL

for design reuse, the emphasis on coding

techniques for design reuse is on
the rise. This article covers devel- Figure 2
D
oping reusable designs using the native-
EN EN
language features of VHDL and design-
reuse techniques pertaining to syn- D
CLK
thesizable VHDL. Unless stated other- EN
wise, the VHDL discussed complies with
COUNT (1:8)
the VHDL-87 standard. RESET_N

VHDL FEATURES PROMOTING REUSABILITY

Chip designers have used VHDL for
more than a decade. One of the primary In this enabled up-counter, bit width equals 2.
intents of developing designs in VHDL
is reusability, although, designers, until EN
recently, have not effectively employed
this technique. You can exploit the
Figure 3
feature-rich VHDL for reuse tech-
niques. VHDL features include generics,
packages of constants, generate state- D
COUNT (1:8)
ments, unconstrained arrays, VHDL at- D

tributes, block statements for inline-de-

sign partitioning, record data types for
data bundling, configuration specifica-
CLK
tions, the ability to tie ports off to known
constants, the ability to leave unused RESET_N

output ports open and unconnected, ar-

ray aggregates, functions, and proce- Simple changes to the HDL code produce a down-counter with no enable.
dures.
A ZERO
TIP 1: GENERICS F ZERO
B B
C C
You use generics to write para- Figure 4
meterized models of varying structure
and behavior (Reference 1). Listing 1
(a) (b)
provides a simple example of a synchro-
nous counter with modifiable structure A double AND-gate segment of combinatorial logic (a) and the same AND-gate logic with one input
and behavior. You accomplish this mod- of the first AND gate tied low (b) show the value of tying off ports to reduce synthesized logic. This
ification through the use of VHDL technique effectively eliminates both logic gates.
generics. This example illustrates the use
of generics for modifying structure and sign may require two counters: one that ● Lines 3 to 14 instantiate the counter
behavior using the language’s features for counts to 1024 and another that counts as a 10-bit up-counter with the count-en-
simulation and synthesis. You can enable to eight. Designing two separate coun- able-logic turned on.
and disable selective features by turning ters—one that is 10 bits wide and one ● The TenBit counter instantiation
generics on and off. For example, if you that is 3 bits wide—has drawbacks of un- uses named association for its generics
set the COUNT_ENABLE generic to necessary investment in design, verifica- and ports.
FALSE in line 8, then none of the logic tion, and synthesis time. ● Unmapped generic values in the in-
described in lines 32 to 38 is elaborated If you use the generic approach to de- stantiation assume default values.
or synthesized, but the parent design can sign a counter with reuse in mind, you ● Lines 18 to 30 instantiate the same
still have a count enable. Using different save a great deal of design, synthesis, and counter as a 3-bit down counter with
values for OutDelay and DOWN_ verification time. The use of generics for count-enable-logic turned off.
COUNT changes the counter’s behavior parameterizing structure and behavior is ● The ThreeBit counter instantiation
(although synthesis ignores the OutDe- essential for design reuse-applications. uses positional association for its gener-
lay), and changing BIT_WIDTH or The following examples illustrate the in- ics and ports. In general, it is not advis-
COUNT_ENABLE modifies the struc- stantiation of the counter in Listing 1 in able to use positional association because
ture of the design. Creating designs with an application that requires a 10-bit up- changing a parameter or port in the
generics enables design reuse in various counter and a 3-bit down-counter reusable design requires the same modi-
circumstances where you need different The example in Listing 2 illustrates the fication in all instances of that design.
structure or behavior. For example, a de- following points: ● The use of generics can help greatly

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designfeature Generating reusable VHDL

in resources and time when you

need multiple instances of the Figure 5 BMSB BMSB-1 BMSB-N-1
same design.
BINARY BMSB BMSB-1 BMSB-2 BLSB
The use of generics to parameterize
designs helps not only to create reusable
design blocks, but also to remove unnec- XOR XOR XOR

essary logic or to modify useful logic dur-

ing synthesis. Some synthesis tools help GRAY G-MSB G-MSB-1 G-MSB-2 G-LSB
create macros and templates when you (a)
parameterize designs through generics.
You can use the feature thus created as a 1 0

library element in subsequent designs for XOR XOR

simulations or synthesis. Parameterizing BINARY 1 0 0

bus and register widths through generics

is a simple example of the use of gener-
ics. (b) GRAY 1 1 0

Consider the example of the counter

in Listing 1 with the following generic
values: This binary-code to gray-code algorithm (a) does conversions, such as binary 100 to its gray-code
BIT_WIDTH => 2 equivalent of 110 (b).
COUNT_ENABLE => true
DOWN_COUNT => true various features on and off. This tech- adder; register address; power-on-reset
OutDelay => 3 ns nique lets you use only the features that value for a register; supported and re-
When synthesis elaborates this design, apply to your current project.You can use served bits in a register; clock-divide ra-
the synthesis tool ignores the generic for generics to specify such features as FIFO tio for a clock-divider circuit; and num-
OutDelay because the tool cannot han- depths; bus interface, such as PCI or ber of buffers in a clock tree.
dle time-delay elements in mapping log- ARM System Bus; architecture, such as If you make the design somewhat
ic. The synthesis tool creates a 2-bit up/down counter, flip-flop-based regis- generic, others can more easily reuse it.
down-counter with the count_enable ter versus latched-based register, and rip- One drawback of the generic approach
logic, as the following examples illustrate. ple-carry adder versus carry-look-ahead occurs when you use generics in a hier-
Consider another case of archy. To apply the generics to
the same counter with the LISTING 1— SYNCHRONOUS COUNTER DESIGNED WITH GENERICS the lowest level of the hierar-
following generics: chy, the generics must pass
BIT_WIDTH => 8 down through the hierarchy.
COUNT_ENABLE => This passing down may in-
false volve generics having to go
DOWN_COUNT => through blocks that do not
false use the value of the generics.
This code creates an 8-bit Another drawback of using
up-counter without the generics is that, as the list of
count-enable logic. If gate generics grows, it becomes
count is an important pa- more cumbersome to carry
rameter, you can efficiently them around at each point in
optimize unused logic using the hierarchy. A third draw-
this method. You can mod- back is that some synthesis
ify the structure (changing tools have limited support for
the BIT_ WIDTH) or be- generics. For example, a syn-
havior (up-or down-count- thesis tool may require all
er, count_ enable disabled generics to be of type integer.
or enabled) during design, An efficient way to avoid these
synthesis, and simulation problems is to use a package
using this elegant approach of constants.
to parameterization.
Generics are excellent for TIP 2: CONSTANTS
specifying widths of coun- A VHDL package is a sim-
ters, buses, shift registers, ple way of grouping a collec-
and other designs, but as tion of related declarations
Listing 2 shows, you can that serve a common pur-
also use generics to turn pose. You can make the pack-
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designfeature Generating reusable VHDL

age visible to the appropriate parts of a model. Some nonsyn-

LISTING 2—COUNTER INSTANTIATION FROM LISTING 1
design blocks by using library thesizeable constructs in gener-
statements. Using library state- ic definitions, such as enumer-
ments means that adding or ated data types, become
changing a parameter requires synthesizeable when you use
you to modify only one package them in a package. The package
file. Also, some synthesis tools may contain other constants
do not allow the use of Boolean, and information that you may
string, enumerated, or array use for parameterization, yet the
types for generics. In such cas- design may still use this infor-
es, using library statements al- mation. The package serves as a
lows you to use a constant in a common place-holder for this
package. Most synthesis tools type of shared information. Fur-
allow most data types, and us- thermore, a package of param-
ing library statements lets pack- eters provides better code struc-
ages use TYPE statements for ture, provides efficient organ-
enumerated data types. A pack- ization, and is self-document-
age of constants also lets you ing.
use the same package for design Figure 1 shows the parame-
and simulation in “design- terized counter for different val-
aware” testbenches. the design, you have to change only the ues of generics and constants. The count-
As an example of the use of a package parameter value in the package, and you er was synthesized using Synopsys’
of constants, consider changing the can see the change in all the units refer- (www.synopsys.com) Design Compiler
counter in Listing 2 to use such a pack- encing the parameter. A package of con- with a 0.2-mm standard-cell library with
age. Also, assume that the package resides stants can also use subtypes and enu- the BIT_WIDTH parameter set to 2 in all
in the “pkgs” VHDL library (Listing 3). merated data types to reference the synthesis tests.
This counter example shows that using parameters for reusability and readabili- In the counter of Figure 1,
a package of constants is similar to using ty, and a central package can serve as a COUNT_ENABLE is false (unconnected
generics for parameterization. In addi- package of parameters to parameterize en enable signal), BIT_WIDTH is 2, and
tion, using a package of constants allows an entire design. Further, using a package DOWN_ COUNT is false (a conven-
any design entity to reference the pa- makes it relatively simple to use arrays tional up-counter). In the counter of Fig-
rameters in the package without any and other composite data types for pa- ure 2, an up-counter with count enable,
overhead. Also, to change the structure of rameterization. COUNT_ENABLE is true (connected en
You can work on a enable signal), BIT_WIDTH is 2, and
LISTING 3—COUNTER DESIGNED USING A PACKAGE OF CONSTANTS package separately as a DOWN_COUNT is false. Also in the
design unit, create the counter of Figure 3, a down-counter
package independently with no enable, COUNT_ENABLE is
of the design, and reuse false (unconnected en enable signal),
the package in different BIT_WIDTH is 2, and DOWN_

LISTING 4—COUNTER USING DEFERRED-CONSTANTS-PARAMETER PACKAGE

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designfeature Generating reusable VHDL

COUNT is true. These three design. For example, a mem-

LISTING 5—PAD-CELL INSTANTIATION
examples show how you can ory-controller design that
modify counter structure translates host/CPU cycles
and behavior by using dif- into memory cycles is unlike-
ferent values of generics and ly to be instantiated multiple
constants while eliminating times in a design. Such de-
unnecessary gates. signs should use a package of
A deferred constant is one constants. You should use
in which you declare but do generics for designs such as
not initialize the constants bus interfaces, counters,
in a package. Instead, you adders, and linear-feedback
initialize the deferred con- shift registers.
stants in the design that uses
the constants. In other TIP 3: GENERATE STATEMENTS
words, you “defer” the bind- You can implement many
ing of the constants. You digital systems, such as mem-
must bound deferred con- ories, as regular iterative com-
stants before you reference positions of subsystems. For
them so that any change to example, memories comprise
the package does not re- rectangular arrays of storage
quire design-counter re- cells. Designers prefer such
compilation or resynthesis implementations, because
LISTING 6—REGISTER DESIGNED USING GENERATE STATEMENTS
(Listing 4). they make it easier to produce
WITH ITERATIVE STRUCTURES
Using a package of con- compact, proven, area-effi-
stants has the same effect as cient layouts, thus reducing
using generics modify struc- cost. If you can express a de-
ture or behavior during syn- sign as a repetition of some
thesis. The package of con- subsystem, you should be able
stants also allows you to to describe the subsystem
effectively use composite once and then describe how it
data types for readability is to be repeatedly instantiat-
and still preserve design syn- ed, rather than describe each
thesizability. Furthermore, it is easier to instantiation individually (Reference 2).
synthesize a design that uses a package of You can use generate statements to ef-
constants than one that uses generics. In LISTING 7—SYNCHRONOUS OR COMBI- fectively produce iterative structures of
other words, it is easier for an engineer to NATORIAL OUTPUT USING CONDITION- a design. Generate statements are con-
learn how to get the synthesis tool to use AL GENERATE STATEMENTS current VHDL constructs that may con-
the package of constants than to use a de- tain further concurrent statements for
sign that uses generics. Some synthesis replication. When you use generate State-
tools have longer runtimes for designs ments in conjunction with generics or
with composite data types. constants, they can efficiently generate
You can use a package of constants in repetitive structures. Consider a situation
much the same way that you use gener- in which you need to drive a 32-bit off-
ics. Packages of constants are easier to use chip data bus from on-chip using eight
than are generics if a lot of parameters output enables through an output pad
are involved. Packages also typically have (Listing 5). This example instantiates 32
better support of synthesis tools than do pad cells for the data bus. Note the use
generics. However, using a package of of the “range” and “length” attributes.
constants means that you cannot use These attributes also promote reuse in
multiple instances of a design with dif- constants requires you to maintain a sep- that they use the previously defined bus
ferent parameters in a single design unit. arate file or library. widths for the data bus. Also note the use
Instead, you need a unique entity and a Compare using a package of constants of “i/4” in the assignment of the output-
unique package for each recurring design with using generics for parameterization enable signals to the pad cell. The syn-
unit. Also, a change in a package that uses after considering the intended scope of thesis tool should be intelligent enough
nondeferred constants causes recompila- an application. As a general practice, use to truncate the division to an integer val-
tion or resynthesis of the designs refer- a package of constants for designs that ue to give to proper assignment of
ring the package even if a parameter does have many parameters and are not in- dataoe(3) to data(31:24), dataoe(2) to
not affect the design. Also, a package of stantiated multiple times within a large data(23:16), and so on.

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designfeature Generating reusable VHDL
Listing 6 illustrates the use of
generate statements with iterative
structures of concurrent state-
ments to create a register from a
flip-flop. You can also use gener-
ate statements to conditionally
create, modify, or remove struc-
tures. This technique involves
code-level optimization, which
removes unwanted structures
during elaboration time. With
the use of generics or packages of
constants, this technique can be
useful in creating a reusable de-
sign.
Using conditional generate
statements, you can enable or dis-
able logic that implements cer-
tain features instead of manually
removing the code or optimizing
via synthesis. As an example of
conditional code inclusion and
exclusion, you can synchronize
an output to the clock or combi-
natorially set it with the constant
CONSTANT SYNC_OUTPUTS :
BOOLEAN : TRUE; This tech-
nique lets you generate a syn-
chronous or a combinatorial out-
put (Listing 7).
The generate statement is a
powerful tool to control the in-
clusion or exclusion of logic. It is
useful for designs that repeatedly
use blocks of logic, such as flip-
flops, in an iterative structure.
These blocks form registers, pad
cells, and many other structures.
Many designers use generate
LISTING 11—CONVERTER WITH BUFFERED-COUNTER OUTPUTS
statements to instantiate cells, as
the pads example illustrates, but
you can also use generate state-
ments to conditionally create,
modify, or remove sections of
VHDL code. Generate statements
are powerful tools promoting de-
sign reuse. A few more examples
that show the application of gen-
erate statements are choosing im-
plementation of a latch-based or
flip-flop-based register; including
fixed, round-robin, or another
arbitration scheme in a bus-ar-
biter design; and including only
those bits of an interrupt con-
troller that you know you are go-
ing to use. Consider the case in
which registered interrupts are
entering the interrupt controller.
58 edn | August 19, 1999
LISTING 8—COUNTER WITH UNCONSTRAINED ARRAYS
FOR THE COUNT OUTPUT
LISTING 9—INSTANTIATING THE COUNTER OF LISTING 8
IN A TOP-LEVEL ENTITY
LISTING 10—BIT-WIDTH-INDEPENDENT IMPLEMENTATION
OF BINARY-CODE-TO-GRAY-CODE CONVERTER
If these inputs go through a sub-
stantial amount of combinatorial
logic before being routed to other
registers, then the use of generate
statements to include only the
necessary flip-flops will help a
synthesis tool to significantly re-
duce the gate count. Be aware that
some synthesis tools cannot opti-
mize across flip-flops. In these cas-
es, even if we know that an input,
such as an unused interrupt, is al-
ways tied high, the synthesis tool
can’t use this information to re-
duce the gate count of the synthe-
sized design.
TIP 4: PORTS
In many instances, you can se-
lectively disable logic by tying off
certain ports to default values.
When synthesized with a top-
down approach, the synthesis tool
uses “optimization by constant
propagation”—optimizing that
path and taking into considera-
tion that tied-off value. You can
later remove the tied-off ports
from the entity. Consider a three-
AND-gate design (Figure 4a). If
you tie one of the inputs to a zero
(Figure 4b), then the resulting
logic eliminates all the AND gates
and the output, F, is always at log-
ic 0.
a1: and3 port map (
a => a,
b => ‘0’, — Valid in
VHDL 93, Tied off to vss <=
‘0’ in 87
c => c,
zo => zo
);
The same situation is true for
port outputs. By leaving unused
port outputs open (zo => open),
you can eliminate the logic that
creates these outputs when you
adopt a top-down synthesis ap-
proach.
TIP 5: UNCONSTRAINED ARRAYS
Using unconstrained arrays is a
helpful method of reusing designs
for variable-width implementa-
tions. You should be careful when
using attributes such as “range”
and “length” in the design to avoid
runtime and elaboration-time er-
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designfeature Generating reusable VHDL

rors. Unconstrained arrays are LISTING 12—TWO COUNTER INSTANCES INSTANTIATED using unconstrained arrays to
particularly suitable for ad- IN A TOP-LEVEL ENTITY support efficient reuse.
dress, data, and register
widths. You can use these ar- TIP 6: VHDL ATTRIBUTES
rays for formal parameters in A few attributes of compos-
functions and procedures as ite types are useful in creating
well as for entity ports. reusable designs. The attrib-
VHDL allows the use of un- utes “left,” “right,” “range,”
constrained-array types that “length,” “low,” and “high” are
let you indicate the type of in- synthesizable and make the
dex values without specifying code independent of data type.
the index bounds. Uncon- Refer to the examples using
strained arrays are useful for unconstrained arrays (listings
making designs that you can 8 and 9), where the function
reuse in different applications Gray2bin and the entity
just by modifying their bit counter use the “range” attrib-
widths. The previous counter ute to promote reusability.
example uses unconstrained
arrays for the count output TIP 7: CONFIGURATION SPECS
(Listing 8). This technique You use configuration spec-
lets you connect the counter ifications to bind component
entity to array signals of any instances to design entities.
size or with any range of index You can also use these config-
values. Note the use of the urations to pass parameters
VHDL attribute “range” to such as generics at the top-
LISTING 13—COUNTER CONFIGURATION IN A TOP-LEVEL ENTITY
create a signal of the same most level in a testbench, to se-
width and range specification lect an architecture for an en-
as the port count. You cannot tity, or to override port
synthesize this design by itself, mappings in an instantiation.
and you have to instantiate it Some synthesis tools do not
in a top-level entity to bind support configuration specifi-
the array values to a finite cations.
range (Listing 9). You must Consider the previous
synthesize the code in Listing counter example that illus-
9 in a top-down manner so trates the use of generics for
that you can synthesize the parameterization. Listing 11
counter along with the rest of illustrates the same counter
the design. with another architecture that
Another use of uncon- buffers the counter outputs
strained arrays occurs in functions and makes efficient reuse possible. Listing 10 with a generate statement. The counter is
procedures. You should write functions is a bit-width-independent implementa- now instantiated in a top-level design us-
and procedures that you design for syn- tion for the binary-code-to-gray-code ing two instances of the counter (Listing
thesis as generically as possible, inde- converter. As another example, consider 12). A configuration specification con-
pendently of bit widths. Consider an ex- the functions and procedures in the IEEE figures the counter in the entity top, as
ample of a binary-code-to-gray-code std_logic libraries. Most of these func- shown in Listing 13. Configuration spec-
converter. To create a gray code from a bi- tions and procedures are implemented ifications let you configure various lev-
nary code, use the algorithm in Figure els of the design’s hierarchy.
5a. Figure 5b is an example of how to TABLE 1—GRAY CODES CORRESPONDING
convert binary 100 to its gray-code TO 3-BIT BINARY CODES TIP 8: BLOCK STATEMENTS
equivalent of 110. Table 1 shows the gray Binary Gray Block statements are VHDL constructs
codes for the 3-bit binary values that the 000 000 that allow inline design partitioning. For
algorithm of Figure 5a creates. You hard- 001 001 example, if you partition a design such
code and optimize this algorithm for a 3- 010 011 that the datapath exists in a separate
bit case. When the design has to accom- 011 010 VHDL entity, then you can partition the
modate more counts, the function has to 100 110 architecture for that entity using block
change, requiring you to revalidate all the 101 111 statements. Block statements are a
logic. Writing a generic function that is 110 101 method of grouping related logic. Block
independent of the bit-vector lengths 111 100 statements also provide the ability to de-

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designfeature Generating reusable VHDL
clare signals within the blocks and, if you
remove the block, unnecessary signals do
not remain unconnected in the code. You
can combine a generate statement with
the block statement to selectively include
or exclude blocks.
TIP 9: UNUSED PORTS
In a hierarchical design, if you do not
use certain ports in an entity, then the
usual practice is to connect them to a
dummy signal. From a top-down syn-
thesis approach, this scenario makes the
synthesizer assume that you’ve connect-
ed the signal to a net. You can avoid this
problem by leaving the port unconnect-
ed or by specifying with the VHDL key-
word “open.”
TIP 10: PREPROCESSORS
In many situations, designers cannot
accomplish what they want using the
available features. In some cases, it is de-
sirable to see only the code that is rele-
vant to the design. In such cases, you can
use a preprocessor to add, eliminate, or
Circle 7 or visit www.ednmag.com/infoaccess.asp
62 edn | August 19, 1999
modify code for a specific application,
through the use of preprocessor direc-
tives.□
References
1. Meiyappan, Subbu, and Peter
Chambers, “Design Reuse Using Script-
ing Methodologies,” DesignCon98, On-
Chip System Design Conference, pg 629.
2. Ashenden, PJ, The Designer’s Guide
to VHDL, Morgan Kaufman Publishers,
San Francisco, CA, 1996.
3. Smith, Douglas J, HDL Chip Design,
Doone Publications, Madison, AL, 1996,
ISBN 0-9651934-3-8.
Authors’ bio graphies
Subbu Meiyappan is a senior design engi-
neer at VLSI Technology. He has worked
for the company for nearly three years, de-
signing, developing, synthesizing,simulat-
ing, and validating high-performance IP
blocks for PCI, ARM-ASB-based devices,
and high-performance ASICs. He has a BE
from Annamalai University (Annamalai
Nagar, India) and an MS from Tennessee
Technological University (Cookeville, TN).
His interests include computer architec-
ture, design automation, volleyball, and
travel.
Ken Jaramillo is a staff engineer at VLSI
Technology. In his three years with the
company, he has worked on high-speed
networking designs, such as fiber-distrib-
uted data interfaces, Firewire, and high-
speed satellite modems. He has a BSEE
from the University of Missouri (Kansas
City, MO) and a BSCoE from the Univer-
sity of Missouri (Columbia, MO). His hob-
bies include basketball, rock climbing, and
travel.
Peter Chambers is an engineering fellow at
VLSI Technology, where he has worked for
six years developing many PCI-based de-
signs, ASICs, chip sets, and reusable IP
cores. He has a BS from the University of
Exeter (UK) and an MS from Arizona
State University (Tempe, AZ). He is a
member of both IEE and IEEE.
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