Logic and Computer Design Fundamentals

Chapter 4 – Sequential
Circuits
Sequential circuits

 Storage elements are circuits capable of

storing binary information that defines
the state of the sequential circuit at that
time.
 Introduction to Sequential Circuits

Inputs Outputs
Combina-
 A Sequential tional
circuit contains: Storage
Logic
Elements
• Storage elements:
Latches or Flip-Flops Present
Next
State State
• Combinational Logic:
 Implements a multiple-output
switching function
 Inputs are signals from the outside.
 Outputs are signals to the outside.
 Other inputs, State or Present State, are
signals from storage elements.
 The remaining outputs, Next State are
inputs to storage elements.
Introduction to Sequential Circuits

Inputs Outputs
Combina-
tional
Storage
Logic
Elements
 Combinatorial Logic Next
• Next state function State State
Next State = f(Inputs, State)
• Output function (Mealy)
Outputs = g(Inputs, State)
• Output function (Moore)
Outputs = h(State)
 Output function type depends on specification and affects
the design significantly
Types of Sequential Circuits

 Depends on the times at which:

• storage elements observe their inputs, and
• storage elements change their state
 Synchronous
• Behavior defined from knowledge of its signals at discrete
instances of time
• Storage elements observe inputs and can change state only in
relation to a timing signal (clock pulses from a clock)
 Asynchronous
• Behavior defined from knowledge of inputs an any instant of
time and the order in continuous time in which inputs change
• If clock just regarded as another input, all circuits are
asynchronous!
• Nevertheless, the synchronous abstraction makes complex
designs tractable!
Discrete Event Simulation

 In order to understand the time behavior of a

sequential circuit we use discrete event
simulation.
 Rules:
• Gates modeled by an ideal (instantaneous) function
and a fixed gate delay (tG)
• Any change in input values is evaluated to see if it
causes a change in output value
• Changes in output values are scheduled for the fixed
gate delay after the input change
• At the time for a scheduled output change, the
output value is changed along with any inputs it
drives
Flip-Flops

 The storage elements used in clocked sequential

circuits are called flip-flops.
 A flip-flop is a binary storage device capable of
storing 1 bit.
 A transition from one state to the other occurs
only at a fixed time intervals.
 Binary information can enter a flip-flop in a
variety of ways.
 Different flip-flops types.
• Different number of inputs
Basic (NOR) S – R Latch

 Cross-coupling two NOR gates gives the SR

Latch:
 Which has the time
sequence behavior:

1
S – R Latch

 “Cross-Coupling” S’ (set)
Q
two NAND gates gives
the S -R Latch:
 Which has the time R’ (reset) Q
sequence behavior:
Time S’ R’Q Q Comment
0 1 1 0
1 1 1 0 “Set” state
1 0 0 1
 S = 0, R = 0 is 1 1 0 1 “Reset” state
forbidden as 0 0 0 1 Undefined
input pattern
Clocked S - R Latch

 Adding two NAND S

gates to the basic Q
S - R NAND latch C
gives the clocked
S – R latch: Q
R
 Has a time sequence behavior similar to the basic S-R
latch except that the S and R inputs are only observed
when the line C is high.
 C means “control” or “clock”.
 Clocked S - R Latch (continued)

 The Clocked S-R Latch can be described by a table:

S
Q
C S R Next state of Q
C
0 X X No change
Q 1 0 0 No change
R
1 0 1 Q=0, Reset state
 The table describes 1 1 0 Q=1; Set state
what happens after the 1 1 1 Undefined

clock [at time (t+1)]

based on:
• current inputs (S,R) and
• current state Q(t).
D Latch

 Adding an inverter D
to the S-R Latch, Q

gives the D Latch: C

 Note that there are Q

no “indeterminate”
states! The graphic symbol for a
Q D Q(t+1) Comment D Latch is:
0 0 0 No change D Q
0 1 1 Set Q
1 0 0 Clear Q
C Q
1 1 1 No Change
Flip-Flops

 The latch timing problem

 Master-slave flip-flop
 Edge-triggered flip-flop
 Standard symbols for storage elements
 Direct inputs to flip-flops
The Latch Timing Problem

 In a sequential circuit, paths may exist through

combinational logic:
• From one storage element to another
• From a storage element back to the same storage
element
 The combinational logic between a latch output
and a latch input may be as simple as an
interconnect
 For a clocked D-latch, the output Q depends on
the input D whenever the clock input C has
value 1
 The Latch Timing Problem (continued)
 Consider the following circuit:
D Q Y

Clock C Q
 Suppose that initially Y = 0.
Clock
Y
 As long as C = 1, the value of Y continues to change!
 The changes are based on the delay present on the loop
through the connection from Y back to Y.
 This behavior is clearly unacceptable.
 Desired behavior: Y changes only once per clock pulse
The Latch Timing Problem (continued)

 A solution to the latch timing problem is

to break the closed path from Y to Y
within the storage element
 The commonly-used, path-breaking
solutions replace the clocked D-latch
with:
• a master-slave flip-flop
• an edge-triggered flip-flop
S-R Master-Slave Flip-Flop
 Consists of two clocked S S S
Q Q Q
S-R latches in series C C C
with the clock on the R R Q R Q Q
second latch inverted
 The input is observed
by the first latch with C = 1
 The output is changed by the second latch with C = 0
 The path from input to output is broken by the
difference in clocking values (C = 1 and C = 0).
 The behavior demonstrated by the example with D
driven by Y given previously is prevented since the
clock must change from 1 to 0 before a change in Y
based on D can occur.
Flip-Flop Problem

 The change in the flip-flop output is delayed by

the pulse width which makes the circuit slower or
 S and/or R are permitted to change while C = 1
• Suppose Q = 0 and S goes to 1 and then back to 0 with
R remaining at 0
 The master latch sets to 1
 A 1 is transferred to the slave
• Suppose Q = 0 and S goes to 1 and back to 0 and R
goes to 1 and back to 0
 The master latch sets and then resets
 A 0 is transferred to the slave
• This behavior is called 1s catching
Flip-Flop Solution

 Use edge-triggering instead of master-slave

 An edge-triggered flip-flop ignores the pulse
while it is at a constant level and triggers only
during a transition of the clock signal
 Edge-triggered flip-flops can be built directly at
the electronic circuit level, or
 A master-slave D flip-flop which also exhibits
edge-triggered behavior can be used.
 Edge-Triggered D Flip-Flop
 The edge-triggered D D S
Q Q Q
D flip-flop is the
C
same as the master- C C Q R Q Q
slave D flip-flop
 It can be formed by:
• Replacing the first clocked S-R latch with a clocked D latch or
• Adding a D input and inverter to a master-slave S-R flip-flop
 The delay of the S-R master-slave flip-flop can be
avoided since the 1s-catching behavior is not present
with D replacing S and R inputs
 The change of the D flip-flop output is associated with
the negative edge at the end of the pulse
 It is called a negative-edge triggered flip-flop
Positive-Edge Triggered D Flip-Flop
 Formed by D D Q S Q
Q
adding inverter C
to clock input C C Q R Q Q

 Q changes to the value on D applied at the

positive clock edge within timing constraints to
be specified
 Our choice as the standard flip-flop for most
sequential circuits
Direct Inputs

 At power up or at reset, all or part

of a sequential circuit usually is S
initialized to a known state before D Q

it begins operation
 This initialization is often done C Q
R
outside of the clocked behavior
of the circuit, i.e., asynchronously.
 Direct R and/or S inputs that control the state of the
latches within the flip-flops are used for this
initialization.
 For the example flip-flop shown
• 0 applied to R resets the flip-flop to the 0 state
• 0 applied to S sets the flip-flop to the 1 state
Sequential Circuit Analysis

 General Model
Inputs Outputs
• Current State Combina-
at time (t) is tional
stored in an Storage Logic
array of Elements
Next
flip-flops. State State
• Next State at time (t+1)
is a Boolean function of CLK
State and Inputs.
• Outputs at time (t) are a Boolean function of
State (t) and (sometimes) Inputs (t).
Example 1

 Input: x(t)
x D Q A
 Output: y(t) A
C Q
 State: (A(t), B(t))
 What is the Output
Q B
Function? D

CP C Q

 What is the Next State y

Function?
Example
 Boolean equations
for the functions: x
A
D Q
• A(t+1) = A(t)x(t) A
C Q
+ B(t)x(t) Next State

• B(t+1) = A(t)x(t)
• y(t) = x(t)(B(t) + A(t)) D Q B

CP C Q'

Output
State Table Characteristics

 State table – a multiple variable table with the

following four sections:
• Present State – the values of the state variables for
each allowed state.
• Input – the input combinations allowed.
• Next-state – the value of the state at time (t+1) based
on the present state and the input.
• Output – the value of the output as a function of the
present state and (sometimes) the input.
 From the viewpoint of a truth table:
• the inputs are Input, Present State
• and the outputs are Output, Next State
Example 1: State Table
 The state table can be filled in using the next state and
output equations:
• A(t+1) = A(t)x(t) + B(t)x(t)
• B(t+1) =A (t)x(t)
• y(t) =x (t)(B(t) + A(t))

Present State Input Next State Output

A(t) B(t) x(t) A(t+1) B(t+1) y(t)
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
Example 1: Alternate State Table

 2-dimensional table that matches well to a K-map.

Present state rows and input columns in Gray code
order.
• A(t+1) = A(t)x(t) + B(t)x(t)
• B(t+1) =A (t)x(t)
• y(t) =x (t)(B(t) + A(t))

Present Next State Output

State x(t)=0 x(t)=1 x(t)=0 x(t)=1
A(t) B(t) A(t+1)B(t+1) A(t+1)B(t+1) y(t) y(t)
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
State Diagrams

 The sequential circuit function can be

represented in graphical form as a state
diagram with the following components:
• A circle with the state name in it for each state
• A directed arc from the Present State to the Next
State for each state transition
• A label on each directed arc with the Input values
which causes the state transition, and
• A label:
 On each circle with the output value produced,
or
 On each directed arc with the output value
produced.
State Diagrams

 Label form:
• On circle with output included:
 state/output
 Moore type output depends only on state
• On directed arc with the output
included:
 input/output
 Mealy type output depends on state and
input
Example 1
Equivalent State Definitions

 Two states are equivalent if their response

for each possible input sequence is an
identical output sequence.
 Alternatively, two states are equivalent if
their outputs produced for each input
symbol is identical and their next states
for each input symbol are the same or
equivalent.
Equivalent State Example
0 1

 For states S3 and S2, S0/0 S1

0/1
• the output for input
0 is 1 and input 1 is 0, 0/1 0/1 1/0
and
• the next state for input 1/0
S3
S2
0 is S0 and for input
1/0
1 is S2.
• By the alternative definition, states S3 and
S2 are equivalent.
Equivalent State Example
0/0
 Replacing S3 and S2 1/0
by a single state gives
S0 S1
state diagram: 0/1
 Examining the new diagram,
states S1 and S2 are equivalent since 0/1 1/0
• their outputs for input
0 is 1 and input 1 is 0,
and S2
• their next state for input
0 is S0 and for input 1/0
1 is S2,
0/0 1/0
 Replacing S1 and S2 by a
single state gives state S0 S1
diagram: 0/1

1/0
Moore and Mealy Models

 Sequential Circuits or Sequential

Machines are also called Finite State
Machines (FSMs). Two formal models
exist:
 Moore Model  Mealy Model
• Named after E.F. Moore • Named after G. Mealy
• Outputs are a function • Outputs are a function
ONLY of states of inputs AND states
• Usually specified on the
• Usually specified on the
state transition arcs.
states.
Moore and Mealy Example Diagrams

 Mealy Model State Diagram

x=1/y=0
maps inputs and state to outputs
x=0/y=0
0 1

 Moore Model State Diagram x=0 x=0/y=0 x=1/y=1

maps states to outputs
S0/0
x=0

x=1 x=1
x=0

S1/0 S2/1
x=1
Moore and Mealy Example Tables

 Moore Model state table maps state to

outputs Present Next State Output
State x=0 x=1
S0 0 1 0
S1 0 2 0
S2 0 2 1
 Mealy Model state table maps inputs and
state to outputs Present Next State Output
State x=0 x=1 x=0 x=1
0 0 1 0 0
1 0 1 0 1
 0 Moore
00/0
I=0 I=1
1 0
At Bt At+1 Bt+1 At+1 Bt+1 Ot
01/0
0 0 0 0 0 1 0
1
0 1 0 0 1 1 0
11/0
1 0 1 0 0 0 1 0 1
0
1 1 0 0 1 0 0
10/1
1
A(t+1) B(t+1)

I\AB 00 01 11 10 I\AB 00 01 11 10
0 0 0 0 0 0 0 0 0 0
1 0 1 1 1 1 1 38
1 0 0
 Moore
I

D Q
A
Q’
O
D Q
B
Q’

At+1= A*I + B * I= I(A+B)

Bt+1= A*I
O = A*B

39
 Mealy

X=0 X=1 X=0 X=1

At Bt At+1 Bt+1 At+1 Bt+1 Ot Ot
0 0 0 0 0 1 0 0
0 1 0 0 1 0 0 0
1 0 0 0 1 1 0 1
1 1 0 0 1 1 0 1

A(t+1)= X(A+B)
B(t+1)= X(A+B’)
O= XA
40
 Mealy

D Q
A
Q’

X Out
D Q
B
Q’

41
Example 2

42
The Design Procedure

 Specification
 Formulation - Obtain a state diagram or state table
 State Assignment - Assign binary codes to the states
 Flip-Flop Input Equation Determination - Select flip-flop
types and derive flip-flop equations from next state entries in the
table
 Output Equation Determination - Derive output equations
from output entries in the table
 Optimization - Optimize the equations
 Technology Mapping - Find circuit from equations and map to
flip-flops and gate technology
 Verification - Verify correctness of final design
Sequence Recognizer Procedure
 To develop a sequence recognizer state diagram:
• Begin in an initial state in which NONE of the initial portion of
the sequence has occurred (typically “reset” state).
• Add a state that recognizes that the first symbol has occurred.
• Add states that recognize each successive symbol occurring.
• The final state represents the input sequence (possibly less the
final input value) occurence.
• Add state transition arcs which specify what happens when a
symbol not in the proper sequence has occurred.
• Add other arcs on non-sequence inputs which transition to
states that represent the input subsequence that has occurred.
 The last step is required because the circuit must recognize the
input sequence regardless of where it occurs within the overall
sequence applied since “reset.”.
Sequence Recognizer Example

 Example: Recognize the sequence 1101

• Note that the sequence 1111101 contains 1101 and "11" is a
proper sub-sequence of the sequence.
 Thus, the sequential machine must remember that the
first two one's have occurred as it receives another
symbol.
 Also, the sequence 1101101 contains 1101 as both an
initial subsequence and a final subsequence with some
overlap, i. e., 1101101 or 1101101.
 And, the 1 in the middle, 1101101, is in both
subsequences.
 The sequence 1101 must be recognized each time it
occurs in the input sequence.
Example: Recognize 1101

 Define states for the sequence to be recognized:

• assuming it starts with first symbol,
• continues through each symbol in the sequence to be
recognized, and
• uses output 1 to mean the full sequence has occurred,
• with output 0 otherwise.
 Starting in the initial state (Arbitrarily named
"A"):
1/0
• Add a state that A B
recognizes the first "1."
• State "A" is the initial state, and state "B" is the state which
represents the fact that the "first" one in the input
subsequence has occurred. The output symbol "0" means
that the full recognized sequence has not yet occurred.
Example: Recognize 1101 (continued)
 After one more 1, we have:
• C is the state obtained
when the input sequence 1/0 1/0
has two "1"s. A B C
 Finally, after 110 and a 1, we have:

1/0 0/0
A 1/0 B C D
1/1

• Transition arcs are used to denote the output function (Mealy Model)
• Output 1 on the arc from D means the sequence has been recognized
• To what state should the arc from state D go? Remember: 1101101 ?
• Note that D is the last state but the output 1 occurs for the input
applied in D. This is the case when a Mealy model is assumed.
Example: Recognize 1101 (continued)

A 1/0
B
1/0 0/0 1/1
C D
 Clearly the final 1 in the recognized sequence
1101 is a sub-sequence of 1101. It follows a 0
which is not a sub-sequence of 1101. Thus it
should represent the same state reached from the
initial state after a first 1 is observed. We obtain:

1/0 0/0
A 1/0 B C D

1/1
Example: Recognize 1101 (continued)

1/0 1/0 0/0

A B C D

1/1
 The state have the following abstract meanings:
• A: No proper sub-sequence of the sequence has
occurred.
• B: The sub-sequence 1 has occurred.
• C: The sub-sequence 11 has occurred.
• D: The sub-sequence 110 has occurred.
• The 1/1 on the arc from D to B means that the last 1
has occurred and thus, the sequence is recognized.
Example: Recognize 1101 (continued)

 The other arcs are added to each state for

inputs not yet listed. Which arcs are missing?
1/0 1/0 0/0
A B C D

 Answer: 1/1
"0" arc from A
"0" arc from B
"1" arc from C
"0" arc from D.
Example: Recognize 1101 (continued)

 State transition arcs must represent the fact

that an input subsequence has occurred. Thus
we get:
0/0 1/0

1/0 1/0 0/0

A B C D

0/0 1/1
0/0
 Note that the 1 arc from state C to state C
implies that State C means two or more 1's have
occurred.
 Formulation: Find State Table

 From the State Diagram, we can fill in the State Table.

 There are 4 states, one 0/0 1/0
input, and one output.
1/0 1/0 0/0
We will choose the form A B C D
with four rows, one for
each current state. 0/0 1/1

 From State A, the 0 and 0/0

1 input transitions have

Present Next State Output
been filled in along with State x=0 x=1 x=0 x=1
the outputs. A A B 0 0
B
C
D
Formulation: Find State Table

 From the state diagram, we complete the

state table. 0/0 1/0

1/0 1/0 0/0

A B C D

0/0 1/1
0/0
Present Next State Output
State x=0 x=1 x=0 x=1
A A B 0 0
B A C 0 0
C D C 0 0
D A B 0 1
 What would the state diagram and state table
look like for the Moore model?
Example: Moore Model for Sequence 1101

 For the Moore Model, outputs are associated with

states.
 We need to add a state "E" with output value 1
for the final 1 in the recognized input sequence.
• This new state E, though similar to B, would generate
an output of 1 and thus be different from B.
 The Moore model for a sequence recognizer
usually has more states than the Mealy model.
Example: Moore Model (continued)
 We mark outputs on 0 1
states for Moore model 1 1 0
A/0 B/0 C/0 D/0
 Arcs now show only
state transitions 0 1
1
 Add a new state E to
produce the output 1 0 E/1
 Note that the new state,
E produces the same behavior 0
in the future as state B. But it gives a different output
at the present time. Thus these states do represent a
different abstraction of the input history.
Example: Moore Model (continued)

 The state table is shown 0 1

below 1 0
A/0 B/0 1 C/0 D/0
 Memory aid re more
0 1
state in the Moore model: 1

“Moore is More.” 0 E/1

0
Present Next State Output
State x=0 x=1 y
A A B 0
B A C 0
C D C 0
D A E 0
E A C 1
State Assignment – Example 2
 Counting Order Assignment: A = 00, B = 01,
C = 10, D = 11
 The resulting coded state table:
Gray code Design for the Sequence
Recognizer
Logic Diagram