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Verilog Tutorial Contents

Ch#1: Introduction
 What is Verilog? (/verilog/verilog-tutorial)
 Introduction to Verilog (/verilog/verilog-introduction)
 Chip Design Flow (/verilog/asic-soc-chip-design-flow)
 Chip Abstraction Layers (/verilog/verilog-design-abstraction-layers)

Ch#2: Data Types

 Verilog Syntax (/verilog/verilog-syntax)
 Verilog Data types (/verilog/verilog-data-types)
 Verilog Scalar/Vector (/verilog/verilog-scalar-vector)
 Verilog Arrays (/verilog/verilog-arrays-memories)

Ch#3: Building Blocks

 Verilog Module (/verilog/verilog-modules)
 Verilog Port (/verilog/verilog-ports)

Verilog Gate Level

Examples

Example #1: 2x1 Multiplexer (/verilog/verilog-gate-

level-examples#example-1-2x1-multiplexer)
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Full Adder (/verilog/verilog-gate-level-examples#full-
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adder)
 adder)
2x4 Decoder (/verilog/verilog-gate-level-
examples#2x4-decoder)
4x2 Encoder (/verilog/verilog-gate-level-
examples#4x2-encoder)

Some of the main built-in primitives were discussed in the

previous (/verilog/verilog-gate-level-modeling) article and
it would be good to see some practical examples of using
simple and , nor and not gates.

Note that in order to write the Verilog code using gates, it

is necessary for you to know how to connect the
elements. This is very different from a behavioral
description in which case the selection and connection of
elements is left upto the synthesis tools.

Example #1: 2x1 Multiplexer

Output of module has to be of type wire in order to

connect with the output port of a primitive.

module mux_2x1 ( input a, b, sel,

output out);
wire sel_n;
wire out_0;

not (sel_n, sel);

and (out_0, a, sel);

and (out_1, b, sel_n);

or (out, out_0, out_1);

endmodule

module tb;
reg a, b, sel;
wire out;
integer
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mux 2x1 u0 ( .a(a), .b(b), .sel(sel), .out(out))
 mux_2x1 u0 ( .a(a), .b(b), .sel(sel), .out(out))

initial begin
{a, b, sel} <= 0;

$monitor ("T=%0t a=%0b b=%0b sel=%0b out=%0b", $t

for (int i = 0; i < 10; i = i+1) begin

#1 a <= $random;
b <= $random;
sel <= $random;
end
end
endmodule

Simulation Log

ncsim> run
T=0 a=0 b=0 sel=0 out=0
T=1 a=0 b=1 sel=1 out=0
T=2 a=1 b=1 sel=1 out=1
T=3 a=1 b=0 sel=1 out=1
T=6 a=0 b=1 sel=0 out=1
T=7 a=1 b=1 sel=0 out=1
T=8 a=1 b=0 sel=0 out=0
T=9 a=0 b=1 sel=0 out=1
T=10 a=1 b=1 sel=1 out=1
ncsim: *W,RNQUIE: Simulation is complete.

Full Adder

module fa ( input a, b, cin,

output sum, cout);

wire s1,
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xor (s1, a, b);
 xor (s1, a, b);
and (net1, a, b);

xor (sum, s1, cin);

and (net2, s1, cin);

xor (cout, net1, net2);

endmodule

module tb;
reg a, b, cin;
wire sum, cout;
integer i;

fa u0 ( .a(a), .b(b), .cin(cin),

.sum(sum), .cout(cout));

initial begin
{a, b, cin} <= 0;

$monitor ("T=%0t a=%0b b=%0b cin=%0b cout=%0b sum

$time, a, b, cin, cout, sum);

for (i = 0; i < 10; i = i+1) begin

#1 a <= $random;
b <= $random;
cin <= $random;
end
end
endmodule

Simulation Log

ncsim> run
T=0 a=0 b=0 cin=0 cout=0 sum=0
T=1 a=0 b=1 cin=1 cout=1 sum=0
T=2 a=1 b=1 cin=1 cout=1 sum=1
T=3 a=1 b=0 cin=1 cout=1 sum=0
T=6 a=0 b=1 cin=0 cout=0 sum=1
T=7 a=1 b=1 cin=0 cout=1 sum=0
T=8 a=1 b=0 cin=0 cout=0 sum=1
T=9 a=0 b=1 cin=0 cout=0 sum=1
T=10 a=1 b=1 cin=1 cout=1 sum=1
ncsim: *W,RNQUIE: Simulation is complete.

2x4 Decoder

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en;
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wire a b c d;
 wire a, b, c, d;
integer i;

dec_2x4 u0 ( .x(x), .y(y), .en(en),

.a(a), .b(b), .c(c), .d(d));

initial begin
{x, y, en} <= 0;
$monitor ("T=%0t x=%0b y=%0b en=%0b a=%0b b=%0b c
$time, x, y, en, a, b, c, d);

en <= 1;
for (i = 0; i < 10; i = i+1) begin
#1 x <= $random;
y <= $random;
end
end
endmodule

Simulation Log

ncsim> run
T=0 x=0 y=0 en=1 a=0 b=0 c=0 d=1
T=1 x=0 y=1 en=1 a=0 b=0 c=1 d=0
T=2 x=1 y=1 en=1 a=1 b=0 c=0 d=0
T=4 x=1 y=0 en=1 a=0 b=1 c=0 d=0
T=5 x=1 y=1 en=1 a=1 b=0 c=0 d=0
T=6 x=0 y=1 en=1 a=0 b=0 c=1 d=0
T=7 x=1 y=0 en=1 a=0 b=1 c=0 d=0
T=10 x=1 y=1 en=1 a=1 b=0 c=0 d=0
ncsim: *W,RNQUIE: Simulation is complete.

4x2 Encoder

module enc_4x2 ( input a, b, c, d,

output x, y);

or (x, b, d);
or (y, c, d);

endmodule

module tb;
reg a, b, c, d;
wire x, y;
integer
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enc 4x2 u0 ( .a(a), .b(b), .c(c), .d(d), .x(x), .y
 g ( g g )
 SystemVerilog Tutorial (/systemverilog/systemverilog-tutorial)
 UVM Tutorial (/uvm/uvm-tutorial)
 Quiz (/quiz/systemverilog-quiz-1)

Quizzes

 Verification Quiz 1 (/quiz/verification-quiz-1)

 SystemVerilog Quiz 1 (/quiz/systemverilog-quiz-1)
 SystemVerilog Quiz 2 (/quiz/systemverilog-quiz-2)
 SystemVerilog Quiz 3 (/quiz/systemverilog-quiz-3)
 UVM Quiz 1 (/quiz/uvm-quiz-1)
 C/C++ Quiz 1 (/quiz/c-cpp-quiz-1)
 C/C++ Quiz 2 (/quiz/c-cpp-quiz-2)

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 enc_4x2 u0 ( .a(a), .b(b), .c(c), .d(d), .x(x), .y

initial begin
{a, b, c, d} <= 0;

$monitor("T=%0t a=%0b b=%0b c=%0b d=%0b x=%0b y=%

$time, a, b, c, d, x, y);

for (i = 0; i <= 16; i = i+1) begin

#1 {a, b, c, d} <= i;
end
end

endmodule

Simulation Log

ncsim> run
T=0 a=0 b=0 c=0 d=0 x=0 y=0
T=2 a=0 b=0 c=0 d=1 x=1 y=1
T=3 a=0 b=0 c=1 d=0 x=0 y=1
T=4 a=0 b=0 c=1 d=1 x=1 y=1
T=5 a=0 b=1 c=0 d=0 x=1 y=0
T=6 a=0 b=1 c=0 d=1 x=1 y=1
T=7 a=0 b=1 c=1 d=0 x=1 y=1
T=8 a=0 b=1 c=1 d=1 x=1 y=1
T=9 a=1 b=0 c=0 d=0 x=0 y=0
T=10 a=1 b=0 c=0 d=1 x=1 y=1
T=11 a=1 b=0 c=1 d=0 x=0 y=1
T=12 a=1 b=0 c=1 d=1 x=1 y=1
T=13 a=1 b=1 c=0 d=0 x=1 y=0
T=14 a=1 b=1 c=0 d=1 x=1 y=1
T=15 a=1 b=1 c=1 d=0 x=1 y=1
T=16 a=1 b=1 c=1 d=1 x=1 y=1
T=17 a=0 b=0 c=0 d=0 x=0 y=0
ncsim: *W,RNQUIE: Simulation is complete.

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