IEEE Asian Solid-State Circuits Conference

9-5 November 8-10,2010 / Beijing, China

A 21.6W Inductively Powered Implantable IC

for Blood Flow Measurement
Pradeep Basappa Khannur, Kok Lim Chan, Jia Hao Cheong, Kai Kang, Andreas Astuti Lee, Xin Liu, Huey Jen Lim,
Kotlanka Ramakrishna and Minkyu Je

Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research)

11 Science Park Road, Singapore Science Park II, Singapore 117685
Email: pradeep@ime.a-star.edu.sg

Abstract—This paper presents a fully integrated inductively

powered implantable circuits for blood flow measurement,
which are embedded within vascular prosthetic grafts for early
detection of graft degradation or failure. The ASIC interfaces
with micro-fabricated pressure sensors and uses a 13.56MHz
carrier frequency for power transfer and command/data
communication. A backscatter-modulated passive telemetry is
used for transmitting sensor readout information to an external
monitoring device. The chip has been fabricated in 0.18µm
CMOS process, occupies a total active area of 1.51.78mm2 and (a)
consumes a total power of 21.6µW. The rectifier achieves an
efficiency of 66%. The sub-µW 10-bit SAR ADC achieves an
ENOB of 8.5 bits at 106KS/s conversion rate.

Graft
I. INTRODUCTION (b)

Hundreds of vascular prosthetic grafts are implanted eve-

Figure 1. (a) Simplified block diagram of the blood flow measurement
ryday for haemodialysis or bypass purposes all over the world. system, (b) Conceptual structure of the prosthetic graft with the sensor, IC
At least 20-30% of the existing renal haemodialysis popula- and coil.
tion have a prosthetic vascular graft in-situ. In addition, thou-
invasiveness (angiograms). More importantly, these proce-
sands of lower limb bypasses are performed all over the world
dures are not entirely risk-free for patients and come with
yearly, of which at least 20% require the use of prosthetic
some procedural morbidity and monitoring of flow rates are
grafts. Prosthetic grafts are frequently used in vascular surgery
done at regular intervals (i.e. once in 4-6 months). There are a
in the context of bypass surgery for lower limb ischemia or as
few commercially available flow rate detection devices (in-
a conduit for haemodialysis in renal failure. In these settings,
travascular) but they are invasive in nature causing trauma to
graft failure can result in deleterious outcomes for the patients
the patient for every measurement. An implantable system that
i.e. worsening ischemia, inability to undergo haemodialysis.
can provide convenient monitoring of blood flow in vascular
Insufficient blood flow rates in these grafts are predictive of
prosthetic grafts with a simple hand-held device is desired.
subsequent graft thrombosis and failure. Underlying this is the
With the sensor-embedded graft, the failing graft can be
presence of stenoses in the graft or downstream from the graft.
detected at its earlier stage thus implementing early interven-
Variations in flow rates can localize the position of significant
tion strategies. Similarly, this will reduce the number of graft
stenosis that may result in graft thrombosis. Flow rate moni-
surveillance scans (CTs, angiograms, etc.) per patient from a
toring provides an indication for early intervention to prevent
routine process to one done only when there are abnormalities
graft failure.
detected in the flow rates.
As such, a large amount of resources are devoted to de-
The ASIC presented in this paper is designed for a passive
tecting failing grafts vis-a-vis decreasing flow rates. In par-
implantable microsystem, Sensor-Embedded Prosthetic Vas-
ticular, significant amounts of time and financial resources are
cular Graft, which can be powered wirelessly (through induc-
spent on using different modalities to monitor graft flow rate
tive coupling) to sense the blood flow rate and transmit it
and detect early failures. These modalities include ultrasound,
through wireless interface to a hand-held device which can
computer tomography (CT) scan and formal angiograms.
send the data to the medical practitioner. The highly sensitive
Disadvantages of these modalities include the need for signifi-
nanowire-based pressure sensor is used in this microsystem,
cant amounts of procedural time (ultrasound, angiogram), the
which is not the scope of this paper, as the sensing element for
use of nephrotoxic contrast (CT scan and angiograms) and
detecting the blood flow rate.

This work is funded by A*STAR (Agency for Science, Technology and

Research) SERC (Science and Engineering Research Council), Singapore
under the grant no. 0921480069.

978-1-4244-8298-6/10/$26.00 ®2010 IEEE

Figure 2. Chip architecture.
The overall system block diagram is shown in Fig. 1. The
implant device consists of (1) sensors, (2) an ASIC and (3) a
coil. These are attached to the inner wall of the prosthetic
graft. The piezoresistive sensor produces resistance change
proportional to the blood flow rate. The ASIC converts the
resistance change into a form of voltage, then digital data and
communicate this acquired information through a passive
wireless telemetry. The coil serves two purposes – (a) through
an inductive coupling with a primary coil placed outside the
patient’s body, delivers power and commands to the ASIC and
backscatters the digitised sensor data; (b) acts as an anchor to
hold the sensor in position when blood is flowing.
This paper presents a low power implantable ASIC for
blood flow rate measurement. In Section II, an overall chip
architecture is presented. The design and implementation of
key circuit blocks are explained in Section III. The ASIC
measurement results are presented in Section IV, followed by
conclusion in Section V.
II. CHIP ARCHITECTURE
The chip architecture is shown in Fig. 2. The DC power
recovering blocks are a rectifier with a parallel resonant tank
at the input, a limiter and a power management block. In the
vascular prosthetic graft, very little RF energy at 13.56MHz
reaches the implanted ASIC, after skin and tissue absorption,
for the RF-to-DC energy conversion to power the ASIC.
Hence, increasing the efficiency of the rectifier and reducing
the power consumption of the ASIC is critical. In this work, a
parallel resonant LC tank having an optimum quality factor
and a highly efficient rectifier are designed along with low
dropout (LDO) regulators.
The sensors based on nanowires provide changes in resis-
tance which is proportional to the flow rate. The sensor inter-
face converts the resistance to the voltage. This analog voltage
is in turn converted to the digital data by the 10-bit ADC. The
clock is extracted from the incoming carrier from the external
hand-held device and the carrier frequency fc is 13.56MHz.
The sampling clock for the ADC is 106 kHz which is fc/128.
The external device configures the implant ASIC by sending
the command. After selecting the sensor to be read and setting
the parameters such as gain, integration time, etc., the ADC
clock is generated. The sensor data is digitized by the ADC
and converted to the serial bit stream. The digital data is coded
to a desired format in the digital block and sent to the external
978-1-4244-8298-6/10/$26.00 ®2010 IEEE
Figure 3. Schematic diagram of RF front-end circuits.
device by backscattering the incoming RF carrier through a
load modulation.
III. BUILDING BLOCKS
As there is no battery to power the ASIC, it is utmost im-
portant how efficiently the RF energy is coupled from the
external device as well as how low power the building blocks
of the ASIC consume to function. Hence, the rectifier and on-
chip LDO regulator are designed to achieve a high efficiency.
The sensor interface circuit operates with the piezoresistive
sensors and translates the resistance change to a voltage signal
that can be processed by the following stages and digitized by
the ADC.
A. RF front-end
The RF front-end connecting to the coupling coil consists
of a rectifier, a clock extractor, a ASK demodulator and a
backscatter modulator. The RF front-end schematic is shown
in Fig. 3. The power conversion efficiency (PCE) of the rec-
tifier is one of the most important parameters. For converting
AC energy to DC energy, an eight-stage differential-drive
rectifier is used [1]. The rectifier core has a cross-coupled
bridge configuration. A differential-drive active gate bias
mechanism enables to achieve both low ON-resistance and
small reverse leakage of diode-connected MOS transistors at
the same time, resulting in a high PCE. Unit stages are seri-
ally stacked along the DC path and connected in parallel to
the input RF terminals. By using this multi-stage configura-
tion, appropriate DC output voltage is obtained at the optimal
operating point where the PCE is maximized. The clock ex-
tractor consists of an input AC-coupled amplifier and a
Schmitt trigger. The clock is divided by two, buffered and fed
to the digital core as its reference clock. The envelope of the
received ASK-modulated signal is compared with the average
value of the envelope to obtain the command from the exter-
nal device.
B. Power Management
The unregulated DC voltage from the rectifier is regulated
by the low-power LDO voltage regulators. The power man-
Figure 4. Digital baseband state-machine.
Figure 5. (a) Schematic diagram of the sensor interface circuit. (b) Timing
diagram and the output voltage waveform of the switched current integrator.
agement block also generates the desired reference voltages
for the SAR ADC and sensor interface block.
C. Digital Core
The state machine of the implemented digital baseband
and controller is shown in Fig. 4.
D. Sensor Interface Circuit
Nanowire-based piezoresistive sensors are used to sense
the blood flow. The sensor’s resistance changes according to
pressure applied to the sensor. The change in resistance, ΔR,
can be in the range of ±10% to ±30%. The sensor interface
circuit converts ΔR, into analog voltage.
Fig. 5(a) shows the schematic diagram of the sensor inter-
face circuit. During reset period (RST), switch S1RST and
S2RST of the integrator are closed while the switch SINT is
open, making the op-amp in the unity gain configuration. The
offset of the op-amp is stored in the capacitor COFF during this
period. There is a non-overlapping time between the reset and
the integration period, pre-integration hold. This is to prevent
the shorting of the sensor to the ground before S2RST is fully
opened. During integration period (INT), S1RST and S2RST are
opened while switch SINT is closed. The selected channel’s
sensor current is then integrated through the capacitor CINT.
During this period, a voltage of 100mV is applied across the
978-1-4244-8298-6/10/$26.00 ®2010 IEEE
Figure 6. (a) SAR ADC Architecture, (b) Common-mode resetting tri-level
switching scheme.
sensor. The output voltage of the integrator, Voutint, settles at
voltage level that depends on both the integration period
(programmable) and the sensor resistance.
The single ended output voltage from the integrator is
amplified and converted to a differential signal by the gain
stage. The gain stage consists of a fully differential folded-
cascade op-amp with a switched-capacitor common-mode
feedback (SC-CMFB), a switched-capacitor (SC) feedback,
and a non-overlapping clock generator. The gain of this stage
is equal to C1/C2 and can be controlled as C1 is a 3-bit pro-
grammable capacitor bank. The operation of the gain stage is
given as follows: During S1, the input voltage is stored in the
capacitor C1, the op-amp holds the previous value while the
charge at C2 is reset during this period. During S2, the charge
in C1 is transferred to C2. Then the cycle repeats again. Ca-
pacitor C3 keeps the op-amp in closed-loop and holds the
previous voltage. However, it does not contribute the gain of
this stage which is given by C1/C2.
E. SAR ADC
The SAR ADC is a suitable solution for micro-power med-
ical devices due to their low power consumption. The SAR
ADC architecture used in this ASIC is shown in Fig. 6(a). It
consists of a capacitor array, a switching array, a time-domain
comparator and a switching logic. A non-binary redundant
algorithm is applied to the capacitor array of the SAR ADC
[2], [3]. A time-domain comparator [4] is utilized to reduce
the power consumption. It converts the voltage signal to pulse
width and compares the duration of the pulses.
A new common-mode resetting tri-level switching scheme
is applied to the SAR ADC. During the sampling period, the
proposed scheme samples the input signal onto the top plates
of the capacitor array while the bottom plates are reset to Vcm
which is equal to Vref/2 as shown in Fig. 6(b). By doing so, the
1st MSB can be determined during the sampling period with-
out a need for another cycle for the MSB decision. As a result,
one conversion cycle is saved. Based on previous bit decision,
the bottom plates of the following capacitor pairs will be
switched to either Vref-hi or Vref-lo whereas the rest of the diffe-
 selected to be equal to the input common mode voltage
(Vin_common).

IV. MEASURED RESULTS

Figure 7. Microphotograph of the ASIC.
The chip has been fabricated in 0.18µm CMOS process
(Fig. 7). As shown in Fig. 8, the RF power from the reader
was converted to DC supply to power the ASIC and command
from the reader is demodulated, clock is extracted from the
incoming carrier, power-on-reset signal is generated to reset
the digital baseband, clock for the ADC is generated to
convert analog sensor information to digital in 10-bit ADC
and this data is processed in digital baseband and fed to the
load modulator to backscatter the unmodulated carrier from
the external device. The measured timing diagrams are shown
in Fig. 9. The ASIC occupies a total active area of
1.51.78mm2 and consumes a total power of 21.6µW. The
measured ASIC performance is summarized in Table I.

TABLE I. MEASURED PERFORMANCE SUMMARY OF THE IC

Received Command from
the External Device Parameter
Carrier frequency
Modulation and Demodulation
Power-On-Reset Signal generated
(Both External and Implant
Devices)
10-bit ADC Clock extracted Communication Protocol
Rectifier efficiency
Transmitted Sensor Data Power management block
to the External Device
ADC
Figure 8. Measured waveforms of the demodulated Rx command, power-on-
reset, ADC clock and sensor Tx data. Total power consumption
Measured Result
13.56MHz
ASK (programmable modulation
depth from 10% to 90% in steps of
10%)
Modified and simplified from ISO
14443 RFID standard
66%
Efficiency : 56%;
Power consumption: 12.8µW
Resolution: 10 bits
ENOB: 8.6bits @ 5kHz input
7.4bits @ 25kHz input
INL/DNL: 1.5LSB / 0.6LSB
21.6µW
(RF front-end: 5µW; ADC: 0.4µW;
Sensor interface: 1.4µW;
Power management: 12.8µW;
Digital core: 2µW)

Figure 9. Measured timing diagram for communication with the external
device.
V. CONCLUSION
The implantable wireless blood flow measurement IC was
presented. The IC along with the nanowire-based sensors and
coil make the complete microsystem for blood flow
measurement within the prosthetic graft. It consumes only
21.6µW and is powered through the inductive link, making it
suitable for the wireless monitoring of various vital bio-
signals inside the human body without the need of battery.

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978-1-4244-8298-6/10/$26.00 ®2010 IEEE