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Abstract:

A project on SAR(Successive approximation register) which is widely used in ADC(Analog to digital


converter). As you know every register is nothing but the collection of flipflops.. If we consider D- Flip
flop,this flipflop traansfers the input to the output side on the arrival of either of edge of the
clock(either rising or falling). Use a D flip flop which will work on both rising and falling edge of the
clock.So speed will get doubled and power consumption is also less. And by using these Double edge
triggered D-Flip flops(DETDFF) make a SAR(Successive Approximation register). This project should be
based on Microwind software or the tool DSCH-3.1 should be used.

Index:-
[1] Introduction

[2] Literature Review

[3] Problem Definition

[4] Proposed Work

4.1 Synchronous Clock.

4.2 Separate code register and sequence coder are replaced by a single row of flip flops.

4.3 Minimum number of Flip-flops.

4.4 Parallel data output.

4.5 To avoid the problem of clock skew.

4.6 Logic for SAR operation with minimum number of gates.

4.7 To study different types of DETDFF and choose the efficient one.

[5] Proposed Methodology

[6] Tools Available

[7] Implications

[8] References
[1] Introduction :
In a recent survey article on data conversion, it was pointed out that the most popular type of analog-
to-digital (A/D) converter in use today is the one employing the successive-approximation (SA) logic. The
main reason for its popularity lies in its inherently fast conversion time which is a constant n clock
periods for an n-bit converter. When compared to other A/D schemes such as the dual-slope integrating
method and the servo-type method, the successive-approximation scheme offers much higher
conversion rates.

Basically, the successive-approximation A/D converter consists of three main components an analog
comparator, a DAC, and a successive-approximation register (SAR) all of which are connected in a
feedback arrangement shown in Fig.

In the proposed SAR design, a single row of DETDFF is used in each bit cell which functions both as
sequencer and code register. This type of design is often referred to as the sequencer/code register
design.

In a conventional single edge-triggered (SET) flip- flop, data moves from input to output in synchrony
with one edge of the clock. The use of double edge-triggered flip-flops has been already proposed for
low-power circuit design. In a DET flip-flop, both rising and falling edges of the clock signal are used to
transfer data from input to output. In this way, for a given throughput, the clock frequency can be
halved with respect to a system using SET flip- flops, with a reduction of power consumption.
Unfortunately, DET flip-flops require a more complex implementation with respect to SET flip flops. This
results not only in larger silicon area but also requires higher number of internal nodes and transistors

Also, since this design is fully synchronous with the clock and data input signals, a reduction in
propagation delay through the register is achieved when compared to asynchronous SAR designs.

• Applications:-
• The proposed SAR is mainly used in data converters like Analog to Digital converter (ADC).
• Double edge triggered D-Flip-flop (DETDFF) can also be used in Phase frequency detector (PFD).
• Objectives:-

Following are the required issues regarding the improvement in performance of SAR:-

 Synchronous Clock.
 Separate code register and sequence coder are replaced by a single row of flip flops.
 Minimum number of Flip-flops.
 Parallel data output.
 Logic for SAR operation with minimum number of gates.
 To study different types of Double edge triggered D-Flip-flops (DETDFF) and chooses the
efficient one.
[2] Literature Review:-
[1] In this paper, SAR uses a separate sequencer and code register made from D-type flip flop. This
designing gives the advantage of simplicity and ease in construction. It consists of reproducing each bit
cell containing only two D-type flip flops. Here sequencer operates synchronously with the clock input
and the code register operate asynchronously since the clock input to the particular flip flop is obtained
from the output of succeeding flip flops. In this design, 3 flip flop delay occurs between the leading clock
edge and the Output of the code register. As the number of flip flop increases, the power requirement is
also high.

So a new design is proposed by Howard T. Russell. In this design a


single D flip flop is used in each bit cell which functions both as sequencer and
code register. This design is often referred as the sequencer/code register design. However it is
necessary to add some steering logic in order to control the clock and data inputs to each cell.

This designing is having the advantage of Less number of flip flops are needed for designing and power
consumption is low as compared to previous one. It is having some of the disadvantages like the
complex steering logic is needed, whose designing is a tedious job. It also introduces delay in the
processing .In this design two extra flip flops are required i.e. n+2 for n bit conversion. One for holding
the parallel data output and other for generating EOC signal.

[2] In this paper, Yuen studied the research done by Anderson and Russell and
proposed his own model.

According to Anderson, the SAR converter consists of number of identical cells , each containing a J-K
flip flop with two AND gates. Russell’s design makes the use of (n+2) D-Flip-Flops ,this design requires
more than two gates per cell. His design includes modification of Anderson’s design and idea in Russell’s
design regarding the enabling of clock. Instead of two AND gates per cell, his model needs two OR
gates. Following figure shows the proposed model of SAR. There are (n+1) J-K flip-flops one for each bit
of the digital output and an extra one to signal completion. As we are using OR gates instead of AND
gates,there is reduction in the complexity of the design as OR gates are easier to fabricate than AND
gates. As J-K flip flops needs more power for its operation compared to D flip flops, the overall power
requirement for the whole circuit increases. Asynchronous clock introduces the more delay in circuit
operation.

[3] In this paper, the design consists of N=6 J-K flip flops used both as a shift register and code register
with k inputs fed by comparator output. The single row solution based on JK-Flip flops does not provide
the expected benefits in terms of power consumption. It uses the asynchronous feedback through the
AND gates which severely limits the maximum clock frequency.

So the new design of SAR is proposed which is based on chain of D flip flops with synchronous
feedbacks. The Di signals are generated by a circuit (D-GEN) using some Qi and Pi signals (with i belongs
to 0 -----5) as inputs. This provides benefits in terms of power consumption with respect to JK flip flop
SAR. The Pi signals are provided by simple synchronous circuit (P-GEN) having Qk and Pk as input. This
solution avoids delay introduced in Pi signals by asynchronous feedback and removes any glitches
affecting Pi signal.

[4] This paper compares two previously published Double Edge Triggered D FlipFlops (DETDFF) with the
proposed design for their performance and power consumption.

In Gago’s DETDFF, at negative edge of the clock, the upper circuit operates and issues the output and at
positive edge of the clock, the lower circuit operates and gives the output. The circuit requires total 22
transistors. As the number of transistors are more, power consumption is more.

In Waichung’s DETDFF, At negative edge of the clock, the left stage issuing the output. At positive edge
of the clock, the right stage issuing e output. When one stage is in action, the other stage is deactivated.
The circuit requires total 26 transistors. Here also the number of transistors are more, so power
consumption is more.

In the proposed designing of DETDFF, At positive edge of the clock, the upper circuit operates and
issues the output. At negative edge of the clock, the lower circuit operates and gives the output. The
circuit requires total 22 transistors. Even though the proposed circuit has the same numbers of
transistors as in Gago and slightly less number of transistors as in Wai Chung, due to effective
construction, the proposed circuit consumes less power and has lower delay as compared with DETDFF
designed by Gago and Wai Chung.

[5] The two circuits proposed in this paper were simulated using 1.5-pm CMOS technology and an
HSPICE simulator at level 6. The static circuit behavior was simulated at several clock frequencies and
maintained a correct performance at frequencies superior to 250 MHz equivalent to 500 MHz in the
SET-FF’s. The dynamic circuit was also simulated at various clock frequencies and, using minimum-size
transistors, performed correctly at frequencies above 400 MHz. The operating frequency could be
increased by accurate scaling of the transistors.

In this paper, two new minimum CMOS circuits are proposed one static and the other dynamic, for
double-edge triggered flip-flops. The circuits have been designed specifically to reduce the number of
transistors, to maintain maximum excursion logic, to obtain high-frequency operations, and to offer a
good level of immunity to problems of metastability (static) and race (dynamic).

[6] In this paper, a special CMOS design methodology is used to implement a D-type double-edge-
triggered flip-flop (DET-FF). This D-type DET-FF offers speed and consumes no static power. A small price
is paid in the number of devices used to build a DET-FF. The same method of powering up and down a
cross-coupled latch with appropriate logic can be used to build other types of DET-FF’s (e.g., JK-type
DET-FF’s). Other logic can also be added to form flip-flops with set/reset functions.

[3] Problem Definition:-


From the comparative study of different SAR logic, a problem is that the complexity, power and delay
get increased. So there is a need to design a successive approximation register (SAR) having low optimal
delay and low power consumption by using double edge triggered D-flip flops (DETDFF).

[4] Proposed Work:-


Following are the proposed issues regarding the improvement in performance of SAR:-

4.1 Synchronous Clock.

The proposed design is fully synchronous with the clock and data input signals, a reduction in
propagation delay through the register is achieved when compared to asynchronous SAR designs.

4.2 Separate code register and sequence coder are replaced by a single row of flip flops.

In the proposed SAR design, a single row of D-type flip-flop is used in each bit cell which functions
both as sequencer and code register. This type of design is often referred to as the sequencer/code
register design.

4.3 Minimum number of Flip-flops.


In order to design a low power and high speed SAR, we have to make the use of minimum numbers
of flip flops in designing. So that delay and power get reduced.

4.4 Parallel data output.

We can take out the output in either serial way or parallel way but in case of serial output, delay
gets increased. A parallel output will increase the overall speed of operation. So we concentrate on
taking parallel output of the SAR.

4.5 To avoid the problem of clock skew.

As we are making the use of synchronous clock , the problem of clock skew will definitely occurs. In
the proposed SAR model, we try to minimize it by developing the appropriate logic for SAR.
4.6 Logic for SAR operation with minimum number of gates.

To implement the SAR logic we need several gates for implementation like AND and OR gates. Every
gate introduces some delay in the circuit and also consumes some power. So we need to design a SAR
logic which requires minimum number of gates which helps to reduce the delay and power
consumption.

4.7 To study different types of DETDFF and choose the efficient one. Several types of DETDFF are
available we need to select the best one by considering the low power consumption and high speed.

Generalized block diagram of Successive Approximation Register (SAR):-

[5] Proposed Methodology :


The probable time span required for the overall designing of SAR is as follows:

 For selection of efficient DETDFF --- 15 Days


 Development of SAR Logic --- 30 Days
 Selection of Tool --- 15 Days
 Implementation of DETDFF --- 15 Days
 To study different methodology of SAR --- 15 Days
 Implementation of SAR --- 30 Days
 Result verification and improvement --- 15 Days
[6] Tools Available: Following are the available tools for our designing:
 Microwind
 Xilinx
 Modelsim
 EDA Tools (H-Spice/T-Spice)
 Quartus II / Maxplus II
[7] Implications:
 As we are using D Flip flops, the power requirement for it is less as compared to other Flip flops.
 We are using double edge triggered Flip flops so the required clock period reduces to half and
we will certainly get the increase in speed of operation.
 The designing of SAR by using DETDFF and the effective logic will certainly improves the
performance of SAR in respect of speed and power consumption.
[8] References:-
[1] An improved Successive Approximation Register Design for use in A/D converter

By Howard T Russell, JR.,Member IEEE. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS

[2] Another design of the successive approximation register for A/D converter by C.K.YUEN.0018-
9219/79/0500-0873$00.75.

[3] A 6-bit, 1.2 GHz Interleaved SAR ADC in 90 nm CMOS. By Silvia Dondi, Davide Vecchi, Andrea Boni
Macro Bigi Dipartimento di Ingegneria dell'Informazione, University of Parma, Italy 1-4244-0157-
7/06/$20.00 C2006 IEEE

[4] Design of Low Power Double Edge Triggered DFFS.By Kaja Mohideen' and. J. Rajapaul Perinbam.IEEE
Indicon 2005 Conference Chennai India 11-13 Dec 2005

[5 ] Reduced Implementation of D-Type DET Flip-Flops By A. Gago, R. Escafio, and J. A. Hidalgo IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 28, NO. 3, MARCH 1993

[6] A Novel CMOS Implementation of Double-Edge-Triggered Flip-Flops SHIH-LIEN LU AND MILOS


ERCEGOVAC, MEMBER, IEEE IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 4, AUGUST 1990

[7] Behavior Analysis of CMOS D Flip-Flops By H Jonathan Chao, member, ieee, and cesar a Johnston

[8] Comparative Analysis of Master–Slave Latches and Flip-Flops for High-Performance and Low-Power
Systems, By Vladimir Stojanovic and Vojin G. Oklobdzija, Fellow, IEEE

[9] Timing Characterization of Dual-Edge Triggered Flip-Flop By Nikola Nedovic, Marko Aleksic and Vojin
G. Oklobdzija
[10] A Comparative Analysis of Low-Power Low-Voltage Dual-Edge-Triggered Flip-Flops By Wai Man
Chung and Manoj Sachdev Department of Electrical and Computer EngineeringUniversity of Waterloo,
Waterloo, Ontario, Canada N2L 3G1 Q-78Q3-5957-7/0Q/$18Q. 2Q000 0 IEEE

[11] Low-power single- and double-edge-triggered flip-flops for high-speed applications By S.H. Rasouli,
A. Khademzadeh, A. Afzali-Kusha and M. Nourani

[12] Design of an Ultra-Low Power Time Interleaved SAR Converter By Fabrizio Erario, Andrea Agnes,
Edoardo Bonizzoni, and Franco Maloberti , Department of Electronics ,University of Pavia

[13] B.Davari, R.Dannard and G.G.Shadi, "CMOS scaling for high performance and low power -the next
Ten years", Proc.IEEE, vol .83,Pp595-606, April1 1995.

[14] A Time-based Successive Approximation Register Analog-to-Digital Converter using a Pulse Width
Modulation Technique with a Single Capacitor by Young-Hwa Kim and SeongHwan Cho

[15] A Cmos Implimetation of a video-rate successive approximation A/D converterBy Keping Chen,
Christer Svensson and Ji-Ren Yuan LSI Design Center, IFM, Linkoping University

[16] Dual time interleaved successive approximation register ADC’s for an ultra wideband receiver. By
Brian P. Ginsburg, Student member, IEEE and Anantha P. Chandrakasan, fellow, IEEE.

[17] Dual Time-Interleaved Successive Approximation Register ADC’s for an Ultra- Wideband Receiver.
By, Brian P. Ginsburg, a student member,IEEE and Anantha P. Chandrakasanfellow, IEEE