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Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY • Surface mount
VDS (V) 200 • Low-profile through-hole
RDS(on) () VGS = 10 V 0.18 • Available in tape and reel Available
Qg max. (nC) 70 • Dynamic dV/dt rating
Qgs (nC) 13 • 150 °C operating temperature Available
ORDERING INFORMATION
Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) I2PAK (TO-262)
Lead (Pb)-free and Halogen-free SiHF640S-GE3 SiHF640STRL-GE3 a SiHF640STRR-GE3 a SiHF640L-GE3
Lead (Pb)-free IRF640SPbF IRF640STRLPbF a IRF640STRRPbF a -
Note
a. See device orientation.
7.0 V
6.0 V
2.0
(Normalized)
101 5.5 V
5.0 V
Bottom 4.5 V
1.5
1.0
100
4.5 V
0.5
20 µs Pulse Width
TC = 25 °C
0.0
10-1 100 101 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160
91037_01 VDS, Drain-to-Source Voltage (V) 91037_04 TJ, Junction Temperature (°C)
VGS 3000
VGS = 0 V, f = 1 MHz
Top 15 V Ciss = Cgs + Cgd, Cds Shorted
10 V 2500 Crss = Cgd
8.0 V Coss = Cds + Cgd
ID, Drain Current (A)
7.0 V
Capacitance (pF)
1000 Coss
100
500 Crss
20 µs Pulse Width
TC = 150 °C
0
10-1 100 101 100 101
91037_02 VDS, Drain-to-Source Voltage (V) 91037_05 VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TJ = 175 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
ID = 18 A
VGS, Gate-to-Source Voltage (V)
VDS = 160 V
150 °C 16
ID, Drain Current (A)
VDS = 40 V
12
25 °C
100 8
4
20 µs Pulse Width For test circuit
10-1 VDS = 50 V see figure 13
0
4 5 6 7 8 9 10 0 15 30 45 60 75
91037_03 VGS, Gate-to-Source Voltage (V) 91037_06 QG, Total Gate Charge (nC)
Fig. 3 - Typical Transfer Characteristics Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
20
ISD, Reverse Drain Current (A)
150 °C
16
4
100
VGS = 0 V
0
0.50 0.70 0.90 1.10 1.30 1.50 25 50 75 100 125 150
91037_07 VSD, Source-to-Drain Voltage (V) 91037_09 TC, Case Temperature (°C)
Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 9 - Maximum Drain Current vs. Case Temperature
RD
103 VDS
5
Operation in this area limited
by RDS(on)
VGS
2
D.U.T.
Rg
ID, Drain Current (A)
102 +
10 µs
5 - VDD
2 100 µs
10 V
10 Pulse width ≤ 1 µs
5 1 ms
Duty factor ≤ 0.1 %
2 10 ms
1 Fig. 10a - Switching Time Test Circuit
5 TC = 25 °C
2
TJ = 150 °C VDS
Single Pulse
0.1 90 %
2 5 2 5 2 5 2 5
0.1 1 10 102 103
10
Thermal Response (ZthJC)
1
0 − 0.5
0.2
0.1 0.1 PDM
0.05
0.02
0.01 Single Pulse t1
10-2 (Thermal Response) t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-3
10-5 10-4 10-3 10-2 0.1 1 10
15 V QG
10 V
VG
Rg D.U.T. +
- VDD
A
IAS
20 V Charge
tp 0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit Fig. 13a - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
VDS
tp 50 kΩ
12 V 0.2 µF
0.3 µF
+
VDS
D.U.T. -
VGS
IAS
3 mA
IG ID
Fig. 12b - Unclamped Inductive Waveforms Current sampling resistors
800
600
400
200
VDD = 50 V
0
25 50 75 100 125 150
- +
-
Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test
VGS = 10 Va
Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
Ripple ≤ 5 % ISD
Note
a. VGS = 5 V for logic level devices
A
2 x b2
2xb c
E
0.010 M A M B
± 0.004 M B
2xe
Base
5 metal D1
Plating 4
b1, b3
(c) c1 5
(b, b2)
Lead tip Section B - B and C - C E1 4
Scale: none View A - A
A
L1
Seating
D1
plane
D
C C
L2
B B L
A
c
3 x b2 E1
3xb A1 Section A - A
2xe Base
metal
Plating b1, b3
0.010 M A M B
c c1
(b, b2)
Lead tip
Section B - B and C - C
Scale: None
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