MEMS Technology

Signal Conditioning
ROCHESTER INSTITUTE OF TECHNOLOGY

MICROELECTRONIC ENGINEERING
Microelectromechanical Systems (MEMs)
Signal Conditioning
Dr. Lynn Fuller
Webpage: http://www.rit.edu/~lffeee
Microelectronic Engineering
Rochester Institute of Technology
82 Lomb Memorial Drive
Rochester, NY 14623-5604
Tel (585) 475-2035
Fax (585) 475-5041
Email: LFFEEE@rit.edu
Department webpage: http://www.microe.rit.edu

4-17-2007 mem_sigl.ppt
© April 17, 2007 Dr. Lynn Fuller Page 1
Signal Conditioning
SIGNAL CONDITIONING
Basic Resistive Bridge Circuits

CMOS Op Amp
Other Resistive Sensor Circuits
Basic Force Balance System
Technology
CMOS
Poly Gate PMOS
Metal Gate PMOS
Bipolar
Capacitive Sensors
Rotary Electrostatic Drives
Ink Jet Printer Driver


Signal Conditioning
BASIC RESISTIVE BRIDGE
Vsupply If R2 is identical to Rp2

but not on the flexible
diaphragm then
R1 Rp1 temperature changes in
Rp2 and R2 will by
cancelled. If Rp1 is also
Rp2 on the diaphragm then the
R2 Vout signal can be
Vout doubled. The Vsupply can
Piezoresistor Gnd be dc or ac. If ac at a
given frequency then
filters for that frequency
can reduce noise.


Signal Conditioning
PRESSURE SENSORS
Pressure Sensor with

Nitride Diaphragm
and Poly Piezo Resistors
over Bulk Etched Cavity
300 µm
Jason Trost, 1995
Harris Semiconductor
Mountaintop, PA

Signal Conditioning
RESISTIVE BRIDGE PRESSURE SENSOR
Vs
-Vout
Rp2
R2
R1
Gnd Rp1
+Vout
One design from Spring 2000
MEMs Class
Signal Conditioning
RESISTIVE BRIDGE AND DIFFERENTIAL

AMPLIFIER CIRCUIT
Vsupply
Rf
R1
Rin
- - Vo
+ Va +
Rp2 Rp1 Rin Rf
R2 Gnd
-
+ Vb
Gnd


Signal Conditioning
TEST SETUP
Buffer
Differential Amp Oscilloscope
Filter


Signal Conditioning
CALCULATION OF EXPECTED OUTPUT VOLTAGE
+5 Volts Vo2
The equation for stress at the center
edge of a square diaphragm (S.K.
R3 Clark and K.Wise, 1979)
R1
R4 Stress = 0.3 P(L/H)2 where P is
R2
pressure, L is length of diaphragm
edge, H is diaphragm thickness
Vo1 Gnd
R1 and R2 will increase in For a 3000µm opening on the back of
value while R3 and R4 will the wafer the diaphragm edge length L
decrease in value. is 3000 – 2 (500/Tan 53°) = 2246 µm

Signal Conditioning

(Cont.)
Stress = 0.3 P (L/H)2
If we apply vacuum to the back of the wafer that is equivalent to

and applied pressure of 14.7 psi or 103 N/m2
P = 103 N/m2
L= 2246 µm
Stress = 2.49E8 N/m2
H= 25 µm
Hooke’s Law: Stress = E Strain where E is Young’s Modulus
σ=Eε
Young’s Modulus of silicon is 1.9E11 N/m2
Thus the strain = 1.31E-3 or .131%

Signal Conditioning

(Cont.)
The sheet resistance (Rhos) from 4 point probe is 61 ohms/sq

The resistance is R = Rhos L/W
For a resistor R3 of L=350 µm and W=50 µm we find:
R3 = 61 (350/50) = 427.0 ohms
R3 and R2 decrease as W increases due to the strain
assume L is does not change, W’ becomes 50+50x0.131%
W’ = 50.0655 µm
R3’ = Rhos L/W’ = 61 (350/50.0655) = 426.4 ohms
R1 and R4 increase as L increases due to the strain
assume W does not change, L’ becomes 350 + 350x0.131%
R1’ = Rhos L’/W = 61 (350.459/50) = 427.6 ohms


Signal Conditioning

(Cont.)
5 Volts 5 Volts
No stress
Vo2-Vo1 = 0
R1=427 R3=427 R3=426.4
R1=427.6
Vo1=2.5v Vo2=2.5v
Vo1=2.4965v Vo2=2.5035v
R2=427 R4=427 R2=426.4 R4=427.6
With stress
Gnd Vo2-Vo1 = 0.007v
Gnd
=7 mV

Signal Conditioning
BUFFER / DIFFERENTIAL AMPLIFIER / FILTER
Vsupply
Rf
Rin
R1 R3 -
+ Va - Vo
+
Rin Rf
R2 R4
Gnd
-
+ Vb
Gnd Electronics Off-Chip

Signal Conditioning
VER2 OPERATIONAL AMPLIFIER

+V 10
M11
L/W M3 M4
8 80/20 2
20/40 20/40 M6
M10 3
80/20
7 20/30 M1 M2 20/30 20/30
5 4
M9
80/20
Vin- 1 Vin+ 9
M7
Vout
6
M5 20/40
20/40
M8 20/40
-V 20
p-well CMOS dimensions

L/W
Rochester Institute of Technology (µm/µm)

Signal Conditioning
OP AMP


§ P-WELL CMOS PROCESS -5v
§ 2.5 UM DESIGN RULES 3v
§ 8 DESIGN LEVELS
-4.5v
§ 11 PHOTOLITHOGRAPHY STEPS 2.5v -4v
2v -3.5v
§ PROCESS DETAILS
§ LOCOS
1.5v
VD
§ POLY GATE
§ SEPARATE NMOS AND PMOS VT ADJUST
§ TWO LAYER METAL
§ 76 STEPS TAKES ABOUT 4 WEEKS
PMOSFET
6000Å n+ Poly NMOSFET 3000Å CVD Ox
0.75 µm Aluminum
10,000Å Field Ox p+ p+ n+
p+ n+ n+
p-well field Vt adj 8e13

B11, 100KeV Bare p+ D/S 2e15, 150 KeV
BF2 thru gate oxide
n+ D/S 4e15, 100KeV Vt adj nmos 1.2e12, 60 KeV
P31 thru gate Oxide B11, 1000Å Kooi Vt adj pmos 1e11, 60 keV
Blanket, 1000Å Kooi
p-well 4e12, 50 keV, B11, 1123 C, 20 hr
CROSSECTION
n-type substrate 10 ohm-cm (100)
Signal Conditioning
LAYOUT FOR VERSION 1 AND 2 OP AMPS


Signal Conditioning
ZERO AND SPAN COMPENSATION

Rochester Institute of Technology Dr. Lynn Fuller 3/28/2007
Microelectronic Engineering Bridge_Balance.xls
Vs This spread sheet can be used to resistor values used to compensate a wheatstone bridge resistor pressure
sensor for output offset voltage and span. If we assume that the resistors are TaN thin film resistors that are
adjusted by laser trimming then the trimmed value has to be higher than the nominal value. First adjust the
Rst value of Rzt and Rzb to set Vout trimmed to zero. Then set Rst and Rsb to make the trimmed stressed value
Rzt equal to the specified output voltage at maximum applied pressure.
R1 R3 Vout Vout Vout Vout

Vsupply 10 volts no trim no trim trimmed trimmed
nominal stressed nominal stressed nominal stressed
Vo- Vo+ R1 500 501.5 Vo+ 5.012392 5.01979 5.008239 5.013157 volts
R2 500 498.5 Vo- 5 5.017719 5.008238 5.00353 volts
R2 R4 R3 495 493.515 Vo+ - Vo- 12.39234 2.070912 0.000561 9.626587 mV

R4 500 501.5
%change 0.3 when maximum pressure is applied (stressed)
Rzb
Rsb Rst
nominal trimmed
250 500 ohms
Rsb 250 500 ohms
Gnd Rzt 10000 10000 ohms

Rzb 10000 12658 ohms
no trim no trim trimmed trimmed

nominal stressed nominal stressed
Rleft 952.381 952.3806 957.1906 957.1627
Rright 995 995.015 995 995.015
Rtotal 986.6121 986.6155 1487.865 1487.861
Itotal 0.010136 0.010136 0.006721 0.006721
Vbridge 4.932152 4.93217 3.278958 3.278942
Ileft 0.005179 0.005179 0.003426 0.003426
Iright 0.004957 0.004957 0.003295 0.003295

Signal Conditioning
FLOW SENSORS
Heater
Resistor
Sensors
Flow

Signal Conditioning
FLOW SENSOR ELECTRONICS
Flow
R1
How would you connect
R1 and R2 to get an output
voltage proportional to flow?
Heater
How do you make sure the
input power is constant?
R2


Signal Conditioning
FLOW SENSOR ELECTRONICS
+6 Volts
10 OHM
R1
+
Vout
-
R2
Gnd
-6 Volts AD534
Vout near Zero so that Constant Power Circuit
it can be amplified

Signal Conditioning
CONSTANT TEMPERATURE CIRCUIT
+9 Volts
Setpoint +
1000
-
I
V +
Heater
Analog -
R=V/I Divider 10 Ω
Using
I -
AD534
+
MORE
Gnd

Signal Conditioning
BASIC FORCE BALANCE SYSTEM
Feedback
If Vo positive
Cc V2
C2 Measure C2
Mass - Vo
+
C1
Measure C1 V1
Cc
Feedback
If Vo negative

Signal Conditioning
CAPACITIVE READOUT FOR MEMS ACCELEROMETER


Signal Conditioning
BULK MICROMACHINED ACCELEROMETER


Signal Conditioning
CAPACITOR MICROPHONE
ALUMINUM DIAPHRAGM
1 µm Aluminum
2.0 µm Gap

Signal Conditioning
CONDENSER MICROPHONE
Vo
Vin Cx
If Cx is fixed Vo is zero. If
Cx changes there will be a
change in current and a
corresponding change in Vo


Signal Conditioning
INVERTER WITH HYSTERESIS

INVERTER WITH HYSTERESIS USING FOR RIT SUB-CMOS NMOSFET, Dr. Lynn Fuller, 1-15-2007
*LINE ABOVE IS TITLE
*START WIN SPICE AND ENTER LOCATION AND NAME OF INPUT FILE
*THIS FILE IS HYSTERESIS.TXT
*EXAMPLE: winspice> source c:/spice/Hysteresis.txt
*THE TRANSISTOR MODELS ARE IN THE FILE NAMED BELOW
.INCLUDE E:\SPICE\WINSPICE\RIT_MICROE_MODELS.TXT
*CIRCUIT DESCRIPTION
*VOLTAGE SOURCES
V1 1 0 DC 5
V2 2 0 DC 0
*TRANSISTORS
M1 7 2 0 0 RITSUBN49 L=2U W=16U ad=96e-12 as=96e-12 pd=44e-6 ps=44e-6 nrd=0.025 nrs=0.025
*RESISTORS
R1 1 3 10000
*REQUESTED ANALYSIS
.OP
.DC V2 5 0 -.1
*.DC V2 0 5 .1
.PLOT DC V(3)
.END


Signal Conditioning
INVERTER WITH HYSTERESIS

1
R=10K
Vout
3 Inverter with Hysteresis
M2
+ V1
- 5V M3 R
2 7
M1 Vout
V2=0-5 +
Or 5-0 - C

RC Oscillator

Signal Conditioning
RC OSCILLATOR, INVERTER WITH HYSTERESIS

1
M4 M5
3
M7 M8
+ M2 4
V1-
7
9V 2 M3
M1 M6
C1
All PMOS Realization

3.0pF
Signal Conditioning
CAPACITANCE TO VOLTAGE
Q = CV
Φ1
Cf
Φ1 Φ2
-
Vo
Vin +
Cx
Vo = - Vin Cx/Cf

Signal Conditioning
ANALOG SWITCHES
I
PMOS zero
Vt= -1
S D
V1 V2
D S
NMOS
Vt=+1
+5
For current flowing to the right (ie V1>V2) the PMOS transistor will be on if V1 is greater than the
threshold voltage, the NMOS transistor will be on if V2 is <4 volts. If we are charging up a
capacitor load at node 2 to 5 volts, initially current will flow through NMOS and PMOS but once V2
gets above 4 volts the NMOS will be off. If we are trying to charge up V2 to V1 = +1 volt the PMOS
will never be on. A complementary situation occurs for current flow to the left. Single transistor
switches can be used if we are sure the Vgs will be more than the threshold voltage for the specific
circuit application. (or use larger voltages on the gates)


Signal Conditioning
(+V to -V) ANALOG SWITCH WITH (0 to 5 V) CONTROL
S D
Vout
Vin D S
+V
0-5V Logic
Control
+5
-V

Signal Conditioning
TWO PHASE NON OVERLAPPING CLOCK
Synchronous circuits that use the two phase non

overlapping clock can separate input quantities from
output quantities used to calculate the results in
feedback systems such as the finite state machine.
Φ1
Φ2


Signal Conditioning
TWO-PHASE CLOCK GENERATORS

A B C R t2 R S Q
0 0 1
CLOCK
Q Φ1 0 0 Qn-1
0 1 0 t1 0 1 1
1 0 0 1 0 0
1 1 0 CLOCKBAR
t3
Φ2 1 1 INDETERMINATE
CLOCK
CLOCK
t1 t1
BAR
Φ1 t2
Φ2 t3
Rochester Institute of Technology =


Signal Conditioning
TRANSISTOR LEVEL SCHEMATIC OF 2 PHASE CLOCK
+V
Φ1 Φ2
Clock
+V


Signal Conditioning
LAYOUT OF TWO PHASE CLOCK


Signal Conditioning
TRANSISTOR LEVEL SCHEMATIC OF C TO V

+V
Φ1 Φ2
Clock +V 10
M11
+V 8
L/W
80/20
M3 M4
2
20/40 20/40 M6
M10 3
80/20
7 20/30 M1 M2 20/30 20/30
5 4
M9
80/20 Vin- 1 Vin+ 9
M7 Vout
6
M5 20/40
20/40
M8 20/40
-V 20
Microelectronic Engineering p-well CMOS dimensions
L/W
(µm/µm)
Signal Conditioning
CAPACITANCE TO CURRENT
+Vdd
Φ1 Φ2
I1 I2
C1 C2
I2-I1= Vdd f (C2-C1)

where f is the clock frequency

Signal Conditioning
LAYOUT OF CAPACITANCE TO CURRENT


Signal Conditioning
POLYSILICON DIAPHRAGM
200 µm
2 µm Poly
1.5 µm Gap

Signal Conditioning
SURFACE MICROMACHINED POLY DIAPHRAGM
30,000 Å SiO2 Si
Si
Si
Photolithography
Etch in BHF
Si Si Si
LPCVD 2.0 µmPoly Photolithography
Etch SiO2 in BHF
Etch Poly in SF6+ O2


Signal Conditioning
POLY DIAPHRAGM FIELD EFFECT TRANSISTOR

Vgate
2 µm n+ Poly Aluminum Plug
Vsource Vdrain
1 µm space
P+ P+
1000 Å Oxide
n-type silicon
Vgate
Vsource
15 µm Vdrain
Poly
75 µm
Diaphragm
Etch Holes
5x Contact Cut
to Poly Gate
Kerstin Babbitt, 1997
BSEE U of Rochester
Signal Conditioning
POLY GATE PMOSFET PRESSURE SENSOR
A B
Gate Drain Stop Source
150
µm
Add alignment marks

and squares in each
A’ B’ corner for each level
200, 400, 800 µm

Signal Conditioning
IC GRAPH LAYOUT
700 µm
8000 µm


Signal Conditioning
POLY DIAPHRAGM
5x
2.5 µm
25 µm


Signal Conditioning
POLY DIAPHRAGM PRESSURE SENSOR TEST

RESULTS
Pressure
No Pressure
An Pham – 1999

Signal Conditioning
POLY DIAPHARGM PRESSURE SENSOR PACKAGING
500 µm


Signal Conditioning
ALUMINUM DIAPHRAGM PRESSURE SENSOR
Source Diaphragm Insulator

Gate Contact
Drain
Si Wafer
Bottom
Plate
Air Gap (~1 atm)
Kerstin Babbitt - University of Rochester
Stephanie Bennett - Clarkson University
Sheila Kahwati - Syracuse University
An Pham - Rochester Institute of Technology

Signal Conditioning
ALUMINUM DIAPHRAGM PRESSURE SENSOR

Oscillator
2000 µm
Sensor 20/100 20/100 20/100 VDD= -10V
C sensor 40/20
5 to 25 pF VO R load
1 Meg
600/20 C load
20 pF
100/20 100/20 100/20
GND
C parasitic = 10pF
0 to 5 mm Hg Pressure Range

Signal Conditioning
RING OSCILLATOR
20/100 20/100 20/100 3

VDD= -10V
40/20
C sensor = 5 to 25 pF
2 4 9
VO
1
600/20
100/20 100/20 100/20

GND
R load C load
1 Meg 20 pF
C parasitic = 10pF
td = T/2N
T = period of oscillation
Microelectronic Engineering N = number of stages
Signal Conditioning
POLY GATE PMOS FOR RING OSCILLATOR
§ 10 UM DESIGN RULES
§ 4 DESIGN LEVELS
§ 4 PHOTOLITHOGRAPHY
STEPS
§ PROCESS DETAILS
§ n-TYPE SUBSTRATE
§ n+ POLY GATE
PMOSFET
§ PMOS VT=-2 VOLTS
§ ONE LAYER METAL 10,000Å Field Ox
p+ p+
§ 30 STEPS TAKES ABOUT 2
WEEKS
n-type substrate 10 ohm-cm (100)
Rochester Institute of Technology CROSSECTION


Signal Conditioning
READOUT ELECTRONICS
Square Wave RC Peak Detector

Generator Integrator
Voltage
LED Divider
Bar And
Display Comparators


Signal Conditioning
CIRCUIT SCHEMATIC


Signal Conditioning
ELECTROSTATIC ROTARY DRIVE
+V1
-V3 +V2 V1
-V2 +V3 V2
-V1 +V1 V3
-V3 +V2
-V2 +V3
-V1

Signal Conditioning
3 BIT ANALOG TO DIGITAL CONVERTER

8V +V Vin 3.5V Segment
0 Detector 0 Decoding Logic
+
7V -
+
0 0
-
6V
+
0 0
5V -
+
0 0
4V -
+
1 1
3V -
+
1 0
2V -
+
1 0
1V -
Comparators
22 0 21 1 20 1
Signal Conditioning
LAYOUT OF A TO D


Signal Conditioning
EMISSION SPECTROSCOPY
Light Emission Light

(Many λ) (Single λ)
Detector
Prism or Grating
Emission
Intensity
Wavelength, λ)

Signal Conditioning
MICRO-SPECTRO-PHOTOMETER
Analog Switches
Diffraction Grating Multiplexer
Shift Registers
1mm Glass
I/O Pads
128 Ion Implanted p+ diode

Photo Detectors
n-type silicon

Signal Conditioning
PHOTODIODE
space charge layer
+ +
B- B- B- p-type B- I
P+ B- B- B- P+
B- B-
-
-
+
P+
-
+ P+
+
P+
ε P+
-
+ P+
- - - -
electron P+ P+ P+ n-type P+
and hole -
pair P+ Phosphrous donor atom and electron
P+ Ionized Immobile Phosphrous donor atom
B- Ionized Immobile Boron acceptor atom
+
B- Boron acceptor atom and hole

Signal Conditioning
PHOTODIODE
V I
p
n I
I
No Light V
+
More Light
V
Most Light
-


Signal Conditioning
RESULTS OF FIRST TEST CHIP
Some Light
More Light
Photodiode Current vs Voltage Measurements from 128 diodes

illuminated through different
Microelectronic Engineering color filters
Signal Conditioning
MICRO-SPECTRO-PHOTOMETER ON CHIP
ELECTRONICS FOR ELECTRONIC READOUT
D1
D2
D3
128 PHOTODIODES
D4
D5
D6
D7
D8
Analog out
SWITCHES A A B B C C
A….G
7 BIT COUNTER Sync Sync pulse

(at 0000000B)
Clock
Reset

Signal Conditioning
POLY GATE PMOS + DEPLETION MODE IMPLANT

MULTIPLEXER
Reset
C Internal Rf
100 pF
-
+ - Vout
+
Ri
A
A’
7 B it Counter
B
B’
C
C’
D7 D0


Signal Conditioning
ANALOG AMPLIFIER ELECTRONICS
Reset
Internal
100 pF
C Rf
- -
+ Ri Analog Vout
+
Integrator and amplifier allow for measurement at low light levels


Signal Conditioning
T TYPE FILP-FLOP
R S Q
R Q
0 0 Qn-1
RS FLIP FLOP 0 1 1
QBAR 1 0 0
S
1 1 INDETERMINATE
TOGGEL FLIP FLOP
T Qn-1 Q
Q 0 0 0
T 0 1 1
1 0 1
QBAR 1 1 0
Q: TOGGELS HIGH AND LOW WITH EACH INPUT


Signal Conditioning
BINARY COUNTER USING T TYPE FLIP FLOPS
A State Table for Binary Counter
TA Present Next F-F

State State Inputs
A A TA TB TC
A B C B C
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
B 0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
TB 1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
B
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1
A A A
C BC 0 1 BC 0 1 BC 0 1
T Qn-1 Q 00 0 0 00 0 0 00 1 1
Input Tc
0 0 0
Pulses C 0 1 1 01 0 0 01 1 1 01 1 1
1 0 1 11 1 1
11 1 1 11 1 1
1 1 0
Rochester Institute of Technology TOGGEL FLIP FLOP 10 0 0 10 0 0 10 1 1
TA TB TC
Signal Conditioning
BINARY COUNTER WAVEFORMS
000 111
The binary counter has flip flops that change state in a binary count
sequence, that is: 000, 001, 010, 011, 100, 101, 110, 111, …

Signal Conditioning
SECOND TEST CHIP
Multiplexer
T Type FF
Binary Counter
Photodiodes


Signal Conditioning
REFERENCES
1. Introduction to VLSI Systems, Carver Mead and Lynn Conway,
Addison-Wesley Publishing Company, 1980.
2. Analog VLSI Design - nMOS and CMOS Malcomb R. Haskard
and Ian C. May, Prentice Hall Publishing Company.
3. Principles of CMOS VLSI Design - A Systems Perspecitive, Neil
Weste, and Kaman Eshraghian, Addison-Wesley Publishing Company,
1985.
4. CMOS Analog Circuit Design, Phillip E. Allen and Douglas R.
Holberg, Holt, Rinehart and Winston Publishers, 1987.
5. Analysis and Design of Analog Integrated Circuits, Paul R. Gray
and Robert G. Meyer, John Wiley and Sons Publishers, 1977.
6. Switched Capacitor Circuits, Phillip E. Allen and Edgar Sanchez-
Sinencio, Van Nostrand Reinhold Publishers, 1984.
7. Analog Devices Company, Norwood, MA,
http://www.analogdevices.com

Signal Conditioning
HOMEWORK - MEMS SIGNAL CONDITIONING
1. Derive an expression for Vo for the circuit on page 6 in terms of

all the resistors, V supply and other appropriate parameters.


MEMS Technology

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Signal Conditioning

ROCHESTER INSTITUTE OF TECHNOLOGY

Rochester Institute of Technology

Basic Resistive Bridge Circuits

Rochester Institute of Technology

© April 17, 2007 Dr. Lynn Fuller Page 2

BASIC RESISTIVE BRIDGE

Vsupply If R2 is identical to Rp2

Rochester Institute of Technology

© April 17, 2007 Dr. Lynn Fuller Page 3

Pressure Sensor with

© April 17, 2007 Dr. Lynn Fuller Page 4

RESISTIVE BRIDGE PRESSURE SENSOR

RESISTIVE BRIDGE AND DIFFERENTIAL

Rochester Institute of Technology

© April 17, 2007 Dr. Lynn Fuller Page 6

Rochester Institute of Technology

© April 17, 2007 Dr. Lynn Fuller Page 7

CALCULATION OF EXPECTED OUTPUT VOLTAGE

© April 17, 2007 Dr. Lynn Fuller Page 8

CALCULATION OF EXPECTED OUTPUT VOLTAGE

Stress = 0.3 P (L/H)2

If we apply vacuum to the back of the wafer that is equivalent to

© April 17, 2007 Dr. Lynn Fuller Page 9

CALCULATION OF EXPECTED OUTPUT VOLTAGE

The sheet resistance (Rhos) from 4 point probe is 61 ohms/sq

Rochester Institute of Technology

© April 17, 2007 Dr. Lynn Fuller Page 10

CALCULATION OF EXPECTED OUTPUT VOLTAGE

© April 17, 2007 Dr. Lynn Fuller Page 11

BUFFER / DIFFERENTIAL AMPLIFIER / FILTER

© April 17, 2007 Dr. Lynn Fuller Page 12

VER2 OPERATIONAL AMPLIFIER

p-well CMOS dimensions

© April 17, 2007 Dr. Lynn Fuller Page 13

Rochester Institute of Technology

© April 17, 2007 Dr. Lynn Fuller Page 14

p-well field Vt adj 8e13

LAYOUT FOR VERSION 1 AND 2 OP AMPS

Rochester Institute of Technology

© April 17, 2007 Dr. Lynn Fuller Page 16

ZERO AND SPAN COMPENSATION

R1 R3 Vout Vout Vout Vout

R2 R4 R3 495 493.515 Vo+ - Vo- 12.39234 2.070912 0.000561 9.626587 mV

Gnd Rzt 10000 10000 ohms

no trim no trim trimmed trimmed

© April 17, 2007 Dr. Lynn Fuller Page 17

© April 17, 2007 Dr. Lynn Fuller Page 18

FLOW SENSOR ELECTRONICS

Rochester Institute of Technology

© April 17, 2007 Dr. Lynn Fuller Page 19

FLOW SENSOR ELECTRONICS

© April 17, 2007 Dr. Lynn Fuller Page 20

CONSTANT TEMPERATURE CIRCUIT

© April 17, 2007 Dr. Lynn Fuller Page 21

BASIC FORCE BALANCE SYSTEM

© April 17, 2007 Dr. Lynn Fuller Page 22

CAPACITIVE READOUT FOR MEMS ACCELEROMETER

Rochester Institute of Technology

© April 17, 2007 Dr. Lynn Fuller Page 23

BULK MICROMACHINED ACCELEROMETER

Rochester Institute of Technology

© April 17, 2007 Dr. Lynn Fuller Page 24