EEEB273 Sem1 16/17 Gain Stage and Simple Output Stage

Chapter 11: (Part 4) BJT Multistage Amplifiers:

Gain Stage and Simple Output Stage
Multistage Operational Amplifier
 Input stage: BJT Diff-amp with three-transistor active load 
amplify difference between op amp inputs v1 and v2.
 Gain stage: Darlington pair  Provide additional gain to op amp.
 Output stage: Emitter-follower Minimise loading effect on output
signal

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EEEB273 Sem1 16/17 Gain Stage and Simple Output Stage

Input Stage:
 BJT diff-amp biased with Widlar current source (IQ)
IQ
 For balanced condition : I O  I B 5   (1   )

 From figure, IO is base current of Q6

I E6 IC7
I O  I B6  
(1   )  (1   )

So for IO = IB5, must have IC7 = IQ .Thus emitter resistors of Q10

and Q11 must be the same (i.e. R2 = R3)

NOTE:
 Q11  active load for the Darlington pair gain stage
 (Q8 + R4)  emitter-follower output stage  minimize loading
effect as its Ro is small.
 (Q7+Q11)  dc level shift by tweaking bias current IC7
Darlington Pair: Input Impedance (Ri) and Voltage Gain (Av=vo3/vb6)

 Rin of Darlington pair determines loading effect on basic diff-amp.

 RL7 : effective resistance between collector Q7 and signal ground.
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EEEB273 Sem1 16/17 Gain Stage and Simple Output Stage

Small-signal equivalent circuit of Darlington pair:

 KVL from B6 to E7
,
o where

o KCL at node E6 is

where

o Therefore

o This gives the input resistance of Darlington Pair:

o Assuming IC7 = IQ

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EEEB273 Sem1 16/17 Gain Stage and Simple Output Stage

o Therefore the input resistance is also

 The output voltage for the Darlington pair:

but

o Small-signal voltage gain of Darlington Pair:

o Substituting Ri,

o RL7 is the parallel combination of impedances at Q7 collector:

Ri looking into Q11’s collector (Rc11) and Ri looking into Q8’s
base (Rb8):

RL7
where
Rc11
Rb8

# Example 11.13
# Ex 11.13
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EEEB273 Sem1 16/17 Gain Stage and Simple Output Stage

Emitter follower: Output impedance

 Output resistance of emitter follower:
r Z 
RO  R4   8 
 (1   ) 

where Z is the impedance at the base of Q8,

Z=Rc11||Rc7

# Example 11.14
# Ex 11.14, TYU 11.18 &11.19

Overall Gain of Multistage Operational Amplifier:

 Input stage: Diff-amp with active load  AV1 ≈ 103
 Gain stage: Darlington pair  AV2 ≈ 103
 Output stage: Emitter-follower  AV3 ≈ 1

 AV = (AV1).(AV2).(AV3) ≈ 106
 typical low frequency, open loop gain of op amp.

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EEEB273 Sem1 16/17 Gain Stage and Simple Output Stage

Simplified BJT Operational Amplifier Circuit

 Multistage op-amp: input + gain + output

 Simplified: resistive loads

 Diff-amp : biased with Widlar current source.

 One-sided output of diff-amp connected to Darlington pair gain stage
 Bypass capacitor CE: increase small-signal voltage gain
 Output stage: emitter follower
 Dc level shifter between vO3 and output voltage vO
 Example 11.15: DC characteristics (Ex 11.15)
 Example 11.16: AC characteristics (Ex 11.16)

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EEEB273 Sem1 16/17 Gain Stage and Simple Output Stage

Example 11.15: DC characteristics

Neglect base currents, VBE(on) = 0.7V for all transistors except Q8 and Q9
in Widlar.
10  0.7  (10)
 Reference current I1: I1   1mA
19.3k
 Bias current IQ (from Widlar)
I 
I Q R2  VT ln  1   IQ = 0.4 mA
I 
 Q
 DC voltage at collector Q2
VO 2  10  I C 2 R2 , where IC1 = IC2 = 0.2 mA
 VO2 = 6V = Vcm(max)
 Common-mode input range: -8.6V ≤ Vcm ≤ 6V
o Vcm(min)= -10 + VBE8 + VBE1 (ignoring IQR2)

 DC voltage at collectors of Q3 and Q4

VO3  10  I R5 R5
o But IR5 ≈ IR4 (neglect base currents)
VO 2  2VBE (on)
o I R4  R4
 0.4mA

 VO3 = 8V: midway between 10V supply voltage and 6V

(VO2 )  maximum symmetrical swing for vO3

 DC voltage level shifting:

VB 6  VO3  VBE 5 (on)  I R 6 R6
o Where IR6 = IQ = 0.4 mA, since R3 = R2
 VB6 = 0.7V: Zero dc output at vO (emitter of Q6) for zero
differential-mode input voltage.
vO  (10)
 Current IR7: I R7   2mA
R7

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EEEB273 Sem1 16/17 Gain Stage and Simple Output Stage

Example 11.16: AC characteristics

Determine the small-signal differential-mode gain of the BJT op-amp
circuit. Given β=100 and VA = ∞.
 Overall differential-mode gain:
 v  v  v 
Ad  Ad 1. A2 . A3   o 2 . o3 . o 
 v1  v2   vo 2   vo3 
 valid if load resistance of following stages are considered
 Ri2 : input resistance to Darlington pair
 Ri3 : input resistance to output stage

 vo 2  g m
 Ad 1     RC || Ri 2 
 vd  2
o Ri 2  r 3  (1   )r 4
 r 4  VT / I R 4  (100)26m / 0.4m  6.5k
 r 3   VT / I R 4  (100) 26m / 0.4m  650k
2 2

 Ri 2  650  (101)(6.5)  1307k

IQ 0.4
g  
o m 2V 2(26m)  7.69mA / V
T

g 7.69m
 Ad 1  m RC || Ri 2   20k || 1307k   75.8
2 2
Since Ri2>>RC , no significant loading effect

 I R4 
 A2   R5 || Ri 3 
 2VT 
o Ri 3  r 5  (1   )[ R6  r 6  (1   ) R7 ]
 r 5  VT / I R6  (100)26m / 0.4m  6.5k
 r 6  VT / I R7  (100)26m / 2m  1.3k
 Ri 3  6.5  (101)[16.5  1.3  (101)5]  52.8M
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EEEB273 Sem1 16/17 Gain Stage and Simple Output Stage

Since Ri3>>R5 , no significant loading effect, so

I   0.4m 
A2   R 4 R5    5k  38.5
 2VT   2( 26 m) 

 Gain of emitter-follower output stage

v 
A3   o   1
 vo 3 

 The overall small-signal voltage gain is

Ad  Ad1. A2 . A3  (75.8)(38.5)(1)  2918

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