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THE CORDIC ALGORITHM March 16, 2018 THE CORDIC ALGORITHM March 16, 2018

OUTLINE
THE CORDIC ALGORITHM AND
• CORDIC algorithm:
CORDIC ARCHITECTURES
– Rotation and vectoring modes
• CORDIC architectures
Implementation of Digital Signal Processing
• Applications of CORDIC

Sabih H. Gerez
University of Twente

© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands

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REFERENCES WHAT IS CORDIC?

• Andraka, R., "A Survey of CORDIC Algorithms for FPGA-Based • CORDIC: abbreviation of coordinate rotation digital computer.
Computers", 6th International Symposium on Field • First publication by Volder, 1959.
Programmable Gate Arrays, Monterey, CA., pp. 191-200, • A method from the field of computer arithmetic allowing for the
(1998). efficient implementation of a wide range of computations.
• Loehning, M., T. Hentschel and G. Fettweis, "Digital Down
Conversion in Software Radio Terminals", 10th European
Signal Processing Conference, EUSIPCO 2000, pp. 1517-
1520, (2000).

© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands
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VECTOR ROTATIONS (1) VECTOR ROTATIONS (2)

• Consider a sequence of rotations of a vector • If , this means:
rotated by to give vector . • For an arbitrary angle , the angle can then be
decomposed as:
• So:

• After rewrite:
• Angles involved:
• If is chosen such that , with , 0 1 2 3 4 5 6 7 8
then the rotations can be executed without multiplications 1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256
except for initial factor [deg] 45.0 26.6 14.0 7.1 3.6 1.8 0.9 0.4 0.2
© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands

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VECTOR ROTATION EXAMPLE ANGLE ACCUMULATION

• The 8 subsequent rotations for a rotation of 15 degrees are: • Keep track of total rotation angle in an angle accumulator:

0 1 2 3 4 5 6 7 8
1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 1/256
45.0 26.6 14.0 7.1 3.6 1.8 0.9 0.4 0.2 • The angle accumulator can be used to determine :
1 -1 -1 1 1 -1 1 1 1
– Initialize .
45.0 18.4 4.4 11.5 15.1 13.3 14.2 14.7 14.9
– Factor becomes 1 when and -1 otherwise.
• The arctangent values can be precomputed and stored in a
look-up table (LUT), say .
• The depend on the required rotation angle.
© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands
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ROTATION-MODE CORDIC
CORDIC EQUATIONS SUMMARY
• Goal is to rotate vector • Final result:
• Original equations were: by angle .

• Initialization:
• Making use of the special values for the tangent, leaving out the • Where:
multiplication by the cosine and combining with angle
accumulation, one gets:

converges to 1.647.
• Conclusion: the result vector is
rotated but scaled version of
original vector.
© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands

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VECTORING-MODE CORDIC BASIC APPLICATIONS OF CORDIC

• Arctangent, vector-magnitude calculation and rectangular-to-
• Determine by an • Final result: polar conversion: direct result of vectoring-mode CORDIC.
alternative rule: • Polar-to-rectangular conversion, i.e. from to :
when – Set , 0 , and in rotation mode.
and when – Result will be cos , sin .
. – Correction for scaling by may be necessary (does not require a full-
fledged multiplier as is constant).
• Initialization: • This means that the initial
• Sine or cosine calculation:
vector has been rotated (and – See above, set 1/ . Then cos and sin .
scaled) onto the X-axis, while
the angle with the X-axis has
been computed as well.
© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands
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ARCHITECTURE ITERATIVE CORDIC UNROLLED ARCHITECTURE

• The iterative architecture requires one clock cycle per iteration.
• It requires a barrel shifter to shift operand over a variable
number of positions.

• One can also unroll the architecture to perform all operations in

a single clock cycle:
– Amounts to instantiate new hardware for each iteration.
– Possibly adding pipelining if the critical path becomes too long.
Controller should take care of – The barrel shifter is no longer necessary: each stage in the hardware has
a fixed shift which costs just wires.
initializations, add/subtract
– One could also unroll the architecture partially.
decisions, number of iterations, etc.
© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands

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DESIGN EXAMPLE: GFSK RECEIVER GFSK RECEIVER DESIGN APPROACH

• What is GFSK?
• Model entire system: transmitter, receiver, and a channel
– Gaussian frequency shift keying adding noise (AWGN).
– Method for digital transmission based on frequency • Leave out analog circuitry for upconversion to RF and
modulation (FM). downconversion back to IF.
– To transmit a 1 carrier frequency is slightly increased and to • Use IT++ to set up testbench.
transmit a 0 the frequency is slightly decreased (or vice
• The testbench computes bit error rates (BERs) for different
versa).
signal-to-noise ratios (SNRs).
– The transition steps are smoothed by a Gaussian filter.
• Goal is to preserve BER performance when designing
– Found in many standards: Bluetooth, DECT, Wavenis, … hardware.
– Proposed version uses parameters not related to any
standard.
© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands
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TVC

DUV
TB
Modulated signal has 16 samples per transmitted bit.
DUV = design under verification
TVC = test-vector controller; TB = testbench
© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands

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IMPLEMENTATION ASPECTS GFSK: MODULATION IN FORMULAE

• The modulated signal:
• Projects focus on designing in Arx.
• where:
• Testbenches for generated C++ and VHDL will be provided.
– is the constant amplitude
• As C++ and VHDL behave exactly the same, most simulations
– is the intermediate frequency (acts as carrier frequency)
will be done in C++ (simulation speed in e.g. BER simulations is
important). – is the phase deviation, derived from the bit stream
• C++ testbenches make use of IT++, an open-source library for • The phase deviation:
telecom/signal processing:
– http://itpp.sourceforge.net • where:
– It provides Matlab-style programming in C++, so vectors, – is the modulation index
matrices, etc. and lots of powerful functions to manipulate – is a Gaussian-filtered square wave
them. – is 1 for a transmitted 1 and -1 for a transmitted 0.
© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands
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DEMODULATOR BLOCK DIAGRAM CORDIC FOR DOWNCONVERSION (1)

• Digital downconversion is a common operation in digital radio
receivers. It is used to shift the carrier frequency of a radio
signal (e.g. from IF to baseband) or correct for frequency offset.
• This is done by multiplying an input signal by a sine and cosine
of some frequency. Think of the GFSK demodulator.

LPF DAM
The 16 samples per transmitted bit are first reduced
to 4 and later back to 1.

© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands

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CORDIC FOR DOWNCONVERSION (2) CORDIC FOR DOWNCONVERSION (3)

This solution requires just one
CORDIC.

Phase Loehning, et al.

accumulator Figure 1

This solution, requires

look-up table (LUT) Phase Loehning, et al.
and 2 multipliers. accumulator Figure 2

© Sabih H. Gerez, University of Twente, The Netherlands © Sabih H. Gerez, University of Twente, The Netherlands
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CORDIC FOR DOWNCONVERSION (4)

IMAGE REJECTION MIXER:
“complex” input with in-phase (I)
and quadrature (Q) component.
CORDIC replaces 4 multipliers!

Phase Loehning, et al.

accumulator Figure 4

© Sabih H. Gerez, University of Twente, The Netherlands