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Threshold Voltage Engineering of

GaN-based n-Channel and p-Channel


Heterostructure Field Effect Transistors

Von der Fakultät für Elektrotechnik und Informationstechnik


der Rheinisch-Westfälischen Technischen Hochschule Aachen
zur Erlangung des akademischen Grades eines Doktors
der Ingenieurwissenschaften genehmigte Dissertation

vorgelegt von

Dipl.-Ing. Herwig Hahn


aus Arnstadt

Berichter: Universitätsprofessor Dr.-Ing. Andrei Vescan


Universitätsprofessor Dr. Michael Uren

Tag der mündlichen Prüfung: 19.12.2014

Diese Dissertation ist auf den Internetseiten der Hochschulbibliothek online


verfügbar.
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D 82 (Diss. RWTH Aachen University, 2014)

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1. Auflage 2015
Abstract
Alternative materials are currently considered to replace Si in diverse areas of solid-
state electronics. One of these areas is power-switching. By increasing the ef-
ficiency of power-conversion systems, total energy consumption can be reduced.
While on the system level, efficiency can be enhanced by improving passive com-
ponents or circuits design, on the transistor level, it can be enhanced by new
device designs or the use of new semiconductor materials. Among such materials,
the group III nitrides (GaN, AlN, InN) are considered as suitable alternatives to Si.
These materials feature inherent polarisation effects (spontaneous and piezoelec-
tric). This polarisation can be engineered by changing the material composition,
i.e. by mixing the compounds to alloys (e.g. GaN and AlN to AlGaN). By growing
a nitride-based heterostructure in which a wider-bandgap material is deposited on
top of a narrower-bandgap material, a polarisation difference is typically present at
the material interface. This difference then leads to a fixed interface charge which
is compensated by the formation of a 2-D electron gas (2DEG). Within this 2DEG,
very sheet high carrier densities (up to 6×1013 cm−2 ) and large mobilities (above
2000 cm2 /Vs) are achievable. Together with the high electrical breakdown strength
of the material, the 2DEG is the cornerstone of the superiority of GaN heterostruc-
ture FETs (HFETs) over Si MOSFETs in terms of power-switching performance.
When it comes to fabricate circuits for power-switching, enhancement mode (e-
mode) behaviour of the power transistor is a necessity to enable fail-safe operation
and to allow for high efficiency of the circuit. However, due to the intrinsic pres-
ence of the 2DEG, GaN devices are typically of depletion type. Although different
approaches have been employed to render these devices e-mode, the single het-
erostructure limits the achievable threshold voltage (Vth ) to below +1 V. This value,
however, is not expected to be sufficient in a real-world application.
As solution for this fundamental problem, the single heterostructure is replaced
in this thesis by a double heterostructure in which at the backside of the GaN
channel another polarisation difference counteracts the one which is responsible
for forming the 2DEG. Moreover, a dielectric is used such that a metal-insulator-
semiconductor double hetero-structure FET (MIS-DHFET) is formed. These two
changes of the device structure allow for diverse approaches to be applied for achiev-
ing a high positive Vth . These different approaches are obtained on basis of a newly
derived electrostatic equation and the most effective ones in terms of shifting Vth are
analysed experimentally. The single steps to render GaN-based devices e-mode are
discussed separately. Hence, it is possible to optimise the approaches individually.
Impact on improved device performance and in particular on the Vth shift, as well
as possible drawbacks are investigated. With the optimised parameters for each
approach, a device which combines all of them is demonstrated, yielding a high
positive Vth of +2.3 V.
Despite the large effort to fabricate GaN-based devices for RF power amplification
and power-switching applications, the technology based on this material system is
limited to n-channel devices. p-Channel devices, on the contrary, have not been
targeted. Prior to the work discussed in this thesis, only two reports on p-channel
devices with very limited data have been published. Yet, by understanding the
working principle and by developing well-performing p-channel devices, numerous
fields of application not accessible to date would be materialised, thereunder digital
logic and voltage amplification under harsh environment. Also, for power-switching
applications, the gate driver could then be monolithically integrated on a single chip
with the power transistors.
In analogy with the n-channel part, for the first time, an electrostatic relation is
derived for a complex GaN-based heterostructure involving the presence of a 2-D
hole gas (2DHG). Based on the derived relation, means to form p-channel e-mode
devices are obtained. Prior to applying these approaches, the p-channel HFET is
subjected to optimisations of basic device properties. On basis of the optimised
devices, concepts which have already been employed for n-channel transistors are
analysed. The p-channel HFETs discussed demonstrate unprecedented perform-
ance. These devices also enable to gain a deeper insight into the proposed device
structure and physics by employing various characterisation methods not used
before for GaN-based p-channel HFETs.
In a final chapter, n- and p-channel devices are monolithically integrated on
a single wafer. By rendering both devices e-mode, the first demonstration of a
GaN-based digital inverter is presented.

4
Contents

1 Introduction 1

2 Fundamentals of Group III-Nitride Heterostructures 5


2.1 Crystal Structure . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Material Properties . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 The Two-Dimensional Electron Gas . . . . . . . . . . . . . . 9
2.4 The Heterostructure Field Effect Transistor . . . . . . . . . . 12
2.5 Limitations of HFETs and Projected Enhancements . . . . . . 14
2.5.1 Current Collapse . . . . . . . . . . . . . . . . . . . . . 14
2.5.2 Early Passivation . . . . . . . . . . . . . . . . . . . . . 17
2.5.3 Threshold Voltage Limit . . . . . . . . . . . . . . . . . 17
2.5.4 Enabling Higher Threshold Voltages . . . . . . . . . . 18

3 Engineering the Threshold Voltage in n-Channel Devices 21


3.1 Electrostatics of the MIS-DHFET . . . . . . . . . . . . . . . . 21
3.2 Approaches to Shift the Threshold Voltage . . . . . . . . . . . 26
3.3 Gate Recessing . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.3.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . 31
3.3.2 Pulsed I-V . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4 Influence of Gate Metallisation . . . . . . . . . . . . . . . . . 37
3.4.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . 37
3.4.2 Pulsed I-V . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.5 Influence of GaN Channel Thickness . . . . . . . . . . . . . . 40
3.5.1 Van der Pauw and Hall Characterisation . . . . . . . . 41
3.5.2 DC Characteristics . . . . . . . . . . . . . . . . . . . . 42
3.5.3 Pulsed I-V . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.6 Influence of Gate Insulation . . . . . . . . . . . . . . . . . . . 46
3.6.1 Aluminium Oxide Prepared by ALD . . . . . . . . . . . 47
3.6.2 Aluminium Oxide Prepared by Plasma-Oxidation . . . 55
3.6.3 Various Insulators Prepared by Plasma Oxidation . . . 61
3.7 Combination of Approaches . . . . . . . . . . . . . . . . . . . 67

4 GaN-based p-Channel Devices 75


4.1 The Two-Dimensional Hole Gas . . . . . . . . . . . . . . . . . 76
4.2 Optimisation of p-Channel Devices . . . . . . . . . . . . . . . 82
4.2.1 Epitaxial Layer Stack . . . . . . . . . . . . . . . . . . . 83
4.2.2 Ohmic Contact Formation . . . . . . . . . . . . . . . . 85
4.2.3 Gate Metallisation . . . . . . . . . . . . . . . . . . . . 85
4.2.4 Optimisation of Leakage Currents . . . . . . . . . . . . 88
4.3 Fabrication of Enhancement Mode p-Channel Devices . . . . 92
4.3.1 Gate Recess . . . . . . . . . . . . . . . . . . . . . . . . 93
4.3.2 Variation in Barrier Composition . . . . . . . . . . . . 96
4.4 p-Channel C-V, small signal and high temperature analysis . 101
4.4.1 C-V Analysis . . . . . . . . . . . . . . . . . . . . . . . 102
4.4.2 Small-Signal Characterisation . . . . . . . . . . . . . . 106
4.4.3 High-Temperature Analysis . . . . . . . . . . . . . . . 109

5 C-GaN digital inverter 117

6 Conclusion and Outlook 123

Appendix 127

References 134

List of Figures 159

List of Tables 166

Journal Publications of The Author 169

Conference Publications of The Author 173

Acknowledgments 177
1 Introduction
The ever increasing use of electronics together with the demand of increas-
ing speed and bandwidth and today’s awareness about saving energy reflect
some of the present challenges in solid-state electronics. A large part of
electronics is thereby based on one specific device. Since the invention of
the working principle of a field effect transistor (FET) in 1925-1933 ([1]–
[3] as cited in [4]) and the first experimental demonstration of a (point-
contact) transistor on the basis of Au contacts on Ge in 1947 ([5], [6] as
cited in [4]), the transistor has become one of the most versatile devices in
the electronic world. The breakthrough of the FET was based on Si and
the close-to-perfect interface to its native oxide SiO2 [7]. Whereas for a
long time, downscaling was an appropriate means to improve device per-
formance and to reduce parasitic losses, material properties such as the
small bandgap of only 1.12 eV and the moderate bulk electron mobility of
about 1000 cm2 /Vs of Si limit operational speed and efficiency of Si-based
devices. In several fields of application, this limitation can be overcome by
replacing Si with appropriate compound semiconductors. Whereas in the
field of digital logic applications, the III-V compound semiconductors and
Ge may replace Si as channel material [8], in the field of low-noise amplific-
ation (LNA) with increasing operation frequencies, the III-Vs do so already
[9], [10]. When it comes to RF power amplification (PA), wide-bandgap
semiconductors offer superior physical properties compared to Si.
GaN is such a wide-bandgap compound semiconductor. Beside its large
bandgap of 3.4 eV and its chemical stability, it also possesses very high
internal polarisation fields, typically a factor of ten above those of other
III-V semiconductors. The polarisation then allows for the accumulation
of a 2-D electron gas (2DEG) at a GaN-based heterointerface. This 2DEG
offers both high carrier density and high mobility. With these properties,
it is possible to fabricate depletion mode (d-mode) heterostructure FETs
(HFETs) which feature both high power densities (up to 40 W/mm [11])
and high operating voltages (typically 48 V [12]) in PA in the GHz range
[12.5 dB gain up to 60 GHz for a single-stage power amplifier ([13] as cited

1
1 Introduction

in [14])]. Hence, by replacing Si-based devices with those based on GaN e.g.
in base stations, buck-converters for supply voltage modulation become
unnecessary, eventually increasing the overall system efficiency [15].
The achievement of these technological benchmarks of GaN-based de-
vices has been driven by a large research effort. The latter also allowed
to gain a better understanding for this material. Recently, thrived by the
increasing number of renewable energy power stations and the overall En-
ergiewende, power-switching comes into focus. Again, the properties of
GaN-based heterostructures make the material a very attractive choice
for the fabrication of FETs for inverters or converters. However, whereas
the problems faced during PA research seem to be solved on an academic
basis, new challenges are encountered whilst designing GaN HFETs for
power-switching. For this type of application, a high breakdown voltage
(>600 V) and a low on-resistance are necessary. Owing to cost-constraints,
GaN growth needs to be performed on large-area Si substrates. Moreover,
enhancement mode (e-mode) behaviour with a sufficiently high threshold
voltage (Vth ) is a must when it comes to fail-safe operation and low circuit
complexity. To realise e-mode behaviour, several solutions have been pro-
posed. The first e-mode device has been realised in 1996 by employing
a very thin AlGaN barrier with very low Al-content [16]1 . Later, common
methods for the realisation have been based on fluorine implantation [18]–
[20], gate recessing [21]–[23] and the introduction of a backbarrier [22],
[24]. More recently, polarisation engineering has evolved as a possible
means to render GaN-based devices e-mode [25]–[28]. Yet, all methods
lack the suitability to obtain a Vth above +1 V.
To realise higher values of Vth , m-plane material featuring no internal po-
larisation across heterostructures has been employed [29], [30]. Also, the
use of a p-(Al,In)GaN gate has been proposed [24], [31]–[33]. Very recently,
positive threshold voltage shifts by the insertion of an insulator have been
investigated [34]–[36]. With the latter two concepts, proper device perform-
ance in combination with a high Vth have been achieved thus far. However,
whereas for the p-type gate approach, epitaxial growth is more complex
and the distribution of the electric field needs to be modulated by field
plates [37], for the latter approach, a stable Vth is one of the key challenges
[38], [39]. Moreover, there is a lack of understanding when it comes to

1
Already in 1995, e-mode behaviour has been claimed. Yet, within this publication, it has
been shown that almost 10% of the on-current was still flowing at 0 V gate voltage [17].

2
combine several approaches. Hence, in this thesis, a thorough study is
performed which comprises the combination of several concepts, which
are gate-recessing, polarisation-reduction, introduction of a backbarrier,
influence of gate metal and gate insulation. The focus is on the dynamic
performance and more importantly on the Vth shift obtained with each ap-
proach and with a combination of them.
Beside the power-switching application, GaN-based devices may also be
exploited in circuits based on a complementary design in harsh environ-
ments, such as for digital logic or for voltage amplification. Such circuits
employing GaN-based devices may be used at temperatures (up to 1000 ◦ C
[40]) or in ambients with ionising radiations not accessible to Si-based
metal-oxide-semiconductor FETs (MOSFETs). For the complementary cir-
cuits, p-channel devices are necessary. However, with this device type
being very new in GaN, there is a lack of understanding about p-channel
device physics. In a p-channel device, the majority carrier channel – a 2-D
hole gas (2DHG) – can be formed in analogy with the 2DEG in n-channel
devices by using a polarisation difference at a heterointerface. Hence, sim-
ilar carrier densities can be achieved, making it very attractive to fabricate
such devices.
So far, only a few publications have dealt with the presence of a 2DHG
[41]–[45] and even less have done so with p-channel HFETs [46]–[48]. Yet,
the device performance shown is far from being mature. Critical require-
ments such as low subthreshold swing, high on/off ratio and clear e-mode
behaviour are still lacking. Nevertheless, owing to the huge opportunities
which would be opened up by well-performing p-channel devices, there is
a large interest to improve and understand the limitation of device per-
formance. To fill this gap, p-channel devices in a double heterostructure
configuration are systematically developed and analysed in this thesis. Fi-
nally, the developed p-channel devices are integrated with their n-channel
counterparts to form a digital inverter.
The thesis is structured as follows. After a short discussion of theoretical
background in Sec. 2, the first results chapter deals with n-channel devices.
Starting with the electrostatic consideration of a possible device structure
(Sec. 3.1), single approaches to shift Vth are discussed: gate-recessing in
Sec. 3.3, the influence of the gate metallisation in Sec. 3.4, backbarrier in-
troduction in Sec. 3.5 and gate insulation in Sec. 3.6. The chapter closes
with Sec. 3.7, in which all design parameters are combined. The second
part again starts with electrostatic considerations in Sec. 4.1, this time

3
1 Introduction

regarding p-channel devices. Thereafter, the optimisation of p-channel


devices is discussed in Sec. 4.2 comprising ohmic and gate metallisation as
well as a discussion of leakage current. The fabrication of e-mode devices
is discussed in Sec. 4.3 by means of gate recessing and polarisation en-
gineering. The chapter closes with a more detailed investigation of the
fabricated devices in Sec. 4.4. In the closing Chap. 5, the integration of p-
and n-channel devices is discussed and a first digital inverter transfer char-
acteristics is shown. Finally, the results are summarised and an outlook
on open challenges is given.

4
2 Fundamentals of Group III-Nitride
Heterostructures
A brief introduction into the group III-nitride material system is provided in
this chapter. Based on the wurtzite crystal structure, material properties
of GaN and its related alloys are presented. The accumulation of carriers
at heterointerfaces is introduced and the electrostatic model necessary to
describe the density of a two-dimensional electron gas is derived. The
heterostructure field effect transistor (HFET) is introduced and the chapter
closes with a short overview of two limitations of GaN-based devices and
how they can be overcome.

2.1 Crystal Structure


GaN and its related alloys can be synthesised in various crystal structures,
which are the zinc blende, rock salt (both cubic) and wurtzite (hexagonal)
structure. To date, zinc blende structures are not of high relevance for elec-
tronic devices. However, owing to the high symmetry in a cubic structure,
reduced phonon scattering is to be expected, thus enabling high electron
or hole mobilities [49]. Additionally, without possessing any polarisation
in [001] direction and no spontaneous polarisation in [111] direction [50],
the zinc blende structure might be suited for application in light emitting
diodes (LED) preventing the quantum-confined Stark effect [51] or for fab-
rication of e-mode HFETs [52].
Today, the wurtzite crystal structure, depicted in Fig. 2.1, is of main
interest for electronic and optoelectronic applications. The basic lattice
parameters are a (in-plane) and c (out-of-plane). Epitaxial growth is typ-
ically performed along the c-axis. Taking a look at the figure, this crystal
structure consists of two hexagonal closed packages (hcp) which are shifted
by 5 /8 c along the c-axis [53]. The single hcp-crystal contains either metal
(Ga, Al and/or In) or N atoms. Each atom possesses a single bond to its

5
2 Fundamentals of Group III-Nitride Heterostructures

a [0001]

[1100]
[1120]

5 N
8 c
Ga, Al, In
c-plane

Figure 2.1: Crystal structure of group III-nitride material. Grey atoms indicate
metal species, while greenish atoms indicate nitrogen. The growth dir-
ection is [0001] [54].

first neighbouring atom of the other species in c-direction and three bonds
to its first neighbouring atoms in the basal plane [53]. Considering the
symmetry of such a wurtzite crystal, it is evident that no inversion centre
is present [53].
In anpideal wurtzite crystal, the lattice parameters c and a have a ratio
c/a = 8 /3 . Additionally and necessary to describe the bond lengths, the
internal cell parameter u is 3 /8 in the ideal case (this can be seen as the
shift of the two hcp) [53]. GaN and its related alloys do not show these
ideal values. Owing to the extremely high electronegativity of N, which is
3.04 and only higher for O, F and Cl [55], electrons tend to concentrate in
the vicinity of N atoms leading to a deformation of the crystal. This results
in values for c/a and u deviating from the aforementioned ideal ones [53].

2.2 Material Properties


The crystal structure described in the previous section leads to unique ma-
terial properties which are discussed in the following. With the aforemen-
tioned properties of no inversion centre present and high electronegativity
of N, a dipole arises in the group III-nitride base cell. As a consequence,
group III-nitrides feature strong polarisation effects in c-direction. These
effects are the spontaneous polarisation Psp and the piezoelectric polarisa-

6
2.2 Material Properties

tion Ppz . The former depends strongly and solely on the composition of
the group III-nitride material. Psp reaches a maximum value for AlN and a
minimum value for InGaN with about 40 % In content [53]. Ppz is mainly
influenced by changing the strain, which is the difference in the in-plane
lattice constant a of two different materials. However, the influence of a
given strain on Ppz also depends on the strained material [53].
To exploit the polarisation for electronic applications, it is necessary
to grow two different materials on top of each other, thereby forming a
heterojunction. By creating such a structure, a polarisation difference
arises at the interface. This difference in polarisation is employed in an
electronic device such as the HFET and its influence is described in the
next section.
A second property of the nitrides is the vast range of bandgaps (Eg ) ac-
cessible with them1 . InN features an Eg of about 0.65 eV - 0.675 eV [56],
[57], GaN of 3.4 eV [58] and AlN of 6.2 eV [59]. Furthermore, the effective
masses (m* ) of electrons differ for these materials. The values are 0.05·m0
[60], 0.19-0.22·m0 [61], [62], 0.33-0.35·m0 [61] for InN, GaN and AlN, re-
spectively. Hence, with the different Eg and m* , it is possible to engineer
high-frequency devices (low Eg , low m* ) e.g. for LNA and PA or high-voltage
devices e.g. for power-switching applications (high Eg , medium m* ).
The fabrication of high-frequency devices benefiting from a high mobility
(low m* ) is further motivated by obtaining a two-dimensional electron gas
(2DEG) in which ionised-impurity scattering is largely eliminated [63] and
thus even higher mobilities than achievable for bulk material are realised.
Further, the saturation velocity of electrons in GaN-based heterostructures
is predicted to be about 3×107 cm/s [64], [65] well above that of most other
semiconductors (except for InSb) [66].
High-voltage devices based on high-bandgap III-nitrides benefit not only
from a high breakdown strength of the material; the high bandgap of GaN
and/or Al(Ga)N also allows for the use of electronic devices in harsh envir-
onment, such as under high temperature. This represents a major advant-
age to Si which is still the most widely used material for power-switching
devices. Si with its small bandgap of 1.12 eV [67] becomes intrinsic already
at about 300 ◦ C. Moreover, the thermal conductivity of GaN and AlN at room
temperature with 2.3 W(cm K)−1 [68] and 2.85-3.40 W(cm K)−1 [69], [70], re-

1
This property allows for the complete visible spectra to be covered and has led to a huge
success of the group III-nitrides for optoelectronic applications.

7
2 Fundamentals of Group III-Nitride Heterostructures

spectively, is considerably higher than the one of Si with 1.5 W(cm K)−1
[71].
To express the suitability of GaN for power-switching applications in
actual numbers, Huang‘s figure of merit (HFOM) [72] can be utilised. It
represents a measure for describing the losses of a transistor for a given
breakdown voltage Vbd . HFOM can be simplified to the material figure of
merit (MFOM). MFOM is calculated by [73]

MFOM = Ebd µ

with Ebd being the electric breakdown field and µ the carrier mobility. Res-
ults for various materials and material systems are presented in Tab. 2.1.
It is obvious that the group III-nitrides outperform Si and even SiC by
far. Hence, it is very promising to fabricate GaN-based devices for power-
switching applications.

Table 2.1: Power-switching figure of merit for various materials and material sys-
tems. All values were taken from [74] except for the mobilities of the
AlGaN/GaN [75] and AlN/AlGaN system ([76] as cited in [77]).

Value Eg (MV/cm) µ (cm2 /(V·s)) MFOM


Si 0.3 1350 11
Bulk GaN 3.3 900 99
6H-SiC 2.4 370 46
Al0.2 Ga0.8 N/GaN 3.3 2000 148
AlN/Al0.8 Ga0.2 N 10.3 180 138

8
2.3 The Two-Dimensional Electron Gas

2.3 The Two-Dimensional Electron Gas


In this chapter, an analytical expression of the 2DEG density (ns ) is derived
on the basis of the charges present within a nitride-based heterostructure
and its associated band diagram2 . The derivation is performed here in
detail (in analogy to [78]) and serves as a fundament for later analyses of
more sophisticated device structures which then allow for specific device
designs. Hence, the most simple heterostructure consisting of barrier and
channel (or buffer) as shown in Fig. 2.2a is taken as basis. The following
boundary conditions are necessary for the calculation. First, the barrier
possesses a higher bandgap and a larger polarisation than the channel. It
is also assumed that the barrier is grown fully strained on top of the fully
relaxed channel. Second, electrons are accumulated at the heterointerface,
causing the conduction band EC to drop below the Fermi level EF . The
height of this drop is expressed by EF - EC = ∆ . Third, for the whole struc-
ture, the presence of n-type or p-type dopants is neglected. For the sake of
simplicity, the aforementioned spontaneous and piezoelectric polarisation
are now summed up to a single quantity. In the diagram shown in Fig. 2.2b,
the fixed charge resulting from the polarisation is then denoted with σ . The
actual conduction band diagram and electron concentration also shown in
this figure were simulated using TCAD Sentaurus [79].
To derive an expression for the 2DEG density, it is necessary to consider
charge densities at each interface as well as the structure of the conduction
band. It is assumed that the electric field is zero outside of the structure.
By applying Gauss’ Law, the following equations are obtained for the top
surface/barrier, the barrier/channel and the channel/bottom surface in-
terface, respectively [78],

ϸb Eb = σs1 − σb (2.1)

ϸch Ech − ϸb Eb = σb − σch − σn (2.2)

−ϸch Ech = σch − σs2 (2.3)

2
To obtain most accurate values for ns , Poisson and Schrödinger equations would need to
be solved self-consistently. However, since ns is set to zero at a later stage, the analysis
performed here is more than sufficient.

9
2 Fundamentals of Group III-Nitride Heterostructures

(a) (b)

Figure 2.2: (a) Simplest form a heterostructure and (b) associated conduction band
diagram obtained by using TCAD Sentaurus [79]. The electron concen-
tration in the 2DEG and fixed charge densities at interfaces are also
shown.

in which ϸ b and ϸ ch denote the permittivity of the barrier and channel


material, respectively. Eb and Ech each denote the electric field in the
barrier region and the channel region. Additionally, σ s1 and σ s2 correspond
to the surface charge at the top and bottom, respectively, while σ b , σ ch are
a result of the polarisation of the barrier and channel material, respectively.
σ n denotes the charge density resulting from the accumulation of the 2DEG.
Charge neutrality is ensured with

σs1 − σn − σs2 = 0 (2.4)

Moving along the conduction band edge from the surface to the right-
hand side of the quantum well, the following equation is derived:

ΦB,n ∆EC ∆
+ tb E b − + =0 (2.5)
e e e

10
2.3 The Two-Dimensional Electron Gas

Here, ΦB,n corresponds to the Schottky barrier height (or surface poten-
tial in a non-metallised case), e to the elementary charge, tb to the barrier
thickness, ∆EC to the conduction band offset between barrier and chan-
nel and ∆ to the depth of the quantum well. ∆ itself depends also on ns
and can be expressed using different simplifications, depending on how
many sub-bands in the quantum well are assumed to be occupied [53],
[80]. However, the approximation of only the first sub-band to be occupied
is sufficient here, since mainly Vth is of interest at the later stage of this
thesis. Also, the energy difference between the first sub-band and EF is
neglected. ∆ is then expressed as [80]

π ~2
∆= ns (2.6)
m∗

in which ~ is Planck’s constant and m* the effective mass of the elec-


trons in the channel. A second equation is obtained by moving along the
conduction band edge in the buffer,

Φ
tch Ech − =0 (2.7)
e

in which tch and Φch denote the channel region (or in the simplest case
the buffer) thickness and the backside potential at the lower boundary of
the channel region, respectively.
Further, Eq. 2.7 is solved for Ech and inserted into Eq. 2.2 which itself is
then solved for Eb . Hence, the following equation is obtained

1 ϸch 1 1
Eb = − (σb − σch − σn ) (2.8)
e tch ϸb ϸb

Finally, Eqs. 2.6 and 2.8 are inserted into Eq. 2.5 which is then solved
for ns leading to

1 ϸb 1 ϸch
1 σb − σch − e tb
(ΦB − ∆EC ) − e tch
Φ
ns = ϸb π ~2
(2.9)
e 1+ tb em ∗

11
2 Fundamentals of Group III-Nitride Heterostructures

Eq. 2.9 can be simplified by replacing the difference between σ b and σ ch


with a single term, the interface charge density at the barrier/channel
interface σ int . Additionally, ϸ index /tindex is substituted with the area-specific
capacitance Cindex . Thus, Eq. 2.9 turns to [78]
1 1
1 σint − e Cb (ΦB − ∆EC ) − e Cch Φ
ns = π~ 2
(2.10)
e 1 + Cb em ∗

Based on this equation, it is apparent that the 2DEG density ns not only
depends on the polarisation difference described in Sec. 2.2, but also on
the barrier capacitance, Schottky (or surface) barrier height, conduction
band offset and the channel region capacitance in relation to the backside
potential. Already at this stage, it shall be stated that the conduction band
offset itself has negligible influence in the semiconductor/semiconductor
heterostructure, since a change in ∆EC is directly reflected as a change in
ΦB,n and the sum of both changes will always be zero or below [81]. This
has an impact on engineering aspects discussed later.

2.4 The Heterostructure Field Effect Transistor


In the previous section, an expression for the 2DEG density has been de-
rived. The 2DEG with its high density and high mobility can be used in
a heterostructure field effect transistor (HFET). In contrast to the Si-based
MOSFET, the HFET has a slightly different structure. A schematic is shown
in Fig. 2.3. Two electrodes, source and drain, form ohmic contacts to the
2DEG and a single electrode, the gate, forms a Schottky contact. In con-
trast to the MOSFET, the gate in the HFET does not overlap the ohmic
contacts. This is possible due to the existence of the 2DEG even without
external bias. The 2DEG connects the intrinsic transistor (region under
the gate with the gate length Lg ) with the ohmic contacts. The region in
between is called access region and by modification of its lengths Lsg and
Lgd , a critical device parameter, the breakdown voltage (Vbd ) can be engin-
eered.
The working principle is similar to that of a MOSFET. By applying a
drain-source bias Vds , an electric field forces the electrons to move in the
channel and therefore, a current can flow from source to drain. This cur-
rent is called drain current. Employing a gate-source bias Vgs , the 2DEG

12
2.4 The Heterostructure Field Effect Transistor

Lg
Lsg Lgd
Source Gate Drain

AlGaN barrier tb
-------------------------------------------
2DEG
GaN buffer

Figure 2.3: Schematic of the simplest form of an HFET showing two alloyed ohmic
contacts source and drain and a Schottky contact as gate.

density beneath the gate is modified by the induced field effect, thus either
depleting or accumulating the 2DEG. As a consequence, the value of the
drain current Id can be modified.
Based on simulations using TCAD Sentaurus, the conduction band pos-
ition relative to the Fermi level for different Vgs is depicted in Fig. 2.4. With
positive Vgs , the conduction band moves into direction of the Fermi level.
Thus, the quantum well below the Fermi level is enlarged and the 2DEG is
accumulated. For negative Vgs , the conduction band is lifted with respect
to the Fermi level up to a point at which the quantum well diminishes. As
a consequence, there is no charge left in the channel. The voltage at which
the 2DEG is depleted is called the threshold voltage (Vth ). By integrating
the simulated carrier concentration n over the depth (from Fig. 2.4), the
sheet charge density ns is obtained. The values of ns for the given Vgs are
plotted in the inset of Fig. 2.4. The depicted curve is only a guide to the
eye.
HFETs can be described by using transfer and output characteristics
for which detailed descriptions can be found in [82]. A transfer character-
istic is shown in Fig. 3.5a on p. 33 and it is used to evaluate Vth and the
transconductance gm – a measure of the transistor’s ability to control the
channel – of the device. Output characteristics are used to evaluate cur-
rent saturation and the on-resistance Ron . Whereas the former is not in the
focus of this thesis, the latter will often be characterised under dynamic
conditions (see next section).

13
2 Fundamentals of Group III-Nitride Heterostructures

Figure 2.4: Simulated conduction band edges for different gate-source biases Vgs .
Also shown is the respective simulated distribution of electrons. In
the inset, the integral of the carrier concentration is plotted vs. the
gate-source bias Vgs .

2.5 Limitations of HFETs and Projected Enhancements


In the following section, limitations of GaN-based HFETs are discussed. In
detail, current collapse and the maximum positive threshold voltage Vth are
described and derived. Following this discussion, steps to prevent current
collapse and to enlarge Vth above the derived value are introduced.

2.5.1 Current Collapse


GaN-based devices have suffered from the so-called current collapse phe-
nomena ever since. These phenomena are partly related to the polarisation
effect inherent to the group III-nitride material. As indicated in Fig. 2.5a,
from an I-V characterisation point of perspective, current collapse describes

14
2.5 Limitations of HFETs and Projected Enhancements

S G D
Barrier
-------------------
GaN
buffer

Substrate
(a) (b)

Figure 2.5: (a) Dynamic characterisation showing the difference between a DC meas-
urement and pulsed IV measurements without bias and with applied
off-state stress. Current collapse is indicated by the increase in Ron .
(b) Illustration of possible trapping mechanisms at donor-type surface
states (yellow arrows) and in acceptor-type states in either the barrier
(black arrow) or the bulk (green arrows).

the reduction of drain current Id during dynamic biasing, that is when the
device is biased from an off-state bias point [here Vgs = -2 V, Vds = 50 V,
marked with pulsed (-2,50) in the figure] to on-state. This test condi-
tion emulates the condition under which a device would be working in
a power-switch configuration. As a result of the current reduction, an in-
crease from the on-resistance Ron of an unbiased measurement [Vgs = 0 V,
Vds = 0 V, marked with pulsed (0,0) in the figure] to the on-resistance Ron,dyn
of a biased measurements [pulsed (-2,50) in the figure] is observed and typ-
ically related to current collapse. This increase is expressed as the ratio of
Ron,dyn /Ron and it is desirable to obtain values very close to 1.
As illustrated in Fig. 2.5b, the origins of the current collapse are trapping
effects at the surface of the barrier (yellow arrows), in the bulk of the barrier
(black arrow) and in the buffer (green arrows). Since GaN devices can be
operated at high electric fields, electrons can gain sufficient energy to be

15
2 Fundamentals of Group III-Nitride Heterostructures

injected into deep-level acceptor-like traps (neutral when empty, negatively


charged when filled). The trapping in bulk and in the barrier is related to
impurities (and also to defects) in the crystal, independent of whether the
crystal is intentionally or unintentionally doped. Intentional doping using
C [83] or Fe [84] is often performed to enhance the breakdown voltage.
Both dopants also affect the dynamic behaviour of the device. For these
two dopants, a different influence on the suppression of Id has been shown
in [85]. C incorporation has been shown to produce severe drain current
reduction especially in the linear region. Hence, C causes a strong increase
in Ron . Furthermore, the emission time, which is the time the electron
needs to be emitted out of the trap, for C-doped material is very long [85].
Fe, on the other hand, has shown to have less effect on the dynamic Ron ,
although also a reduction in Id is present in the saturation region [85]. It
is noted that the material used within this thesis is either undoped (i.e.
unintentionally doped) or doped with Fe.
Beside bulk trapping and barrier trapping phenomena, surface trapping
(also called "virtual gate" effect [86]) is very strong in GaN-based devices.
This effect is related to the polarisation of the material, which leads to ion-
ised donor-type surface trap states (positively charged when empty, neutral
when filled). In these trap states, electrons can be captured, hence neut-
ralising the donor, but also depleting the channel. This phenomenon is
very strong for unpassivated devices. In 2000, Green et al. [87] have been
the first to use SiN on top of the barrier to passivate devices. With such a
passivation layer3 , a very large reduction in current collapse has been ob-
served. The application of a passivation layer has since then drawn a lot of
attention and has become a standard process step [80], [88]–[91]. A second
approach to minimise current collapse is to reduce the electric field at the
gate edge towards the drain. This can be performed by using (multiple) field
plates [92]. A third approach is to use an n-type doped GaN cap on top
of the barrier [93], [94], thus forming a GaN/AlGaN/GaN heterostructure.
This GaN cap provides a positive polarisation difference just beneath the
surface and therewith current collapse is reduced. Beside the application
of a GaN cap, the approach used during this thesis is to combine passiva-
tion and shaping of the electric field into a single step which is discussed
in the next section.

3
As the surface donor charge (+σ s2 ) is necessary for the presence of a 2DEG, the SiN layer
is actually no passivant (which would remove +σ s2 ), but an encapsulant.

16
2.5 Limitations of HFETs and Projected Enhancements

2.5.2 Early Passivation


The passivation-last approach introduced by Green et al. [87] has a severe
drawback. If gates are deposited on a bare surface, the gate has a trapezoidal
like appearance (as indicated in Fig. 2.5b) and hence, the angle at the gate
foot is typically sharp. Consequently, the electric field at the gate edge to-
wards the drain is very high, still allowing for very strong electron injection
into the donor-states at the SiN/III-nitride interface. As discussed earlier,
this effect can partly be circumvented by using field plates. However, the
solution used within this thesis is to deposit the passivation layer prior to
the gate deposition. An additional step, the gate-trench opening in the pas-
sivation layer, needs to be accepted. This opening is typically performed by
using a fluorine-based dry etch as has been discussed in [95]. With this
method, the gate foot can be shaped (indicated e.g. in Fig. 3.4a on p. 32)
in a way to reduce the peak electric field. In [96], by using simulations,
the reduction of the electric field at the gate edge has been shown to be
about 60 %. With this simple approach, a much improved dynamic beha-
viour has been observed [96]. The method used within this thesis has been
developed in [97].4

2.5.3 Threshold Voltage Limit


The electrostatics in an HFET define the value of the threshold voltage
Vth . This limit is derived in the following. To calculate Vth , Eq. 2.10 from
the previous section is reconsidered. In this equation, ns is set to zero.
As a consequence, the conduction band lies above the Fermi level. The
additional potential difference necessary to obtain ns = 0 corresponds to Vth .
Vth needs to be subtracted from ΦB,n . Hence, the following equation is
obtained

1 1
1 σint − e Cb [(ΦB − Vth ) − ∆EC ] − e Cch Φ
0= π~ 2
(2.11)
e 1 + Cb em ∗

which is then solved for Vth


4
It is noted that a similar process can be employed using SiN which is deposited in-situ during
MOCVD. Using this approach, the GaN surface is not exposed to air, hence preventing
oxidation of the same. In-situ SiN is thoroughly discussed in [54].

17
2 Fundamentals of Group III-Nitride Heterostructures

ΦB,n ∆EC σint Cch Φ


Vth = − − + . (2.12)
e e Cb Cb e

This equation can be simplified for the typical AlGaN/GaN heterostruc-


ture. Since GaN buffers are commonly grown very thick (usually 2 µm) to
improve the material quality and to reduce the dislocation density [98], Cch
is very small compared to Cb (typical barrier thicknesses are up to 30 nm)
and hence, Cch can be neglected5 . Finally, the equation is

ΦB,n ∆EC σint


Vth = − − . (2.13)
e e Cb

Based on this equation, it can be deduced that even in the case of σ int ≡ 0
(which can be achieved by polarisation matching [25]–[27], [99]), Vth cannot
be higher than the result of ΦB,n /e - ∆EC /e, a difference which typically
does not exceed 1 eV [77].

2.5.4 Enabling Higher Threshold Voltages


Based on the results of the last section, it is concluded that the fabrication
of GaN-based HFETs with a Vth above 1 V is not achievable by Schottky-
gated single heterostructures. A possible solution is to move towards the
AlN/AlGaN system which allows for higher differences in ΦB,n /e - ∆EC /e
as proposed in [77]. Another approach is to use a p-doped (Al,In)GaN
gate instead of a Schottky gate, allowing for higher effective barrier heights
[24], [31]–[33]. Here, ΦB,n is replaced by the diffusion potential of the p-n
junction.
The approach discussed within this thesis is to expand the simple HFET
structure to a more sophisticated structure. First, the HFET is modified
by the insertion of an insulator on top of the barrier (or GaN cap, respect-
ively). This offers the possibility to engineer the oxide/semiconductor inter-
face charge in a way in which a positive Vth is more easily obtained [100],
[101]. Second, below the GaN channel/buffer, another barrier is employed.
This barrier induces a negative polarisation charge density at the chan-
5
This assumption is only valid for structure in which doping which is compensating n-type
conductivity (such as Fe or C) is not applied close to the channel.

18
2.5 Limitations of HFETs and Projected Enhancements

nel/backbarrier interface, counteracting to the positive one at the upper


barrier/GaN interface. This leads to a confined 2DEG which is also easier
to deplete [22], [24], [102]. Based on the results of [102], a more positive
Vth should also be possible. With these two approaches, a new analytical
expression of Vth for this modified structure is derived. Based on the final
expression for Vth , approaches to engineer the band diagram are discussed.

19
3 Engineering the Threshold Voltage in
n-Channel Devices
In this chapter, electrostatic considerations, conclusions for e-mode device
design and experiments following these conclusions are presented. First,
based on a band diagram of a metal-insulator-semiconductor
double-heterostructure FET (MIS-DHFET), an equation is derived to form
an analytical correlation between the threshold voltage Vth and the hetero-
structure as well as device parameters which are accessible for engineering.
On the basis of this equation, individual approaches are compiled and dis-
cussed with their accompanying advantages and trade-offs. Thereafter,
experimental results and their consequences are discussed separately for
each approach. The final section of this chapter deals with the results of
a combination of the aspects considered before and proceeds towards a
device which could be used as power-switch in a real application.

3.1 Electrostatics of the MIS-DHFET


As discussed in the previous chapter, obtaining a threshold voltage in
GaN-based Schottky-gated single heterostructures higher than ΦB,n is im-
possible. Hence, the basic electrostatic consideration is expanded to a
structure which comprises also an insulator and a backbarrier together
with the corresponding interface charge densities. Based on this equation,
proper approaches to shift Vth are presented in the subsequent section.
The band diagram for a MIS-DHFET is depicted in Fig. 3.1. With the
oxide being introduced into the heterostructure, a new interface emerges,
which is the oxide/semiconductor interface. Many different terminologies
of charges present at this specific interface have been proposed in the liter-
ature [80], [100], [101], [103]. To keep consistency throughout this thesis,
the charges present at this interface are defined here in detail. It is re-
lated – in some degree – to the definition in [101]. First, we assume that

21
3 Engineering the Threshold Voltage in n-Channel Devices

Figure 3.1: Band diagram of a structure comprising insulator (oxide), cap, barrier,
channel and backbarrier. Electron distribution in the 2DEG and fixed
charge densities σ at the boundaries are shown.

ionised surface donors (positively charged) σ sd compensate for the negative


polarisation charge density (in this case -σ cap ) at the uppermost semicon-
ductor layer, as has also been shown in [100]. Now, with +σ sd - σ cap = 0,
we define the fixed interface charge density σ it (unit: per area) as the only
charge present at the oxide/semiconductor interface. In addition, we in-
troduce the fixed oxide charge density Nox (which contributes with a sheet
density calculated by 1 /2 Nox tox e for uniformly distributed Nox , unit: per
volume). Nox can considerably contribute to a conduction band shift. For
the rest of the structure, which is the cap, the barrier, the channel and the
backbarrier, polarisation charge densities are given with the correspond-
ing indexes. To have the same polarisation at the top and the bottom of
each layer, all layers are assumed to be grown fully strained on top of the
backbarrier which is relaxed1 . To obtain charge neutrality and zero field
outside the heterostructure, surface charges at the top and the bottom are
introduced2 .
The following six equations are obtained by applying Gauss’ Law for each
1
This is also a necessary condition to obtain epitaxial material of high quality [98].
2
It is additionally necessary that the valence band EV does not cross EF (not shown).

22
3.1 Electrostatics of the MIS-DHFET

single interface:

ϸox Eox = σs1 (3.1)

1
ϸcap Ecap − ϸox Eox = σit + /2 Nox tox e = P4 (3.2)

ϸb Eb − ϸcap Ecap = σcap − σb = P3 (3.3)

ϸch Ech − ϸb Eb = σb − σch − σn = P2 (3.4)

ϸbb Ebb − ϸch Ech = σch − σbb = P1 (3.5)

−ϸbb Ebb = σbb − σs2 (3.6)

in which ϸ index , Eindex and σ index are the relative permittivity, electric field
and polarisation charge density, respectively, for the different materials/regions
with the indexes ox for oxide, cap for GaN cap, b for barrier, ch for channel
and bb for backbarrier. In addition, tox denotes the oxide thickness and
σ n is equal to the charge density in the quantum well. To simplify the
equations, the charges present at single interfaces are lumped into a single
quantity. These quantities are denoted by P1 , P2 , P3 and P4 for the back-
barrier/channel interface, the channel/barrier interface, the barrier/cap
interface and the cap/oxide interface, respectively.
Charge neutrality is ensured with

1
σs1 + Nox tox e + σit + σsd − σn − σs2 = 0 (3.7)
2

in which σ s1 and σ s2 are the top and bottom surface charge densities.
By moving along the conduction band edge, the following two equations
are obtained. While the first equation reflects the movement from surface
to just below the quantum well, the second equation is obtained by moving
from the lower edge of the quantum well down to the bottom of the structure

23
3 Engineering the Threshold Voltage in n-Channel Devices

ΦB,MIS ∆EC,MIS ∆
+ tox Eox − + tcap Ecap + tb Eb + =0 (3.8)
e e e

∆EC,bb Φ
tch Ech + + tbb Ebb − =0 (3.9)
e e

In Eq. 3.8, ΦB,MIS , ∆EC,MIS and ∆ denote the metal-oxide barrier height,
the oxide-semiconductor conduction band offset and the depth of the quantum
well, respectively. The thicknesses of the layers are given by tindex with the
indexes mentioned before. In Eq. 3.9, ∆EC,bb and Φ correspond to the
conduction band offset between channel and backbarrier and the backside
potential, respectively.
With this set of equations, an expression for Vth is derived. First, Eq. 3.5
is rearranged to

ϸbb Ebb = P1 + ϸch Ech (3.10)

and inserted into Eq. 3.9. This yields the following equation:

∆EC,bb tbb Φ
tch Ech + + (P1 + ϸch Ech ) − =0 (3.11)
e ϸbb e

which then is rearranged to

Φ ∆EC,bb tbb
e
− e
− P
ϸbb 1
ϸch Ech = tch tbb
ϸch
+ ϸbb
1 1
e
(Φ − ∆EC,bb ) − P
Cbb 1
= 1 1
(3.12)
Cch
+ Cbb
Cbb
e
(Φ − ∆EC,bb ) − P1
= Cbb
.
1+ Cch

Eq. 3.12 can now be used to obtain new expressions for Eqs. 3.2 - 3.4.

24
3.1 Electrostatics of the MIS-DHFET

Cbb
e
(Φ − ∆EC,bb ) − P1
ϸb Eb = ϸch Ech − P2 = Cbb
− P2 (3.13)
1+ Cch

Cbb
e
(Φ − ∆EC,bb ) − P1
ϸcap Ecap = ϸb Eb − P3 = Cbb
− P2 − P3 (3.14)
1+ Cch

Cbb
e
(Φ − ∆EC,bb ) − P1
ϸox Eox = ϸcap Ecap − P4 = Cbb
− P2 − P3 − P4 (3.15)
1+ Cch

Cbb
(Φ−∆EC,bb )−P1
In the following, e
C is substituted by ζ . The insertion of Eqs. 3.13 –
1+ Cbb
ch
3.15 into Eq. 3.8 then leads to the following expression:

ΦB,MIS ∆EC,MIS 1 1
− + ( ζ − P2 ) + ( ζ − P2 − P3 )
e e Cox Ccap
1 ∆
+ ( ζ − P2 − P3 − P4 ) + = 0. (3.16)
Cb e

To derive an equation for Vth , σ n (in P2 ) and ∆ are set to zero (ns = 0) and
ΦB,MIS is replaced by ΦB,MIS - eVth . The equation for Vth is then

ΦB,MIS ∆EC,MIS 1
Vth = − + ( ζ − P2 )
e e Cb
1 1
+ ( ζ − P2 − P3 ) + (ζ − P2 − P3 − P4 ). (3.17)
Ccap Cox

ζ is resubstituted and the resulting equation is solved for Vth giving the
following expression

25
3 Engineering the Threshold Voltage in n-Channel Devices

ΦB,MIS ∆EC,MIS
Vth = −
e e
Cbb
1 1 1 e
(Φ − ∆EC,bb )
+( + + )· Cbb
Cb Ccap Cox 1+ Cch
1 1 1 P1
−( + + ) Cbb
Cb Ccap Cox 1 +
Cch (3.18)
1 1 1
−( + + ) P2
Cb Ccap Cox
1 1
−( + ) P3
Ccap Cox
1
− P4 .
Cox

Compared to the equation of Vth for a Schottky-gated single heterostruc-


ture (cf. Eq. 2.13 on p. 18), there is not much similarity left. To obtain a
high positive Vth , several approaches are offered by each term in Eq. 3.18.
These approaches are discussed in the next section.

3.2 Approaches to Shift the Threshold Voltage


In the last section, a comprehensive equation has been derived which de-
scribes Vth as a function of all available design parameters. This equation
can be used to analyse the possible approaches to shift Vth well into the pos-
itive range. In the following, each line of Eq. 3.18 is discussed separately
and graphs are used to illustrate the effect for a few cases. The basic struc-
ture for the following discussion with layer thicknesses and compositions
is depicted in Fig. 3.2a. Both default parameter and parameter variations
are also given in the figure.
First, the term ΦB,MIS - ∆EC,MIS may be maximised by a careful choice of
gate metal and insulator. By replacing Ni which is typically used as gate
electrode [25]–[27], [95], [99], [104] with Pt, a shift of about +0.5 V could
be possible. For this aspect, an experimental investigation is performed
in Sec. 3.4. For modifications of ∆EC,MIS , refer to [105]. There, differences
in ΦB,MIS - ∆EC,MIS up to 0.5 V by the choice of the insulator material have

26
3.2 Approaches to Shift the Threshold Voltage

(a) (b)

Figure 3.2: (a) Schematic of the basic structure for which critical layers are varied
as indicated. (b) Positive Vth shifts obtained by employing backbar-
riers with different compositions in dependence on the GaN channel
thickness. Dotted line indicates the reference point which is when no
backbarrier is used. Dashed line indicates a negative shift which is
unavoidable and which is related to the barrier.

been shown and discussed. However, the preferred choice, which would
then be SiN, does not feature sufficient conduction band offset to GaN to
offer promising insulating properties. In this thesis, the optimisation of the
sum is not discussed.
For each, the second, the third and the fourth line, the sum of Cb , Ccap
and Cox is appearing. For σ it = Nox = 0, maximisation of these terms will lead
to a more positive Vth for typical device structures3 . This maximisation can
be achieved by reducing the thickness of the barrier, thereby increasing Cb .
This can be performed by a gate recess, thus affecting only the intrinsic
device. This measure is discussed in Sec. 3.3.
In the second line, an additive term (positive Vth shift) is shown which is
independent of polarisation charge. By increasing this term, Vth increases
as well. The only possibility to increase this term is to increase Cbb while
3
Typical here means that the value of P2 is at least as large as P1 . In most cases, it is
considerably larger.

27
3 Engineering the Threshold Voltage in n-Channel Devices

at the same time increasing Cch , a means which leads to a poor quality
of the epitaxial layer stack and in a low mobility of the electrons in the
2DEG [106]. In addition, typical values for this term are below 0.1 V (for
Cch >> Cbb ). Hence, this term is not contributing strongly to a positive Vth .
For an estimation of the effect of the third line, the sign of P1 needs to
be known. In the case of the GaN channel on top of an AlGaN backbarrier,
P1 is negative as the polarisation of the backbarrier is higher than the one
of the channel. Hence, the term as such is additive (positive Vth shift) and
can be maximised by increasing P1 . This can be realised by growing a high
Al content backbarrier as is indicated in Fig. 3.2b. For higher Al content
backbarriers, higher positive Vth are expected. However, to gain full benefit
which is a maximum shift in Vth of such high Al content backbarrier, one
has to scale down the channel thickness with increasing Al content (cf.
Fig. 3.2b). In reality, however, such high Al content backbarriers so far
have rarely been presented. One issue is the possible 2DHG formation
as discussed in [107]. Another big challenge is the successful growth
of a thick high-quality high Al content backbarrier. Furthermore, such
backbarriers would additionally deplete the channel in the access region
and thus cause the on-resistance to increase. Here, measures such as
graded barrier would be necessary to circumvent this effect [27]. The effect
of a Vth shift with increasing Al concentration in the backbarrier has been
shown experimentally up to an Al content of 10 % [108]. In this thesis,
the experimental evaluation of the channel thickness influence on Vth for a
given backbarrier with 7 % Al is performed in Sec. 3.5.
The fourth line is the typical barrier depletion term also present in the
HFET-Eq. 2.13 on p. 18. It causes a negative Vth shift which is as high as in-
dicated in Fig. 3.2b by the dashed line. The difference P2 can be minimised
by reducing the Al content in the barrier or by performing polarisation-
matching [25]–[27], [99]. However, the trade-off of increasing the access
resistance needs to be considered.
The fifth line which regards the effect of the barrier/GaN cap interface
(as also Cox is present in this term, the total sum of GaN cap and oxide
thickness is given4 ) is illustrated in Fig. 3.3a for different backbarrier com-
positions. If no backbarrier is present, the GaN cap cannot change Vth
(for σ it = 0), independent of its thickness. As a backbarrier is introduced, a

4
The effect of the oxide thickness is only valid if a GaN cap is present. If no GaN cap is
present, the addition of an oxide leads to a more negative Vth (for σ it = 0) [109].

28
3.2 Approaches to Shift the Threshold Voltage

(a) (b)

Figure 3.3: (a) Changes in Vth vs. the total thickness of GaN cap and oxide plotted
for different backbarrier compositions and GaN buffer. (b) Changes in
Vth for different fixed interface charge and fixed bulk oxide charge dens-
ities. The reference is plotted for a charge-free interface (no backbarrier
present).

considerable shift of Vth is apparent by the presence of the GaN cap. This
is caused by the negative polarisation difference P3 at the GaN cap/barrier
interface. However, one cannot grow the GaN cap too thick as at a given
point the valence band EV can cross the Fermi level [110] (similar to the
case of the backbarrier as discussed above). At this point, a 2DHG would
be formed, effectively hindering the modulation of the 2DEG as discussed
vice versa in [111].
The effect of the sixth line is illustrated in Fig. 3.3b for different nit
(nit = σ it /e) and in dependence on tox . As is shown, very large differences
in Vth can be obtained by the control of nit . By providing a net negative
charge P4 (due to negative nit ), this term adds to Vth . As indicated for the
case of nit = 0, the presence of Nox would cause a parabolic behaviour of
Vth , with positive charge leading to concave function (dotted) and negative
charge leading to a convex function (dashed). The presence of nit and Nox
is discussed in Sec. 3.6.
Hence, out of the six possible approaches presented, experimental res-

29
3 Engineering the Threshold Voltage in n-Channel Devices

ults of four are individually discussed in the following sections: gate re-
cessing (increasing Cb ), work function engineering (increasing ΦB,MIS ), in-
troduction of the backbarrier (obtaining a negative P1 ) and the application
of a gate insulator (obtaining a negative nit ).
Before closing this section, a very important point needs to be noted. As
has been discussed earlier, the application of an oxide on top of the GaN
cap would lead to a positive Vth shift. If a gate recess is applied prior to
oxide deposition, the oxide would be placed on top of the barrier. For this
case with nit = 0, the oxide would lead to a more negative Vth (as would do
a thicker barrier), counterbalancing the effect of a gate recess. This effect
is investigated in Sec. 3.7.

3.3 Gate Recessing


In this chapter, the effect of gate recessing on device characteristics is de-
scribed. As shown in the previous section, a gate recess should lead to
a more positive Vth . This is a result of an increased gate-channel capacit-
ance Cg-ch (the sum of Cox , Ccap and Cb from a more general point of view).
Already in 1997, gate recessing has shown to be a proper means [112]. In
2002, the first e-mode device with a Vth of 0 V has been realised by gate re-
cessing [113] and since then, this approach has often been used to fabricate
such devices. However, general observations show that the recess process
itself increases the surface roughness [114] or that it introduces damage
into the barrier [115], both possibly causing a drop in electron mobility µn
in the 2DEG5 . Also, the "dead-time" – the time at the beginning of an etch
process with zero etch rate – typically observed during dry etching of GaN
[116] distorts the determination of exact etch rates and hence, aiming for
a precise etch depth necessary for gate recessing is nearly impossible.
The effect on surface roughness, the damage and the inaccuracy in the
etch rate determination can be minimised by applying a new technique in
which the barrier layer is intentionally oxidised and the resulting oxide is
removed subsequently. By applying appropriate conditions, these oxida-
tion and oxide removal process steps can be performed even for only a few
atomic monolayers of the barrier material. This technique has been intro-
duced by Burnham et al. for the first time in 2010 [117]. However, the
5
Also, an increase in gate leakage current may be expected for a thinner barrier. This effect
is likely to be worse for processes which cause severe damage to the barrier.

30
3.3 Gate Recessing

process has been performed with a reactive-ion etch (RIE) tool, in which
the control of the plasma density and the ion energy cannot be separated.
Thus, non-optimal etch results were to be expected. To improve this situ-
ation and to demonstrate the full potential of the process, it is transferred
to an inductively coupled plasma-RIE (ICP-RIE) tool [104]. In an ICP-RIE
tool, it is possible to obtain a high-density plasma with at the same time
low DC bias values, leading to a rather soft bombardment of the surface.
This allows to reduce the damage introduced into the barrier.
This so-called digital etch process first oxidises a few monolayers of the
nitride-based material via an oxygen-plasma. Subsequently, the resulting
oxide is removed via a BCl3 plasma etch step. Both steps together are called
cycle. The optimisation of this etch process can be found in the appendix
on pp. 127– 130. In the following, the performance of HFETs which were
gate-recessed using the digital etch technique is discussed.

3.3.1 DC Characteristics
To evaluate the digital etch process when applied to HFETs, it was utilised
to fabricate e-mode devices with a deep gate recess [104]. The epitaxial
structure used was commercial material provided by Nitronex Corp. The
layer stack on a Si substrate consists of a step-graded AlGaN/AlN trans-
ition layer on which a 1.5 µm GaN buffer was grown. On top of the buffer,
an approx. 15 nm thick Al0.26 Ga0.74 N barrier with 2 nm GaN cap has been
deposited. Three samples were fabricated for this series. After ohmic con-
tact formation using alloyed Ti/Al/Ni/Au stacks, SiN was deposited via a
plasma-enhanced chemical vapour deposition (PECVD) process. By means
of van der Pauw measurements, a sheet resistance Rsh of 440 Ω/sq. has
been extracted for the passivated access region. The gate trenches were
opened with a fluorine-based dry etch process [95], [97], [118]. Using the
remaining SiN as hard mask, the gate recess was performed with the optim-
ised digital etch process. One sample was etched with six cycles (sample
name DE06), whereas a second sample was etched with ten cycles (sample
name DE10). A reference sample without gate recess was also processed
(sample name DE00). On all samples, Ni/Au gate electrodes were formed
by means of electron beam evaporation. To improve the Ni/barrier inter-
face and to reduce forward gate leakage currents [119], [120], an annealing
step under N2 was performed for 10 min at 400 ◦ C. After the pad metal-
lisation, a chlorine-based dry etch was employed for mesa isolation. The

31
3 Engineering the Threshold Voltage in n-Channel Devices

(a) (b) (c)

Figure 3.4: Schematic cross sections for the devices of the recessed gate series
for (a) the reference sample without recessed gate and the samples for
which (b) 6 and (c) 10 cycles of the digital recess etch were applied.

final device structures for sample DE00, DE06 and DE10 are depicted in
Fig. 3.4.
The gate-channel separation tg-ch is extracted from the gate capacitance
determined by C-V measurements at ns = 3×1012 cm−2 . tg-ch is calculated
to be 17.6 nm and 11.2 nm for samples DE00 and DE06, respectively. Ow-
ing to high gate leakage current in forward direction, a reliable extraction
of gate capacitance values has not been possible for sample DE10. How-
ever, by assuming a constant etch rate per cycle [117], the extrapolation
of the first two results yields a remaining tg-ch of about 7.1 nm. Taking an
interface-channel separation ∆ of about 4 nm at the given ns into account
[121], the remaining barrier thicknesses are 13.6 nm, 7.2 nm and 3.1 nm
for samples DE00, DE06 and DE10, respectively. The value for sample
DE00 is slightly smaller than the nominal value of the epitaxial layer stack.
The reasons can be both variations in epitaxial growth as well as a slight
etch rate of the fluorine-based etch process in GaN [122]. The barrier thick-
ness of sample DE10 should ensure e-mode behaviour with a Vth well above
0 V.
Transfer characteristics for the processed devices are shown in linear
scale in Fig. 3.5a. For samples DE00 and DE10, the threshold voltages
are extracted to be Vth = -1.0 V and Vth = +0.5 V, respectively. Hence, clear
e-mode behaviour has been realised for the latter sample. Additionally,
the maximum extrinsic transconductance gm,max is increasing from sample
DE00 to sample DE10. Although this lies within the expected results, for
deep recessed samples, typically, no increase in gm,max has been observed

32
3.3 Gate Recessing

(a) Lg = 1 µm (b) Lg = 0.9 µm

Figure 3.5: Transfer characteristics in (a) linear scale at Vds = 3 V and (b) in semi-
logarithmic scale at Vds = 10 V. Device dimensions in (a) as indicated in
(b) except for Lg . After [104].

[123]. Therefore, the present result reflects a significant improvement. To


corroborate this, a calculation of the expected values of the intrinsic max-
imum transconductance gi m,max using the charge-control model [124] ex-
hibits an unchanged µ n at the point of gm,max [104]. It can be concluded
that the etch-induced damage of the barrier material is minimal.

From Fig. 3.5a, a decrease in maximum drain current Id,max from


600 mA/mm for samples DE00 and DE06 to 500 mA/mm for sample DE10
is observed. This can be related to the turn-on of the gate diode for sample
DE10, preventing further accumulation of the channel beneath the gate. In
Fig. 3.5b, in which the gate leakage current Ig is plotted in semi-logarithmic
scale, the effect of the gate diode turn-on is seen immediately. The vari-
ation in the turn-on of Ig for the different samples can be explained with
two reasons. First, Vgs is applied extrinsically. The intrinsic gate diode
however follows with [125], [126]
Vgs −Id ·Rs
Ig ∝ e kT

33
3 Engineering the Threshold Voltage in n-Channel Devices

with Rs being the combined series resistance of ohmic contact Rc and sheet
resistance between source and gate Rsh ·Lsg . Hence, having a smaller cur-
rent Id in the channel at a given Vgs , Ig is higher. The second reason leading
to an increase in Ig is the reduced barrier thickness. Especially for sample
DE10 with a remaining barrier thickness of 3.1 nm, tunnelling currents
are likely playing a role. Nevertheless, both Id,max as well as gm,max repres-
ented record DC values for e-mode AlGaN/GaN-on-Si HFETs at the time of
publication [104].

3.3.2 Pulsed I-V


To investigate the dynamic behaviour of the devices, output characterist-
ics were measured under static and pulsed conditions (see Fig. 3.6). The
pulsed measurements were performed with a pulse length of 200 ns and a
cycle time of 1 ms. After performing an unbiased measurement to eliminate
self-heating effects, off-state stress measurements with applied quiescent
gate and quiescent drain bias were performed to evaluate the device char-
acteristics as if the device were operated as a power-switch.
In Fig. 3.6, large differences between the unrecessed sample (DE00) and
the recessed samples are obvious. The differences in maximum drain cur-
rent for the DC and unbiased measurement for the three samples are re-
lated to the value of Vgs = 1 V6 . Comparing unbiased and biased pulsed
measurements, a rather strong reduction of Id in the knee is recorded for
sample DE00. For samples DE06 and DE10, however, this reduction turns
out to be only very low. This allows the assumption that the gate recess
is beneficial for optimising the dynamic behaviour. As is shown in the
next paragraph, the reason for this is a reduction in peak electric field.
To quantify the differences between the samples, the on-resistance under
biased conditions Rds,on-dyn (here, in this case Vgs,q = -2 V, Vds,q = -50 V) is
compared with the on-resistance under unbiased conditions Rds,on . The
ratio of these two values gives a measure of device quality when used in
a power-switching application. This comparison is performed at 75% of
maximum Id . For sample DE00, the ratio is 1.65. This means that un-
der the given bias conditions, the dynamic Rds,on-dyn is increased by 65%
compared to the static Rds,on . In contrast, for samples DE06 and DE10,

6
This value has been chosen since high gate currents distort measurements using off-state
biased conditions [127].

34
3.3 Gate Recessing

Figure 3.6: Output characteristics under static and pulsed conditions (pulse length
200 ns, cycle length 1 ms). The voltage insets represent the applied gate
bias. After [104].

much smaller ratios of 1.13 and 1.09, respectively, are extracted. The lat-
ter two values are among the best reported values using a 200 ns pulse and
a Vds,q of 50 V (especially when considering the small gate-drain separation
of 2.5 µm) [91], [128].
To shed light on the reason for the improvement, the electric field in
the devices has been simulated using TCAD Sentaurus [79]. The device
structure as used in the experiments has been compiled with and without
gate recess. Special focus is on the distribution of the electric field under
off-state biased conditions which were used in the pulsed measurements.
Thus, the device simulation was performed by starting at the initial condi-
tions without bias. In accordance to the dynamic characterisation, the end
point was set to an off-state with Vds = 50 V. The results of the distribution
of the electric field are shown in Fig. 3.7. In the figure, the gate region
(white area) towards the drain is shown. The gate was set in a slanted
manner. As discussed in Sec. 2.5.2, this slanted gate is a result of the
early passivation process [97].
For sample DE00 (Fig. 3.7a), for which no gate recess was performed,
the peak electric field is located at the SiN/GaN interface. This interface is

35
3 Engineering the Threshold Voltage in n-Channel Devices

e
at
G

Gate
Gate

(a) Sample DE00 (b) Sample DE06 (c) Sample DE10

Figure 3.7: Simulated distribution of the electric field at the drain edge of the gate.
The peak of the electric field is moved from the SiN/GaN cap interface
to the AlGaN barrier.

known to be imperfect [129] and a considerable amount of interface traps


are located there. Electron injection (by a field-assisted process) into these
interface traps leads to the so called “virtual-gate” effect [86] (surface trap-
ping as discussed in Sec. 2.5.1), for which an increased drain resistance is
a typical symptom. This effect leads to the decreased slope in the linear
region of the output characteristics depicted in Fig. 3.6 on the left. As soon
as the gate is recessed, the peak electric field is repositioned and located
in the barrier (cf. Figs. 3.7b and 3.7c). There, the density of trap states is
significantly smaller than at the SiN/GaN interface, resulting in reduced
electron injection. The field at the SiN/GaN cap interface is considerably de-
creased from about 5 MV/cm for the unrecessed device to about 1 MV/cm
for the deepest recessed device. This leads to a significant reduction of
electron injection probability and as a consequence, the slope in the linear
region for the biased measurement is maintained with reference to the un-
biased measurement. The improvement gained by using a gate recess as
demonstrated here is in agreement with [130].

36
3.4 Influence of Gate Metallisation

3.4 Influence of Gate Metallisation


This chapter deals with the engineering of the barrier height ΦB,n for GaN-
based HFETs. From Eq. 3.18 on p. 26, the direct influence of ΦB,n on Vth is
apparent. In the absence of Fermi level pinning, ΦB,n 7 directly depends on
the metal work function ΦM [131]. The focus of work function engineering
has mainly been on the ohmic contact stack, for which a low contact res-
istivity is a prerequisite for well-performing HFETs. In several publications,
results regarding the gate stack with the main focus being on the reduction
of gate leakage by the utilisation of high work function gate metals [120],
[132] and/or the improvement of the device reliability [133] have also been
demonstrated. However, less attention has been paid to Vth shifts caused
by such high work function metals [134]–[136].
Typically, Ni-based gate stacks are used in III-nitride HFETs. Ni has a
work function ΦM of about 5.1 eV [137]. To shift Vth to more positive values,
a higher ΦM is necessary. Only a few metals fulfil this criterion. These are
Ir, Pd, Pt and Re [137]. Ir, Pd and Re are rarely used metals for GaN-based
HFETs and device results shown are inconsistent in terms of ΦB,n relative
to Ni-gated devices [134], [138].
Thus, for this study, Pt with the highest ΦM of about 5.65 eV [137] is
used as gate metallisation and the resulting transistors are compared to
Ni-gated devices. The epitaxial layer stack was provided by the Ferdinand-
Braun-Institut für Höchstfrequenztechnik, Berlin, Germany, and a schem-
atic device cross section can be seen in Fig. 3.10b on p. 41. The layer stack
consists of a double heterostructure with a 50 nm GaN channel. The 17 nm
Al0.19 Ga0.81 N barrier is capped with a 3 nm Si-doped GaN layer. A conven-
tional fabrication method was employed. Mesa-isolation was performed by
a chlorine-based dry etch. Ohmic contact formation was realised by an
alloyed Ti/Al/Ni/Au stack. For the gate, either Ni/Au or Pt/Au were depos-
ited. Pad contacts were formed by a Ni/Au stack. Finally, the devices were
passivated by PECVD-SiN.

3.4.1 DC Characteristics
Fig. 3.8a shows linear transfer characteristics of a device with a Ni gate
and of a device with a Pt gate. The devices exhibit similar DC characterist-
7
As no insulator is used here ΦMIS needs to be replaced by ΦB,n

37
3 Engineering the Threshold Voltage in n-Channel Devices

(a) (b)

Figure 3.8: Transfer characteristics in (a) linear and (b) semi-logarithmic scale (in (b)
with associated gate leakage currents). Device dimensions: Lsg = 1.5 µm,
Lg = 1.0 µm, Lgd = 2.5 µm, Wg = 2×50 µm.

ics such as a nearly identical Id at Vgs = +2 V and similar values of gm,max .


For the Pt-gated device, gm is slightly higher throughout the measurement
range. Additionally, Vth is shifted from -1.0 to -0.7 V. This value of Vth shift
is consistent with results reported in the literature [139]. To verify whether
this is an effect of the different ΦM or of different barrier thicknesses by
inhomogeneity in epitaxial layer growth (cf. Fig. 3.5a), C-V measurements
were performed (not shown). From these measurements, the same barrier
thickness is extracted for both samples. Thus, the Pt-gated device obvi-
ously benefits from the increased value of ΦM . In Fig. 3.8b, Id and Ig are
plotted vs. Vgs in semi-logarithmic scale. In the off-state, an improvement
of nearly 2 orders of magnitude of leakage current can be seen. This re-
duction also has an effect on the subthreshold swing (SS)8 [141] which is
an indicator of the metal/semiconductor interface quality. SS is reduced
from 88 mV/dec for the Ni-gated device to 76 mV/dec for the Pt-gate device.
8
SS turns out to be an important value for power-switches, since the Vgs necessary to
turn a device on is reduced with a smaller SS. SS describes the channel control in the
subthreshold region which is limited by the Fermi-Dirac distribution to a lowest value of
60 mV/dec at room temperature [140].

38
3.4 Influence of Gate Metallisation

Figure 3.9: Output characteristics under static and pulsed conditions (pulse length
200 ns, cycle length 1 ms). The voltage insets represent the quiescent
Vgs and Vds .

In forward direction, no improvement is realised compared to the Ni-gated


device.

3.4.2 Pulsed I-V


To analyse the dynamic behaviour of the Pt-gated device, pulsed I-V meas-
urements have been utilised in a similar fashion as in Sec. 3.3. The results
are shown in Fig. 3.9.9 In the figure, again the output characteristics are
shown for DC (black curves) and pulsed conditions. Pulsed conditions
were applied unbiased (red curves) and under off-state stress (dark green
curves). Both samples show a similar behaviour. A slight knee walk-out
is to be seen for both samples, indicating some electron capture effects in
9
It has to be noted that the device named "Ni" was processed in a second lot and is not the
device for which the results are shown in Fig. 3.8. This is because the pulsed I-V measure-
ments of the original sample were extremely distorted, showing unstable behaviour. This
was not true for the Pt-gated device. However, the DC characteristics of "Ni" are similar
and show a slightly more negative Vth with at the same time a slightly increased maximum
Id . Although the Ni- and Pt-gated samples are not processed in the same lot, it seems
reasonable to compare them.

39
3 Engineering the Threshold Voltage in n-Channel Devices

the access region. The Pt-gated device shows superior characteristics com-
pared to the Ni-gated device. The reason for this cannot be fully explained
yet. Damage introduced by the electron beam evaporation used for gate
metal deposition cannot play the major role here, since Pt is evaporated at
an even higher temperature than Ni and hence with a higher current of the
electron beam. Thus, it might be an effect of an improved interface in terms
of a reduced number of electrically active states at the metal-semiconductor
interface [142]. However, since a passivation-last approach was used for
fabrication of these devices, the possible variation in gate shape could affect
the dynamic performance. It has to be noted that although the off-state
drain bias is lower here compared to the samples shown in Fig. 3.6, both
devices show increased current collapse. Since the samples shown here
were not processed using the early-passivation approach [95], the less ideal
dynamic performance is in agreement with the expectations discussed in
Sec. 2.5.2.

3.5 Influence of GaN Channel Thickness


In the following section, a shift of Vth towards positive values is targeted
by introducing a backbarrier. As explained in Sec. 3.1 and illustrated in
Fig. 3.2b on p. 27, by employing a thin channel with a backbarrier, the back-
side heterointerface at which a negative polarisation difference is present
is closer towards the 2DEG. Hence, the 2DEG is depleted and Vth shifts to
more positive values. As was discussed in Sec. 3.2, no significant Vth shift
is expected for a channel thickness below 100 nm (cf. Fig. 3.2b). This ex-
pectation is experimentally investigated in the following. Although a high
Al content in the backbarrier would be preferable for obtaining high posit-
ive values of Vth (refer to Sec. 3.2), the Al content for this study was limited
to 7% to ensure a high epitaxial quality of the double heterostructure.
The device fabrication included a conventional process without using the
early passivation process [97]. All devices were fabricated simultaneously
with the same process using a BCl3 mesa isolation process, ohmic con-
tacts formed by a Ti/Al/Ni/Au stack annealed at 825 ◦ C and gate contacts
formed by a Ni/Au electrode. For this lot, the difference in the devices
is based solely on the epitaxial structure. The epitaxial layer stacks were
provided by the Ferdinand-Braun-Institut für Höchstfrequenztechnik. The
main difference between the samples is the thickness of the GaN channel.

40
3.5 Influence of GaN Channel Thickness

(a) (b) (c) (d)

Figure 3.10: Schematic cross sections for (a) the reference sample without backbar-
rier and 1 µm channel and for the samples with backbarrier and (b)
50 nm, (c) 20 nm and (d) 10 nm channel.

For the samples with the Al0.07 Ga0.93 N backbarrier, the channel thickness
is varied between 50 nm, 20 nm and 10 nm for samples BB50, BB20 and
BB10, respectively. As a reference, a single heterostructure with a GaN
buffer has also been processed (named SHFET). Schematics of the four
samples are depicted in Fig. 3.10. The results can also be found in [143].

3.5.1 Van der Pauw and Hall Characterisation


To characterise the properties of the 2DEG, van der Pauw and Hall meas-
urements were carried out. The results are shown in box plots in Fig. 3.11.
It can be seen that µ n (Fig. 3.11a) reaches only moderate values for all
samples. This is mainly caused by two effects. First, without an AlN
spacer, the 2DEG is distributed deeper into the barrier, in which electrons
have a dramatically reduced electron mobility [73]. Second, alloy disorder
scattering is increased by the direct presence of the ternary AlGaN instead
of the binary AlN in the vicinity of the 2DEG [144]. Beside µ n , the value of
ns (Fig. 3.11b) for sample BB50 is lower than for sample SHFET. This is in
agreement with the expectation. However, for samples BB20 and BB10, ns
is higher. The reasons here are likely carriers which are located in a buried
parasitic channel. This assumption is confirmed by the high buffer leakage
of these samples as shown in Fig. 3.12b on p. 43. As is seen in Fig. 3.11c,
the Rsh is increased for the DHFET samples. Hence, an increased access
resistance for DHFET samples is a drawback when realising e-mode devices

41
3 Engineering the Threshold Voltage in n-Channel Devices

(a) (b)

(c)

Figure 3.11: (a) Electron mobility µ n , (b) sheet carrier density ns and (c) sheet res-
istance Rsh extracted from van der Pauw and Hall measurements.

with double heterostructures.

3.5.2 DC Characteristics
Transfer characteristics in linear and in semi-logarithmic scale are shown
in Figs. 3.12a and 3.12b, respectively. Id decreases with lower channel
thickness. This is in agreement with the expectation, since the access
resistance is increasing with decreasing channel thickness (as shown in
the previous section). However, the value of sample BB10 does not follow
this trend. The reason for this is not fully clear, but is most likely related to
a parasitic channel below the backbarrier (cf. pp. 130–133 in the appendix).
Additionally, and also as a result of the increased access resistance (here,
the effect is mainly caused by the source resistance Rs ), gm,max is decreasing
in the same manner as Id .
Vth is positively shifted with decreasing channel thickness. However, the

42
3.5 Influence of GaN Channel Thickness

(a) (b)

Figure 3.12: Transfer characteristics in (a) linear and (b) semi-logarithmic scale.
The colours used in (b) refer to the identical devices from (a).

value of sample BB10 is deviating. In numbers, the values are shifted from
-1.0 V over -0.5 V to -0.2 V for samples SHFET, BB50 and BB20, respectively
(Vth of sample BB10 is about -0.7 V). This shift is a consequence of the
channel depletion under the gate. Yet, the difference between the devices
BB50 and BB20 of 0.3 V is higher than the expected value of about 0.05 V
(cf. Fig. 3.2b). The reason for this is not really clear. As extracted from C-V
analysis (not shown), the barrier thicknesses are identical. However, the
difference in Vth could be related to a slight variation in the Al content of the
barrier. For sample BB10, a very high off-state drain current is already
seen in the linear scale. The device cannot be pinched off satisfactorily (see
p. 130).
Compared to the samples shown in Sec. 3.3, Id and gm shown here
are considerably reduced even for the SHFET. This behaviour is, first, a
consequence of a thicker barrier here (gate channel separation approx.
21.0 nm compared to 17.6 nm). Second, it results from a reduced Al con-
tent in the barrier in combination with the fact that no AlN spacer layer was
deposited here. The two latter differences which may be seen as polarisa-
tion engineering cause a reduction in both ns and µ n . Hence, Rsh is strongly

43
3 Engineering the Threshold Voltage in n-Channel Devices

increased. However, considering the application to be power-switching,


drain currents in the range of 300 mA/mm are still reasonable10 . This is
true due to the high power dissipation in on-state for very large devices
with gate widths exceeding 300 mm [145].
To analyse leakage currents, Fig. 3.12b is now considered. Depicted are
Id and the gate leakage current Ig . It is obvious that the off-state currents
(devices show values close to the logarithmic mean of devices over the
whole sample) do not scale with the GaN channel thickness. In contrast
to results in the literature, the lowest value is achieved for the SHFET
device [92], [146]. Since the pinch-off behaviour of the device should be
improved by the presence of a backbarrier, and thus, off-state currents
should be reduced, the reason for this effect has to be found in another
fact. A second aspect being very obvious is the dramatically higher off-
state drain leakage compared to Ig . This is a very non-typical behaviour
for Schottky-gated devices and the reason is usually found to be a non-
isolating buffer [147]. Since AlGaN is used as a backbarrier, the isolation
should even be improved compared to the SHFET. Obviously, this is not
the case. The reason for this poor pinch-off behaviour is found in a second
parasitic polarisation-induced channel which is buried below the AlGaN
backbarrier. For more information on this aspect, it is referred to pp. 130–
133 in the appendix.

3.5.3 Pulsed I-V


For the analysis of the dynamic behaviour, samples SHFET, BB50 and
BB20 are characterised. The measurement setup known from the previous
sections was equally applied for this characterisation. First, Fig. 3.13 show-
ing the output characteristics is analysed. Similar to the results shown
in the semi-logarithmic plot, a clear dependence of Id,max on the channel
thickness is observed. In comparison to sample SHFET, an increased knee
voltage for samples BB50 and BB20 can be seen in the DC measurement.
This is an effect of the increased Rsh . However, from the pulsed I-V curve
measured using off-state stress, a steady qualitative improvement is ob-
served from sample SHFET via sample BB50 to sample BB20. The knee
walkout is dramatically reduced, indicating a decreased degree of buffer
trapping. For the SHFET sample, trapping is likely to occur both at Fe and
10
Actual values for Rds,on are discussed at the end of this section.

44
3.5 Influence of GaN Channel Thickness

Figure 3.13: Output characteristics under static and pulsed conditions (pulse
length 200 ns, cycle length 1 ms). The values given in the caption
represent the quiescent Vgs and Vds .

C acceptors [85]. The reduction for samples BB50 and BB20 can be related
to a reduced peak electric field in the buffer. The electric field is effectively
weakened by the AlGaN backbarrier, thus hindering electron injection into
buffer traps [108].
For a quantitative analysis, the values of dynamic Rds,on (normalised
to the area) and the ratio of dynamic vs. static Rds,on are depicted in
Fig. 3.14. The two different trends indicated earlier can now be seen in
the graph. First, the ratio Rds,on-dyn /Rds,on decreases when using a backbar-
rier in the device structure. While for sample BB20 already quite low values
of about 1.25 are achieved, for sample SHFET, a value of over 2 already at
Vds = 30 V reflects a poor results. However, considering the total number of
Rds,on-dyn ×A, the lowest value is achieved for sample SHFET. The reason is
found in the rather small sheet resistance. Thus, if the samples would be
used as a power switch, sample SHFET would still be suited best. What is
missing here for a full picture is the breakdown voltage (Vbd ). This would
allow to gain access to the Rds,on-dyn ×A vs. Vbd behaviour. Here, the best
result is expected for sample BB50. Since the off-state leakage currents
are much higher than expected, a characterisation of Vbd has not been

45
3 Engineering the Threshold Voltage in n-Channel Devices

Figure 3.14: Overview of extracted values for the ratio of dynamic vs. static Rds,on
and for absolute values of dynamic Rds,on-dyn ×A.

carried out. However, references in the literature already give a promising


picture [92], [108], [148]. Based on the results presented and the results
found in the literature, it seems most promising to use sample BB50 for
further experiments and for the optimisation of Vth .

3.6 Influence of Gate Insulation


In this section, the influence of an insulator between gate electrode and
barrier material on device characteristics is described. For e-mode devices,
it is necessary to deposit a dielectric between gate metal and semiconductor
to be able to accumulate carriers in the channel beneath the gate without
drawing excessive gate leakage current. Moreover, as has been discussed
in Sec. 3.2, the insulator plays a very important role in determining Vth of
the transistor. By controlling the insulator/semiconductor interface, i.e.
controlling the charge present at that interface – the fixed interface charge
density σ it (in the following, when actual numbers are quoted, it is referred
to nit =σ it /e) – one is able to control Vth . Hence, beside the reduction of
Ig , the main focus is on the shift of Vth with application of the dielectric.
However, also challenges such as a stable Vth under stress conditions are
evaluated.
As is evident from electrostatics, the requirements for a dielectric layer
in the access region are different to those in the gate region. For the passiv-
ation, obtaining positive σ it for the accumulation of the 2DEG is beneficial.

46
3.6 Influence of Gate Insulation

Thereby, the parasitic resistances can be improved. Moreover, limiting


trapping phenomena is important to guarantee low current-collapse (as
discussed in Sec. 2.5.1). By using the early-passivation process described
in Sec. 2.5.2, it is possible to deposit the gate dielectric in such a way that
it only influences the intrinsic device. Hence, gate and access region can
be optimised separately, leading to largely improved device characteristics.
Important for this thesis is that with this approach, the influence of the
gate dielectric can be investigated and optimised with respect to the gate
region only.
During this thesis, work was performed on atomic layer deposited (ALD)
AlOx , for which the results are presented in Sec. 3.6.1, as well as on plasma-
oxidised metal layers, for which the results are described in Secs. 3.6.2
and 3.6.3. For the latter, various metals – Al, Ti and Zr – have been used.

3.6.1 Aluminium Oxide Prepared by Atomic Layer Deposition


Several dielectrics which have been deposited by various methods have
been investigated so far [149]. It has been reasonable to investigate the
native oxides as in Si-based MOS technology, i.e. using Ga2 O3 [150], [151]
and Al2 O3 [88], [90], [152]–[158] as gate dielectric on AlGaN/GaN hetero-
structures. However, Ga2 O3 only features a low bandgap of 4.8 eV and a
low conduction band offset ∆EC to GaN of 0.46 eV [131]. Hence, insulation
is expected to be only moderate. This is different in the case of Al2 O3 which
features a very high bandgap of 7-9 eV with a ∆EC of 2.16 eV [131], a rather
high relative permittivity ϸr of about 9 and a large breakdown field of about
10 MV/cm [88]. These properties allow for Al2 O3 being the first choice as
gate dielectric for GaN-based devices.
Al2 O3 can be deposited by various methods, such as ALD [152]–[154],
MOCVD [155], [156], electron cyclotron resonance (ECR) sputtering [157],
thermal oxidation of an e-beam evaporated Al layer [90] or ECR plasma
oxidation of an Al layer prepared by molecular beam epitaxy [158]. Among
these, the most established platform for the deposition is ALD. It is even
used in Si industry for the deposition of high-ϸr layers. ALD guarantees
a very homogeneous layer growth, a very good controllability of the layer
thickness, all at low to moderate temperatures between 100◦ C [141] and
300◦ C [152]. Using Al2 O3 deposited by ALD, an extremely large suppres-
sion of forward leakage current has been shown [152], [153].

47
3 Engineering the Threshold Voltage in n-Channel Devices

Figure 3.15: I-V characteristics of large-area diodes for samples with ALD-AlOx as
gate insulator. Additionally shown is an I-V curve of an unrecessed,
but passivated Schottky-gated reference diode.

Hence, in this section, AlOx 11 deposited by ALD is evaluated as a possible


gate dielectric for e-mode devices. The analysis comprises C-V and I-V
characterisation as well as an assessment of Vth stability. The results
presented herein are partly discussed in [159].
For the following analysis, four samples were prepared. The samples
were mesa isolated by a chlorine-based dry etch, after which Ti/Al/Ni/Au
contacts were deposited and annealed to form ohmic contacts. The samples
were then passivated with 120 nm SiN by PECVD. The gate trenches were
opened by a fluorine-based dry etch [95]. Subsequently, a gate recess was
performed with 10 cycles using the digital etch technique and the depth
was calculated to be about 13 nm using C-V analysis [103]. Prior to the
gate metallisation, AlOx was deposited by means of ALD.12 The samples
processed within this series feature nominal oxide thicknesses of 3 nm
(AlOx3), 6 nm (AlOx6), 9 nm (AlOx9) and 12 nm (AlOx12). Instead of a Ni
gate, a Pt gate was used within this series.
I-V characteristics of large-area diodes are shown in Fig. 3.15. For the
3 nm thick sample, leakage current is weakly suppressed compared to an
unrecessed Schottky-gated reference. In reverse direction, the suppression
is about 3 orders of magnitude. In forward direction, the suppression is
11
It is referred to AlOx rather than Al2 O3 as no characterisation has been performed to verify
the Al:O ratio.
12
The ALD process for these samples and for all samples hereafter was performed at the
Fraunhofer Institute for Applied Solid State Physics, Freiburg, Germany.

48
3.6 Influence of Gate Insulation

Figure 3.16: C-V characteristics of large-area diodes. The sweeps were first per-
formed from negative to positive bias and then from positive to negative
bias.

indicated by the reduced slope of the curve, a sign that the leakage current
is not dominated by thermionic emission (as it is for the Schottky sample).
For the sample with 6 nm AlOx , the leakage current density at negative bias
is extremely low with a value of about 1×10−8 Acm−2 . In forward direction,
the current is suppressed up to a voltage of 3 V, at which a tunnelling
process is the most likely explanation for the current to increase. Current
suppression in forward direction is further enhanced for the two samples
with 9 and 12 nm oxide thickness. For the 12 nm sample, the steep slope
begins at about 7.5 V. Based on these results, an oxide thickness of at least
6 nm appears necessary to obtain a proper insulation behaviour.
For a further analysis, C-V values of large-area diodes at 1 MHz were ob-
tained. The resulting C-V curves are shown in Fig. 3.16. All samples show
a clear transition from pinch-off to an accumulated 2DEG. As expected, the
capacitance in accumulation is decreasing with increasing oxide thickness
tox . Based on results from [103], the oxide permittivity ϸ r for this series
was extracted to be 9.6ϸ 0 . The oxide capacitance Cox was calculated for all
samples at the same 2DEG density (to prevent errors by a variation of the
distance of 2DEG to the barrier/channel interface [121]). These values are
shown in Tab. 3.1 and are used to calculate tox for each sample. Assuming
the barrier to have the same thickness for all samples, the extracted values

49
3 Engineering the Threshold Voltage in n-Channel Devices

Figure 3.17: Sheet charge density vs. applied voltage for the large-area diodes. The
results were obtained by integrating the C-V curves shown in Fig. 3.16.

for tox are 3.4, 6.0, 9.7 and 12.1 nm for samples AlOx3, AlOx6, AlOx9 and
AlOx12, respectively. These values are also shown in Tab. 3.1.
Further, the 2DEG densities were determined by integrating the capa-
citance values over the applied voltages. The resulting values of ns were
then plotted vs. the voltage as shown in Fig. 3.17. From a linear extrapol-
ation (not shown), Vth of the four samples was extracted. As a hysteresis
is seen for all C-V characteristics, the resulting values for Vth are different
for forward and backward sweeps by about 0.1 V. The values of Vth vary
in dependence on the oxide thickness, but differently to what one would
expect. The variation of Vth with oxide thickness (Fig. 3.3b) appears non-
linear, indicating the presence of fixed bulk oxide charge Nox . Consequently,

Table 3.1: Extracted values of the oxide capacitance, the associated oxide thick-
ness and threshold voltages for the measurement in forward (Vth,p ) and
backward (Vth,n ) direction. Calculated fixed interface and fixed bulk oxide
charge densities to account for the Vth trend with tox .

Cox tox Vth,p / Vth,n nit Nox


Sample (nF/cm2 ) (nm) (V) / (V) (cm−2 ) (cm−3 )
AlOx3 2450 3.4 -1.54 / -1.41 -1.5×1013 1.6×1019
AlOx6 1420 6.0 -1.63 / -1.51 -1.5×1013 1.6×1019
AlOx9 875 9.7 -2.00 / -1.93 -1.5×1013 1.6×1019
AlOx12 700 12.1 -2.76 / -2.56 -1.5×1013 1.6×1019

50
3.6 Influence of Gate Insulation

Figure 3.18: Values for Vth extracted from forward and backward sweeps of C-V
measurements in dependence on tox . The fit to meet Vth was per-
formed assuming negative fixed interface charge and positive bulk ox-
ide charge. A second curve assuming only negative interface charge
(the value taken from the fit) is also shown.

Eq. 3.18 from p. 26 was fitted to the data to extract the individual contri-
bution of nit and Nox . Assumptions need to be made for a few parameters
such as the conduction band offset ∆EC,MIS between AlOx and Al0.26 Ga0.74 N.
To maintain consistency with the next section, the AlN spacer layer was
neglected in the calculation and instead, a single interface charge density
σ int between barrier and channel was assumed which fits well to the case
of a Schottky-gated HFET13 . Hence, the fixed parameters for the fit are
∆EC,AlOx/AlGaN = 2.1 eV ([160] as cited in [103]), ∆EC,AlGaN/GaN = 0.4 eV [161]
and σ int = 1.53 µC/cm2 .
The result of the calculation is illustrated in Fig. 3.18 and it was ob-
tained by assuming the barrier height to be 3.3 eV, chosen to be in very
good agreement to an experimentally obtained value of the Ni/Al2 O3 bar-
rier height [100]. A positive Nox of 1.6×1019 cm−3 and a negative nit of
-1.5×1013 cm−2 were further assumed to obtain the best fit. Bulk oxide
charges have often been reported to be of positive type for ALD-Al2 O3 de-
posited on other III-V semiconductors [162]–[164]. In the case of GaN, both

13
The experimental interface charge is smaller than the theoretical one by 33%. This is in
accordance with [36].

51
3 Engineering the Threshold Voltage in n-Channel Devices

negative [101] as well as positive [165] Nox values have been reported for
ALD-Al2 O3 . The negative number of nit indicates an incomplete compens-
ation of the polarisation-induced surface charge of the barrier by surface
donors. As is shown in Sec. 3.7, the reason for this is most likely the
gate recess which modifies the surface as has been discussed in [166] and
[167]. The estimated nit is within the range of reported values [36], [101],
[168], [169]. In the case shown here, σ it exceeds the polarisation difference
between AlGaN and GaN. If it were possible to obtain Nox = 0, a positive Vth
shift could be obtained with increasing tox . This is indicated by the dashed
line in Fig. 3.18 and it reflects the ideal case for e-mode devices.
For the application as power-switch, Vth stability is crucial. Whereas a
positive Vth shift may lead to a reduced on-current, a negative one might
even be more severe. As soon as the subthreshold region of the devices
reaches the y-axis intercept, the off-state current dramatically increases
by orders of magnitude. Together with a high drain bias typically applied
in power-switching applications, dissipation of huge power densities would
be necessary which may eventually lead to a fatal breakdown of the device
and/or system.
Consequently, the stability of the achieved Vth is discussed. Hence, tran-
sistors on the different samples were subjected to various stress conditions
in on- and off-state. Stress conditions were applied for different time peri-
ods ranging from 1 s to 1000 s in logarithmic steps (as discussed in [99]).
Subsequently, after stress, transfer curves were measured. Using these
measurements, Vth was extracted in dependence on stress time.
In Fig. 3.19, several transfer curves are shown for a variation in stress
time between 1 s and 1000 s. With applied off-state stress (Vgs = -8 V,
Vds = 10 V), Vth is shifted towards negative values in dependence on stress
time. Whereas for 10 s only a minor shift is visible, the shift is expanded for
100 s and 1000 s stress time. For the final measurement without applied
bias stress, the shift in Vth is partly recovered. Since the stress forces Vth
towards negative values, a hole capture process or an electron emission
process can be made responsible for this phenomenon. With the stress
times varying over orders of magnitude for both processes [170], [171], the
actual origin cannot be identified with this set of data. An emission pro-
cess may be related to the oxide/AlGaN interface at which electrons may
be emitted from donor-like states. By applying Shockley-Read-Hall statist-
ics as described in [172] and taking the stress times used within this set
of experiments, the depth of the trap states is estimated to be in-between

52
3.6 Influence of Gate Insulation

Figure 3.19: Transfer characteristics of a MIS-HFET. The measurement was per-


formed after various stress times at Vgs = -8 V, Vds = 10 V. The stress
times are indicated with the colour intensity. The second sweep for
0 s (dashed line) was performed immediately after the 1000 s measure-
ment. A shift in Vth in dependence on the stress time is observed.

0.29 eV and 0.37 eV below the conduction band. Based on the results
shown in Fig. 3.19, which shows the main Vth to occur after 1000 s, the
trap depth is closer to 0.37 eV below EC .
To further evaluate Vth stability, Vth values extracted from transfer char-
acteristics of the four samples are analysed. These values were extracted at
Id = 1 mA/mm to exclude any influence of gm on Vth [173]. Hence, the values
are slightly more negative than the ones obtained from the C-V measure-
ments (cf. Fig. 3.16). Three different stress conditions (different quiescent
bias points) were chosen to evaluate the performance as if the device were
working as power switch. As a consequence, the bias points were set for

• off-state stress with applied drain bias (emulate blocking state):


Vgs = -8 V, Vds = 10 V

• on-state stress with low bias (linear region in the output characterist-
ics): Vgs = 4 V, Vds = 4 V

• on-state stress with high bias (saturation region in the output char-
acteristics): Vgs = 4 V, Vds = 10 V.14
14
This on-state point has been chosen to simulate the effect for a device suffering from current
collapse and for which consequently a higher Vds would be necessary to draw a specific
current.

53
3 Engineering the Threshold Voltage in n-Channel Devices

(a) (b) (c)

Figure 3.20: Different values for Vth in dependence on sample and stress time for
three different bias conditions (a) off-state with applied Vds (b) on-state
at a point close to the knee and (c) on-state in the saturation region.

Data extracted from these measurements is plotted vs. stress time and
the results are shown in Fig. 3.20. The open symbols reflect the results
of the measurement without stress immediately after the 1000 s stress
measurement.
A comparison of all samples under the off-state quiescent bias point
shows almost identical Vth shifts for samples AlOx6, AlOx9 and AlOx12.
The shift is in the order of 1 V at 1000 s stress time. As explained above, the
physical reason for the shift of these three samples is most likely related
to an electron-emission process. However, for sample AlOx3, an almost
constant Vth is observed. This may be related to the rather high leakage
current of this sample (cf. Fig. 3.15) which prevents an electric field from
building up, necessary for an emission process to take place.
In the on-state with low drain bias, no consistent picture is obtained. The
slight positive Vth shift may be an electron capture process which occurs

54
3.6 Influence of Gate Insulation

under positive Vgs in donor-type bulk oxide charges. The capture process
may be limited by a tunnelling process as described in [99].
In the on-state with a high drain bias, Vth remains almost constant. No
strong negative or positive shift is seen. Here, a mixture of capture and
emission processes may occur [174]. This seems reasonable for the follow-
ing reason. Whereas on the source side of the gate, a positive electric field
may lead to electron capture and/or hole emission, on the drain side of the
gate, a negative electric field is leading to electron emission.
In summary, ALD AlOx shows very good insulation properties. Owing
to a large σ it , Vth for the samples with 3 nm and 6 nm thickness is shifted
only marginally. However, all samples except sample AlOx3 exhibited an
unstable Vth . Consequently, Vth stability needs to be further optimised for
a possible application in a power-switch.

3.6.2 Aluminium Oxide Prepared by Plasma-Oxidation


As was already noted in Sec. 3.6.1, several methods have been employed for
the fabrication of metal-insulator-semiconductor HFETs (MIS-HFETs). Be-
side the commonly used method of ALD, for which the results have been dis-
cussed in the previous section, methods such as plasma-enhanced chem-
ical vapour deposition (PECVD) [175], pulsed laser deposition (PLD) [176],
MOCVD [155], [156], electron cyclotron resonance (ECR) sputtering [157],
thermal oxidation of electron beam (e-beam) evaporated metal [90] or ECR
plasma oxidation of molecular beam epitaxy (MBE) deposited Al [158] have
been employed in the past. However, the methods have in common that
the dielectric is deposited over the complete wafer and therefore requires
additional process steps. Furthermore, a gate dielectric in contact to ohmic
contacts could lead to a parasitic leakage path either at the SiN/dielectric
interface (in case of early passivation) or at the dielectric/semiconductor
interface (in case of passivation last). A deposition which is constrained
to the gate region only is difficult to be realised with common deposition
methods since the temperature necessary for the deposition or the depos-
ition method itself does not allow such a procedure. Plasma oxidation of
an e-beam evaporated metal layer, however, is a suitable alternative for a
deposition which is constrained to specified areas. The temperature step
necessary to form well-performing dielectrics is postponed to a later stage
of the process flow (e.g. after gate metal deposition), thus allowing for the
use of soft masks for patterning.

55
3 Engineering the Threshold Voltage in n-Channel Devices

Prior to the work performed during this thesis, only results of a single
study regarding the plasma oxidation approach have been reported [177].
However, effects of post deposition annealing have not been investigated so
far. On the other hand, a few studies on the plasma oxidation of barrier
layers have been reported [178]–[181]. Beside a reduction in leakage cur-
rent which has been shown in all those publications, a Vth shift to positive
values has also been demonstrated [179]. As this is beneficial for e-mode
devices, the combination of a simple fabrication method allowing for a gate-
specific insulation and the prospect of obtaining a positive Vth shift seems
to be very promising. Parts of the results have been published in [109],
[182].
The fabrication for all samples included standard steps such as mesa
isolation by a chlorine-based dry etch and ohmic contact formation by an
alloyed Ti/Al/Ni/Au stack. The oxide formation and gate deposition (in the
following called gate stack formation) is different to those of samples dis-
cussed earlier and hence these process steps are explicitly described. The
process flow of the gate stack formation with Al is illustrated in Fig. 3.21.
The process began with gate lithography on the basis of a two-layer resist
of which the lower one is used as lift-off resist (LOR). Hence, an undercut
below the upper resist was ensured. After an HCl:DI 1:1 dip, the samples
were transferred to an e-beam evaporation chamber, in which metal (in
this case Al) was deposited. After the deposition, the sample was subjec-
ted to an oxygen plasma in an ICP-RIE15 (see Fig. 3.21b) during which Al
is oxidised to AlOx . Subsequently, a Ni/Au gate electrode was evaporated
in the e-beam chamber and the complete sample was subjected to a lift-off
procedure, after which the oxide remained only beneath the final gate elec-
trode (cf. Fig. 3.21c). Finally, a thermal treatment under N2 atmosphere
was performed. A passivation layer was not deposited on these samples.
Thermal treatments are typically performed for dielectric layers in MIS
structures. Annealing under various ambients has often shown to be
beneficial in reducing interface trap states Dit or fixed oxide charges Nox
[151], [162], [164], [183]. To analyse the effect of thermal treatment for
the plasma-oxidised layers, for one sample on which 3.5 nm Al was depos-
ited for gate insulation purposes, temperature steps of 400 ◦ C, 500 ◦ C and
600 ◦ C were performed in N2 atmosphere. If the dielectric is assumed to be
amorphous as deposited, it should maintain its amorphous state during

15
The exact process details can be found in Tab. 3.2.

56
3.6 Influence of Gate Insulation

Oxygen plasma
Al
Photo- AlOx Photo-
resist resist Ni AlOx
Au
S LOR D S LOR D S D
20 nm Al0.26Ga0.74N 20 nm Al0.26Ga0.74N 20 nm Al0.26Ga0.74N
2 µm GaN 2 µm GaN 2 µm GaN
AlN nucleation AlN nucleation AlN nucleation
Si <111> Si <111> Si <111>
(a) (b) (c)

Figure 3.21: Process scheme for the plasma-oxidised samples. (a) First, a metal
layer, in this case Al, is evaporated. (b) Second, the sample is exposed
to oxygen plasma in an ICP-RIE. (c) Third, Ni and Au are evaporated
and a subsequent lift-off is performed. After [182].

annealing because even the highest of the applied annealing temperatured


is below the recrystallisation temperature of Al2 O3 [154], [184].
First, insulation properties of the plasma-oxidised Al are investigated.
I-V characteristics of large-area diodes with a diameter of 100 µm are de-
picted in Fig. 3.22a. Compared to a reference Schottky diode on the same
epitaxial layer stack, AlOx improves the leakage current of the large-area
diode both in forward and reverse direction. The effect is already visible for
the unannealed devices. Further improvement especially in reverse direc-
tion is achieved by increasing the temperature during the annealing step.
The lowest current density is reached with the sample being annealed at
600 ◦ C. In forward direction, the effect is less pronounced. Nonetheless,
at +4 V gate voltage, the 600 ◦ C sample again exhibits the lowest leakage
current. The zero-current crossing (change of sign in J) deviating from 0 V
is observed for all samples with the plasma-oxidised layer and it is related
to charge injected into the oxide or at the oxide-semiconductor interface
(during the I-V measurement)[185]. As is shown later, this zero-current
shift does not influence the stability of Vth in these MIS-HFETs.
In addition to the large-area diode measurements, the extracted data
of gate-source diode leakage occurring in transistors with gate lengths
Lg = 1 µm at Vgs = -8 V is shown in Fig. 3.22b. Again, a constant reduc-
tion in leakage current with annealing temperature is observed with the
lowest value being in the low nA/mm range. Compared to the large-area

57
3 Engineering the Threshold Voltage in n-Channel Devices

(a) (b)

Figure 3.22: (a) Large-area diode leakage current density versus voltage for different
annealing temperatures. (b) Comparison of off-state transistor gate
leakage current at Vgs = -8 V, Vds = 10 V versus annealing temperature.
After [182].

diodes, the leakage current reduction with increasing annealing temperat-


ure is even stronger in the case of the FET, thereby indicating that for the
600 ◦ C sample, the residual current is flowing through the bulk oxide.
To allow for the extraction of values for Cox and Vth and to be able to
correlate them, the C-V characteristics shown in Fig. 3.23 are discussed.
The C-V curves are extracted from measurements at 1 MHz from positive
to negative voltages (to) and reverse (back). All curves show accumulation
and depletion of the 2DEG. As has been expected for the reference samples
with the Schottky gate, the highest capacitance C is extracted. Insertion
of the plasma-oxidised metal layer leads to a reduced capacitance. By
comparison of the capacitance values at the same 2DEG density, an as-
deposited oxide capacitance of 1150 nF/cm2 is extracted. This value is
equal to 7 nm when assuming ϸ r of Al2 O3 to be 9ϸ 0 [88]. Furthermore, the
voltage necessary to deplete the 2DEG is shifting towards more negative
values for the sample with the as-deposited oxide.
By applying the thermal treatment, C is continuously decreasing with
the lowest value obtained for the sample annealed at 600 ◦ C. Here, an

58
3.6 Influence of Gate Insulation

Figure 3.23: C-V measurements of large-area diodes at f = 1 MHz in dependence on


the annealing temperatures. After [182].

oxide capacitance of 490 nF/cm2 is measured, leading to the equivalent


oxide thickness to Al2 O3 to be 16 nm. The reason for this reduction in Cox
has yet not been identified. It is likely that interfacial layers are formed
either between Ni and AlOx or between AlOx and AlGaN. However, partial
oxidation of Ni could also be possible. Despite the reduction in C, Vth is
shifting back to more positive values; still, the value of the HFET is not
reached. The reason for the positive shift is likely related to either the
presence of negative nit , of negative Nox or of both. Indeed, a more in-depth
analysis based on methods published in [186], [187] indicates the presence
of deep-level states in the oxide, governing Poole-Frenkel conduction [182].
The charge state of the traps does not change because of their depth below
EC [188]. However, it does affect Vth [188].
For a final analysis, transfer characteristics in semi-logarithmic scale
are plotted in Fig. 3.24a. The transfer characteristics are shown for the as-
deposited sample and the different annealing temperatures. The leakage
current reduction was already shown in Fig. 3.22b. A shift in the pinch-off
voltage Vp (defined for sign change of ∂Id /∂Vgs ) is observed with each tem-
perature step. Furthermore, the subthreshold swing decreases with each
temperature step. This reduction is likely to be caused by an improving
interface quality between oxide and semiconductor [189]. A value below
80 mV/dec is reached for the device on the sample annealed at 600 ◦ C,

59
3 Engineering the Threshold Voltage in n-Channel Devices

(a) (b)

Figure 3.24: (a) Transfer characteristics of transistors for the samples subjected to
different annealing temperatures. Values for subthreshold swing are
indicated. Vds = 10 V. Lg = Lsg = Lgd = 2 µm. Wg = 246 µm. (b) Vth and
gm,max extracted from transfer characteristics in linear scale. After
[182].

already very close to the room temperature limit and also comparable to
those of devices with ALD-Al2 O3 as gate dielectric [141], [190].
Furthermore, the values of Vth and gm,max have been extracted from
transfer characteristics on a linear scale. The resulting data is shown
in Fig. 3.24b. Similar to the results of the C-V measurements, a continu-
ous Vth shift is observed. The value of Vth between the as-deposited sample
and the sample annealed at 600 ◦ C differs by +0.7 V. The values of gm,max
are continuously increasing with annealing temperatures from a value of
about 80 mS/mm to a value of more than 140 mS/mm. Hence, despite the
reduced capacitance, the controllability of the channel is largely improved.
The reason again is likely to be found in an improved interface quality by
a reduced density of interface states ([191] as cited in [88], [89], [192]).
With the previous experiments, the feasibility to shift Vth has been shown.
Nonetheless, although a Vth shift of 0.7 V by annealing has been demon-
strated, a positive Vth shift compared to the reference Schottky-gated HFET
has not been achieved. Hence, the previous results only serve as a basis
for further experiments.

60
3.6 Influence of Gate Insulation

3.6.3 Various Insulators Prepared by Plasma Oxidation


To allow for further engineering of Vth , additional metal layers were utilised
for the plasma oxidation process. Beside Al discussed beforehand, Ti and
Zr were chosen as suitable alternatives. TiO2 features a very high dielectric
constant of up to 100 [193] and could thus allow for high values of Cox . On
the other hand, ZrO2 has recently attracted increasing interest due to its
sufficiently high conduction band offset and its large dielectric constant of
about 25 [193]. Additionally, ZrO2 deposited by MOCVD has shown decent
behaviour [194].
Hence, further experiments were performed on a different epitaxial struc-
ture as compared to the one used in the previous section. Within the follow-
ing experiments, six samples were processed. Thereof, one sample serves
as a reference sample with a Ni/Au Schottky gate. The other five samples
were prepared by using the plasma-oxidation process as described in the
previous section. As discussed above, the metals used within this series
are Zr, Al and a double-layer stack of Al and Ti.16 The complete sample
list is given in Tab. 3.2. Based on previous experiments, which are not
described in detail here, an optimised oxidation process and an optimised
annealing temperature were chosen for each sample. Details on the oxida-
tion parameters and on the annealing temperature can be found in [182],
[185] for sample Al4, in [185], [195] for sample AlTi, in [185], [196] for
samples Zr3 and Zr5 and in [185] for sample AlTi2.
For characterisation of Cox of each sample, C-V measurements were per-
formed on large-area diodes at 1 MHz. The results can be found in Fig. 3.25.
The Schottky sample serves as a reference and hence, based on this sample,
Cox can be calculated for the plasma-oxidised samples. It is obvious that no
complete oxide was formed for sample Zr5. The capacitance of that sample
is similar to the one of the Schottky-gated sample. This indicates that there
is a physical limitation in metal layer oxide thickness which prevents the
formation of a thick oxide layer. Apart from sample Zr5, all samples show
a reduction in C and hence the formation of an insulation layer between
gate electrode and barrier is indicated. Moreover, it becomes visible that
for sample Al4, the lowest C is realised. This is in accordance with the
expectation, since for AlOx , the lowest value of ϸr is expected [193]. Sample
16
The processing for sample AlTi2 included evaporation of Al/Ti, plasma oxidation, evapor-
ation of Al/Ti, plasma oxidation and evaporation of Ni/Au. Hence, better insulation is
expected.

61
3 Engineering the Threshold Voltage in n-Channel Devices

Zr3 follows with ZrOx offering a higher ϸr and owing to the large contribu-
tion of Ti, C of sample AlTi lies even above the one of sample Zr3 [193]. For
sample AlTi2, it becomes visible that a higher C is obtained in comparison
to sample AlTi. Hence, it may be assumed that no complete oxidation was
obtained. The extracted values for Cox are plotted in Fig. 3.26.
Beside the differences in C, there is also a Vth shift. Whereas sample
AlTi2 and sample Al show a negative shift, samples Zr3 and AlTi show
a slightly positive shift. The exact values for Cox and Vth are plotted in
Fig. 3.26.17 The shift in Vth for sample Al4 relates very well to the results
shown in the previous section. For sample AlTi, a positive shift of +0.1 V is
extracted. This value equals the one presented in [195]. It is noted that for
sample Zr3, a Vth shift of +0.5 V is extracted, the highest Vth shift achieved
thus far in this set of experiments.
Apparently, fixed charges play a major role for the samples with plasma-
oxidised metal layers. Since no thickness variation was performed for the
different samples, Nox cannot be extracted and hence Nox and nit are lumped
into a single quantity, which is now called net sheet charge density nnet .
The electrostatic model derived in Sec. 3.1 needs to be simplified, because
of GaN cap and backbarrier not being present in the structure used for
these experiments. Using these simplifications, nnet can be calculated with
17
Since no complete oxide was formed for sample Zr5, it is left out in that comparison.

Table 3.2: Processed samples of the plasma oxidation series given with metal, metal
layer thickness, DC bias during plasma oxidation and annealing temper-
ature. All samples share the oxidation time of 10 min (except for sample
Zr5 for which it was 15 min) and ICP power during oxidation of 50 W.

Metal layer Annealing


Sample Metal thickness DC-bias temp.
(nm) (V) (◦ C)
Schottky - - - -
Al4 Al 4 -55 600
AlTi Al/Ti 1/4 -55 400
AlTi2 Al/Ti/Al/Ti 1/4/1/4 -55 400
Zr3 Zr 3 -90 600
Zr5 Zr 5 -110 600

62
3.6 Influence of Gate Insulation

Figure 3.25: C-V measurements of large-area diodes at f = 1 MHz for the different
samples. Solid line indicates the measurement from negative to pos-
itive voltage and the dotted line corresponds to the reverse direction.
After [197].

Coxide 1 P2
nnet = − (Vth,meas − (ΦB,n − ∆EC,AlGaN/GaN ) + ) (3.19)
q e Cmeas

However, the assumption that the difference between Schottky barrier


height and MIS barrier height is counterbalanced by the difference in con-
duction band offset between insulator and AlGaN barrier must be made.
This seems reasonable as only minor deviations have been reported in the
literature ([105] as cited in [185]). For the calculation, the values of ΦB,n
and P2 = σ b -σ ch (cf. Eq. 3.4 on p. 23) need to be known. In the given device
structure, P2 is calculated based on the C-V curve of the Schottky-gated
sample. By assuming a barrier height ΦB = ΦM,Ni - χ GaN = 5.1 eV - 4.2 eV = 0.9 eV,
the polarisation charge at the interface is estimated to be 1.53 µC/cm2
(corresponding to a charge density of 9.5×1012 cm−2 ). With the estimated
values of ΦB,n and P2 , the single quantity of nnet can be calculated for each
sample. As is shown in Fig. 3.27, different values are extracted for the
different samples. A change in ΦB,n could not be the reason for this large
difference [105]. More interesting is the fact that nnet does reach values
above P2 /e. If this net charge would only consist of charge located at the

63
3 Engineering the Threshold Voltage in n-Channel Devices

Figure 3.26: Extracted values for Vth and Cox . Data is extracted from C-V meas-
urements shown in Fig. 3.25. The orange line indicates Vth of the
Schottky-gated sample.

oxide-semiconductor interface (nnet = nit ,Nox = 0), this would eventually allow
to shift Vth to the positive only by increasing the oxide thickness [100].
To further illustrate this finding, Fig. 3.27 is discussed. Vth is shown as
a function of inverse Cox , that is vs. tox /ϸ ox . As is easily seen, for sample
2xAl/Ti and sample Al, more negative ∆Vth can be expected for increasing
tox . However, for sample Al/Ti and even more so for sample Zr, more
positive ∆Vth can be realised by adding a charge-free insulator on top of the
plasma-oxidised layer.
To investigate the insulating properties of the various plasma-oxidised
layers, leakage currents observed in the samples are discussed. The results
of I-V measurements on large-area diodes are shown in Fig. 3.28. The very
high leakage current of sample Zr5 is apparent. Hence, it can be concluded
that this sample was not fully oxidised and even more so, the gate contact
properties seem to be dominated by Zr. The latter is indicated by a shift
of the forward current onset towards smaller voltages. Based on this, a
smaller Schottky barrier height can be extracted which is in accordance
withvalues of Zr reported in the literature [198]. All other samples show
leakage current in reverse direction which is either equal or below the one of
the Schottky sample. In forward direction, all samples reveal a suppression
of leakage current within the used measurement range. The best results
here are obtained for sample Al4 and Zr3.
Summarising the C-V and I-V analysis, a thin plasma-oxidised Zr layer
seems to be an appropriate means to shift Vth to a more positive value and

64
3.6 Influence of Gate Insulation

Figure 3.27: Behaviour of Vth vs. inverse Cox for four different interface charge dens-
ities nit which were extracted for the four samples. The stars depict
the actual values extracted for the samples. The dashed line indicates
the case of the σ it matching the polarisation difference between barrier
and channel [185].

to improve the insulation characteristic of a device.


The Vth stability of MIS-HFETs with plasma-oxidised metal dielectric
was investigated for samples Zr3 and Al4. An exemplary stress meas-
urement for sample Zr3 with applied off-state stress conditions is shown
in Fig. 3.29a. Beside a very low off-state leakage current in the pA/mm
range, only a slight shift is seen when applying off-stress stress. In con-
trast to the results shown for ALD-AlOx , the evolution of Vth with stress
time is in the positive direction. The reduction of Id is most likely related to
the unpassivated state of the devices; it is thus caused by the virtual gate
effect [86].
From the extracted data shown in Fig. 3.29b, very large time constants
are also seen for the aforementioned stress condition. Since electron cap-
ture is rather improbable at negative gate bias18 , it is most likely that an
emission process of holes can be made responsible for the shift in Vth . How-
18
In off-state, there is negative bias throughout the gate region, in on-state there is negative
bias at least at the drain-side of the gate

65
3 Engineering the Threshold Voltage in n-Channel Devices

Figure 3.28: Current density vs. voltage of large-area diodes the samples with
plasma-oxidised metal layers. As a reference, the Schottky-gated
sample is also shown. After [197]

ever, the observed shift is considerably smaller than the one observed for
ALD-AlOx . In comparison to sample Zr3, sample Al4 exhibits a larger shift,
but again this one is occurring into the positive direction.
For a more detailed analysis of the plasma-oxidised metal layers which
allows for a separation of nit and Nox , a thickness variation would be ne-
cessary. Nonetheless, the results are very promising and it may be a very
viable alternative to combine the features of ALD-Al2 O3 and the plasma-
oxidised metal layer, that is combining the very good insulation property of
ALD-AlOx together with the positive Vth shift of a plasma-oxidised Zr layer.

66
3.7 Combination of Approaches

(a) (b)

Figure 3.29: (a) Transfer characteristics of an MIS-HFET of sample Zr3. The


measurement was performed as already discussed for the ALD-AlOx
samples. The off-state stress times are indicated with the colour in-
tensity. The second sweep for 0 s was performed immediately after the
1000 s measurement. (b) Extracted Vth vs. stress time for sample
Zr3 and sample Al4 at two different stress conditions in on- and
off-state. Device dimensions: Lsg = 2.0 µm, Lg = 2.0 µm, Lgd = 2.5 µm,
Wg = 2×50 µm.

3.7 Combination of Approaches


The final section concerning n-channel HFETs comprises a device series for
which all aforementioned methods to shift Vth were applied consecutively.
On the one hand, this serves as a means to verify the results from the pre-
vious sections and on the other hand, the combination effect is evaluated
and a final device showing real e-mode behaviour is targeted. Parts of the
results have been reported in [166].
Five samples were processed. For these, the schematic cross sections il-
lustrating the differences of the individual samples are depicted in Fig. 3.30.
The samples were mesa-isolated by a chlorine-based dry etch and ohmic
contacts were formed by a Ti/Al/Ni/Au stack. All samples feature the early
passivation process [95], [97] and the gates were processed with integrated
gate-connected field plates. A Ni-gated single HFET serves as a reference

67
3 Engineering the Threshold Voltage in n-Channel Devices

(a) (b) (c) (d) (e)

Figure 3.30: Schematic cross sections for the devices of the final series comprising
all methods. (a) Starting point, a Ni-gated single heterostructure FET.
(b) Pt-gate instead of Ni-gate. (c) Introduction of the Al0.07 Ga0.93 N back-
barrier. (d) Insertion of the ALD-AlOx gate insulator. (e) Employing of
the digital etch technique to recess the gate.

sample (device A, Fig. 3.30a). In a first step, the Ni gate is exchanged by


the Pt gate (device B, Fig. 3.30b) with higher work function (see Sec. 3.4).
The Pt-gated sample is also processed as a DHFET (device C, Fig. 3.30c).
Here, the GaN channel thickness was chosen to be 50 nm. As discussed
in Sec. 3.5, with this value, a good trade-off between Id and gm reduction
on the one hand and Vth shift on the other hand is obtained 19 . For the
double heterostructure, Fe dopant addition during epitaxy was performed
from the beginning of the growth until the growth of the first few nm of
the backbarrier. Hence, Fe is effectively hindering the formation of a para-
sitic 2DEG20 . The DHFET with Pt gate has also been processed with the
gate dielectric ALD-AlOx (device D, Fig. 3.30d). A 6 nm thick dielectric was
chosen as a good compromise between reduction of leakage current and a
negative Vth shift (cf. Sec. 3.6.1). In a final step, a gate recess based on
the digital etch technique was applied with a recess depth of about 15 nm
(device E, Fig. 3.30e).
Transfer characteristics for the devices are depicted in Fig. 3.31. Except
for device A, all devices were measured consecutively in forward and reverse
direction. Only very minor hysteresis effects are observed for the samples.
19
Both epitaxial layer stacks were grown by Ferdinand-Braun-Institut für Höchstfrequenztech-
nik, Berlin, Germany.
20
For more information of this aspect, refer to pp. 130 – 133 in the appendix.

68
3.7 Combination of Approaches

Figure 3.31: Transconductance and transfer characteristics measured in forward


and reverse direction (except for device A). After [166].

Device A offers Id and gm,max of about 450 mA/mm and 170 mS/mm, re-
spectively. Owing to the low Al content in the barrier, a low Vth value of
-1.0 V is extracted. For device B with the Pt-gate, Vth is shifted to a value
of -0.65 V. Hence, the result from Sec. 3.4 is confirmed. Further and also
confirming the result of Sec. 3.4, gm,max is enhanced for this sample. By
introducing the backbarrier with device C, a further shift in Vth by about
0.45 V is realised. As a trade-off, both Id,max as well as gm,max are reduced
by about 23 %. The off-state leakage current of transistors on the double
heterostructure using the improved epitaxial layer growth is as low as 1-
10 nA/mm, which is 4-5 orders of magnitude lower than devices on the
preceding epitaxial layer stack and about 3-4 orders of magnitude lower
than the device on the single heterostructure (cf. Sec. 3.5), hence verifying
improved carrier confinement and buffer isolation.
The insertion of ALD-AlOx as gate dielectric with device D leads to a
negative shift in Vth . This negative shift is counterbalancing the effects of
both Pt gate and backbarrier. Since this large negative shift is unexpected
from the electrostatics derived in Sec. 3.1 and since it is opposite to the
results in Sec. 3.6.1, it is discussed in detail on p. 70. Despite the increased
gate-channel separation, gm remains at the same level. This is likely to

69
3 Engineering the Threshold Voltage in n-Channel Devices

be related to an increased effective mobility in the 2DEG under the gate


contact which itself stems from reduced scattering effects in MOS-HFETs
compared to Schottky-gated HFETs [199]. By employing the gate recess to
reduce the gate-channel separation, a large positive Vth shift of more than
3 V is observed. Device E exhibits a positive Vth of 2.3 V, the value being
among the highest reported so far for GaN-based HFETs [35], [36]. gm is
slightly increased for this sample, which is however not as high as expected.
Id above 250 mA/mm is realised with this device. Additionally for device E,
off-state leakage currents below 1 nA/mm and subthreshold swings below
70 mV/dec are extracted (cf. Fig. 3.34).
The Vth shifts observed in the I-V measurements are analysed by means
of C-V measurements21 and the analytical expression of Eq. 3.18 derived
in Sec. 3.1. The C-V measurements of devices B - E at 1 MHz are depicted
in Fig. 3.32. Compared to the transfer characteristics, similar shifts in Vth
are observed. The extracted values for Vth are denoted in Tab. 3.3. Based
on these results, the influence of fixed bulk oxide and interface charge on
Vth for devices D and E is analysed. For that purpose, the interface charge
densities P1 , P2 and P3 are calculated on the basis of theoretical values
[53], [161]. For the given epitaxial layer stack, these fit quite well to the
experimental values. As discussed in Sec. 3.6.1, the barrier height ΦB,MIS
for devices D and E was assumed to be 3.3 eV with an associated ∆EC,MIS
of 2.16 V. In accordance to the results discussed in Sec. 3.6.1, Nox was
assumed to be +1.6×1019 cm−3 . By employing Eq. 3.18 (from p. 26), a large
difference between the fixed interface charge density of devices D and E is
found. Whereas for device D, a positive nit = +9.6×1012 cm−2 is calculated,
for device E a negative nit = -2.2×1013 cm−2 is extracted. It is noted that
both values fit very well to values obtained by using TCAD Sentaurus,
validating the derived electrostatic model [166]. The positive nit in device
D indicates that not only surface donors compensate for the polarisation
charge of the GaN cap, but also additional positive charge is present at
the oxide/semiconductor interface. The origin of this charge is not fully
clear yet. However, it may well be related to the positive bulk charge in the
oxide. For device E however, the negative nit needs be explained either by
a reduction of surface donor concentration or by the presence of oxygen
21
The presence of leakage current prevented a C-V characterisation of large-area diodes for
device E. The oxide was too thin for the obtained threshold voltage to suppress the leakage
current effectively for such a large diode region. Instead, transistors with a gate length of
10 µm were characterised.

70
3.7 Combination of Approaches

Figure 3.32: C-V characteristics of devices B - E measured at 1 MHz. For Device B,


C and D, large-area diodes were measured. For sample E, a transistor
with Lg = 10 µm was characterised.

on etch-induced N vacancies [200] in the AlGaN barrier itself. Whereas


the former has been demonstrated on Schottky-gated HFETs by using a
chlorine-based etch [167], the latter could have a similar effect as oxygen
excess in Al2 O3 [162]. Hence, it is concluded that a gate recess is not only
beneficial in increasing the gate-channel capacitance, but also in providing
a negative nit . Both allow for very high Vth to be obtained.
The performance of device E is further analysed with pulsed I-V char-
acteristics. For a comparison, device C is employed. The results for both
devices are depicted in Fig. 3.33. Both device show almost the same drain
current in DC and in unbiased pulsed mode. In the drain-biased mode,

Table 3.3: Extracted threshold voltages for devices B - E. Extracted oxide capacit-
ance and interface charge density for devices D and E.

Vth,meas Cox nit


Device (V) nF/cm2 (µC/cm2 )
B -1.03 - -
C -0.73 - -
D -1.34 1580 +9.6×1012
E +1.95 1580 -2.2×1013

71
3 Engineering the Threshold Voltage in n-Channel Devices

(a) (b)

Figure 3.33: Pulsed I-V measurements of (a) device C and (b) device E. Tran-
sistor dimensions were Lsg = 1.5 µm, Lg = 1.0 µm, Lgd = 2.5 µm and
Wg = 2×50 µm. Pulse time = 200 ns, cycle time = 1 ms. After [166].

both devices suffer only from minor current collapse. The effect of knee
walkout is even less pronounced for device E. Similar to the results of
Sec. 3.3, this indicates again the superiority of the gate recess in terms
of dynamic behaviour. Based on these results, the ratios Rds-on,dyn /Rds-on
are calculated for the devices. Whereas for device C, a ratio of 1.24 (with
Rds-on,dyn = 8.8 Ωmm) is obtained, for device E it is only 1.16 (with Rds-on,dyn = 8.0 Ωmm).
Compared to the results of Sec. 3.3, the value here is slightly higher which
may be related to the buffer design.
As was described in Sec. 3.6.1, a significant Vth shift was observed for the
samples with ALD-AlOx . To verify the stability for device E, transfer char-
acteristics shown in semi-logarithmic scale in Fig. 3.34 are analysed for a
pristine device directly before and directly after pulsing. The measurements
were performed in forward (solid) and reverse (dashed) direction. For the
pristine device, a significant hysteresis is observed. At positive gate bias,
electron capture is very likely to occur [198]. The electrons are likely to be
injected into donor-like trap states, hence, causing this positive Vth shift.
However, for the second measurement, this large hysteresis is diminished.
Only a minor hysteresis of about 80 mV is measured. After performing
the pulsed I-V measurements including the off-state stress, the transfer

72
3.7 Combination of Approaches

Figure 3.34: Transfer characteristics of device E for a pristine device, for a second
measurement before a pulsed I-V measurement and a third measure-
ment immediately after the pulsed I-V measurement. After [166].

characteristics are almost identical. Compared to the measurement before


pulsing, only a minor negative shift of 50 mV (with a hysteresis of 70 mV) is
seen. Hence, the device may offer sufficient stability in a real application.
In summary, by combining all approaches, a well performing e-mode
device with a reasonably high Vth together with decent DC and dynamic
performance has been successfully demonstrated.

73
4 GaN-based p-Channel Devices
GaN-based p-channel devices have attracted much less attention than their
n-channel counterparts. With an effective mass of holes being in the range
of 1.1-2.0·m0 [61], [201], p-channel device fabrication appears – on a first
glance – not very promising. Maximum reported values for hole mobilities
thus far have been about 24 cm2 /(V·s) for very lightly doped p-GaN [202]
and about 18 cm2 /(V·s) in a 2-D hole gas (2DHG) [203], the latter value
being about a factor of 100 lower than the mobility of electrons in a 2DEG
[54]. Yet, these values are also far below the predicted ones of about
100 cm2 /(V·s) ([204], [205] as cited in [44]), and a moderate mobility is not
necessarily a huge drawback for certain types of application such as gate
drivers [77], [206]. Furthermore, there is indeed a need for understanding
the working principle and the fundamental limitations of p-channel devices
as such devices would allow for a variety of applications not accessible to
date with GaN. Examples are complementary logic, voltage amplification
circuits or gate drivers for power-switching applications.
p-Channel devices can – in analogy with n-channel devices – rely on the
presence of a 2-D gas, which is in this case a 2DHG. This 2DHG can be
formed similarly to the 2DEG by a polarisation difference at a heteroint-
erface. The difference between the formation of 2DEG and 2DHG is that
for a 2DHG, the low bandgap, low polarisation material needs to be on
top of the high bandgap, high polarisation material. Several groups have
studied 2DHG properties so far [41]–[45]. It has already been proven by
temperature-dependent van der Pauw and Hall measurements that indeed
the carrier concentration in a 2DHG is temperature-independent as one
would expect for a polarisation-induced channel [44]. Based on the pres-
ence of such a 2DHG, also transistor fabrication should be possible in a
way similar to the one of n-channel devices. Yet, the devices which have
been presented so far lack either high currents and/or reasonable on/off
ratios together with steep turn-on characteristics [46]–[48]. All these char-
acteristics are mandatory for p-channel device applications. Furthermore,
the actual verification of the polarisation to be the main reason for the

75
4 GaN-based p-Channel Devices

presence of the 2DHG is yet missing. Hence, the main purpose of this part
of the thesis is to improve the understanding of 2DHG formation, to in-
crease transistor performance by comprehensive optimisation studies and
to improve the characterisation level of p-channel devices.
In this chapter, GaN-based p-channel devices are studied on the basis
of a double heterostructure which features both 2DHG and 2DEG. The
basic stack used throughout all experiments in this chapter is depicted in
Fig. 4.1a. On the basis of this structure, electrostatic equations to obtain
expressions for the 2DHG density ps and for the threshold voltage Vth of
p-channel devices are derived. The expected influence of 2DHG on 2DEG
and vice versa are outlined. Next, the basic stack shown in Fig. 4.1a is
optimised and the optimised and more sophisticated stack is discussed.
On this basis, experiments concerning ohmic contact formation and gate
metallisation are presented. The origin of leakage currents is discussed
and approaches to prevent them are applied. Based on an optimised device
structure, state-of-the-art device performance is shown and the effects of
a gate recess and of a variation of the polarisation of the barrier on device
characteristics is analysed. To gain insight into the mutual dependence
of 2DEG and 2DHG seen in the electrostatic equations, experimental C-V
characteristics are discussed and compared with equivalent-circuit models.
A first report on small-signal characteristics and a high-temperature device
performance analysis finalise this chapter.

4.1 The Two-Dimensional Hole Gas


In analogy with the equations derived in Sec. 3.1, the equations for a p-
channel HFET can be obtained. For the formation of a 2DHG, a negative
polarisation difference at an interface is required. A structure suitable for
this purpose is shown in Fig. 4.1a. The structure consists of a GaN buffer
(in the following called n-channel region), a barrier and a top GaN layer (in
the following called p-channel region). GaN above and below the barrier
leads to two effects; first, above the barrier, the required negative polarisa-
tion difference is obtained and second, the polarisation charge density at
the upper and lower interface are equal in size (|σ b - σ ch,p | = |σ ch,n - σ b |),
turning electrostatics considerably easier. A band diagram of such a struc-
ture simulated using TCAD Sentaurus [79] is depicted in Fig. 4.1b with
associated boundary conditions and interface charges. To be able to derive

76
4.1 The Two-Dimensional Hole Gas

p-Channel
+++++++++++++

Barrier
-------------

n-Channel
≈ ≈

(a) (b)

Figure 4.1: (a) Epitaxial layer stack comprising n-region, barrier and p-region. A
2DEG and a 2DHG are formed below and above the heterointerface,
respectively. (b) Band diagram of this epitaxial layer stack. Conduction
and valence band are shown together with the accumulated 2DHG (blue)
and 2DEG (red) concentrations. Interfaces are depicted with associated
polarisation charges.

an analytical expression for the 2DHG density, Gauss’ Law is applied with
the charge at each interface from the left to the right. The electric field is
assumed to be zero outside of the structure. Additionally, the presence of
dopants is neglected for the derivation. Hence, the following equations are
obtained at the surface, the p-channel/barrier, the barrier/n-channel and
the n-channel/bottom interface, respectively

ϸch,p Ech,p = σs1 − σch,p (4.1)

ϸb Eb − ϸch,p Ech,p = σch,p + σp − σb (4.2)

77
4 GaN-based p-Channel Devices

ϸch,n Ech,n − ϸb Eb = σb − σch,n − σn (4.3)

0 − ϸch,n Ech,n = σch,n − σs2 (4.4)

for which σ s1 , σ s2 correspond to the top and bottom surface charge dens-
ity, respectively. σ b , σ ch,n and σ ch,p represent the total polarisation charge
density of barrier material and upper and lower GaN (the latter two be-
ing equal in size), respectively. σ n and σ p denote the electron and hole
charge density, respectively, and finally, ϸ index and Eindex are the specific
permittivity and electric field for each given region with indexes ch,p , b and
ch,n denoting p-channel, barrier and n-channel region, respectively. The
charge neutrality condition is given by

σp − σn = σs1 − σs2 (4.5)

In addition to the equations above, the following ones are derived by


moving along the valence band edge from the surface to the left-hand side
of the quantum well and from the left-hand side of the quantum well to the
bottom of the structure, respectively

ΦB,p
− + tch,p Ech,p = 0 (4.6)
e

∆p ∆EV 1 ∆EV 2 Φp
− + tb E b + + tch,n Ech,n + =0 (4.7)
e e e e

with e being the elementary charge and ΦB,p denoting the Schottky bar-
rier height, assuming the existence of metal on top of the semiconductor
surface. In the case of a free surface, ΦB,p needs to be replaced by the
surface potential ΦS . tindex denotes the thickness of the corresponding
layers as mentioned above. ∆EV1 and ∆EV2 reflect the valence band edge
differences. Φp represents the potential at the backside of the GaN buffer.

∆p represents the height of the valence band edge quantum well above
the Fermi level and can be expressed with the following equation (assuming

78
4.1 The Two-Dimensional Hole Gas

only the first discrete energy level to be occupied) [80]:

π ~2
∆p = ps (4.8)
m∗

in which ~ is Planck’s constant, m* the effective mass of the holes in the


channel and ps the sheet carrier concentration in a 2DHG.
In the case of GaN below and above the barrier, Eq. 4.7 can be simplified
with ∆EV1 = ∆EV2 leading to

∆p Φp
+ tb Eb + tch,n Ech,n + =0 (4.9)
e e

Eq. 4.2 together with Eq. 4.6 can be rewritten as

1 ΦB,p
tb E b = · (Cch,p + σch,p + σp − σb ) (4.10)
Cb e

Additionally, Eqs. 4.2, 4.3 and 4.6 are rearranged to

1 ΦB,p
tch,n Ech,n = · (Cch,p + σ p − σn ) (4.11)
Cch,n e

Eqs. 4.10 and 4.11 are inserted into Eq. 4.9 and the resulting equation
is solved for ps
Cb Cb
1 σb − σch,p − Cch,p ΦB,p (1 + Cch,n
)+ Cch,n
σn − Cb Φp
ps = π ~2 Cb
(4.12)
e 1+ Cb em ∗ + Cch,n

This final equation is longish and it is not directly clear by which para-
meter ps is influenced most. Eq. 4.12 can be simplified for the device struc-
ture used for the later experiments. In the given structure, the n-channel
layer is much thicker than the barrier layer and the p-channel layer on top,
hence Cch,p >> Cch,n and Cb >> Cch,n . Additionally, the absolute value of
the term π ~ 2 ·(em* )−1 is much smaller than 1. Applying these two simplific-
ations to Eq. 4.12, a much shorter form is derived and can be applied as a
first-order approximation.

79
4 GaN-based p-Channel Devices

σn ΦB,p
ps ≈ − Cch,p (4.13)
e e

Now, ps depends only on the 2DEG density (ns = σ n ·e −1 ) below the barrier
and the surface depletion term expressed by p-type Schottky barrier and p-
channel capacitance. The density of the 2DEG however is fixed as long as a
2DHG is present [207]. With both conduction band EC and valence band EV
crossing the Fermi level, the band slopes in between these crossing points
are fixed. Hence, the depth of the 2DEG quantum well cannot change,
thereby fixing the electron concentration. The hole concentration however
can be modulated by applying a potential to the surface1 or by increasing
Cch,p as has been shown in [207]. Based on TCAD Sentaurus simulations
[79], this effect is illustrated in Fig. 4.2. Fig. 4.2a shows the band diagrams
for different voltages (similar to Fig. 2.4 on p. 14) indicating the fixed band
slopes. In Fig. 4.2b, the extracted electron and hole concentrations are
plotted vs. the gate-source voltage Vgs . It is clearly seen that the n-channel
concentration is constant as long as a 2DHG exists. Only after the 2DHG
is depleted, the 2DEG concentration is increasing. Hence, it is also seen
that it is not possible to deplete the 2DEG by applying a voltage at the
top of the structure. This effect can be exploited for n-channel devices.
By eliminating the surface-sensitivity of the 2DEG in the access region
("virtual gate" effect [86]), improved results for the dynamic behaviour are
expected. A first study on the consequences of a fixed 2DEG concentration
on dynamic device performance has been performed in [207].
With this verified assumption of a fixed σ n , Vth then can be calculated
by setting ps to zero and adding the voltage term Vth to ΦB,p . The resulting
equation is

ΦB,p σn
Vth ≈ − + (4.14)
e Cch,p

This means that threshold voltage engineering for p-channel devices on


the given layer stack is possible by three different approaches which are

1. increasing the barrier height (work function engineering, as discussed


1
Indeed, the 2DEG density could be modulated by a potential at the backside which due to
practical reasons is not considered here.

80
4.1 The Two-Dimensional Hole Gas

(a) (b)

Figure 4.2: (a) Simulated band diagrams of a structure with an Al0.42 In0.03 Ga0.55 N
barrier in dependence on gate-source voltage. Clearly visible is the fixed
2DEG quantum well as long as the 2DHG quantum well is present. (b)
Extracted electron and hole concentration illustrating the behaviour
which is observed in (a).

for n-channel devices in Sec. 3.4),

2. increasing the p-channel capacitance (gate recess, as discussed for


n-channel devices in Sec. 3.3),

3. reducing the 2DEG density (low polarisation in the barrier).

Similar to the structure in Chap. 3, these three different approaches 1, 2


and 3 are discussed separately.

Electrostatics for single heterostructure with a 2DHG only The simplest case to
form an expression for the 2DHG density is obtained with a single hetero-
structure in which GaN is on top of a barrier. For this case, the barrier
would typically be thicker than the channel and hence, Cch,n would go to

81
4 GaN-based p-Channel Devices

infinity. Thus, Eq. 4.12 can be simplified to


ΦB,p Φp
1 σb − σch,p − Cch,p e
− Cb e
ps = π~ 2
(4.15)
e 1 + Cb em ∗

However, since the bottom heterostructure with ∆EV2 does not exist in this
case, ∆EV1 needs to be accounted for. Thus, the final equation
ΦB,p Φp ∆EV 1
1 σb − σch,p − Cch,p e
− Cb ( e
− e
)
ps = π ~2
(4.16)
e 1 + Cb em ∗

is almost equivalent to Eq. 2.9 of the n-channel structure derived in


Sec. 2.3. Only, ∆EV1 is now related to the capacitance of the lower layer
which can be easily understood by taking a look at the band diagram.
To calculate Vth for the single heterostructure, again the term Vth is
subtracted from ΦB,p , ps is set to zero and the resulting equation is solved
for Vth

ΦB,p σb − σch,p Cb Φp EV 1
Vth = − + − ( + ) (4.17)
e Cch,p Cch,p e e

Similar to the discussion for n-channel devices, in the p-channel single


heterostructure, Vth is limited to an upper boundary of -ΦB,p ·e −1 . However,
due to the high bandgap of GaN in conjunction with its high electron affin-
ity, very high values of ΦB,p [111] are allowed. Furthermore, due to possible
applications for p-channel devices not involving power-switching, this limit
is sufficiently high.

4.2 Optimisation of p-Channel Devices


Since only a very limited number of studies have been performed on p-
channel devices, it is necessary to conduct fundamental studies, such as
on the contacts of a transistor and limiting mechanism of leakage current.
Hence, after a discussion of the epitaxial layer stack used for p-channel
HFET fabrication, the optimisation of the ohmic contacts and the gate
contact is described in this section. The presence of leakage currents and

82
4.2 Optimisation of p-Channel Devices

measures to prevent them from flowing are discussed in-depth.

4.2.1 Epitaxial Layer Stack


Other than for the n-channel devices presented in Chap. 3, the epitaxial
layer stack used for the p-channel devices was grown in-house. This al-
lowed for the quick development of a structure which was capable of the
demonstration of state-of-the-art performance. The epitaxial layer stack is
shown in Fig. 4.3. The four bottom layers, namely, Sapphire, AlN, GaN and
Alx Iny Ga1−x−y N form a conventional heterostructure suitable for n-channel
device fabrication. The composition of the AlInGaN layer was varied as
listed in Tab. 4.1. Hence, with different concentrations of Al, Ga and In,
it was possible to obtain different polarisation differences between barrier
and buffer. On top of the quaternary layer, several GaN layers with different
doping levels were deposited. Since hole accumulation is occurring at the
upper GaN/AlInGaN interface, the first GaN layer with a thickness of 3 nm
is undoped. This reduces scattering at ionised impurities and hence allows
for a high hole mobility µ p . The second layer is lightly doped with Mg. As
the background doping in MOCVD-grown GaN is of n-type [208], [209] and,
thus, hinders the formation of a 2DHG, the p-type doping compensating
for the background donors is a necessity when realising the formation of a
2DHG via MOCVD growth. The necessity of p-type doping for the formation
of a 2DHG has been experimentally confirmed by comparing Hall and van
der Pauw characteristics from growth runs with different doping levels as
has been discussed in [210]. During the growth of the third layer, the Mg
doping concentration was first ramped up and with its final value, another
5 nm of highly Mg-doped GaN was grown. The last two layers are intended
to enable the formation of low-resistive ohmic contacts. The latter is typ-
ically a function of majority carrier concentration as has also been shown
for p-channel ohmic contacts in the literature [211]. Although nominally
a constant Mg concentration was applied for the topmost layer, the Mg
concentration constantly increases in the final stack. This effect has been
confirmed by secondary ion mass spectroscopy [210]. Therefore, both lay-
ers are summed up to a single one in the device schematic. A very high
doping concentration of 1019 up to 1021 cm−3 was realised in the uppermost
6-7 nm [210]. This highly doped layer, however, will severely affect device
characteristics such as leakage currents present in the device. Hence, the
effect of this layer is investigated in Sec. 4.2.4.

83
4 GaN-based p-Channel Devices

Graded GaN:Mg++ 7 nm
GaN:Mg (p ~ 1016 cm-3) 23 nm
2DHG +++++++++ uid-GaN +++++++++ 3 nm
AlxInyGa1-x-yN 35 nm
2DEG ---------------------------
GaN ~ 2.0 µm
AlN ~ 0.3 µm
Sapphire

Figure 4.3: Epitaxial layer stack for all p-channel devices. The various compositions
of the Alx Iny Ga1−x−y N backbarrier are shown in Tab. 4.1. A detailed
analysis of doping concentrations can be found in [210]. After [210].

During analysis of several device characteristics in the following sections,


five different backbarrier compositions resulting in different polarisations
are employed. The epitaxial layer stacks are named in order of the polar-
isation of the backbarrier, with sample α featuring the lowest polarisation
and sample ϸ the highest. The samples are listed in Tab. 4.1 with their cor-
responding sheet carrier density ps and µ p . An extensive characterisation
of the different layers has been performed in [210].

Table 4.1: Epitaxially grown layer stacks with associated backbarrier compositions.
Additionally given are polarisation difference between barrier and GaN
channel (σ int ) [210], sheet hole densities, hole mobilities and sheet resist-
ances.

Backbarrier σ int ps µp Rsh


Sample composition (C/cm2 ) (cm−2 ) (cm2 /(V·s)) (kΩ/sq.)
α Al0.14 In0.02 Ga0.84 N -0.006 6.4×1011 23 430
̙ Al0.20 In0.02 Ga0.78 N -0.010 1.2×1012 29 180
γ Al0.25 In0.02 Ga0.73 N -0.014 2.2×1012 30 91
δ Al0.42 In0.03 Ga0.55 N -0.027 9.8×1012 19 34
ϸ Al0.54 In0.04 Ga0.42 N -0.036 2.0×1013 12 26

84
4.2 Optimisation of p-Channel Devices

4.2.2 Ohmic Contact Formation


The realisation of ohmic contacts on p-type group-III nitride material e.g.
for light emitting diodes has been performed with a wide variety of meth-
ods [212]. For contacting a 2DHG, however, experimental results have been
only sparsely reported. According to publications dealing with p-channel
HFETs, ohmic contacts have been realised by different schemes, thereun-
der Pd(5 nm)/Au(5 nm) [46], Ni(10 nm)/Au(20 nm) [47] and Ni(10 nm)/Au(5 nm)
[48]. Despite the different metal schemes, an annealing step has always
been reported to be performed in an O2 -rich ambient.
Employing sample ϸ, which is listed in Tab. 4.1, ohmic contact formation
was investigated using several metal schemes. Beside the above mentioned
Pd/Au and Ni/Au stack, Pt/Au and NiO(/Ni)/Au stacks were employed for
the investigation. The latter stack was fabricated using a plasma oxidation
step similar to the one discussed in Sec. 3.6.2. The contacts were annealed
using different temperatures both in O2 -rich as well as in N2 atmosphere.
A compilation of the complete study can be found in [213].
Overall, Ni/Au contacts have shown the lowest contact resistivity of all
stacks. For this stack, a Ni:Au thickness ratio of 1:1 and an annealing
step at 535 ◦ C in O2 -rich atmosphere have been found to be optimal. The
specific contact resistivity ρc realised for the samples with a 2DHG density
ps of 1–2×1013 cm−2 was as low as 7.3×10−4 Ωcm2 . This is within the range
of published values (7×10−3 – 4×10−6 Ωcm2 ) for Ni/Au stacks annealed in
O2 or O2 -rich ambient [214]–[216]. For the samples with low sheet carrier
concentrations of 2×1012 cm−2 or below, ρc increased to values between
1.7×10−3 Ωcm2 (sample γ) to 1.3×10−2 Ωcm2 (sample ϸ).

4.2.3 Gate Metallisation


Similar to ohmic contacts, the knowledge of Schottky contacts on p-channel
HFETs is very limited. In theory, a low metal work function is necessary
to obtain a high p-type Schottky barrier height. However, reactions of the
gate metal and the semiconductor are to be avoided and, thus, metals such
as Ti and Al may not be suitable to form a proper Schottky contact for a
p-channel HFET. In [47] and [48], Ni/Au is used as gate electrode. This is
similar to n-channel devices for which Ni/Au is the most commonly used
gate stack. However, Ni with its work function of about 5.15 eV [137] may
be less suited as Schottky gate metal than other metals such as Mo or

85
4 GaN-based p-Channel Devices

Zr with lower work functions of 4.35-4.7 eV and 4.1 eV, respectively [198],
[217]. This is underlined by the high gate leakage currents reported for the
Ni/Au stack [47], [48].
For the investigation of the Schottky contact behaviour, sample γ has
been employed with different gate metallisations. Three samples were pre-
pared with either a Zr/Au, a Mo/Au or a Ni/Au stack (each 50 nm/200 nm).
The samples were analysed by means of I-V characterisation of large-area
diodes and HFETs.
I-V characteristics of large-area diodes are depicted in Fig. 4.4a. In re-
verse direction (positive voltages), all diodes show about the same leakage
current density independent of the gate metallisation. The total value of
about 1×10−5 A·cm−2 at V = 6 V is well below the current density in forward
direction. This indicates a proper rectification of the gate diode. In con-
trast to the reverse direction, in the forward direction, distinct differences
are seen between the Ni, Mo and Zr gate, respectively. According to the dif-
ferent expected Schottky barrier heights, the current onset of the various
gate diodes depends on the metal work function and occurs for the Ni gate
at the lowest voltage values. The Zr gate shows the current onset at the
highest voltage values.
Based on these forward I-V characteristics, the Schottky barrier height
ΦB,p and the ideality factor n were extracted using the linear fit approach,
for which ΦB,p and n depend on the y-axis intercept and slope, respect-
ively2 [126]. The results are plotted in Fig. 4.4b showing mean values and
standard deviation. ΦB,p values of 1.09, 1.29 and 1.43 eV were extracted
for the Ni, Mo and Zr gate, respectively. Although the difference is not as
high as expected from the differences in metal work function, they demon-
strate once again that the Fermi level in GaN-based semiconductor-metal
interfaces is at least not fully pinned (cf. Section 3.4). It is noted here that
the ideality factor is rather high with values of above 2. Hence, it is as-
sumed that thermionic emission is not the only current mechanism [126]
and tunnelling by e.g. a trap-assisted tunnelling process is likely to play a
role. This assumption has been indicated by a temperature-dependent I-V
characterisation of large-area diodes [218].
Considering the shown results, the Zr gate appears to be most appro-
priate for the realisation of p-channel HFETs. To investigate this further,

2
Since regions with a low ΦB,p dominate the gate current, the extracted values of ΦB,p by
this method can only reflect the lower limit.

86
4.2 Optimisation of p-Channel Devices

(a) (b)

Figure 4.4: (a) Current density vs. voltage characteristics of large-area diodes for
samples with Ni, Mo and Zr metallisation. (b) Extracted values for the
Schottky barrier height and the ideality factor.

transfer characteristics plotted in Fig. 4.5 in semi-logarithmic scale are eval-


uated for the different gate metallisations. The Ni- and Mo-gated transistors
show reasonable transfer characteristics with steep subthreshold slopes
and high on/off ratios. For the Zr-gated devices, however, the drain leak-
age current is well above the gate leakage current in the off-state, leading
to a device which cannot be pinched off. Based on the results of the other
two samples, buffer leakage can be excluded for this epitaxial layer stack.
Hence, it has to be assumed that a large number of interface states in a
far-from-ideal interface causes this behaviour [89]. The formation of a thin
interfacial oxide between Zr and GaN may be the reason for this effect.
Further investigation of the transfer characteristics leads to an important
additional result. The pinch-off voltages Vp of the Ni- and Mo-gated samples
differ by 0.8 V, about the difference in metal work function ∆ΦM between
Ni and Mo. Hence, it shows that despite the small changes in effective
ΦB,p extracted from the large-area diode I-V characteristics, the transfer

87
4 GaN-based p-Channel Devices

Figure 4.5: Transfer characteristics of transistors for samples with Ni, Mo and Zr
metallisation.

of ∆ΦM to ∆Vth occurs with a ratio of 1. This indicates the absence of


Fermi level pinning [77]. Additionally, the Mo-gated sample exhibits a
steeper subthreshold behaviour with a value of only 86 mV/dec compared
to 114 mV/dec for the Ni-gated device. It also features a lower off-state
leakage current by about one order of magnitude. In summary, Mo is
found to be the most suitable gate metal (out of the three investigated in
this experiment) for the use in a Schottky-gated p-channel HFET.

4.2.4 Optimisation of Leakage Currents


In the previous experiments, ohmic and gate contacts have been evaluated.
Using the low-resistive Ni/Au ohmic contacts and the Mo/Au Schottky gate
contact with its high value of ΦB,p , transistor structures were processed
for a deeper characterisation of leakage currents present in the device.
The focus of this analysis is on the highly Mg-doped GaN layer on top
of the structure which is expected to affect leakage current severely. The
influence of its presence beside and beneath the gate contact on the leakage
and the gate current is investigated on the basis of devices of sample α and
γ, respectively. The results discussed have already been published [111].

88
4.2 Optimisation of p-Channel Devices

(a) (b)

Figure 4.6: Sample α: (a) Transfer characteristics and gate currents of transistors
with different recess depth in the access region. [111] (b) Extracted
values of the drain current and gate leakage current in dependence on
access region recess depth. [111]

Access region recess To investigate the influence of the highly Mg-doped


GaN layer beside the gate on device characteristics, devices were fabricated
by means of mesa isolation, ohmic and gate metallisation. Thereafter, the
region between ohmic and gate contact was recessed using the digital etch
process [104]. Transfer characteristics of three processed samples with
access region recess depths of 0, 6 and 12 nm are depicted in Fig. 4.6a.
For the unrecessed device (squares), the gate current becomes equal to the
drain leakage current at about Vgs = -4 V. By applying a recess of 6 nm, the
gate leakage current at this gate voltage is reduced by 5 orders of mag-
nitude. However, also the drain current is reduced by a factor of 10. The
latter reduction is indicated by TCAD Sentaurus simulations (not shown)
which show for the recessed sample a strong decrease in hole density below
the surface. Whereas for the device without recess, holes are distributed
from just below the surface down to the GaN/AlInGaN interface, for the

89
4 GaN-based p-Channel Devices

device with access region recess, only the 2DHG remains present (total
hole density reduced from 3.5×1011 cm−2 to 1.0×1011 cm−2 ). Hence, for the
device without access region recess, a significant part of the drain cur-
rent may actually flow below the surface. For the deeper recess depth of
12 nm, the drain current drops more significantly, while the gate current
is reduced less strongly. Here, the 2DHG is already completely vanished
because of the surface depletion effect (-Cch,p ·ΦB,p ·e −1 in Eq. 4.13 on p. 80)
which is apparently much stronger than in n-channel devices due to the
high values of ΦB,p . This is again verified by TCAD Sentaurus simulations
which show a hole concentration in the order of 106 cm−2 (not shown).
In Fig. 4.6b, extracted values for |Id | and |Ig | at a gate-source voltage
of -3 V are shown. By analysing this data, the optimal access region re-
cess depth is identified to be 6 nm. While it is not possible to suppress
the forward gate current with less recess depth, larger recess depths lead
to strongly reduced on-state Id . Considering results from secondary ion
mass spectroscopy (SIMS) which reveal the exact concentration of Mg in
the epitaxial layer stack [210], it is obvious that the highest value of Mg
concentration is present in the upper 6 nm. Owing to this very high Mg con-
centration, the valence band is very close to the Fermi level in the access
region near the surface (solid black and red curves in Fig. 4.7a). Hence, a
parasitic channel is formed (as indicated in Fig. 4.7b top). Whereas this
channel can easily be contacted by the ohmic contacts, it is blocked by the
gate electrode in reverse direction or without external bias (black curves in
Fig. 4.7a). However, as soon as a negative Vgs is applied, the gate potential
rises with respect to the Fermi level and a direct leakage path is created
between ohmic and gate contact. This effect is illustrated by the red curves
in Fig. 4.7a. By recessing this region, the hole density can be reduced con-
siderably (blue curve in Fig. 4.7a), hence hindering leakage current to flow
(Fig. 4.7b bottom).

Shallow gate recess In the literature, tunnelling transmission through deep-


level defects forming a sub-band has been reported to allow for current to
flow in highly Mg-doped GaN layers [211]. In the used layer structure, this
effect is very likely to cause parasitic leakage currents when the GaN:Mg++
layer is beneath the gate contact. To investigate the magnitude of this effect,
two samples based on sample γ were fabricated. Thereof, one sample was
processed without gate recess (GaN:Mg++ beneath the gate) and another

90
4.2 Optimisation of p-Channel Devices

Surface channel
S G D
++++++ +++++++
Graded GaN:Mg++
GaN:Mg
+++++ uid-GaN +++++
AlInGaN
S G D

Graded GaN:Mg++
GaN:Mg
+++++ uid-GaN+++++
AlInGaN

(a) (b)

Figure 4.7: (a) Valence bands (solid) and hole concentrations (dashed) in the ac-
cess and gate region just beneath the surface. Three different condi-
tions are shown: Vgs = 0 V (black) and Vgs = -2 V (red) for the schematic
shown in (b) top; Vgs = -2 V for the schematic shown in (b) bottom (blue).
(b) Schematics of the device structure with (top) and without (bottom)
highly Mg-doped GaN layer (top).

sample was fabricated using a low-power BCl3 /Ar gate recess with a depth
of 7 nm. Schematics of these samples are depicted in Fig. 4.8a.
Transfer characteristics for the two samples are depicted in Fig. 4.8b. It
can be seen that the saturated on-state current is almost the same for
both samples. However, in off-state, a reduction in leakage current by
nearly 5 orders of magnitude is realised by the removal of the GaN:Mg++
beneath the gate. As is seen from the gate current, this is completely
driven by a reduction in gate leakage. The reason for this is found in a
reduced acceptor concentration below the gate, therefore preventing the
above mentioned tunnelling transmission to occur. Schottky behaviour
with thermionic emission is now dominating. In addition, N vacancies
are likely to be created by the dry etch process. These vacancies form
donor states in the p-GaN and thus, effectively compensate the p-type
doping. Owing to the reduced leakage current, the subthreshold swing
is also strongly reduced. A value of about 93 mV/dec as mean over 3
decades is extracted for the recessed device. In forward direction, the

91
4 GaN-based p-Channel Devices

S G D
++++++ +++++++
Graded GaN:Mg ++

GaN:Mg
+++++ uid-GaN +++++
AlInGaN
S D
+++++ G +++++++
Graded GaN:Mg++
GaN:Mg
+++++ uid-GaN+++++
AlInGaN

(a) (b)

Figure 4.8: (a) Schematic of devices with (top) and without (bottom) the GaN:Mg++
layer beneath the gate. The devices are based on sample γ. (b) Transfer
characteristics and gate currents of these two samples. Device dimen-
sions: Lsg = 1.5 µm, Lg = 1.0 µm, Lgd = 2.5 µm, Wg = 2x50 µm [111].

device also benefits from the improved metal/semiconductor interface, and


the gate current at e.g. Vgs = -3 V is reduced by about 3 orders of magnitude.
Although this indicates an increase in Schottky barrier height, this value
should not change for the devices investigated here.

4.3 Fabrication of Enhancement Mode p-Channel


Devices
Obtaining e-mode behaviour is crucial for the utilisation of p-channel
devices in digital logic circuits based on complementary devices [219]. Since
p-channel devices are typically of d-mode behaviour, Vth needs to be engin-
eered. Hence, in the following section, such engineering is in the focus. As
has been discussed in Sec. 4.1, this can e.g. be realised by increasing the
p-channel capacitance, but also by reducing the polarisation in the barrier.
Hence, both approaches, gate recessing as was discussed for n-channel
devices in Sec. 3.3 and polarisation engineering of the backbarrier are sys-
tematically analysed. Beside shifts in Vth , also other DC parameters such

92
4.3 Fabrication of Enhancement Mode p-Channel Devices

as subthreshold swing (SS) and leakage currents are investigated.

4.3.1 Gate Recess


As shown in Sec. 4.1, ps and Vth depend on the top GaN layer thickness.
Hence, a gate recess is an effective approach for the realisation of e-mode
p-channel devices. For n-channel devices, the gate recess has already been
discussed based on the digital etch recess (cf. Sec. 3.3). For p-channel
devices, no early passivation process is applied at this early development
stage. Furthermore, the oxygen cycle in the digital etch process in com-
bination with photoresist masks is problematic. The oxygen cycle typic-
ally ashes the resist and a proper etching is not ensured. Therefore, a
low-power BCl3 /Ar etch process is employed for p-channel gate recessing
[123].
Before the characterisation of the final devices, band diagrams were cal-
culated with TCAD Sentaurus [79]. The calculations are based on the epi-
taxial structure and recess depths applied during processing. The samples
used for the experiments were fabricated on pieces of samples γ. The re-
cess depths were 7, 14 and 21 nm for samples γ-GR7, γ-GR14 and γ-GR21,
respectively. In Fig. 4.9, all band diagrams with associated charge dens-
ities of electrons and holes are plotted. For ease of understanding, cross
sections of the final devices structure are also shown. In the band diagram
of sample γ-GR7 (Fig. 4.9a), both valence band EV and conduction band EC
cross the Fermi level. Hence, both a 2DHG with a density of 1.0×1012 cm−2
and a 2DEG with a density of 4.9×1012 cm−2 are accumulated. For samples
γ-GR14 and γ-GR21, no accumulation of a 2DHG is observed in the sim-
ulation. This indicates e-mode behaviour. Additionally, the 2DEG concen-
tration increases for these two samples up to 6.4×1012 cm−2 . This effect is
based on the pinning-effect which has been explained in Sec. 4.1. As long
as a 2DHG is present, the 2DEG density remains almost constant; how-
ever, as soon as the 2DHG is depleted, the 2DEG density increases with
reducing top GaN thickness [110].
Based on the previous results, e-mode behaviour is predicted for samples
γ-GR14 and γ-GR21. To verify this, experimental transfer characteristics of
the final devices of all three samples are plotted in Fig. 4.10. For sample γ-
∂I
GR7, the pinch-off voltage Vp (the gate-source voltage at which ∂Vdgs changes
its sign) is about 1 V. This voltage is shifted to more negative values with
deeper recess depths. A value of -0.7,V is achieved for sample γ-GR21.

93
4 GaN-based p-Channel Devices

S G D
GaN:Mg++
GaN:Mg
+++++ + + ++++++
Al0.25In0.02Ga0.73N
ͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲ
GaN

(a) (b)

S D
G GaN:Mg++
GaN:Mg
+++++ +++++++
Al0.25In0.02Ga0.73N
ͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲ
GaN

(c) (d)

S D
G GaN:Mg++
GaN:Mg
+++++ +++++++
Al0.25In0.02Ga0.73N
ͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲ
GaN

(e) (f)

Figure 4.9: Band diagrams and structure for samples γ-GR7 (a), (b), γ-GR14 (c), (d)
and γ-GR21 (e), (f), respectively. The vertical dashed lines in the struc-
tures indicate the region from which the band diagrams are derived. All
graphs [111].

94
4.3 Fabrication of Enhancement Mode p-Channel Devices

Figure 4.10: Transfer characteristics and gate currents in semi-logarithmic scale


of three samples with different gate recess depths of 7, 14 and 21 nm.
After [111].

This large value is only realised due to the band structure in GaN and the
resulting high Schottky barrier height for p-channel devices. In addition to
the shift in Vp , the subthreshold swing (SS) remains very low and is about
76 mV/dec for sample γ-GR21. Regarding the leakage currents, neither
improvement nor degradation of gate and drain leakage current in the off-
state are observed. In the on-state however, the kink in gate current seen
for sample γ-GR7 is not present for the other two devices. This kink is
thus related to a yet too high Mg-concentration below the gate for sample
γ-GR7. This is in accordance to the results of SIMS measurements [210].
All devices can still be turned on properly, showing that the high Schot-
tky barrier height expected for GaN p-channel devices allows for channel
accumulation even for e-mode devices with such a negative Vp .
Since gate recessing has been shown to be a proper means for the real-
isation of a Vp shift, actual values are now compared. For this comparison,
band diagrams for the device structures shown in Fig. 4.9 have been sim-
ulated in dependence on Vgs . By integration of the channel charge, the
2DHG density is obtained. Then, by plotting the 2DHG density vs. Vgs ,
the extraction of Vth is possible by applying a linear fit to the curve. The
results of 2DHG density vs. Vgs and the associated linear fits are plotted

95
4 GaN-based p-Channel Devices

(a) (b)

Figure 4.11: (a) Symbols indicate 2DHG densities extracted from band diagram cal-
culated in dependence on Vgs and recess depth. The x-axis intercepts
of the linear fits indicate Vth . (b) Comparison of the simulated and
experimental threshold voltages in dependence on recess depth. After
[111].

in Fig. 4.11a. Different slopes of the curves are apparent. The increasing
slope from sample γ-GR7 to sample γ-GR21 is related to the decreasing
gate-channel separation which allows for a better control of the channel
and, thus, the same charge density can be accumulated or depleted with
less difference in Vgs . At the intercepts of the x-axis, values for Vth of
0.50, -0.45 and -1.20 V are extracted (see also Fig. 4.11b). To obtain the
values of Vth for the processed devices, the voltages are taken at which 1%
of the respective maximum Id is reached. These values are compared to
the ones from the simulation and the results are shown in Fig. 4.11b. A
good agreement between simulation and experiment is obtained and as a
consequence, the simulation is validated.

4.3.2 Variation in Barrier Composition


The barrier present in the device structure is necessary to obtain a polarisa-
tion difference to GaN. As has been discussed in Sec. 2.2, the composition
and the strain determine the magnitude of the polarisation. Hence, by

96
4.3 Fabrication of Enhancement Mode p-Channel Devices

Figure 4.12: Final device structure including ohmic contacts, access region recess
in between and gate metallisation. No pads were deposited for the final
devices [218].

varying the quaternary composition in the barrier layer, one is able to ob-
tain varying polarisation differences. As has been derived in Sec. 4.1, these
differences then have an impact on both 2DHG density ps as well as on Vth .
Due to the large Schottky barrier heights achievable for p-channel devices,
it should be possible to obtain p-channel devices with real e-mode beha-
viour by reducing the polarisation difference only and without any further
gate recess. On the other hand, devices offering large drain currents could
be achieved by increasing the polarisation difference. Hence, in this sec-
tion, the influence of the barrier composition on the device characteristics
is discussed.
Transistors were processed based on five epitaxial layer stacks for which
the barrier compositions are listed in Tab. 4.1 on p. 84. The compos-
ition of the barrier was varied from Al0.14 In0.02 Ga0.84 N for sample α to
Al0.54 In0.04 Ga0.42 N for sample ϸ in four steps, allowing for a very low polar-
isation difference of 0.6 µC/cm2 (= ˆ 3.7×1012 cm−2 ) for α as well as for a very
high polarisation difference of 3.6 µC/cm2 (= ˆ 2.2×1013 cm−2 ) for ϸ [210]. On
the basis of the results concerning leakage currents discussed in Sec. 4.2.4,
the fabrication included a recess between the ohmic contacts of about 6 nm
before gate processing. Thus, the GaN:Mg++ layer is only present below the
ohmic contacts and fulfils only its original function without deteriorating
device performance. The final device structure is depicted in Fig. 4.12.
While the ohmic contacts are only on top of the mesa, the gate metal is
overlapping the mesa. The results presented in the following have already
been published [111] and are summarised here.
Van der Pauw and Hall measurements were performed for the different

97
4 GaN-based p-Channel Devices

samples. Despite the nominally identical Mg acceptor concentration for


all samples, different 2DHG densities in the range between 1011 cm−2 to
1013 cm−2 were measured. This proves the existence of the 2DHG charge to
be polarisation-induced rather than doping-dependent. The 2DHG densit-
ies are listed in Tab. 4.1 on p. 84. For sample α, a value of 6.4×1011 cm−2
was measured. This is considerably lower than the charge related to the
polarisation difference, and it is governed by two different effects. As ex-
plained in Sec. 4.1, the 2DHG density depends on the 2DEG density rather
than directly on the polarisation difference. Further, the surface depletion
is stronger than for n-channel devices. For sample ϸ, a 2DHG density of
2.0×1013 cm−2 is measured which should allow for high current devices.
To gain access to the transistor performance, transfer characteristics
were measured in dependence on the drain-source voltage Vds . The results
are plotted in Fig. 4.13. For each of the five devices, an array of five different
curves for each Vds (-0.1, -0.5, -1.0, -5.0 and -10 V) is depicted.
First to note, all samples differ in their Vp . This is similar to the influence
of a variation in polarisation of the barrier in n-channel devices [25], [220]
and proves the validity of the electrostatic model derived in Sec. 4.1. With
sample α, e-mode behaviour has been realised without further gate recess-
ing. However, due to the high value of Rsh of 430 kΩ/sq., the on-current
of less than 0.1 mA/mm is very limited. This effect is independent of Vds .
Also independently of Vds , the leakage current in the off-state with less
than 1 pA/mm (detection limit of the measurement tool [221]) is extremely
low. Owing to this, the subthreshold slope is very steep. Hence, a quick
accumulation of the channel after reaching Vp is guaranteed.
With the devices of sample ̙ and γ, Vp is slightly shifted above 0 V. While
for the devices based on these two samples, increased on-state currents are
observed, the off-state currents are also increased and they are dependent
on Vds . For sample γ, the drain leakage current in the off-state increases
to 1 nA/mm. However, the subthreshold slope is not affected much by this
increase.
A different appearance of the transfer characteristics is observed for
sample δ. Here, the subthreshold slope is less steep. This is an effect of
the increase in off-current being stronger than the increase in on-current,
hence resulting in a smaller on/off ratio ([141] as cited in [111]). The
higher on-current is reasonable since for this epitaxial layer stack, the
parasitic resistances contact resistance Rc [213] and channel resistances
(cf. Tab. 4.1) are reduced. The increase in off-state |Id | is not fully un-

98
4.3 Fabrication of Enhancement Mode p-Channel Devices

Figure 4.13: Transfer characteristics and gate currents in semi-logarithmic scale of


the samples with different barriers [111].

derstood thus far. The effect is similar to the one observed in n-channel
devices [25], [220] and may be related to the value of the polarisation differ-
ence between barrier and channel. Additionally, Vp becomes a function of
Vds . This effect is called drain induced barrier lowering (DIBL) [222], [223]
and is discussed at a later stage. The effects seen for the device based on
sample δ are even more pronounced for the device based on sample ϸ. The
ratio between on- and off-state current is further reduced and with that
the slope in the subthreshold region is even smaller. For this device, DIBL
is very pronounced.
To further characterise the devices based on the different epitaxial layer
stacks, several parameters have been extracted from the transfer charac-
teristics. In Fig. 4.14a, the on- and off-state currents at Vds = -0.1 and
-5.0 V are depicted in dependence on the Al content in the backbarrier. The
values extracted at Vds = -5.0 V might be more meaningful as soon as device

99
4 GaN-based p-Channel Devices

downscaling comes into play. With reduced devices dimensions, such as a


gate-drain separation of 170 nm [224] instead of 2.5 µm used here, increas-
ing electric fields may already lead at low |Vds | to the same effects observed
in the devices presented here at high |Vds |. As seen from the figure, both
on- and off-state currents are functions of induced sheet charge, which
is a function of the Al content in the backbarrier. The effect of increasing
on-state current is mainly based on the reduction of parasitic resistances
while the Al content is increased. Over the whole range of Al contents em-
ployed in samples α – ϸ however, the increase in off-state current turns
out to be stronger than the one in on-state. Hence, the on/off ratio also
becomes a function of the Al content. While it is possible to obtain an
on/off ratio of 105 for the device of sample γ even at Vds = -5.0 V, a ratio of
only 102 is realised for the devices of sample ϸ. This detrimental effect is
based on gate leakage currents which directly depend on the polarisation-
induced hole density. Improved performance for heterostructures featuring
high-polarisation differences can only be obtained by inserting a gate dielec-
tric between metal and semiconductor as was discussed in Sec. 3.6.1 for
n-channel devices.
In Fig. 4.14b, the values for DIBL and SS are shown as a function of the
Al content. The value for DIBL is almost zero for the devices with the two
lowest polarisation differences. The effect, although small in its impact, is
first observed for the device based on sample γ. For the two devices based
on samples δ and ϸ, DIBL reaches substantial values. For an n-channel
device with nominally the same gate length and drain-source separation,
a DIBL of 40 mV/dec has been reported [225]. Compared to the device in
that reference, sample ϸ with a comparable DIBL of 50 mV/dec features
a much higher polarisation difference between channel and barrier. A
possible explanation for the better performance is the location of the high-
bandgap layer which is in our case below the channel, rather than above
the channel. Thus, the barrier acts like a backbarrier in n-channel devices
and allows for lower values of DIBL [226], hence improving the suitability
of p-channel devices to be used in complementary logic circuits for which
Vp stability is crucial.
With respect to DIBL, a similar behaviour is seen for SS. The SS values
were extracted at Vds = -0.1 V as an average over three orders of magnitude
for samples α - δ. Only for sample ϸ, the extraction was performed over two
orders of magnitude. For the samples based on samples α – γ, the SS is
rather low and close to the theoretical limit. For the two other devices, SS

100
4.4 p-Channel C-V, small signal and high temperature analysis

(a) (b)

Figure 4.14: (a) Value of the on- and the off-current extracted from the semi-
logarithmic transfer characteristics [111]. (b) Values for the sub-
threshold slope (SS) and the drain induced barrier lowering (DIBL)
extracted from the semi-logarithmic transfer characteristics [111].

increases and reaches a value as high as 200 mV/dec for the device based
on sample ϸ. The main reason for this is the strong reduction in on/off
ratio [141].
Based on the previous results, the device based on sample γ may be
suitable for the utilisation in an inverter based on complementary devices.
Here, sufficient on-current, a high on/off-ratio, a low value of SS and negli-
gible DIBL have been observed. For a combination of very high Id and high
on/off ratio, the application of a gate dielectric seems to be unavoidable.

4.4 C-V, small-signal and high temperature


characterisation of p-Channel Devices
So far, basically all results published for p-channel devices are based on
Hall measurements and I-V characterisation at room temperature. To

101
4 GaN-based p-Channel Devices

widen the basis and to enhance the understanding of p-channel devices,


results of further characterisation methods are discussed within this sec-
tion. These results have partly been published [218], [227], but also new
findings not published so far are presented. After a discussion of the in-
terpretation of C-V measurements, small-signal analysis is presented to
verify whether the presence of a 2DEG beneath the 2DHG is mitigating the
p-channel HFET high frequency characteristics or not. The section closes
with a high-temperature analysis in which – among other things – the C-V
measurement discussed beforehand is also employed.

4.4.1 C-V Analysis


Prior to the work presented in this thesis, no C-V measurement of a gate
diode employing a hole channel has been shown in the literature. The
structure used for the p-channel devices features an additional 2DEG,
making the interpretation of a C-V measurement less trivial. Hence, a
fatFET fabricated based on sample γ was subjected to C-V measurements
at frequencies between 1 kHz and 1 MHz. C-V curves calculated using a
parallel equivalent circuit model (Cp –D) are shown in Fig. 4.15a. For the
device measured, the 2DHG is depleted at positive voltages. This is in
good agreement with the simulated band diagrams, of which the results
have been discussed in Sec. 4.3.1. Although a depletion is observed inde-
pendently of frequency, the extracted capacitance in depletion is about 2
orders of magnitude higher that what is typically observed in n-channel
devices. This is most likely related to the presence of the 2DEG. In forward
direction between about -0.5 V and about -1.8 V, accumulation can be ob-
served. However, a strong dispersion effect is seen between the curves for
frequencies of 10 and 100 kHz and 1 MHz.
To obtain a deeper understanding of the C-V curves, obviously, the
simple Cp –D equivalent circuit cannot be applied for calculating C. Hence,
the raw data (|Z|–ϕ) of the measurement is analysed. This data is shown
in Fig. 4.15b. In the graph, the absolute value and phase angle ϕ of the
complex impedance Z are shown for the four different frequencies f in de-
pendence on Vgs . In the off-state (Vgs > 0), ϕ is similar at all frequencies
and shows values around -90◦ . Hence, the calculated values for C which
were shown in Fig. 4.15a represent a real capacitive component. In the on-
state, however, considerable dispersion is observed. For f = 100 kHz and
1 MHz, ϕ deviates by far from -90◦ and thus, the calculated values for C

102
4.4 p-Channel C-V, small signal and high temperature analysis

(a) (b)

Figure 4.15: (a) Capacitance values normalised to the gate area in dependence on
Vgs and frequency. [218] (b) Raw data of absolute value and phase
angle ϕ of the complex impedance Z. Values are shown for different
frequencies [colours as in (a)] in dependence on Vgs .

cannot be relied on.


As is seen, the interpretation of the C-V measurement for the given device
structure is somewhat more difficult than the one of a simple n-channel
device. To gain further insight, an equivalent-circuit model for the given
device structure in off-state is proposed in Fig. 4.16. On the basis of the
simplified epitaxial layer stack (cf. Fig. 4.3), relevant capacitive and resist-
ive elements are displayed. The displayed capacitive components reflect
complex impedances which were formed by a capacitive components and
a shunt resistor. The equivalent-circuit model shows capacitors between
gate metal and 2DEG Cg-e as well as between 2DEG and 2DHG Ch-e in the
access region and below the ohmic contacts. Additionally, there are two
stray capacitors Cstr which are connected from gate to 2DHG. However, be-
cause of the large distances between gate metal and 2DHG and the small
area of the 2DHG, these stray capacitors can be neglected. Resistors rep-
resent the sheet resistances of the 2DHG and the 2DEG as well as the
ohmic contacts.

103
4 GaN-based p-Channel Devices

>ŵŽ >ŽŚŵŝĐ >ĂĐĐĞƐƐ >ŐĂƚĞ

KŚŵŝĐ 'ĂƚĞ KŚŵŝĐ

ZĐ Ɛƚƌ Ɛƚƌ ƉͲ'ĂE ZĐ


ннннннннннннн нннннннннннннн
ZϮ,' ŐͲĞ ZϮ,'
ŚͲĞ ů/Ŷ'ĂE ŚͲĞ

ͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲ
ZϮ' 'ĂEďƵĨĨĞƌ ZϮ'
EƵĐůĞĂƚŝŽŶůĂLJĞƌͬ^ƵďƐƚƌĂƚĞ

Figure 4.16: Equivalent-circuit model for the off-state of the fatFET. Lengths are
given for accurate capacitor calculation. After [218].

>ŵŽ >ŽŚŵŝĐ >ĂĐĐĞƐƐ >ŐĂƚĞ

KŚŵŝĐ 'ĂƚĞ KŚŵŝĐ

ZĐ ͛ŐͲŚ ƉͲ'ĂE ZĐ
нннннннннннннннннннннннннннннннннннннн
ZϮ,' ZϮ,'
ŚͲĞ ͛ŚͲĞ ŚͲĞ
ů/Ŷ'ĂE
ͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲͲ
ZϮ' 'ĂEďƵĨĨĞƌ ZϮ'
EƵĐůĞĂƚŝŽŶůĂLJĞƌͬ^ƵďƐƚƌĂƚĞ

Figure 4.17: Equivalent-circuit model for the on-state of the fatFET. Lengths are
given for accurate capacitor calculation.

104
4.4 p-Channel C-V, small signal and high temperature analysis

In the on-state, the equivalent-circuit model is appearing a bit different


(see Fig. 4.17). Since in the on-state, the 2DHG is accumulated beneath
the gate contact, the former gate-2DEG capacitor Cg-e is replaced by two
capacitors in series between gate and 2DHG C’g-h and between 2DHG and
2DEG C’h-e . Furthermore, the stray capacitors Cstr are removed due to the
presence of the 2DHG.
To verify the validity of these two equivalent-circuit models, SPICE simu-
lations using LTSpice IV [228] were employed. In the on-state, the capacit-
ors were distributed both in access and in gate region to achieve a better
agreement of the simulation to the measured results. The results of both
simulation and measurement are depicted in Figs. 4.18a and 4.18b for the
off- and on-state, respectively. |Z| and ϕ are plotted in dependence on
frequency for different gate-source voltages.
In the off-state, the values for |Z| and ϕ do not vary much in depend-
ence on Vgs . The simulated curve (in grey) is valid independently of Vgs
and accurately reflects the measured values. A very good agreement is
already achieved with this simplified equivalent-circuit model for which
only two capacitors Cg-e and Ch-e with associated parallel resistors have
been assumed3 .
In the on-state, the situation is more complex. In Fig. 4.18b, the meas-
ured results are shown in dark colour while the simulated values are
plotted in the associated light colours. It is seen that in contrast to the
off-state, the values of |Z| and ϕ depend on Vgs . |Z| decreases with
an increasing |Vgs | while different peak values of ϕ occur at different fre-
quencies. Though the simplified equivalent-circuit model is based on the
same basic elements for all Vgs in on-state, the values of the resistors and
capacitors needed a slight adaption in dependence on Vgs . This adaption
of the resistors is based on a reduction of Rsh in the 2DHG since it is ac-
cumulated with decreasing Vgs . Additionally, the distance between gate
metal and channel is smaller for higher 2DHG densities. Therefore, the
capacitance values below the gate are increased as well. For Vgs = -1.5 V,
ϕ decreases at low frequency owing to the turn-on of the gate diode. This
is implemented by a reduced parallel resistance of C’g-h . With these adap-
3
As has been discussed in Sec. 4.3.2, the leakage current in the device has been found to
be very low for devices based on samples α, ̙ and γ (cf. Sec. 4.3.2). However, for devices
based on samples δ and ϸ, rather high leakage current has been found, distorting the
measurement in depletion. Hence, for those devices, the validity of the off-state model is
not guaranteed.

105
4 GaN-based p-Channel Devices

(a) (b)

Figure 4.18: |Z| and ϕ values in dependence on frequency for different Vgs in (a)
off-state and (b) on-state. (a) Grey and (b) light coloured curves show
the simulated fits using the equivalent-circuit models displayed in
Figs. 4.16 and 4.17, respectively. The kink appearing at 77 kHz is
related to the measurement setup.

tions, the C-V measurements can be reconstructed very well.


The question remains whether the device will be able to operate at high
frequencies or if the coupling between 2DHG and 2DEG does not allow for
sufficient cut-off frequencies. First insights towards the answer are given
in the next section.

4.4.2 Small-Signal Characterisation


For a possible application in an amplifier based on complementary logic,
small-signal parameters are evaluated in the following section. Beside the
extraction of the cut-off frequencies fT and fmax , it allows for the estimation
of the hole saturation velocity in an HFET. The results discussed here have

106
4.4 p-Channel C-V, small signal and high temperature analysis

Figure 4.19: Transfer characteristic and associated transconductance at Vds = -8 V


for the device based on sample ϸ [227].

already been published in [227].


For the following characterisation, a transistor based on sample ϸ has
been used. The sample is equivalent to the one for which the results have
been discussed in Sec. 4.3.2. Although DC characteristics have been ana-
lysed in that chapter, a transfer characteristic in linear scale with the asso-
ciated transconductance gm is necessary for an evaluation of the extracted
small-signal figures. Hence, the DC curves are shown in Fig. 4.19.
From the figure, a Vth of +3.5 V is derived by extrapolation of a linear
fit at the point of maximum transconductance gm,max . At Vgs = -3 V, an Id
in excess of -25 mA/mm is reached. A relatively flat gm curve is also seen
with a value of about 5 mS/mm. This gm value which is rather high for
a p-channel HFET [48], [111], [210] and it makes the device suitable for
small-signal characterisation. By consideration of Rc and Rsh in the access
region, the intrinsic gm,max can be calculated. This value is as high as
12 mS/mm [227].
For this specific device, S-parameters have been measured. The short-
circuit current gain |h21 | and the maximum unilateral gain (MUG) have
been calculated in dependence on measurement frequency. The resulting
values for the bias point Vgs = 0 V and Vds = -12 V are plotted in Fig. 4.20.
|h21 | decreases as expected with -20 dB/dec and the transit frequency fT
can be extrapolated with this slope. At the x-axis intercept of the extrapol-

107
4 GaN-based p-Channel Devices

Figure 4.20: Extrapolation of small-signal parameters |h21 | and MUG. [227]

ation, a value of 206 MHz is extracted. fmax was extracted directly at the
x-axis intercept of MUG yielding a value of 640 MHz.
For comparison, fT can be estimated according to an equation derived
from a simplified equivalent-circuit model is taken [229]

gm gm
fT = = . (4.18)
2π · Cgs ϸ0 ·ϸr ·Wg ·Lg
2π dg−ch

Here, Cgs denotes the gate-source capacitance, dg-ch the gate-channel


separation, and ϸ 0 ·ϸ r the permittivity of GaN. At the bias point which was
used to extract the values for |h21 |, gm is 4.5 mS/mm (cf. Fig. 4.19). With
this value for gm and dg-ch = 26 nm, the calculated fT is 226 MHz. This is in
good agreement to the value shown earlier and verifies that the frequency
response is originated from the 2DHG and additionally that the presence
of the 2DEG is not deteriorating the high frequency response of the 2DHG.
Furthermore, extracted values of fT are plotted in dependence on Vds for
different Vgs . The results are shown in Fig. 4.21. The dependence of fT on
the bias point is similar to the behaviour observed for n-channel HFETs
[230].
Based on the small-signal parameter evaluation, it is clear that p-channel

108
4.4 p-Channel C-V, small signal and high temperature analysis

Figure 4.21: Dependence of fT on drain-source bias for different gate-source biases


[227].

devices suffer from the high effective hole mass which already distorts the
low-field mobility.

4.4.3 High-Temperature Analysis


Since high-temperature logic is one possible niche application, it is ne-
cessary to understand the device behaviour at higher temperature levels.
Hence, a characterisation of p-channel devices at elevated temperatures
is presented in the following. High-temperature measurements also allow
for the characterisation of certain device properties which are not access-
ible via room temperature analysis. The devices were fabricated based on
sample γ and the results presented here have been published in [218]. Be-
fore the analysis of the fabricated transistors, the contact resistance Rc and
the effective hole mobility in the 2DHG are evaluated in dependence on the
temperature.
The transfer length method (TLM) was employed for the characterisation
of Rc . As can be seen from Fig. 4.22a, the y-axis intercept and the slope of
the fits depend strongly on temperature. Moreover, at room temperature,
it was not possible to fit the curve with a reasonable result. This effect
is based on non-linear I-V curves as indicated in Fig. 4.22b. Based on

109
4 GaN-based p-Channel Devices

(a) (b)

Figure 4.22: (a) Results of transfer length method at different temperatures [218].
(b) I-V measurement of an open-channel structure with a gap of 5 µm
[218].

the TLM results, the contact resistance Rc is decreasing from 600 Ω·mm at
75 ◦ C to 113 Ω·mm at 175 ◦ C. The result evidences that the current through
the ohmic contact at low temperatures is not governed by a tunnelling
mechanism; it is rather dominated by thermionic emission. The limitations
are most likely related to a limited concentration of ionised acceptors. With
increasing temperature, more acceptors are ionised and hence Rc decreases.
In the literature, it has been speculated on this effect, but no values were
given for Rc [48]. Whereas Rc decreases, Rsh increases with temperature
from a value of 90 kΩ/sq. at 75 ◦ C to 200 kΩ/sq. at 175 ◦ C. Since ps
is independent of temperature [44], this increment in Rsh is a result of a
reduced µ p (as shown in Fig. 4.23b). To evaluate the two opposing effects
in total, I-V measurements of open-channel structures with a separation
of 5 µm are shown in Fig. 4.22b. It is seen that despite the increased value
of Rsh , the current at a given voltage even increases with temperature. It
can be concluded that in the given temperature range the reduction of Rc
has a stronger impact on current than the drop in µ p .

110
4.4 p-Channel C-V, small signal and high temperature analysis

To gain further insight into the increasing Rsh with temperature, C-V
and I-V measurements of fatFETs were employed4 . In Fig. 4.23a, I-V meas-
urements of a fatFET are shown in dependence on temperature. One can
clearly see not only a reduction of |Id,max | but also a slight shift of the point
∂I
at which |Id | starts to decrease ( ∂Vdgs changes sign). This indicates a high
gate current. The results of these measurements are used in conjunction
with C-V measurements of the same fatFET to calculate the effective hole
mobility. The frequency at which the capacitance values were extracted is
10 kHz, since at this frequency, the phase angle is very close to -90◦ both in
off- and on-state (cf. Fig. 4.16 on p. 104)5 . The results of the calculation of
the effective hole mobility are shown in Fig. 4.23b. One can clearly see the
dependence of the hole mobility on temperature. The room temperature
value of 35 cm2 ·(Vs)−1 is very close to the result of 30 cm2 ·(Vs)−1 extracted
from Hall measurements (see Tab. 4.1). The mobility is reduced with in-
creasing temperature and a value of 16 cm2 ·(Vs)−1 is still reached at 175 ◦ C.
Based on these results, it is clear that the increase in Rsh observed earlier
is strongly related to a temperature-dependent mobility degradation and
not related to a reduction of the 2DHG concentration.
Based on the previous results, the performance of transistors is evalu-
ated. Temperature-dependent output characteristics are shown in Fig. 4.24.
The curves were measured at Vgs = -2 V and +1 V. For temperatures up to
125 ◦ C, a clear distinction between linear and saturation region is seen. In
the very first onset of the linear region (|Vds ≤ -0.5 V), the currents are al-
most equal independent of temperature. This is based on the reduced Rc
which was discussed earlier. In the saturation region however, there is a
clear dependence of Id on the temperature. This is in agreement to most
of the reports of n-channel devices in literature [232]–[234]. However, in
other reports, a constant Id is observed which is explained either with Id
to be saturation velocity limited [235] (rather than mobility-limited) or with
the application of a gate recess [236]. Here, clearly no saturation velocity
limitation is observed owing to the large Lg in conjunction with rather low
|Vds |. Also, the gate recess is not leading to the effect reported in [236].
Hence, the reduction in µ p which was shown before is causing the drop in
Id .
4
The method including the correction for the access resistances is described in [231].
5
For the measurement at 175 ◦ C, ϕ changed and false values for C were extracted. Hence,
the values of the measurement at 125 ◦ C were taken while additionally considering the
shifted turn-on of the gate diode at 175 ◦ C.

111
4 GaN-based p-Channel Devices

(a) (b)

Figure 4.23: (a) Transfer characteristics of a fatFET at Vds = -0.1 V for different tem-
peratures. (b) Extracted intrinsic effective hole mobilities from C-V
measurements and I-V measurements of fatFETs.

Linear and semi-logarithmic transfer characteristics at different |Vds |


are shown in Figs. 4.25a and 4.25b, for room temperature and 175 ◦ C, re-
spectively. At room temperature, a sharp pinch-off is observed independent
of |Vds |. However, at a high bias, the off-state leakage current increases
with Vds . In the on-state, the current saturation clearly depends on Vds .
However, in all cases, the saturation level is not limited by gate current.
At an elevated temperature of 175 ◦ C, the off-state current, although at
a higher level, still depends on Vds . A slight DIBL is observed. At this
temperature, it seems that for |Vds |, the gate current starts to limit the
accumulation of the channel.
A deeper investigation of the characteristics shown in the linear region of
the output characteristics of Fig. 4.24 is performed. In the output charac-
teristics, it was seen that up to 125 ◦ C, the drain current is almost constant.
This behaviour is again seen in Fig. 4.26a (for another device). However, at
175 ◦ C, a dramatic drop is observed. This drop contradicts the findings
from the open-channel measurements which were shown in Fig. 4.22b and
for which with increasing temperature, higher currents in the linear region
were observed. The only difference between the final transistor and the
open-channel structure is that the gate is overlapping the mesa edge (cf.
Fig. 4.12 on p. 97) and thus, that it has potentially contact to both 2DEG
and 2DHG at the sidewall of the mesa edge. This contact is likely to be-

112
4.4 p-Channel C-V, small signal and high temperature analysis

Figure 4.24: Output characteristics of the device based on sample γ measured at


different temperatures at Vgs = -2 V and +1 V [218].

come less resistive at higher temperatures and hence, it is assumed that it


distorts the device behaviour for the transistor, for which the measurement
was shown at 175 ◦ C. Vp is almost stable independent of temperature. Only
between 25 ◦ C and 75 ◦ C, the onset is slightly shifted towards a more pos-
itive value. This effect is related to trap states which may be activated with
elevated temperature. This temperature stability of Vp is a huge benefit
of GaN heterostructure-based transistors compared to Si-based MOSFETs
for which this effect is not observed. In the off-state, Id depends on tem-
perature. This effect is related to Poole-Frenkel conduction, as it has been
discussed in [218].
The data of on/off ratio and SS was extracted from transfer character-
istics at Vds = -0.1 V and it is shown in Fig. 4.26b. It is seen that the on/off
ratio is decreasing with increasing temperature, but is still as high as 5×106
at 125 ◦ C. With this value, the devices here are very much comparable to
state-of-the-art junctionless Si MOSFETs [237]. A further improvement
may be expected with the utilisation of an oxide beneath the gate. SS ex-
tracted as a mean value over 3 decades of Id increases with higher temper-
ature in a way expected from the increased broadening of the Fermi-Dirac
distribution. Only at 175 ◦ C, the value is drastically increased. This strong
increase is related to the large reduction in on/off ratio and is eventually
related the gate overlapping the mesa (as discussed earlier).
The fabricated p-channel HFETs have shown promising characteristics
at elevated temperature. However, it seems necessary to isolate the mesa
by ion implantation instead of the utilised dry etch. Hence, a possible

113
4 GaN-based p-Channel Devices

(a) (b)

Figure 4.25: Transfer characteristics in linear and semi-logarithmic scale at (a)


room temperature and (b) at 175 ◦ C for different Vds [218].

lateral gate contact at the mesa edge is then prevented and better results
are to be expected at temperatures above 125 ◦ C.
Although the results presented in this chapter may allow for certain
applications, the main task for optimising GaN-based p-channel devices
is to find a way for reducing the effective hole mass. Possible approaches
may be found in applying different strain states to the channel material
[61], in using different lattice-planes for the channel material [238] or in
changing the channel material from GaN to AlGaN with an Al content
above 58 % [239], [240]. All these approaches may be a possible way to
go for further enhancing the performance of p-channel devices which may
eventually allow for diverse applications to be accessed using these devices.

114
4.4 p-Channel C-V, small signal and high temperature analysis

(a) (b)

Figure 4.26: (a) Transfer characteristics in semi-logarithmic scale at Vds = -1 V for


different temperatures. (b) Extracted values for on/off ratio and SS at
Vds = -0.1 V [218].

115
5 Complementary GaN digital inverter
As shown in the previous two chapters, e-mode behaviour has been realised
both for n-channel and p-channel devices. By combining these two device
types, a monolithically integrated inverter, e.g. for digital logic applications,
could be formed. In this chapter, a first proof of concept of such an inverter
is demonstrated.
For the integration of n- and p-channel devices on a single wafer, the
basic structure already used for p-channel device development was em-
ployed (see. Fig. 5.1a). As barrier, Al0.42 In0.03 Ga0.55 was chosen to allow
for high on-currents and sufficient on/off-ratios of the p-channel devices.
Prior to the experiment involving both devices types on a single wafer, n-
and p-channel devices were fabricated separately. These devices serve as
reference samples for the integrated devices. Schematic cross sections of
both device types are depicted in Fig. 5.1b.
n-Channel device processing started with the removal of the p-type lay-
ers on top of the barrier using the digital etch process. It also included
mesa isolation by a chlorine-based dry etch, ohmic contact formation by
a thermally annealed Ti/Al/Ni/Au stack at 825 ◦ C in N2 atmosphere and
gate contact formation by a 50 nm Ni/200 nm Au stack. For the p-channel
devices, ohmic contact formation was realised by a 20 nm Ni/20 nm Au
stack annealed at 535 ◦ C in air. Subsequently, the graded GaN:Mg++ layer
was removed using the digital etch process and 50 nm Mo/200 nm Au gates
were deposited. Finally, the devices were mesa-isolated by chlorine-based
dry etch.
Semi-logarithmic transfer characteristics of the fabricated devices are
plotted for different Vds in Fig. 5.2. For the n-channel device, a pinch-
off voltage Vp of about -11 V is extracted. off-state currents are in the
order of 1 µA/mm. on-state currents vary with Vds and are in the range
of 100 mA/mm for Vds = 1 V, leading to an on/off-ratio of 105 . For the p-
channel device, Vp is 2 V. Here, both on- and off-current depend on Vds .
on/off-ratios are also in the range of 105 -106 .
From these results, two conclusions can be drawn. First, for the realisa-

117
5 C-GaN digital inverter

p-HFET n-HFET
Graded GaN:Mg++ 7 nm S D
G
GaN:Mg (p ~ 1016 cm-3) 23 nm
3 nm
++++++uid-GaN++++++ 2DHG GaN:Mg
++++ +++++ D G S
Al0.42In0.03Ga0.55N 35 nm Al0.42In0.03Ga0.55N
- - - - - - - - - - - - - - - 2DEG ----------- ---- ---
GaN 2.0 µm GaN
AlN 0.3 µm AlN
Sapphire Sapphire

(a) (b)

Figure 5.1: (a) Epitaxial layer stack used for the experiments. (b) Schematic of the
integrated n- and p-channel device.

tion of a digital inverter, approaches to render both device types e-mode


are necessary to be applied. Second, to account for the large differences
in on-state currents, it would be necessary to combine a large gate width
p-channel devices together with a small gate width n-channel (gate width
difference of about a factor of 50).
With this knowledge, n- and p-channel devices were fabricated on a
single wafer. An overview of the process flow is depicted in Fig. 5.3. The
devices were fabricated as described above for the separate process. Non-
etheless, some aspects needed to be considered. With the highest thermal
budget, n-type ohmic contacts were processed at an early process stage.
Furthermore, to protect the n-type regions from oxidation during p-contact
annealing in air, n-type devices were passivated by a PECVD SiN layer.
This layer was removed using buffered oxide etch (BOE) prior to the gate
formation of the n-type device. To avoid gates contacting 2DEG and/or
2DHG on mesa edges, the mesa isolation was performed as last process
step.
Semi-logarithmic transfer characteristics of several devices of both types
(monolithically fabricated) are shown in Fig. 5.4. For both devices, e-mode
behaviour was realised successfully. An ideal Vp of about 0 V was ob-
tained. The p-channel devices feature also a very low off-current and a
steep subthreshold slope (≈ 60 mV/dec). Also, the gate electrode appears to

118
Figure 5.2: Transfer characteristics and gate leakage currents for different |Vds | of
separately fabricated depletion mode n- and p-HFETs. These transist-
ors were fabricated without gate-recess [241].

be unaffected by the gate recess. Yet, the on-current of about 0.2 mA/mm
is considerably lower than for the device which was processed separately.
The low current is related to a very high ohmic contact resistance which
itself is related to insufficient activation of Mg acceptors1 .
For the n-channel device, very high off-state currents are observed in
Fig. 5.4. They are 1-3 orders of magnitude higher than for the devices which
were processed separately. This effect is related to the high off-state gate
current. In on-state, the gate diode current prevents the accumulation of
the 2DEG, hindering the device from reaching high drain currents. The
reason for the degraded gate diode is the deep gate recess. Also, the use
of the BCl3 /Ar etch process is probably causing higher damage than the
digital etch would have2 [123].
In Fig. 5.5, output characteristics of a n- and p-channel device are shown
which were used for fabricating the inverter. For the n-channel device, a
1
The high resistivity is related to the Mg activation step prior to device fabrication during
which an error occurred. Hence, it is believed that the activated Mg acceptor concentration
beneath the ohmic contacts is not sufficient to allow for low-resistive ohmic contacts.
2
The digital gate recess could not be applied since at this early development stage, photoresist
masks were applied for gate etching.

119
5 C-GaN digital inverter

p-HFET n-HFET p-HFET n-HFET


S D GaN:Mg++ recess
GaN:Mg++ for p-HFET
GaN:Mg GaN:Mg SiN
+++++++++++++++++++++++++ ++++++++++++ D S
Al0.42In0.03Ga0.55N Al0.42In0.03Ga0.55N
---------------------- ---------------- ---
GaN GaN
AlN
Sapphire S D p-HFET gate
G
recess and metal
GaN:Mg++ p-Region recess GaN:Mg SiN
GaN:Mg for n-HFET ++++ +++++ D S
++++++++++++ Al0.42In0.03Ga0.55N
Al0.42In0.03Ga0.55N ----------------------
GaN
----------------------
GaN
S Removal of
D
G n-HFET
GaN:Mg++ n-HFET ohmic
contacts GaN:Mg
passivation
GaN:Mg
D S ++++ +++++ D S
++++++++++++ Al0.42In0.03Ga0.55N
Al0.42In0.03Ga0.55N
---------------------- ----------------------
GaN
GaN

Passivation for n- S D n-HFET gate


GaN:Mg++ G
HFET recess and metal
GaN:Mg SiN GaN:Mg
++++++++++++ D S ++++ +++++ D G S
Al0.42In0.03Ga0.55N Al0.42In0.03Ga0.55N
---------------------- ---------------- ---
GaN GaN

S D p-HFET ohmic S D Pads and mesa


GaN:Mg++ G
contacts isolation
GaN:Mg SiN GaN:Mg
++++++++++++ D S ++++ +++++ D G S
Al0.42In0.03Ga0.55N Al0.42In0.03Ga0.55N
---------------------- ----------- ---- ---
GaN GaN

Figure 5.3: Process flow for the integrated devices.

120
Figure 5.4: Transfer characteristics and gate leakage currents in dependence on
|Vds | of e-mode n- and p-HFETs integrated on a single wafer [241].

Figure 5.5: Output characteristics of both p-channel and n-channel HFET which
were also measured in an inverter configuration. For the n-channel
HFET, gate leakage is very pronounced [241].

121
5 C-GaN digital inverter

Figure 5.6: Voltage transfer curve (Vdd = 1 V) of the fabricated inverter structure
showing a clear high output level and a steep transition from VOH to
VOL close to the Vdd /2 [241].

poor pinch-off behaviour (Vgs = 0 V and Vgs = 0.2 V) is seen. Additionally,


the gate diode renders Id negative at low Vds for Vgs > 0.4 V. The p-channel
device, on the other hand, does not show such effects. Owing to the de-
graded performance of the n-channel device, the on-currents of both device
types are in the same range, allowing for the use of same gate width devices
in an inverter configuration.
The n- and p-channel devices for which the output characteristics were
discussed beforehand were also measured in an inverter configuration.
Here, only a single finger of each transistor was used because of technical
limitations. The digital inverter was measured using 6 source measure-
ment units (SMU). The supply voltage Vdd was set to 1.0 V and the input
voltage Vin was swept from 0 V to 1.0 V. The output voltage Vout was re-
corded during the measurement. The resulting curve is shown in Fig. 5.6.
Basic inverter operation is demonstrated. While there is a constant plateau
of the output high VOH at about 0.9 V, the output low VOL does not satur-
ate. This effect is related to the high gate current of the n-channel devices
which hinders the output level to become zero. However, the digital inverter
shows a trigger voltage VM very close to Vdd /2 and also a steep transition
from the input low VIL to the input high VIH . Although this inverter is still
at a very early development stage, it gives reason to believe that charge and
discharging of the output level will be reasonably fast and that digital logic
can be successfully realised with C-GaN.

122
6 Conclusion and Outlook
Several GaN-based n- and p-channel devices have been developed and
characterised during this thesis.
For the n-channel devices, a thorough investigation of shifting Vth has
been performed. Based on a comprehensive electrostatic model for insu-
lated-gate double heterostructures, distinct approaches to modify Vth have
been identified and their influence on Vth has been discussed. Of these
approaches, several have been investigated separately, gate-recessing, in-
fluence of gate metallisation and of a backbarrier as well as of gate insu-
lators. For each, devices were processed and characterised in terms of DC
performance and dynamic behaviour.
For gate recessing, a digital etch process has been optimised to obtain
damage-free etching. This process has been employed successfully for the
fabrication of record performance AlGaN/GaN-on-Si HFETs. It has been
shown that Vth can be shifted successfully while improving the transcon-
ductance significantly. Additionally, the recessed-gate devices have out-
performed the non-recessed-gate devices in terms of dynamic behaviour.
This effect has been explained with the distribution of the electric field
employing TCAD simulations.
Work function engineering has been performed by replacing the typically
used Ni-gate with a Pt gate. Although the effect of Fermi level pinning in
GaN-based devices is still discussed, it has been shown that with the Pt
gate, a significant Vth shift is possible. In addition, it has been shown that
the DC performance improves in terms of transconductance and off-state
leakage current. The Pt-gated device has also shown to be superior during
pulsed I-V characterisation.
The insertion of a backbarrier to form a double heterostructure has been
analysed. Positive Vth shifts were confirmed with 50 nm and 20 nm channel
thicknesses. Whereas gate recess and Pt gate have shown beneficial effects
only, trade-offs in terms of gm and Id,max have been identified for the double
heterostructure devices. The reason has been found to be an increase in
sheet resistance. A parasitic buried channel below the backbarrier has

123
6 Conclusion and Outlook

been identified as the origin of high off-state leakage currents. Compared


to the single heterostructure, the double heterostructure devoces have also
been identified as being less prone to the current collapse effect.
The application of gate insulators by two different methods, ALD and
plasma oxidation, has been evaluated. For the characterisation of sam-
ples with ALD oxide, a thickness series of AlOx has been analysed. It
has been found that a 6 nm oxide is necessary to obtain proper insulating
characteristics. By an increase of that thickness, the maximum applicable
gate voltage has been extended. By employing C-V measurements, positive
fixed bulk oxide charge has been identified as the reason for a parabolic
Vth trend. Also the presence of negative fixed interface charge has been
identified, causing an overall positive Vth shift. An evaluation of the influ-
ence of applied stress conditions on Vth has been performed. Considerable
negative and minor positive Vth shifts of the fabricated devices have been
identified. The optimum thickness considering the shown results has been
estimated to be 6 nm.
An analysis of thermal treatments of devices using a plasma-oxidised
metal layer as gate insulation has been performed for the first time. It has
been found that Al can be oxidised by an oxygen plasma process in an ICP-
RIE tool. A positive Vth shift has been obtained after annealing the devices
with temperatures up to 600 ◦ C. Improved DC characteristics have been
found in addition. A second series with different oxidised metals (Al, Al/Ti,
Zr) has revealed that a positive Vth shift is possible by the plasma oxidation
technique. Since only one oxide thickness was realised for each metal, it
has not been possible to separate the influence of fixed bulk oxide charge
and fixed interface charge. The Vth shift induced by stress conditions has
been found to be less pronounced compared to the ALD oxide.
In a combined approach, the aforementioned approaches have been in-
cluded into one process. The single approaches have shown identical ef-
fects on Vth , validating the presented results. The threshold voltage of
the final devices has been as high as +2.3 V, one of the highest values ever
reported for MIS-DHFETs. Additionally, the device has shown very good dy-
namic characteristics, very low off-state leakage and a steep subthreshold
slope. Hence, with the presented concept, the fabrication of an e-mode
device for power-switching applications is possible.
Future experiments may target on a further shift in Vth by optimising the
fixed interface charge density at the oxide/semiconductor interface and by
application of higher Al content backbarriers. Additionally, a thicker oxide

124
should be used to be able to turn-on devices with a larger gate swing. The
Vth stability needs to be further analysed and additionally, a characterisa-
tion of breakdown phenomena is to be performed.
Devices on the basis of a 2DHG have been optimised and analysed to
gain an understanding of p-channel HFET devices. After establishing the
electrostatics for the presented epitaxial layer stack, ohmic contacts have
been optimised in terms of contact resistance. A Ni/Au contact annealed
in oxygen-rich atmosphere has been found to yield the smallest values.
Also, different gate contacts have been subjected to an analysis of their
insulating and channel-controlling capabilities. A Mo-based gate has been
found to be the optimum showing low leakage current and good channel
control. The optimisation of the devices has been finalised by considering
a highly doped GaN:Mg++ as a possible source of leakage current. Both in
the access region and below the gate contact, this layer has been found
to cause leakage current either in forward or in reverse direction. The
underlying mechanisms have been identified, partly by employing TCAD
simulations.
The effects of a gate recess have also been discussed for the p-channel
devices. For these devices, obtaining e-mode behaviour has been shown
to be achievable much easier. The threshold voltage which has been ob-
tained with the gate recess has been compared with and validated by TCAD
simulations.
With the optimised device design, a total of five samples with different
barrier compositions has been processed. Effects on pinch-off voltage, on-
and off-currents, subthreshold swing and DIBL have been discussed in
detail. Extremely high on/off-ratios of 108 have been reported for e-mode
devices.
Based on these optimised devices, a first C-V characteristic has been
shown of this structure. The presence of the 2DEG beneath the barrier
has been found to complicate the understanding of C-V measurements.
Equivalent-circuit models have been proposed for the on- and the off-state
of the device. |Z| – ϕ plots of the proposed models have been validated
by a comparison to the measurement results. A device with high transcon-
ductance was subjected to a small-signal analysis and the first values for
cut-off frequencies and hole saturation velocity have been reported.
Finally, a thorough discussion of the p-channel devices in terms of high-
temperature behaviour has been performed. A gate overlapping the mesa
edge has been identified as the reason of degraded device performance at

125
6 Conclusion and Outlook

a temperature of 175 ◦ C. Up to 125 ◦ C, the device performance has been


shown to be as expected and to be comparable to Si-based junctionless
MOSFETs. Ohmic contacts have been found to be limited by activated
acceptor species.
As was already discussed in the last paragraph of the p-channel de-
vices section, the main future goal should be the improvement of the hole
mobility. Additionally, as also ohmic contacts currently limit device per-
formance, optimisation in terms of stability and contact resistivity should
be performed, e.g. by means of ion implantation. Once these goals are
reached, complementary logic circuits may be fabricated and operated at
elevated temperatures. A first proof of concept towards complementary
GaN (C-GaN) has been performed showing a transfer characteristics of a
digital inverter.

126
Appendix

Optimisation of a Digital Etch Process


The digital etch processes were carried out in a Sentech SI-500 ICP-RIE
etch tool. The experiments to obtain a low-damage process were performed
on similar epitaxial material as the HFETs processed later. The samples
were provided by Aixtron SE. The layer stack consisted of a GaN-capped
Al0.26 Ga0.74 N/GaN structure, for which the AlGaN barrier layer and GaN
buffer layer thicknesses are about 20 nm and 2 µm, respectively. The ex-
periments were carried out using samples in van der Pauw configuration.
On 5 x 5 mm2 samples, contacts were deposited using a shadow mask. Sub-
sequently, rapid thermal annealing ensured ohmic contact behaviour. The
characterisation was performed via van der Pauw and Hall measurements.
A baseline digital etch process was derived from [117]. The basic process
parameters are shown in Tab. 6.1. Based on this process, the optimisation
was targeted upon reducing the mobility degradation caused by the etch
process. The parameters varied for the investigation were the chamber
pressure during the oxidation and the etching step, as well the RF power
during both steps.
Exemplarily, the influence of the chamber pressure during oxidation is
discussed. After each single etch cycle, the 2DEG properties of the sample
were characterised. As discussed earlier in Sec. 2.4, the 2DEG density ns
is a function of the barrier thickness. Since etching results in a mono-
tonically decreasing barrier thickness, ns is also decreasing monotonically.
To analyse the measurement results, the electron mobility µn is plotted vs.
ns . Results for samples which were etched employing different chamber
pressures during oxidation are shown in Fig. 6.1a. A clear influence of the
chamber pressure is observed. The mobility drops most rapidly for the low-
est pressure used. This is in agreement with the expectation. By reducing
the chamber pressure, a reduced probability of collisions between ions is
leading to a more vertically aligned bombardment of the sample surface.

127
Appendix

Thus, for such processes, it is likely that oxygen ions are implanted deeper
in the barrier. Using TRIM simulations [242], the depth oxygen ions can
reach was estimated to be 2.2 nm. Thereby, oxygen ions can form scatter-
ing centers, reducing the µn . By increasing the chamber pressure, a more
non-directional incidence of the ions occurs (TRIM simulations yielded a
maximum depth of 1.7 nm using an incidence angle of 15◦ ). Also, a more
homogeneously oxidised layer is to be expected. By that, a full removal
of the oxidised layer using the BCl3 step should be possible. Finally, less
oxygen remains in the barrier and the µn degradation with reduced ns is
decreased. The best results are obtained for the highest pressure possible
within the etching tool, which is 13.32 Pa. It has to be noted though, that
it is not possible to maintain a constant value of µn throughout the range
of measured ns . This is due to different scattering mechanisms limiting µn
for different values of ns [243] and also due to an increasing influence of
remote surface roughness scattering as the barrier thickness is reduced
[244].
The variation of the ion energy (influenced by the RF power) during the
oxidation step has a similar effect on the mobility degradation. Here, the
applied value should not be set too high to avoid penetration of oxygen ions
into the barrier.
A quite different finding is true for the chamber pressure during the
oxide removal step. If the pressure is set too high, no efficient removal of
the oxidised layers is ensured (the etch rate is reduced by a factor of 5
[245]). By that, a too high oxygen concentration is present in the barrier.

Table 6.1: Process parameters for the baseline process of the digital etch technique
derived from Ref. [117]. The process parameters of the optimised process
which differ from the baseline process are indicated in brackets.

Step Oxidation Oxide removal


Parameter Unit
Gas (-) O2 BCl3
Gas flow (sccm) 45 10
Pressure (Pa) 5 (13.32) 1.3
ICP power (W) 100 50
RF power (W) 30 (15) 15
Time (s) 30 45

128
(a) (b)

Figure 6.1: Dependence of µn on ns (a) as a function of the chamber pressure during


oxidation and (b) as a comparison of the baseline process and the optim-
ised process. While the first symbol (upper right corner) indicates data
of pristine samples, each following symbol represents a measurement
after an individual etch cycle.

The scattering centers created by the oxygen deteriorate the mobility.


Similar to the chamber pressure during etching, the RF power has to be
set at a compromise value. It is found that a too low value of the RF power
causes the same effect as a too high pressure, while a too high value of the
RF power causes too much damage introduced into the barrier. A more
detailed analysis of the latter three effects is described in [246].
The optimised process conditions are given in Tab. 6.1 on p. 128. In
Fig. 6.1b, the comparison of this optimised process vs. the baseline process
is depicted. A clear improvement is observed. This should lead to the µn
degradation of the electrons in the 2DEG to be as small as possible.
Furthermore, an investigation of the applicability to etch different nitride-
based materials has been performed for the optimised process. Specifically,
the etch rate of AlN is of great interest. As AlN is typically used as an
interlayer between the GaN channel and the barrier to enhance the µn , it
would be a proper means to use it as an etch-stop layer [247], [248]. A
detailed investigation was performed on that topic for which the complete
results can be found in [245]. The basic observation of that analysis is that

129
Appendix

the digital etch process is suitable for etching all group-III nitride materials1
with etch rates ranging from 0.45 nm (AlN) to 2.0 nm (In0.18 Ga0.82 N) per
cycle. Smooth semiconductor surfaces with root means square roughness
of about 1 nm in a 5×5 µm2 area remain smooth during the etching process.
Additionally, a selectivity of GaN:AlN of roughly 4:1 has been found. This is
also true for the selectivity of Alx Ga1−x N:AlN with x < 25 %. Together with
the good controllability of the process, an AlN spacer can thus be used
as an etch stop layer. The utilisation of such an etch stop layer during
digital recess etching has already been applied in transistor fabrication.
The results have been published in [103].

Parasitic Channel in Double Heterostructures and


Prevention Thereof
To identify the reason of this high off-state current, I-V measurements
between two isolated mesas have been performed. The isolation was real-
ised by a chlorine-based dry etch, and its depth is about 80 nm. As indic-
ated in Fig. 6.2a, the cap, the barrier and the GaN channel are removed
between the two mesas. The results are plotted in Fig. 6.2b. In agreement
with the transistor measurements, the highest leakage current is found
for sample BB10. With the knowledge provided by the results of van der
Pauw and Hall measurements, obviously parasitic carriers located below
the 2DEG are present in the layer stack for sample BB10. For low electric
fields, also the leakage currents of sample BB20 and BB50 are above that
of sample SHFET. Only at very high fields, an improvement in leakage is
seen for sample BB50 compared to sample SHFET. Considering these res-
ults, it has to be assumed that the leakage current is either flowing in the
AlGaN backbarrier, at the lower AlGaN/GaN buffer interface or in the GaN
buffer.
Taking a further look at the epitaxial layer stack, it is seen that the GaN
buffer leakage should be prevented by Fe doping applied for that layer.
Fe is forming an acceptor-like state in GaN [249] and thus compensates
donor-like states formed by either Si or O [250]–[252]. Although Si is a very
shallow donor also in Alx Ga1−x N with (x ≤ 10 %) [253], leakage originating
1
It has to be noted that BN (boron nitride) has not been part of the investigation as it is not
considered to be of importance so far for group-III nitride electronic devices.

130
(a) (b)

Figure 6.2: (a) Leakage current between two isolated mesas. (b) Illustration of the
recess depth between two isolated mesa.

from the AlGaN bulk may be excluded because of the band structure in
the grown structure (cf. Figs. 6.3a and 3.1). Nevertheless, the AlGaN/GaN
interface needs to be taken into account. Here, identical to the top bar-
rier/GaN channel interface, the polarisation difference between AlGaN and
GaN leads to an interface charge and the change in material to a conduc-
tion band offset. Together, both effects, even if less strong than in the upper
region, might lead to the formation of a parasitic 2DEG below the AlGaN
backbarrier.
To verify this, TCAD simulation have been performed [79]. A rather high
donor concentration of 1×1017 cm−3 is assumed for the GaN buffer [252].
This is - to a certain extent - supported by the rather high mesa leakage
of sample SHFET. Additionally, to compensate the donor states, a consid-
erable concentration (1×1018 cm−3 and 1×1019 cm−3 ) of Fe dopants2 using
a trap-level of 0.7 eV below the conduction band and a capture-cross sec-
tion of 8×10−13 cm2 [254], [255] has been implemented. The addition of Fe
dopants is stopped 50 nm before growth of the AlGaN backbarrier. The res-
ulting band diagrams for the region of the lower interface of all samples are
depicted in Fig. 6.3a. As can be seen in the figure, indeed, a second channel
is the likely reason for high off-state leakage current. The sheet electron
2
The actual doping concentration is undisclosed by the epitaxial growers.

131
Appendix

(a) Fe doping stopped 50 nm before back- (b) Fe doping stopped 1 nm before back-
barrier growth barrier growth

Figure 6.3: Band diagrams showing the lower AlGaN backbarrier/GaN:Fe buffer
interface with (a) an accumulation of electrons there, independent of
doping level and (b) no accumulation of holes

densities for the presented diagrams are in the range of 2.9×1012 cm−2 (for
Fe = 1×1018 cm−3 ) to 2.7×1012 cm−2 (for Fe = 1×1019 cm−3 ). Even in the case
that the Fe doping is performed up to the AlGaN/GaN interface, a conduct-
ive channel with a carrier concentration of 0.5×1012 cm−2 is obtained (not
shown). This channel can easily be contacted by vertical leakage current
paths along screw type threading dislocations [256]. An improvement of
this situation can be achieved by the application of several approaches.
First, the Fe dopants could be added well into the backbarrier, thus ef-
fectively hindering the formation of the parasitic channel. The result for
Fe doping applied for the first 50 nm of backbarrier growth can be seen in
Fig. 6.3b. Second, the alloyed ohmic contacts could be replaced e.g. by
ohmic contacts fabricated using an n-GaN regrowth process [256], [257]
which would hinder contacting the buried channel. Third, the utilisation
of an AlN nucleation instead of the used GaN nucleation would hinder such
an effect [54]. Owing to the accompanying large wafer bow however, this
approach is typically not employed for large-diameter (4 inch or larger) sub-
strates. The first approach has successfully been employed for the growth

132
of further BB50 wafers which are utilised in Sec. 3.7.

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and U. Mishra, ‘Effect of ohmic contacts on buffer leakage of GaN transist-
ors’, IEEE Electron Device Lett., vol. 27, no. 7, pp. 529–531, 2006.
[257] H.-C. Seo, P. Chapman, H.-I. Cho, J.-H. Lee and K. Kim, ‘Ti-based non-
alloyed Ohmic contacts for Al0.15 Ga0.85 N/GaN high electron mobility tran-
sistors using regrown n+ -GaN by plasma assisted molecular beam epitaxy’,
Appl. Phys. Lett., vol. 93, no. 10, 102102, 2008.

158
List of Figures

2.1 Crystal structure of group III-nitride material. Grey atoms indicate


metal species, while greenish atoms indicate nitrogen. The growth
direction is [0001] [54]. . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 (a) Simplest form a heterostructure and (b) associated conduction
band diagram obtained by using TCAD Sentaurus [79]. The electron
concentration in the 2DEG and fixed charge densities at interfaces are
also shown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Schematic of the simplest form of an HFET showing two alloyed ohmic
contacts source and drain and a Schottky contact as gate. . . . . . . . 13
2.4 Simulated conduction band edges for different gate-source biases Vgs .
Also shown is the respective simulated distribution of electrons. In
the inset, the integral of the carrier concentration is plotted vs. the
gate-source bias Vgs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5 (a) Dynamic characterisation showing the difference between a DC
measurement and pulsed IV measurements without bias and with
applied off-state stress. Current collapse is indicated by the increase
in Ron . (b) Illustration of possible trapping mechanisms at donor-type
surface states (yellow arrows) and in acceptor-type states in either the
barrier (black arrow) or the bulk (green arrows). . . . . . . . . . . . . . 15

3.1 Band diagram of a structure comprising insulator (oxide), cap, barrier,


channel and backbarrier. Electron distribution in the 2DEG and fixed
charge densities σ at the boundaries are shown. . . . . . . . . . . . . 22
3.2 (a) Schematic of the basic structure for which critical layers are varied
as indicated. (b) Positive Vth shifts obtained by employing backbar-
riers with different compositions in dependence on the GaN channel
thickness. Dotted line indicates the reference point which is when no
backbarrier is used. Dashed line indicates a negative shift which is
unavoidable and which is related to the barrier. . . . . . . . . . . . . . 27
3.3 (a) Changes in Vth vs. the total thickness of GaN cap and oxide plotted
for different backbarrier compositions and GaN buffer. (b) Changes
in Vth for different fixed interface charge and fixed bulk oxide charge
densities. The reference is plotted for a charge-free interface (no back-
barrier present). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

159
List of Figures

3.4 Schematic cross sections for the devices of the recessed gate series
for (a) the reference sample without recessed gate and the samples for
which (b) 6 and (c) 10 cycles of the digital recess etch were applied. . . 32
3.5 Transfer characteristics in (a) linear scale at Vds = 3 V and (b) in semi-
logarithmic scale at Vds = 10 V. Device dimensions in (a) as indicated
in (b) except for Lg . After [104]. . . . . . . . . . . . . . . . . . . . . . . 33
3.6 Output characteristics under static and pulsed conditions (pulse
length 200 ns, cycle length 1 ms). The voltage insets represent the
applied gate bias. After [104]. . . . . . . . . . . . . . . . . . . . . . . . 35
3.7 Simulated distribution of the electric field at the drain edge of the gate.
The peak of the electric field is moved from the SiN/GaN cap interface
to the AlGaN barrier. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.8 Transfer characteristics in (a) linear and (b) semi-logarithmic scale
(in (b) with associated gate leakage currents). Device dimensions:
Lsg = 1.5 µm, Lg = 1.0 µm, Lgd = 2.5 µm, Wg = 2×50 µm. . . . . . . . . . . 38
3.9 Output characteristics under static and pulsed conditions (pulse
length 200 ns, cycle length 1 ms). The voltage insets represent the
quiescent Vgs and Vds . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.10 Schematic cross sections for (a) the reference sample without back-
barrier and 1 µm channel and for the samples with backbarrier and
(b) 50 nm, (c) 20 nm and (d) 10 nm channel. . . . . . . . . . . . . . . . 41
3.11 (a) Electron mobility µ n , (b) sheet carrier density ns and (c) sheet res-
istance Rsh extracted from van der Pauw and Hall measurements. . . . 42
3.12 Transfer characteristics in (a) linear and (b) semi-logarithmic scale.
The colours used in (b) refer to the identical devices from (a). . . . . . 43
3.13 Output characteristics under static and pulsed conditions (pulse
length 200 ns, cycle length 1 ms). The values given in the caption
represent the quiescent Vgs and Vds . . . . . . . . . . . . . . . . . . . . 45
3.14 Overview of extracted values for the ratio of dynamic vs. static Rds,on
and for absolute values of dynamic Rds,on-dyn ×A. . . . . . . . . . . . . . 46
3.15 I-V characteristics of large-area diodes for samples with ALD-AlOx as
gate insulator. Additionally shown is an I-V curve of an unrecessed,
but passivated Schottky-gated reference diode. . . . . . . . . . . . . . 48
3.16 C-V characteristics of large-area diodes. The sweeps were first per-
formed from negative to positive bias and then from positive to negative
bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.17 Sheet charge density vs. applied voltage for the large-area diodes. The
results were obtained by integrating the C-V curves shown in Fig. 3.16. 50

160
List of Figures

3.18 Values for Vth extracted from forward and backward sweeps of C-V
measurements in dependence on tox . The fit to meet Vth was per-
formed assuming negative fixed interface charge and positive bulk
oxide charge. A second curve assuming only negative interface charge
(the value taken from the fit) is also shown. . . . . . . . . . . . . . . . 51
3.19 Transfer characteristics of a MIS-HFET. The measurement was per-
formed after various stress times at Vgs = -8 V, Vds = 10 V. The stress
times are indicated with the colour intensity. The second sweep for
0 s (dashed line) was performed immediately after the 1000 s meas-
urement. A shift in Vth in dependence on the stress time is observed. . 53
3.20 Different values for Vth in dependence on sample and stress time for
three different bias conditions (a) off-state with applied Vds (b) on-state
at a point close to the knee and (c) on-state in the saturation region. . 54
3.21 Process scheme for the plasma-oxidised samples. (a) First, a metal
layer, in this case Al, is evaporated. (b) Second, the sample is exposed
to oxygen plasma in an ICP-RIE. (c) Third, Ni and Au are evaporated
and a subsequent lift-off is performed. After [182]. . . . . . . . . . . . 57
3.22 (a) Large-area diode leakage current density versus voltage for different
annealing temperatures. (b) Comparison of off-state transistor gate
leakage current at Vgs = -8 V, Vds = 10 V versus annealing temperature.
After [182]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.23 C-V measurements of large-area diodes at f = 1 MHz in dependence
on the annealing temperatures. After [182]. . . . . . . . . . . . . . . . 59
3.24 (a) Transfer characteristics of transistors for the samples subjected
to different annealing temperatures. Values for subthreshold swing
are indicated. Vds = 10 V. Lg = Lsg = Lgd = 2 µm. Wg = 246 µm. (b) Vth and
gm,max extracted from transfer characteristics in linear scale. After [182]. 60
3.25 C-V measurements of large-area diodes at f = 1 MHz for the different
samples. Solid line indicates the measurement from negative to pos-
itive voltage and the dotted line corresponds to the reverse direction.
After [197]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.26 Extracted values for Vth and Cox . Data is extracted from C-V meas-
urements shown in Fig. 3.25. The orange line indicates Vth of the
Schottky-gated sample. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
3.27 Behaviour of Vth vs. inverse Cox for four different interface charge dens-
ities nit which were extracted for the four samples. The stars depict
the actual values extracted for the samples. The dashed line indicates
the case of the σ it matching the polarisation difference between barrier
and channel [185]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.28 Current density vs. voltage of large-area diodes the samples with
plasma-oxidised metal layers. As a reference, the Schottky-gated
sample is also shown. After [197] . . . . . . . . . . . . . . . . . . . . . 66

161
List of Figures

3.29 (a) Transfer characteristics of an MIS-HFET of sample Zr3. The


measurement was performed as already discussed for the ALD-AlOx
samples. The off-state stress times are indicated with the colour
intensity. The second sweep for 0 s was performed immediately after
the 1000 s measurement. (b) Extracted Vth vs. stress time for sample
Zr3 and sample Al4 at two different stress conditions in on- and
off-state. Device dimensions: Lsg = 2.0 µm, Lg = 2.0 µm, Lgd = 2.5 µm,
Wg = 2×50 µm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.30 Schematic cross sections for the devices of the final series comprising
all methods. (a) Starting point, a Ni-gated single heterostructure FET.
(b) Pt-gate instead of Ni-gate. (c) Introduction of the Al0.07 Ga0.93 N back-
barrier. (d) Insertion of the ALD-AlOx gate insulator. (e) Employing of
the digital etch technique to recess the gate. . . . . . . . . . . . . . . 68
3.31 Transconductance and transfer characteristics measured in forward
and reverse direction (except for device A). After [166]. . . . . . . . . . 69
3.32 C-V characteristics of devices B - E measured at 1 MHz. For Device B,
C and D, large-area diodes were measured. For sample E, a transistor
with Lg = 10 µm was characterised. . . . . . . . . . . . . . . . . . . . . 71
3.33 Pulsed I-V measurements of (a) device C and (b) device E. Tran-
sistor dimensions were Lsg = 1.5 µm, Lg = 1.0 µm, Lgd = 2.5 µm and
Wg = 2×50 µm. Pulse time = 200 ns, cycle time = 1 ms. After [166]. . . . 72
3.34 Transfer characteristics of device E for a pristine device, for a second
measurement before a pulsed I-V measurement and a third measure-
ment immediately after the pulsed I-V measurement. After [166]. . . . 73

4.1 (a) Epitaxial layer stack comprising n-region, barrier and p-region. A
2DEG and a 2DHG are formed below and above the heterointerface,
respectively. (b) Band diagram of this epitaxial layer stack. Con-
duction and valence band are shown together with the accumulated
2DHG (blue) and 2DEG (red) concentrations. Interfaces are depicted
with associated polarisation charges. . . . . . . . . . . . . . . . . . . . 77
4.2 (a) Simulated band diagrams of a structure with an Al0.42 In0.03 Ga0.55 N
barrier in dependence on gate-source voltage. Clearly visible is the
fixed 2DEG quantum well as long as the 2DHG quantum well is
present. (b) Extracted electron and hole concentration illustrating
the behaviour which is observed in (a). . . . . . . . . . . . . . . . . . . 81
4.3 Epitaxial layer stack for all p-channel devices. The various composi-
tions of the Alx Iny Ga1−x−y N backbarrier are shown in Tab. 4.1. A de-
tailed analysis of doping concentrations can be found in [210]. After
[210]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

162
List of Figures

4.4 (a) Current density vs. voltage characteristics of large-area diodes for
samples with Ni, Mo and Zr metallisation. (b) Extracted values for the
Schottky barrier height and the ideality factor. . . . . . . . . . . . . . 87
4.5 Transfer characteristics of transistors for samples with Ni, Mo and Zr
metallisation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.6 Sample α: (a) Transfer characteristics and gate currents of transistors
with different recess depth in the access region. [111] (b) Extracted
values of the drain current and gate leakage current in dependence
on access region recess depth. [111] . . . . . . . . . . . . . . . . . . . 89
4.7 (a) Valence bands (solid) and hole concentrations (dashed) in the ac-
cess and gate region just beneath the surface. Three different condi-
tions are shown: Vgs = 0 V (black) and Vgs = -2 V (red) for the schematic
shown in (b) top; Vgs = -2 V for the schematic shown in (b) bottom (blue).
(b) Schematics of the device structure with (top) and without (bottom)
highly Mg-doped GaN layer (top). . . . . . . . . . . . . . . . . . . . . . 91
4.8 (a) Schematic of devices with (top) and without (bottom) the GaN:Mg++
layer beneath the gate. The devices are based on sample γ. (b) Trans-
fer characteristics and gate currents of these two samples. Device
dimensions: Lsg = 1.5 µm, Lg = 1.0 µm, Lgd = 2.5 µm, Wg = 2x50 µm [111]. 92
4.9 Band diagrams and structure for samples γ-GR7 (a), (b), γ-GR14 (c),
(d) and γ-GR21 (e), (f), respectively. The vertical dashed lines in the
structures indicate the region from which the band diagrams are de-
rived. All graphs [111]. . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.10 Transfer characteristics and gate currents in semi-logarithmic scale
of three samples with different gate recess depths of 7, 14 and 21 nm.
After [111]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.11 (a) Symbols indicate 2DHG densities extracted from band diagram cal-
culated in dependence on Vgs and recess depth. The x-axis intercepts
of the linear fits indicate Vth . (b) Comparison of the simulated and
experimental threshold voltages in dependence on recess depth. After
[111]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.12 Final device structure including ohmic contacts, access region recess
in between and gate metallisation. No pads were deposited for the
final devices [218]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.13 Transfer characteristics and gate currents in semi-logarithmic scale
of the samples with different barriers [111]. . . . . . . . . . . . . . . . 99
4.14 (a) Value of the on- and the off-current extracted from the semi-
logarithmic transfer characteristics [111]. (b) Values for the sub-
threshold slope (SS) and the drain induced barrier lowering (DIBL)
extracted from the semi-logarithmic transfer characteristics [111]. . . 101

163
List of Figures

4.15 (a) Capacitance values normalised to the gate area in dependence on


Vgs and frequency. [218] (b) Raw data of absolute value and phase
angle ϕ of the complex impedance Z. Values are shown for different
frequencies [colours as in (a)] in dependence on Vgs . . . . . . . . . . . 103
4.16 Equivalent-circuit model for the off-state of the fatFET. Lengths are
given for accurate capacitor calculation. After [218]. . . . . . . . . . . 104
4.17 Equivalent-circuit model for the on-state of the fatFET. Lengths are
given for accurate capacitor calculation. . . . . . . . . . . . . . . . . . 104
4.18 |Z| and ϕ values in dependence on frequency for different Vgs in (a)
off-state and (b) on-state. (a) Grey and (b) light coloured curves show
the simulated fits using the equivalent-circuit models displayed in
Figs. 4.16 and 4.17, respectively. The kink appearing at 77 kHz is
related to the measurement setup. . . . . . . . . . . . . . . . . . . . . 106
4.19 Transfer characteristic and associated transconductance at Vds = -8 V
for the device based on sample ϸ [227]. . . . . . . . . . . . . . . . . . 107
4.20 Extrapolation of small-signal parameters |h21 | and MUG. [227] . . . . 108
4.21 Dependence of fT on drain-source bias for different gate-source biases
[227]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.22 (a) Results of transfer length method at different temperatures [218].
(b) I-V measurement of an open-channel structure with a gap of 5 µm
[218]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.23 (a) Transfer characteristics of a fatFET at Vds = -0.1 V for different tem-
peratures. (b) Extracted intrinsic effective hole mobilities from C-V
measurements and I-V measurements of fatFETs. . . . . . . . . . . . 112
4.24 Output characteristics of the device based on sample γ measured at
different temperatures at Vgs = -2 V and +1 V [218]. . . . . . . . . . . . 113
4.25 Transfer characteristics in linear and semi-logarithmic scale at (a)
room temperature and (b) at 175 ◦ C for different Vds [218]. . . . . . . . 114
4.26 (a) Transfer characteristics in semi-logarithmic scale at Vds = -1 V for
different temperatures. (b) Extracted values for on/off ratio and SS
at Vds = -0.1 V [218]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

5.1 (a) Epitaxial layer stack used for the experiments. (b) Schematic of the
integrated n- and p-channel device. . . . . . . . . . . . . . . . . . . . 118
5.2 Transfer characteristics and gate leakage currents for different |Vds |
of separately fabricated depletion mode n- and p-HFETs. These tran-
sistors were fabricated without gate-recess [241]. . . . . . . . . . . . . 119
5.3 Process flow for the integrated devices. . . . . . . . . . . . . . . . . . . 120
5.4 Transfer characteristics and gate leakage currents in dependence on
|Vds | of e-mode n- and p-HFETs integrated on a single wafer [241]. . . 121

164
List of Figures

5.5 Output characteristics of both p-channel and n-channel HFET which


were also measured in an inverter configuration. For the n-channel
HFET, gate leakage is very pronounced [241]. . . . . . . . . . . . . . . 121
5.6 Voltage transfer curve (Vdd = 1 V) of the fabricated inverter structure
showing a clear high output level and a steep transition from VOH to
VOL close to the Vdd /2 [241]. . . . . . . . . . . . . . . . . . . . . . . . 122

6.1 Dependence of µn on ns (a) as a function of the chamber pressure


during oxidation and (b) as a comparison of the baseline process and
the optimised process. While the first symbol (upper right corner)
indicates data of pristine samples, each following symbol represents a
measurement after an individual etch cycle. . . . . . . . . . . . . . . . 129
6.2 (a) Leakage current between two isolated mesas. (b) Illustration of the
recess depth between two isolated mesa. . . . . . . . . . . . . . . . . . 131
6.3 Band diagrams showing the lower AlGaN backbarrier/GaN:Fe buffer
interface with (a) an accumulation of electrons there, independent of
doping level and (b) no accumulation of holes . . . . . . . . . . . . . . 132

165
List of Tables

2.1 Power-switching figure of merit for various materials and material sys-
tems. All values were taken from [74] except for the mobilities of the
AlGaN/GaN [75] and AlN/AlGaN system ([76] as cited in [77]). . . . . 8

3.1 Extracted values of the oxide capacitance, the associated oxide thick-
ness and threshold voltages for the measurement in forward (Vth,p )
and backward (Vth,n ) direction. Calculated fixed interface and fixed
bulk oxide charge densities to account for the Vth trend with tox . . . . . 50
3.2 Processed samples of the plasma oxidation series given with metal,
metal layer thickness, DC bias during plasma oxidation and annealing
temperature. All samples share the oxidation time of 10 min (except
for sample Zr5 for which it was 15 min) and ICP power during oxidation
of 50 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.3 Extracted threshold voltages for devices B - E. Extracted oxide capa-
citance and interface charge density for devices D and E. . . . . . . . 71

4.1 Epitaxially grown layer stacks with associated backbarrier composi-


tions. Additionally given are polarisation difference between barrier
and GaN channel (σ int ) [210], sheet hole densities, hole mobilities and
sheet resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.1 Process parameters for the baseline process of the digital etch tech-
nique derived from Ref. [117]. The process parameters of the optimised
process which differ from the baseline process are indicated in brackets.128

167
Journal Publications of The Author
The following bibliography presents a complete list of peer-reviewed journal paper
which are direct or indirect results of the work performed during this thesis.

1. H. Hahn, F. Benkhelifa, O. Ambacher, F. Brunner, A. Noculak, H. Kalisch, A.


Vescan, ‘Threshold Voltage Engineering in GaN-Based HFETs: A Systematic
Study with the Threshold Voltage Reaching More Than +2 V’, IEEE Trans.
Electron Devices, 2015, DOI 10.1109/TED.2014.2381292.

2. H. Yacoub, D. Fahle, M. Finken, H. Hahn, C. Blumberg, W. Prost, H. Kalisch,


M. Heuken and A. Vescan, ‘The effect of the inversion channel at the AlN/Si
interface on the vertical breakdown characteristics of GaN-based devices’,
Semicond. Sci. Technol., vol. 29, no. 11, 115012, 2014.

3. H. Hahn, B. Reuters, A. Pooth, H. Kalisch, A. Vescan , ‘Characterisation of


GaN-based p-channel device structures at elevated temperatures’, Semicond.
Sci. Technol., vol. 29 no. 7, 075002, 2014.

4. B. Reuters, H. Hahn, A. Pooth, B. Holländer, U. Breuer, M. Heuken, H.


Kalisch, A. Vescan, ‘Fabrication of p-channel heterostructure field effect tran-
sistors with polarization-induced two-dimensional hole gases at metal-polar
GaN/AlInGaN interfaces’, J. Phys. D: Appl. Phys, vol. 47, no. 17, 175103,
2014.

5. B. Reuters, J. Strate, H. Hahn, M. Finken, A. Wille, M. Heuken, H. Kalisch,


A. Vescan, ‘Selective MOVPE of InGaN-based LED structures on non-planar
Si (111) facets of patterned Si (100) substrates’, J. Crys. Growth, vol. 391,
pp. 33-40, 2014.

6. H. Hahn, B. Reuters, A. Pooth, A. Noculak, H. Kalisch, A. Vescan, ‘First


Small-Signal Data of GaN-Based p-Channel Heterostructure Field Effect
Transistors’, Jpn. J. Appl. Phys., vol. 52, no. 12, 128001, 2013.

7. H. Hahn, B. Reuters, A. Pooth, B. Holländer, M. Heuken, H. Kalisch, A. Ves-


can, ‘p-Channel enhancement and depletion mode GaN-based HFETs with
quaternary backbarriers’, IEEE Trans. Electron Devices, vol. 60, no. 10, pp.
3005-3011, 2013.

169
Journal Publications of The Author

8. H. Hahn, F. Benkhelifa, O. Ambacher, A. Alam, M. Heuken, H. Yacoub, A.


Noculak, H. Kalisch, A. Vescan, ‘GaN-on-Si Enhancement Mode Metal Insu-
lator Semiconductor Heterostructure Field Effect Transistor with On-Current
of 1.35 A/mm’, Jpn. J. Appl. Phys., vol. 52, no. 9, 090204, 2013.

9. W. Witte, B. Reuters, D. Fahle, H. Behmenburg, K.-R. Wang, A. Trampert, B.


Hollaender, H. Hahn, H. Kalisch, M. Heuken, A. Vescan, ‘AlGaN/GaN hetero-
structure field-effect transistors regrown on nitrogen implanted templates’,
Semicond. Sci. Technol., vol. 28, no. 8, 085006, 2013.

10. H. Hahn, B. Reuters, H. Kalisch, A. Vescan, ‘AlN barrier HFETs with AlGaN
channels to shift the threshold voltage to higher positive values: a proposal’,
Semicond. Sci. Technol., vol. 28, no. 7, 074017, 2013.

11. H. Hahn, H. Behmenburg, N. Ketteniss, M. Heuken, H. Kalisch, A. Ves-


can, ‘Enhancement mode AlInGaN/GaN MISHFETs with plasma-oxidised
AlOx/TiOx as gate insulator’, phys. status solidi C, vol. 10, no. 5, pp.
840-843, 2013.

12. B. Reuters, H. Hahn, H. Behmenburg, M. Heuken, H. Kalisch, A. Vescan,


‘Insulating behaviour of interfaces in regrown Al0.23 Ga0.77 N/GaN double het-
erostructures on Al0.07 Ga0.93 N back-barrier templates’, phys. status solidi c,
vol. 10, no. 5 , pp. 799-802, 2013.

13. Ö. Tuna, H. Hahn, H. Kalisch, C. Giesen, A. Vescan, M. V. Rzheutski, V. N.


Pavlovskii, E. V. Lutsenko, G. P. Yablonskii, M. Heuken, ‘MOVPE Growth,
Optical and Electrical Characterization of Thick Mg-Doped InGaN Layers’, J.
Cryst. Growth, vol. 370, pp. 2-6, 2013.

14. B. Reuters, A. Wille, N. Ketteniss, H. Hahn, B. Holländer, M. Heuken,


H. Kalisch, A. Vescan, ‘Polarization-Engineered Enhancement-Mode High-
Electron-Mobility Transistors Using Quaternary AlInGaN Barrier Layers’, J.
Electronic Mater., vol. 42, no. 5, pp. 826-832, 2013.

15. H. Hahn, J. B. Gruis, N. Ketteniss, F. Urbain, H. Kalisch, A. Vescan, ‘Influ-


ence of mask material and process parameters on etch angle in a chlorine-
based GaN dry etch’, J. Vac. Sci. Tech. A, vol. 30, no. 5, 051302, 2012.

16. H. Hahn, A. Alam, M. Heuken, H. Kalisch, A. Vescan, ‘Investigation of


plasma-oxidised aluminium as gate dielectric for AlGaN/GaN MISHFETs’,
Semicond. Sci. Technol., vol. 27, no. 6, 062001, 2012.

17. H. Hahn, B. Reuters, A. Wille, N. Ketteniss, F. Benkhelifa, O. Ambacher,


H. Kalisch, A. Vescan, ‘First polarisation-engineered compressively strained
AlInGaN barrier enhancement-mode MISHFET’, Semicond. Sci. Technol., vol.
27, no. 5, 055004, 2012.

170
18. N. Ketteniss, H. Behmenburg, H. Hahn, A. Noculak, B. Holländer H. Kalisch,
M. Heuken, A. Vescan, ‘Quaternary Enhancement-Mode HFET With In Situ
SiN Passivation’, IEEE Electron Device Lett., vol. 33, no. 4, pp. 519-521,
2012.

19. H. Hahn, J. Achenbach, N. Ketteniss, A. Noculak, H. Kalisch, A. Vescan,


‘Oxygen addition to fluorine based SiN etch process: Impact on the electrical
properties of AlGaN/GaN 2DEG and transistor characteristics’, Solid-State
Electron., vol. 67, no. 1, pp. 90-93, 2012.

20. H. Hahn, G. Lükens, N. Ketteniss, H. Kalisch, A. Vescan, ‘Recessed-Gate


Enhancement-Mode AlGaN/GaN Heterostructure Field-Effect Transistors on
Si with Record DC Performance’, Appl. Physics Express, vol. 4, no. 11,
114102, 2011.

171
Conference Publications of The Author
The following list of conferences presents a complete summary of oral talks and
poster presentations on international conferences.

1. A. Vescan, H. Hahn, B. Reuters and H. Kalisch, ‘Novel GaN-based Transistors


Using Polarization Engineering’, Invited talk at 10th International Conference
on Advanced Semiconductor Devices and Microsystems (ASDAM), Smolenice,
Slowakia, 2014.

2. H. Hahn, B. Reuters, A. Pooth, G. Lükens, S. Geipel, S. Kotzea, B. Holländer,


U. Breuer, M. Heuken, H. Kalisch and A.Vescan, ‘p-Channel GaN HFETs for
application in harsh environments’, oral presentation at 7th Wide Band Gap
Semiconductor and Components Workshop, Frascati, Italy, 2014.

3. H. Hahn, B. Reuters, S. Geipel, H. Kalisch and A. Vescan, ‘Charge balancing


in GaN-based devices by employing 2DHG and 2DEG’, oral presentation at
The International Workshop on Nitride Semiconductors (IWN), Wroclaw, Poland,
2014.

4. H. Yacoub, D. Fahle, M. Finken, C. Blumberg, W. Prost, H. Hahn, H. Kalisch,


M. Heuken and A. Vescan, ‘Investigations of the Limiting Mechanisms of Ver-
tical Breakdown of GaN-on-Silicon’, poster presentation at The International
Workshop on Nitride Semiconductors (IWN), Wroclaw, Poland, 2014.

5. H. Hahn, B. Reuters, S. Kotzea, G. Lükens, S. Geipel, H. Kalisch and A.


Vescan, ‘First Monolithic Integration of GaN-Based Enhancement Mode
n-Channel and p-Channel Heterostructure Field Effect Transistors’, oral
presentation at 72nd Device Research Conference (DRC), Santa Barbara,
California, USA, 2014.

6. H. Hahn, B. Pécz, M. Heuken, H. Kalisch and A. Vescan, ‘Plasma-oxidised


metal layers for gate insulation in GaN-based devices’, oral presentation at
the 38th Workshop on Compound Semiconductor Devices and Integrated Cir-
cuits held in Europe (WOCSDICE), Delphi, Greece, 2014.

7. H. Hahn, F. Benkhelifa, O. Ambacher, H. Kalisch and A. Vescan, ‘Threshold


voltage behaviour in GaN-based MIS-HFETs by thickness variation of atomic
layer deposited AlOx ’, oral presentation at the Workshop on Dielectric in Mi-
croelectronics (WODIM), Cork, Ireland, 2014.

173
Conference Publications of The Author

8. H. Kalisch, B. Reuters, H. Hahn, A. Pooth, A. Wille, N. Ketteniss, B. Hol-


laender, M. Heuken and A. Vescan, ‘Polarization Engineering for Advanced
GaN-Based Transistors’, invited talk at the 5th International Symposium on
Growth of III-Nitrides (ISGN-5), Atlanta, USA, 2014.

9. H. Hahn, F. Benkhelifa, O. Ambacher, F. Brunner, J. Würfl, A. Noculak,


H. Kalisch and A. Vescan, ‘Systematic study towards enhancement mode
GaN-based HFETs’, oral presentation at the 41st International Symposium on
Compound Semiconductors (ISCS), Montpellier, France, 2014.

10. B. Reuters, B. Foltynski, H. Hahn, B. Holländer, M. Heuken, H. Kalisch, A.


Vescan, ‘Epitaxial Growth of AlInGaN layers on AlN templates for backbarrier
application in DHFET’, oral presentation at the 41st International Symposium
on Compound Semiconductors (ISCS), Montpellier, France, 2014.

11. B. Reuters, H. Hahn, A. Pooth, B. Holländer, M. Heuke, H. Kalisch, A. Vescan,


‘Novel p-channel HFET Using Polarization-Induced Two-Dimensional Hole
Gases at Metal-Polar GaN/AlInGaN Interfaces’, oral presentation at the 10th
International Conference on Nitride Semiconductors (ICNS), Washington D.C.,
USA, 2013.

12. H. Hahn, B. Reuters, A. Pooth, H. Kalisch, and A. Vescan, ‘p-Channel


GaN/AlInGaN Heterostructure Field Effect Transistor Operation at Elevated
Temperatures’, oral presentation at the 10th International Conference on
Nitride Semiconductors (ICNS), Washington D.C., USA, 2013.

13. N. Ketteniss, B. Reuters, B. Holländer, H. Hahn, F. Benkhelifa, O. Ambacher,


H. Kalisch, A. Vescan, ‘Quaternary nitride enhancement mode MISHFETs
with different gate dielectrics’, oral presentation at the 37th Workshop on Com-
pound Semiconductor Devices and Integrated Circuits held in Europe (WOC-
SDICE), Warnemünde, Germany, 2013.

14. B. Reuters, H. Hahn, A. Pooth, B. Holländer, H. Kalisch, A. Vescan, ‘Control


of two-dimensional hole gas density at GaN/AlInGaN interfaces by polar-
ization engineering’, oral presentation at the 37th Workshop on Compound
Semiconductor Devices and Integrated Circuits held in Europe (WOCSDICE),
Warnemünde, Germany, 2013.

15. W. Witte, B. Reuters, D. Fahle, H. Behmenburg, B. Holländer, H. Hahn, H.


Kalisch, M. Heuken, A. Vescan, ‘Characterization of AlGaN/GaN HFET re-
grown on nitrogen-implanted templates’, oral presentation at the 37th Work-
shop on Compound Semiconductor Devices and Integrated Circuits held in
Europe (WOCSDICE), Warnemünde, Germany, 2013.

174
16. H. Hahn, B. Reuters, A. Pooth, H. Kalisch, and A. Vescan, ‘Depletion and
enhancement mode p-channel GaN/AlInGaN/GaN HFETs’, oral presentation
at the 37th Workshop on Compound Semiconductor Devices and Integrated
Circuits held in Europe (WOCSDICE), Warnemünde, Germany, 2013.

17. N. Ketteniss, H. Hahn, B. Reuters, H. Kalisch, A. Vescan, ‘Concepts And


Technologies For Enhancement Mode GaN-based Heterostructure Field Effect
Transistors’, oral presentation on ESA - MOD workshop on wide bandgap
semiconductors, Noordwijk, The Netherlands, October 2012

18. H. Hahn, H. Behmenburg, N. Ketteniss, M. Heuken, H. Kalisch, A. Ves-


can, ‘Enhancement mode InAlGaN/GaN MISHFETs with plasmaoxidised
AlOx/TiOx as gate insulator’, oral presentation at the 39th International
Symposium on Compound Semiconductors (ISCS), Santa Barbara, California,
USA, 2012.

19. B. Reuters, H. Hahn, H. Behmenburg, M. Heuken, H. Kalisch, A. Vescan,


‘Insulating behaviour of interfaces in regrown Al0.23 Ga0.77 N/GaN double het-
erostructures on Al0.07 Ga0.93 N back-barrier templates’, poster presentation at
the 39th International Symposium on Compound Semiconductors (ISCS), Santa
Barbara, California, USA, 2012.

20. W. Witte, B. Reuters, D. Fahle, H. Behmenburg, H. Hahn, M. Heuken, H.


Kalisch, A. Vescan, ‘Regrowth of AlGaN/GaN HEMT on N-Implanted Tem-
plate’, poster presentation at the 39th International Symposium on Compound
Semiconductors (ISCS), Santa Barbara, California, USA, 2012.

21. N. Ketteniss, B. Reuters, B. Holländer, H. Hahn, H. Kalisch, A. Vescan, ‘Qua-


ternary nitride enhancement mode HFET with 260 mS/mm and a threshold
voltage of +0.5 V’, oral presentation at 70th Device Research Conference (DRC),
State College, Pennsylvania, USA, 2012.

22. B. Reuters, A.Wille, B. Holländer, N. Ketteniss, H. Hahn, M. Heuken, H.


Kalisch, A. Vescan, ‘Polarization-engineered high electron mobility transist-
ors using quaternary AlInGaN barrier layers’, oral presentation at 54th An-
nual Electronic Materials Conference (EMC), State College, Pennsylvania, USA,
2012.

23. H. Hahn, H. Kalisch, A. Vescan, ‘Device properties of AlGaN/GaN-based MIS


heterostructures with plasma-oxidised AlOx/TiOx as gate dielectric’, oral
presentation at the 36th Workshop on Compound Semiconductor Devices and
Integrated Circuits held in Europe (WOCSDICE), Porquerolles, France, 2012.

24. H. Behmenburg, N. Ketteniss, H. Hahn, A. Noculak, B. Holländer, H. Kalisch,


M. Heuken and A. Vescan, ‘Enhancement mode HFET with Ultrathin InAl-
GaN Barrier Layer and In Situ SiN Passivation’, poster presentation at 16th

175
Conference Publications of The Author

International Conference on Metal Organic Vapor Phase Epitaxy (ICMOVPE),


Busan, South Korea, 2011.

25. N. Ketteniss, H. Hahn, W. Witte, H. Kalisch and A. Vescan, ‘Dry etching


processes for GaN device technology‘, oral presentation at Seminar Plasma
Prozesstechnologie, Berlin, Germany, 2011 (invited).

26. B. Reuters, A. Wille, H. Hahn, N. Ketteniss, B. Holländer, M. Heuken, H.


Kalisch, A. Vescan, ‘Polarization-engineered HEMT structures using pulsed
MOCVD AlInN/(Al)InGaN layer growth’, oral presentation at 26th DGKK-
Workshop, Stuttgart, Germany, 2011.

27. W. Witte, H. Koch, D. Fahle, H. Hahn, H. Kalisch, M. Heuken, A. Vescan,


‘Electrical Characterization of GaN Vertical Schottky Diodes on Sapphire’,
oral presentation at the 20th European Workshop on Heterostructure Techno-
logy (HETECH), Lille, France, 2011.

28. H. Hahn, G. Lükens, N. Ketteniss, H. Kalisch, A. Vescan, ‘Effects of gate-


recessing onto DC and RF performance of AlGaN/GaN HFETs’, oral presenta-
tion at the 20th European Workshop on Heterostructure Technology (HETECH),
Lille, France, 2011.

29. H. Hahn, J. Achenbach, N. Ketteniss, A. Noculak, H. Kalisch and A. Vescan,


‘Influence of oxygen addition in SiN dry etch process on device characteristics
of passivated AlGaN/GaN HFETs’, oral presentation at the 35th Workshop
on Compound Semiconductor Devices and Integrated Circuits held in Europe
(WOCSDICE), Catania, Italy, 2011.

176
Acknowledgments
Die Arbeit entstand an der RWTH Aachen innerhalb des Lehr- und For-
schungsgebietes GaN-Bauelementtechnologie, an welchem ich als wissen-
schaftlicher Mitarbeiter seit Oktober 2010 tätig bin. Die Finanzierung der
Arbeit erfolgte zu einem Großteil aus Geldern des Bundesministeriums für
Bildung Forschung (BMBF).
Mein besonderer Dank gilt Prof.Dr.-Ing. Andrei Vescan, der mir frühzeitig
die Sicherheit gab in seiner Arbeitsgruppe einen festen Platz einnehmen zu
können. Vor allem das entgegengebrachte Vertrauen in Form von Freiheit
im Bereich der Umsetzung eigener Ideen liegt mir besonders am Herzen,
aber auch die Menschlichkeit, die er stets hat walten lassen.
My sincere appreciation is to Prof. Michael J. Uren, PhD. for having been
the co-supervisor. I will always see it as a privilege to have received remarks
and hints from him.

Großer Dank gebührt aber auch folgenden Leuten

• Herrn Dr. rer. nat. Holger Kalisch für die lange Zeit, die er verbracht
hat um jegliche Veröffentlichungen zu korrigieren.

• Herrn Dipl.-Phys. Ben Reuters für die beste Zusammenarbeit, die man
sich wünschen kann, das Teilen verrückter Ideen und seine Künste
an der MOCVD.

• Herrn Dr.-Ing. Nico Ketteniss für das Heranziehen während der An-
fangsphase und die gute spätere Zusammenarbeit.

• Herrn Dipl.-Phys. Frank Otto Jessen für seine Geduld mein Treiben
zu ertragen und die nach Möglichkeit rasch erfolgte Reparatur di-
verser Anlagen.

• Frau Dipl.-Phys. Wiebke Witte für die Zusammenarbeit und ihr Vor-
ranschreiten zur Aufrechterhaltung des guten Institutsklimas.

177
Acknowledgments

• Herr M. Sc. Jan Gruis für seine gute Stimmung und die Hilfsbereit-
schaft die er allzeit an den Tag legt.

• Herr M. Sc. Hady Yacoub für den Austausch in Bauelementfragen und


das Ertragen der Tour de France Liveübertragungen während jeden
Julis.

• Allen weiteren wiss. Mitarbeiten des GaN-BETs, welche die Zeit zu


einer besonderen werden ließen.

• Herrn Gerrit Kuivenhoven für seine allzeit genialen mechanischen Kon-


struktionen.

• Frau Gabriele Nogueira-Glenski und Frau Sonja Buchholz-Trappe für


ihre stete Unterstützung und ihren Einsatz in der Lithographie.

• Meinen Studenten, welche hervorragende Arbeit leisteten, mir das


Leben leichter machten, durch die viele Ergebnisse erst möglich ge-
macht wurden und die jetzt zum Teil meine Kollegen geworden sind.

178