ADVANCED ANALOG IC DESIGN

15 EC 5232
M. Tech VLSI
I – Year Semester – II AY 2017 – 18
LAB MANUAL

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
KLEF
(Deemed to be University)
NAAC ‘A’ Grade, Approved by UGC, ISO 9001:2008 Certified.
Green Fields, Vaddeswaram-522 502
List of Experiments:

1. I-V characteristics of nMOS and pMOS and the effect of substrate potential on the
threshold voltage and I-V characteristics.
2. Design & analysis of different current mirrors (Simple & Cascode) under active loads
and passive loads.
3. Design & analysis of common source amplifier with resistive load, diode connected
load, constant current source load and triode load.
4. Design & frequency analysis of common drain and cascode amplifiers (CS-CG) with
resistive load and active load.
5. Design & analysis of two stage differential amplifier (Two stage op-amp).
6. Design & analysis of folded Cascode operational amplifier.
7. Design & high frequency analysis of voltage feedback amplifiers.
8. Design & high frequency analysis of current feedback amplifiers.
Lab objective:

The objective of the lab is to apply and experience the practicality of concepts learned in various

courses related to analog integrated circuits and design. This lab imparts the skill set to enhance the

analytical and critical thinking to understand, apply, analyze and conclude various analog circuits

that are been used commercially. The study of various analog circuits are carried out using MENTOR

GRAPHICS tool, specifically using Pyxis Layout Editor.

Initial lab sessions are dedicated to the understanding and application of basic concepts and practical

limitations followed by the analysis of frequently employed circuits like single stage amplifiers,

differential amplifiers and cascode amplifiers. Further, students will design and analyze high level

circuits like operational amplifiers and feedback amplifiers.

Students are encourage in due course to take up a case study or develop a project based on the lab

course to show case their skill set achieved in the process.

Outcome of the lab:

At the end of the lab course, students learn the Pyxis Layout Editor by concentrating on the design

and analysis of analog circuits and practical pit falls. Students will achieve strong foundation of basics

that has be understood by hands on experience through MENTOR GRAPHICS, able to analyze analog

circuits and confident enough to attended interviews for core jobs, will be enthusiastic to pursue PhD

on future analog circuits using nano-technologies.

Introduction to MENTOR GRAPHICS:

Overview of MOS analog circuit design using MENTOR GRAPHICS tool.

The basic steps are:

1. Design of schematic in Pyxis Layout Editor.
2. Simulate the schematic using ELDO.
3. Parametric analysis and visualization of characteristics.

Invoking MENTOR tools:

 Right click on desktop and choose option open terminal.
 Type csh and press enter.
 Type source /home/software/cshrc/hep.cshrc which will invoke the mentor tools
environment.
 Type dmgr_ic & and press enter then pyxis project manager window will be invoked.

Creating Project:
 In project navigator, to create new project click on File new project, that invokes the new
project window.
 Browse on the folder and specify the project path.
 After creating a folder or choosing a specific location of project click ok.
 Next technology libraries have to be added to the project. In order to add the technology
files browse on the folder as Navigate to /home/software/FOUNDRY/GDK/Pyxis_SPT_HEP
/ic_reflibs/tech_libs and select the generic13 file and click on OK.
 Again click on OK then manage external/logic libraries window will pop up.
 Click on the Add Standard Libraries.
 Then the standard libraries will be added up.
 Then the pyxis project manager window will be shown where the technology libraries are added to
the project and are placed below the project name.

Creating new cell:

 To create a library right click on the project name and select new library or click on the icon

on the icon bar.

 Then a new library window will pop up asking for the library name.
 Next name the library and click OK.
Creating schematic in cell:
 To create a schematic cell view, a new cell has to be created in which new schematic has to
be defined. In order to create new cell right click on the manual library below the project

name and select new cell or select the library and click on the icon in the icon bar.
 Then a new cell window will pop up asking for the cell name in which give the cell name and
click OK.
 To create a schematic in the cell, right click on the cell name and select new schematic or

click on the new cell and select the icon in the icon bar.
 A window will pop up asking for the schematic name.
 Now name the schematic and click on OK which in turn leads to the pyxis schematic editor
window.

Creating a Schematic:
In this section you will become familiar with placing primitive analog devices for a inverter.
You’ll learn how to:
 place primitives on the schematic
 select and manipulate devices
 customizing hotkeys for placing devices
 route devices
 edit device parameter values
 name instances
 check and save the schematic
 create upper hierarchical symbols
 create test bench
 simulate using Eldo
 view results

Creating an Inverter:
 From the left icon bar press on add instance icon or will be found in the ADD option on the
top toolbar.
 Then a file browser which contains entire libraries will pop up.
 Next click on the double click on generic13 in the library list.
 And then follow the path to select pmos from $generic13/symbols/pmos
  Select the pmos and click on OK to place the pmos on the workspace.

Changing device properties:

 In order to change the properties of the devices on the workspace click on the then the
corresponding device properties will be shown in the object editor.
 Now enter the prescribed value in the field provided and press enter .Then the value will be
changed .Here the width has been set to 0.15u and length to 0.13u.
 Similarly select the nmos and change the W=0.13u,L=0.15u and the schematic would look as
follows.

Adding the ports and connecting the devices:

 In the similar way select the VDD and ground from the generic lib or click on the library in
the layer palatte window then layer palatte will be shown as ic library window. Then select
generic library and place VDD and ground.
 Place in IN and OUT ports in a similar way as above from the generic library or click on the
add ports icon in the left icon bar and connect the circuit.
 Then the schematic would look as follows

For changing the port names click on the port and change the net name in the object editor to the
required name which is shown below.
 Next click on check/save icon in the icon bar.
 This will result to a window which shows the error report where the errors and warnings in
the schematic.
 Add the IN and OUT net as before by selecting the hot key i. Name the nets with hot key “q”.
 • Add VDD and Ground ports in a similar fashion.
 Add a DC voltage source dc_v_source, from the MGC_IC_SOURCES_LIB. Change the value of
the DC property to be 3.3 V. Add PULSE voltage source pulse_v_source and change the value
of the pulse_value property to be 3.3 V

 Next click on check/save icon in the icon bar

 This will result to an window which shows the error report where the errors and warnings
in the schematic can be seen.
 If no errors, click on simulation option in the palette area which the schematic enters in to
simulation mode.
 When you have no errors select the Simulation icon from the left icon palette to go into
design context and simulate our design or select context in the menu bar and select run
simulation.
 In the design context from menu bar select Simulation-> setup simulation or click on setup
simulation icon in the left icon palatte.
 A set up simulation window will pop up.
 To set up analysis select analysis in the simulation panel and in the analysis setup select the
required analysis and set the values of the analysis in the beside window. After specifying the
values click on apply
 To probe the waveforms, click on the outputs in the selection panel, then select the input port
of the schematic in the pyxis schematic window as shown.
 To probe the waveforms, click on the outputs in the selection panel ,then select the input port
of the schematic in the pyxis schematic.
 In the setup simulation window, click Add button then the port will be added to the
waveform. Similarly add all the waveforms required to see in the ezwave.
 After adding the analysis, eldo models and probing waveforms minimize the setup simulation
window and run the simulator. To run the simulation select from the left icon palette or select
simulate-> run simulation.
 View the simulation results by selecting the plot results from latest run icon from the left icon
palatte. This will open EZWave for you with the output waveforms.
 Click on Measurement tool in the icon bar which opens up the measurement tool window
where we can measure the different properties of your waveforms.
 Lab Experiment: 1

Objective: a. To study the I-V characteristics of nMOSFET and pMOSFET.

b. To analyze the effect of back gate on the transfer characteristics of an inverter, drain to
source voltage of nMOSFET and threshold voltage of nMOSFET.
Tools required: Mentor Graphics – Pyxis layout editor.
Theory:
The top view of MOSFET is shown below

Where the gate length, L, and gate width, W, are identified. Note that the gate length does not equal
the physical dimension of the gate, but rather the distance between the source and drain regions
underneath the gate. The overlap between the gate and the source/drain region is required to ensure
that the inversion layer forms a continuous conducting path between the source and drain region.
Typically this overlap is made as small as possible in order to minimize its parasitic capacitance.
The voltage applied to the gate controls the flow of electrons from the source to the drain. A positive
voltage applied to the gate attracts electrons to the interface between the gate dielectric and the
semiconductor. These electrons form a conducting channel called the inversion layer. No gate current
is required to maintain the inversion layer at the interface since the gate oxide blocks any carrier
flow. The net result is that the applied gate voltage controls the current between drain and source.
We will primarily consider the n-type or n-channel MOSFET in this chapter. This type of MOSFET is
fabricated on a p-type semiconductor substrate. The complementary MOSFET is the p-type or p-
channel MOSFET. The p-type MOSFET contains p-type source and drain regions in an n-type
substrate. The inversion layer is formed when holes are attracted to the interface by a negative gate
voltage. While the holes still flow from source to drain, they result in a negative drain current. CMOS
circuits require both n-type and p-type MOSFETs.
The typical I-V characteristics of MOSFET are shown below

MOSFET Large signal model

Cutoff: (VGS ≤VTh) ----> ID= 0

Triode: (VGS ≥VTh and VDS≤VGS – VTh)

ID= µn Cox (W/2L) (VGS – VTh – VDS/2) VDS (1 + λVDS)

Saturation: (VGS ≥ VTh and VDS ≥ VGS – VTh)

ID= µn Cox (W/2L) (VGS – VTh )2 (1 + λVDS)

The same circuit without small signal Vgs is used

to obtained I-V characteristics of nMOSFET.
Procedure: Open Pyxis layout editor and create a new schematic with proper connection as shown
below. The input can be a DC source or a pulse or pattern.
Calculation of threshold voltage of nMOS:

An inverter circuit is simulated with varying VGS and output of the inverter is measure at drain
terminal of nMOS. VGS and VDS are plotted with one over another to find the threshold voltage of
MOSFET.
MOSFETs are included in the schematic window by clicking instance “i” and choose either nMOS or
pMOS from the symbols in generic 13.
Interconnections are carried out using wire by pressing hot key ‘w’, and DC sources and Ground are
available in Generic sources and source libraries in the palette area.
Study of effect of substrate potential on threshold voltage:
In the above circuit, the bulk terminal is connected to source to avoid the effects of bulk terminal. To
study the effect of substrate potential on the threshold voltage nMOSFET, a voltage source is
connected between the source and substrate terminal.
DC analysis is performed for inverter circuit by varying VBS from a finite +ve voltage to –ve voltage
and the transfer characteristics are plotted for various values of VBS.
Simulation and setting parameters:
The simulation setup are explained vividly in the introduction to MENTOR GRAPHICS.

Result:
1. Attach the I–V characteristics of nMOS and pMOS along with the schematic.
2. Transfer characteristics of inverter with substrate potential applied to substrate terminal of
nMOS.
Lab Experiment: 2

Objective: a. Design and analysis of simple current mirror

b. Design and analysis of cascode current mirror.
Tools required: Mentor Graphics – Pyxis layout editor.
Theory:
A current mirror consists of a current-to-voltage converter consecutively connected to a voltage-to-
current converter.

The simple current mirror circuit is shown below. We know that transistor M1 is operating in the
saturation region because VDS is greater than or equal to VGS. Transistor M2 will also be in saturation
so long as the output voltage is larger than its saturation voltage. In this simple configuration, the
output current IOUT is directly related to IIN.
Using VDG=0 for transistor M1, the drain current in M1 is ID = f (VGS,VDG=0), so we find: f (VGS, 0) = IIN,
implicitly determining the value of VGS. Thus IIN sets the value of VGS. The circuit in the diagram forces
the same VGS to apply to transistor M2. If M2 also is biased with zero VDG
and provided transistors M1 and M2 have good matching of their
properties, such as channel length, width, threshold voltage etc., the
relationship IOUT = f (VGS,VDG=0 ) applies, thus setting IOUT = IIN; that is,
the output current is the same as the input current when VDG=0 for the
output transistor, and both transistors are matched.

However, the channel length modulation results in significant error in coping currents, for a simple
current mirror circuit, the drain currents of M1 and M2 are given as
While VDS1=VGS1=VGS2, VDS2 may not be equal to VGS2 because of
the circuitry fed to the M2. In order to suppress the effect of channel
length modulation, a cascode current source can be used.
Modified cascode current mirror: Instead of using an external voltage
supply for Vb, it can achieved by ensuring the node potentials of X and
Y are equal, to ensure that we must guarantee Vb-VGS3=Vx or Vb =
VGS3+Vx. This result suggests that if a gate-source voltage is added to
Vx results in required Vb. Hence, M0 another transistor diode connected
transistor is connected in series to M1, there by generating the required voltage at VN = VGS0+Vx.
Proper choice of dimensions of M0 with respect of M3 yields VGS0=VGS3.
The major drawback of the cascode mirror is it consumes substantial the voltage headroom. For
simplicity we neglect channel length modulation to calculate the minimum allowable voltage at
node P,
VN-VTh=VGS0+VGS1-VTh = (VGS0-VTh) + (VGS1-VTh) + VTh
which is two overdrive voltages plus on threshold voltage.

Procedure: Open Pyxis layout editor and create a new schematic with proper connections and check
for errors and simulate using DC analysis of basic circuit as shown below
From the basic simulation, we obtain drain current and VGS by doing DC analysis. Using the obtained
parameters k’ of transistors are calculated. Using the obtained data for a given input drain current a
current mirror is designed.

Result:
Attach the input and output currents with respect to W/L ratio of a simple current mirror.
Calculation:
Sr. No. Input reference current Output current

Attach the input and output currents with respect to W/L ratio of a cascode current mirror.
Calculation:
Sr. No. Input reference current Output current
Lab Experiment: 3

Objective: a. Design and analysis of common source amplifier with resistive load.
b. Design and analysis of common source amplifier with active loads.
Tools required: Mentor Graphics – Pyxis layout editor.
Theory:
CS stage with resistive load and various active loads are shown below

By the virtue of transconductance of a MOSFET, it converts the variations in gate-source voltage to a

small signal drain current that can pass through a resistor to generate output voltage. The basic
common source stage and its transfer characteristics are shown below
CS stage with diode connected load:
In CMOS technologies, it is difficult to fabricated resistors with tightly controlled values and
reasonable sizes, hence it is desirable to replace resistors with transistors. A MOSFET can be operated
a resistor it is gate and drain are shorted, which is called as diode-connected transistor. The diode
connected transistor is always be in saturation because the gate and drain are connected together.
Using small signal equivalent the resistance looking in to the source is calculated using a test source,
as shown below.
CS stage with current source load:
In applications required large voltage gain in a single stage, the relationship Av = –gmRD suggest that
we increase the load resistance, with a load resistance or diode connected transistor, however it
limits the output voltage swing. The more practical approach is to replace the load with a current
source.
Av = –gm1 (ro1||ro2)
The key point is that the output impedance and the minmum required |V DS| of M2 are less strongly
coupled than the value and voltage drop of a resistor.
|VDS2, min| = |VGS2–VTh| can be reduced by a few mill volts by simply increasing the width of M2.
CS stage with triode source load:
A MOS transistor operating in deep triode region behaves as a resistor and can sever as the load in a
CS stage, as shown in the following figure. The circuit biases the gate of M2 at a sufficiently low level,
ensuring the load in deep triode region for all output voltage swings.

The major drawback of this circuit stems from the dependence of Ron2 upon the fabrication process
parameters and threshold voltage of M2. The triode load however consumes very less headroom
voltage then the diode connected transistor, Vout,max=VDD.
Procedure:
Design the amplifier stage with given parameters and specifications.
Launch Pyxis layout editor and follow the steps as explained in the initial experiments.
Implement the circuits discussed above in accordance with the given specifications.
Setup simulation parameters:
DC analysis with varying inout source and W/L ratio of MOSFET are to be carried out.
Transient response are carried out to obtain the small signal gain.
Frequency analysis are carried out to obtain small signal gain with respect to frequency.

Result:
DC analysis:
Vout and Id

Sr. No Simulated Calculated Error %

Small signal Gain

Sr. No Simulated Calculated Error %

Frequency response

Sr. No Frequency Gain

Lab Experiment: 4

Objective: a. Design and frequency response of common drain amplifier.

b. Design and frequency response of cascode amplifier stage.
Tools required: Mentor Graphics – Pyxis layout editor.
Theory:
In general, common source is widely used for high gain applications with limited voltage supply.
If such a stage is to drive a low impedance load then a buffer must be placed after the amplifier so
as to drive the low impedance load with negligible loss of signal, the source follower is also known
as common drain and can operate as voltage buffer. The source follower senses the signal at the
gate and drives the load at the source, allowing the source potential to follow the gate voltage.

Large signal analysis:

Vin<VTh M1 is off and Vout = 0,
Vin>VTh M1 is on and ID1 flows through RS and Vout gradually increases with respect to input. As
input voltage increases further the Vout follows the input with a difference equal to VGS. We can
express the input-output characteristics as

Small signal gain can be calculated by differentiating the above equation with respect to Vin or the
gain can be calculated with small signal equivalent of MOSFET.
Source follower with current source load
The basic cascode configuration is a combination of common source stage and common gate
configuration, where the CG stage is cascaded to the CS stage.

Large signal analysis:

For M1 to be operating in saturation, VX ≥ Vin – VTh, if M1 and M2 both are in saturation, then VX
is determined primarily by VTh2 if Vb is chosen to place M1 at the edge of saturation. Hence, the
minimum output voltage level for which both transistors operate in saturation is equal to the
overdrive voltage of M1 plus that of M2. Therefore the addition of cascode stage reduces the output
swing by at least the overdrive voltage of M2.

For Vin varies from 0 to VDD, for Vin ≤ VTh1, M1 and M2 are off and Vout = VDD, and VX ≈ Vb–VTh2.
As Vin exceeds the threshold voltage, M1 begins to draw current, and Vout drops. Since ID2 increases
the VGS2 must increase as well, causing VX to fall.
Vin is sufficiently large, two effects will occur
1. VX drops below Vin by VTh1 forcing M1 in to triode region.
2. Vout drops below Vb by VTh2 driving M2 in to triode region.
Depending on the device dimensions and the values of RD and Vb, one effect may occur before the
other.
Ex: If Vb is relatively low, M1 may enter triode region first, note that if M2 goes into deep triode
region, VX and Vout become nearly equals.
Procedure:
Design the amplifier stage with given parameters and specifications.
Launch Pyxis layout editor and follow the steps as explained in the initial experiments.
Implement the circuits discussed above in accordance with the given specifications.
Setup simulation parameters:
DC analysis with varying input source and W/L ratio of MOSFET are to be carried out.
Transient response are carried out to obtain the small signal gain.
Frequency analysis are carried out to obtain small signal gain with respect to frequency.

Result:
DC analysis:
Vout and Id

Sr. No Simulated Calculated Error %

Small signal Gain

Sr. No Simulated Calculated Error %

Frequency response

Sr. No Frequency Gain

Lab Experiment: 5

Objective: Design and analysis of two stage differential amplifier.

Tools required: Mentor Graphics – Pyxis layout editor.
Theory:
In general, two stage op-amps the first stage provides the gain and the second stage provides the
necessary output swings

The simple implementation of two stage op amp is shown below

The figure show that the first stage is cascode stage that provides high gain and the output stage
provides the high output swing. Similarly the two stage op amp can be realized by employing
cascode differential amplifier as the first stage is shown below

Procedure:
Design the amplifier stage with given parameters and specifications.
Launch Pyxis layout editor and follow the steps as explained in the initial experiments.
Implement the circuits discussed above in accordance with the given specifications.
Setup simulation parameters:
DC analysis with varying input source and W/L ratio of MOSFET are to be carried out.
Transient response are carried out to obtain the small signal gain.
Frequency analysis are carried out to obtain small signal gain with respect to frequency.

Result:
DC analysis: To find range of input operating voltage and output swing.
AC analysis to obtain the small signal gain.
Small signal Gain

Sr. No Simulated Calculated Error %

Frequency response

Sr. No Frequency Gain

Lab Experiment: 6

Objective: Design and analysis of folded cascode operational amplifier

Tools required: Mentor Graphics – Pyxis layout editor.
Theory:
The following figure show basic NMOS cascode stage and respective NMOS output folded cascode
stage and Figure (b) show the cascode configuration with PMOS transistors and respective PMOS
output cascode stage. Similarly, the basic cascode op amp and respective folded op amp stage is
shown below

In order to obtain high gain the same folded cascode can be implemented with cascode op amps
stages as shown below
Procedure:
Launch Pyxis layout editor and follow the steps as explained in the initial experiments.
Implement the circuits discussed above in accordance with the given specifications.
Setup simulation parameters:
DC analysis with varying input source and W/L ratio of MOSFET are to be carried out.
Transient response are carried out to obtain the small signal gain.
Frequency analysis are carried out to obtain small signal gain with respect to frequency.

Result:
DC analysis: To obtained transfer characteristics.
From DC analysis find the minimum and maximum values of input DC voltage and also find the
output swing.
Transient analysis is carried out to find the speed of operation of folded cascode circuit.
Frequency response is performed to obtained gain characteristics with respect to frequency.
Small signal Gain

Sr. No Simulated Calculated Error %

Frequency response

Sr. No Frequency Gain

Lab Experiment: 7

Objective: Design and analysis of voltage feedback amplifier.

Tools required: Mentor Graphics – Pyxis layout editor.
Theory:
Most of the circuits studied thus far can be considered “voltage amplifiers” because they sense a
voltage at the input and produce a voltage at the output. However, three other types of amplifiers can
also be constructed such that they sense or produce currents. Shown in Figure below, the four
configurations have quite different properties: (1) circuits sensing a voltage must exhibit a high input
impedance (a voltmeter measures a voltage with minimal loading) whereas those sensing a current
must provide a low input impedance (a current meter inserted in a wire must negligibly disturb the
current); (2) circuits generating a voltage must exhibit a low output impedance (as a voltage source)
while those generating a current must provide a high output impedance (as a current source).

Voltage-Voltage Feedback
This topology senses the output voltage and returns the feedback signal as a voltage.1 Following the
conceptual illustrations of Figs. 1.17 and 1.18, we note that the feedback network is connected in
parallel with the output and in series with the input port (Fig. 1.21). An ideal feedback network in
this case exhibits infinite input impedance and zero output impedance because it senses a voltage
and generates a voltage. We can therefore write VF = βVout, Ve = Vin − VF, Vout = A0(Vin − βVout), and
hence
Vout/ Vin = A0/1 + βA0
We recognize that βA0 is the loop gain and that the overall gain has dropped by 1 + βA0. Note that
here both A0 and β are dimensionless quantities.
As a simple example of voltage-voltage feedback, suppose
we employ a differential voltage amplifier with single
ended output as the feedforward amplifier and a resistive
divider as the feedback network.

1 This configuration is also called “series-shunt” feedback, where the first term refers to the input connection and the second to the output connection.
Voltage-Current Feedback
In this type of feedback, the output voltage is sensed and a proportional current is returned to the
summing point at the input.2 Note that the feedforward path incorporates a transimpedance amplifier
with gain R0 and the feedback factor has a dimension of conductance.
A voltage-current feedback topology is shown in Figure. Sensing a voltage and producing a current,
the feedback network is characterized by a transconductance gmF, ideally exhibiting infinite input and
output impedances. Since IF = gmf Vout and Ie = Iin − IF,
we have Vout = R0, Ie = R0(Iin − gmf Vout). Following our
reasoning for the other two types of feedback studied
above, we surmise that voltagecurrent feedback
decreases both the input and the output impedances. As
shown in Fig. 1.38(a) and noted
inExample8.3,theinputresistanceof R0
appearsinserieswithitsinputport.Wewrite IF = IX −VX/Rin
and (VX/Rin)R0gmF = IF.
Reference: DOI: 10.1109/ISCAS.2000.857400

Procedure:
Launch Pyxis layout editor and follow the steps as explained in the initial experiments.
Implement the circuits discussed above in accordance with the given specifications.
Setup simulation parameters:
DC analysis with varying input source and W/L ratio of MOSFET are to be carried out.
Transient response are carried out to obtain the small signal gain.
Frequency analysis are carried out to obtain small signal gain with respect to frequency.

Result:
DC analysis: To obtained transfer characteristics.
From DC analysis find the minimum and maximum values of input DC voltage and also find the
output swing.
Transient analysis is carried out to find the speed of operation of voltage feedback amplifier.
Frequency response is performed to obtained gain characteristics with respect to frequency.
Small signal Gain

Sr. No Simulated Calculated Error %

2 This topology is also called “shunt-shunt” feedback.

Frequency response

Sr. No Frequency Gain

Lab Experiment: 8

Objective: Design and analysis of current feedback amplifier.

Tools required: Mentor Graphics – Pyxis layout editor.
Theory:
Current-Voltage Feedback
In some circuits, it is desirable or simpler to sense the output current to perform feedback. The
current is actually sensed by placing a (preferably small) resistor in series with the output and using
the voltage drop across the resistor as the feedback information. This voltage may even serve as the
return signal that is directly subtracted from the input.

An ideal feedback network in this case exhibits zero input and output impedances.
It is instructive to confirm that Gm RF is indeed the loop gain. We set the input voltage to zero and
break the loop by disconnecting the feedback network from the output and replacing it with a short
at the output (if the feedback network is ideal). We then inject the test signal It, producing VF = RF It,
and hence Iout = −Gm RF It. Thus, the loop gain is equal to Gm RF and the transconductance of the amplifier
is reduced by 1 + Gm RF when feedback is applied.
Is it realistic to assume that the input impedance of the feedback network is zero? Why do we use a
test current rather than a test voltage? Does the type of test source affect the loop gain calculations?
These questions are addressed later in this chapter.
Sensing the current at the output of a feedback system increases the output impedance. This is
because the system attempts to make the output current a faithful replica of the input signal (with a
proportionality factor if the input is a voltage quantity). Consequently, the system delivers the same
current waveform as the load varies, in essence approaching an ideal current source and hence
exhibiting a high output impedance.
Current-Current Feedback
Figure 1.41 illustrates this type of feedback. Here, the feed
forward amplifier is characterized by a current gain, AI ,
and the feedback network by a current ratio, β. In a fashion
similar to the previous derivations, the reader can easily
prove that the closed-loop current gain is equal to AI /(1 +
βAI ), the input impedance is divided by 1 + βAI and the output impedance is multiplied by 1 + βAI .

Procedure:
Launch Pyxis layout editor and follow the steps as explained in the initial experiments.
Implement the circuits discussed above in accordance with the given specifications.
Setup simulation parameters:
DC analysis with varying input source and W/L ratio of MOSFET are to be carried out.
Transient response are carried out to obtain the small signal gain.
Frequency analysis are carried out to obtain small signal gain with respect to frequency.

Result:
DC analysis: To obtained transfer characteristics.
From DC analysis find the minimum and maximum values of input DC voltage and also find the
output swing.
Transient analysis is carried out to find the speed of operation of voltage feedback amplifier.
Frequency response is performed to obtained gain characteristics with respect to frequency.
Small signal Gain

Sr. No Simulated Calculated Error %

Frequency response

Sr. No Frequency Gain