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1 1

Compal Confidential
2 2

QCL70 MB Schematic Document


LA-8222P
3 3

Rev: 1.0
2012.01.09

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 1 of 61
A B C D E
1 2 3 4 5

Compal Confidential
ZZZ1
QCL70
PCB-MB
PCB P/N for Load BOM DDR3 1333/1600MHz 1.5V DDR3-SO-DIMM X 2
BANK 0, 1, 2, 3
A DAZ0NE00100 Mobile +1.5V, +0.75VS A

Dual Channel Page 10, 11

NV N13P-GL / GS PEG 16X Ivy Bridge


(N13M-GE1) Processor
rPGA 988B Socket
Page 4 ~ 9
Page 20 ~ 29 +VCC_CORE, +VCCP,
+VCC_GFXCORE_AVG, +1.5V_CPU_VDDQ, port 5,1
+1.8VS, _VCCSA
USB conn x2
USB Board Page 33
FDI x8
DMI x4
(UMA) 100MHz port 3
100MHz Camera
5GB/s
2.7GT/s Page 30

LCD conn LVDS, EDID, DISPOFF#, PWM USB2.0


Page 30
port 4 Card Reader Memory Card Slot
SD/MMC
RTS5137 Page 34
RGB, HV Sync, DDC Page 34
CRT Conn
B
Page 30 Intel port 10
B

MiniCard-2
HDMI, DDC
PANTHER-POINT Page 41

HDMI PCH
Page 35
port 0,2
USB3.0 conn x2
USB3.0 port 1,3
Page 37
HM76/HM75
Audio Jack (HP)
Page 33

Azalia Realtek
FCBGA 989 Balls ALC269 Page 33 Audio Jack (MIC)
Page 33

Page 12 ~ 19 SATA
2.5" SATA HDD Connector Speaker Connector
port 0 Page 33
C Page 31 C

PCI-e
port 1
+1.05VS, +1.8VS, +3VS, 2.5" SATA HDD Connector
port 1 port 2 +3V_PCH, +5V_PCH, +RTCVCC,
+VCCAFDI_VRM Page 31
LAN/CRT Board Mini Card-1
10/100/1000 LAN WLAN port 2
Realtek GbE Bluetooth SATA ODD Connector
RTL8111F Page 32 Page 41 Page 31

SPI SPI ROM


4MB For win7
8MB For win8
Page 12
LPC BUS

Touch Pad CONN. ENE KB9012QF


D
Page 39 Reserve KB930QF
+3VLP/+3VALW Int. KBD
D

page 40
Page 39
DC/DC Interface CKT.
Page 29,42

SPI ROM
Security Classification Compal Secret Data Compal Electronics, Inc.
Fan Control Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

Page 38 Page 40 SCHEMATIC A8222


128KB THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom
Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019G8
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 2 of 61
1 2 3 4 5
A

X76@:

VRAMX16X8 HYN 128*16*8 CLKOUT DESTINATION USB3 PORT DESTINATION USB2 PORT DESTINATION
ZZZ X76L01@ ZZZ2 X76L02@ ZZZ3 X76L15@

PCI0 PCH_LOOPBACK 1 USB2.0+3.0 0 USB2.0+3.0

2G SAM 2G B HYN 2G D HYN PCI1 EC PCH 2 USB2.0+3.0 1 USB2.0+3.0


ZZZ5 X76L05@ ZZZ6 X76L06@
PCI2 None 3 None 2 USB2

PCI3 LPC Debug Port 4 None 3 CAMERA


1G SAM 1G HYN

PCI4 None 4 Card Reader


VRAMX16X8-GS N13P-GS N13P-GL
ZZZ11 X76L12@ ZZZ12 X76L11@ 5 USB2
GS@ GL@ Voltage Rails
U10 GS@ U10 GL@ 6 None
Power Plane Description S1 S3 Deep S5
GS 2G SAM GS 2G HYN S3
VIN Adapter power supply (19V) N/A N/A N/A N/A PCH 7 None
N13P-GS N13P-GL BATT+ Battery power supply (12.6V) N/A N/A N/A N/A
B+ AC or battery power rail for power circuit N/A N/A N/A N/A 8 None
+3VLP 3.3V power rail for 51ON power management ON ON ON ON
GEL@: N13M-GE1 or N13P-GL N13M-GE1 N13M-GE1 x8
GS@: N13P-GS +3VALW 3.3V always on power rail ON ON ON AC/ON; DC/OFF 9 None
GE@ GE8@
+LAN_IO 3.3V power rail for ethernet ON ON OFF OFF
DIS@: VGA componet U10 GE@ U10 GE8@
+3VS_WLAN 3.3V power rail for WLAN/BT Combo ON OFF OFF OFF 10 JMINI1 (WLAN) Bluetooth
9012@: EC(ENE 9012 chip)
+3V_PCH 3.3V power rail for PCH suspend well plane ON ON OFF OFF
XDP@: Intel debug port
+3VS 3.3V power rail for DDR SPI,PCH,HDD,Audio,Card Reader ON OFF OFF OFF 11 None
930@: EC(ENE 930 chip) N13M-GE1 N13M-GE1 x8
+3VSG 3.3V power rail for VGA ON OFF OFF OFF
IU3@: USB3.0 by PCH PS8520 ASM1466 +LCDVDD 3.3V power rail for LCD ON OFF OFF OFF 12 None
USB30@: USB3.0 controller IC ZZZ9 PAR8520@ ZZZ10 ASM1466@
+5VALW 5V always on power rail ON ON ON AC/ON; DC/OFF
+5V_PCH 5V power rail for PCH suspend well plane ON ON OFF OFF 13 None
AI@: AI Charger
+5VS 5V power rail for HDD,AUDIO,FAN,Touch PAD ON OFF OFF OFF
NAI@: Non AI Charger
+5VS_ODD 5V power rail for SATA ODD ON OFF OFF OFF
PS8520 ASM1466
+1.8VS 1.8V power rail for CPU,PCH ON OFF OFF OFF
W7@: WIN7 PCI EXPRESS DESTINATION
+1.05VS 1.05V power rail for PCH ON OFF OFF OFF
W8@: WIN8
+VCCP 1.05V power rail for CPU VCCIO,PCH ON OFF OFF OFF
1 Lane 1 10/100/1G LAN 1

+1.05VSG 1.05V power rail for N13P ON OFF OFF OFF


+1.5V 1.5V power rail for DDR3 system memory ON ON ON OFF
Lane 2 MINI CARD WLAN
+1.5V_CPU_VDDQ 1.5V power rail CPU VDDQ ON OFF OFF OFF
SMBUS Control Table +1.5VSG 1.5V power rail for N13P,VRAM ON OFF OFF OFF
Lane 3 None
+1.5VS 1.5V power rail for PCH,WLAN/BT combo ON OFF OFF OFF
SOURCE MINI1 BATT PCH EC SODIMM DGPU +0.75VS 0.75V power rail for DDR VREF ON OFF OFF OFF
Lane 4 None
+VCCSA VCCSA for CPU system agent ON OFF OFF OFF
EC_SMB_CK1
EC_SMB_DA1
KB930 X V X X X X +VCC_CORE
+VCC_GFXCORE_AXG
CORE Voltage for CPU
1.5V power rail for N13P,VRAM
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
Lane 5 None
EC_SMB_CK2
EC_SMB_DA2
KB930 X X V X X V +VGA_CORE CORE Voltage for N13P Graphics ON OFF OFF ON OFF OFF OFF
Lane 6 None
PCH_SMBCLK
PCH_SMBDATA PCH V X X X V X Lane 7 None
SATA DESTINATION
PCH_SMLCLK
SATA0 HDD Lane 8 None
PCH_SMLDATA PCH
X X X V X V
SATA1 HDD
DIFFERENTIAL DESTINATION FLEX CLOCKS DESTINATION
SATA2 ODD
CLKOUT_PCIE0 10/100/1G LAN CLKOUTFLEX0 CLK_SD_48M
SATA3 None
CLKOUT_PCIE1 MINI CARD WLAN CLKOUTFLEX1 None
SATA4 None
CLKOUT_PCIE2 None CLKOUTFLEX2 None SATA5 None
CLK CLKOUT_PCIE3 None CLKOUTFLEX3 None QCL70 * 16 (LA8222P)
Board ID Table for AD channel
CLKOUT_PCIE4 None Vcc 3.3V +/- 5%
Ra / Rc 100K +/- 5%
CLKOUT_PCIE5 None Symbol Note : Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
33K +/- 5% 0.634 V 0.819V 0.945 V
CLKOUT_PCIE6 None : means Digital Ground

CLKOUT_PCIE7 None Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title
: means Analog Ground SCHEMATIC A8222
CLKOUT_PEG_B None THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom
Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 3 of 61
A
5 4 3 2 1

+VCCP

1
JCPU1I
R1 PEG_ICOMPI and RCOMPO signals should be shorted and routed
24.9_0402_1% with - max length = 500 mils - typical impedance = 43 mohms
PEG_ICOMPO signals should be routed with - max length = 500 mils
- typical impedance = 14.5 mohms T35 F22

2
JCPU1A VSS161 VSS234
T34 VSS162 VSS235 F19
D PEG_COMP D
PEG_ICOMPI J22 T33 VSS163 VSS236 E30
PEG_ICOMPO J21 T32 VSS164 VSS237 E27
14 DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22 T31 VSS165 VSS238 E24
14 DMI_CRX_PTX_N1 B25 DMI_RX#[1] T30 VSS166 VSS239 E21
14 DMI_CRX_PTX_N2 A25 DMI_RX#[2] PCIE_GTX_C_CRX_N[0..15] 20 T29 VSS167 VSS240 E18
14 DMI_CRX_PTX_N3 B24 K33 PCIE_GTX_CRX_N15 DIS@ C1 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N15 T28 E15
DMI_RX#[3] PEG_RX#[0] PCIE_GTX_CRX_N14 DIS@ C2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N14 VSS168 VSS241
PEG_RX#[1] M35 1 2 T27 VSS169 VSS242 E13
14 DMI_CRX_PTX_P0 B28 L34 PCIE_GTX_CRX_N13 DIS@ C3 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N13 T26 E10
DMI_RX[0] PEG_RX#[2] PCIE_GTX_CRX_N12 DIS@ C4 0.22U_0402_10V6K PCIE_GTX_C_CRX_N12 VSS170 VSS243
14 DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35 1 2 P9 VSS171 VSS244 E9
14 DMI_CRX_PTX_P2 A24 J32 PCIE_GTX_CRX_N11 DIS@ C5 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N11 P8 E8

DMI
DMI_RX[2] PEG_RX#[4] PCIE_GTX_CRX_N10 DIS@ C6 0.22U_0402_10V6K PCIE_GTX_C_CRX_N10 VSS172 VSS245
14 DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34 1 2 P6 VSS173 VSS246 E7
H31 PCIE_GTX_CRX_N9 DIS@ C7 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N9 P5 E6
PEG_RX#[6] PCIE_GTX_CRX_N8 DIS@ C8 0.22U_0402_10V6K PCIE_GTX_C_CRX_N8 VSS174 VSS247
14 DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 1 2 P3 VSS175 VSS248 E5
E22 G30 PCIE_GTX_CRX_N7 DIS@ C9 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N7 P2 E4
14 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] VSS176 VSS249
F21 F35 PCIE_GTX_CRX_N6 DIS@ C10 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N6 N35 E3
14 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9] VSS177 VSS250
D21 E34 PCIE_GTX_CRX_N5 DIS@ C11 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N5 N34 E2
14 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] VSS178 VSS251
E32 PCIE_GTX_CRX_N4 DIS@ C12 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N4 N33 E1
PEG_RX#[11] PCIE_GTX_CRX_N3 DIS@ C13 0.22U_0402_10V6K PCIE_GTX_C_CRX_N3 VSS179 VSS252
14 DMI_CTX_PRX_P0 G22 DMI_TX[0] PEG_RX#[12] D33 1 2 N32 VSS180 VSS253 D35
D22 D31 PCIE_GTX_CRX_N2 DIS@ C14 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N2 N31 D32
14 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] VSS181 VSS254
F20 B33 PCIE_GTX_CRX_N1 DIS@ C15 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N1 N30 D29

PCI EXPRESS* - GRAPHICS


14 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] VSS182 VSS255
C21 C32 PCIE_GTX_CRX_N0 DIS@ C16 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_N0 N29 D26
14 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15] VSS183 VSS256
PCIE_GTX_C_CRX_P[0..15] 20 N28 VSS184 VSS257 D20
J33 PCIE_GTX_CRX_P15 DIS@ C17 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P15 N27 D17
PEG_RX[0] PCIE_GTX_CRX_P14 DIS@ C18 0.22U_0402_10V6K PCIE_GTX_C_CRX_P14 VSS185 VSS258
PEG_RX[1] L35 1 2 N26 VSS186 VSS259 C34
K34 PCIE_GTX_CRX_P13 DIS@ C19 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P13 M34 C31
FDI_CTX_PRX_N0 PEG_RX[2] PCIE_GTX_CRX_P12 DIS@ C20 0.22U_0402_10V6K PCIE_GTX_C_CRX_P12 VSS187 VSS260
14 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35 1 2 L33 VSS188 VSS261 C28
FDI_CTX_PRX_N1 H19 H32 PCIE_GTX_CRX_P11 DIS@ C21 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P11 L30 C27
14 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] VSS189 VSS262
FDI_CTX_PRX_N2 E19 G34 PCIE_GTX_CRX_P10 DIS@ C22 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P10 L27 C25
14 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5] VSS190 VSS263
FDI_CTX_PRX_N3 F18 G31 PCIE_GTX_CRX_P9 DIS@ C23 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P9 L9 C23
14 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] VSS191 VSS264
14 FDI_CTX_PRX_N4
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
B21
C20
FDI1_TX#[0] Intel(R) FDI PEG_RX[7] F33
F30
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_P7
DIS@
DIS@
C24
C25
1
1
2
2
0.22U_0402_10V6K
0.22U_0402_10V6K
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_P7
L8
L6
VSS192 VSS265 C10
C1
14 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8] VSS193 VSS266
FDI_CTX_PRX_N6 D18 E35 PCIE_GTX_CRX_P6 DIS@ C26 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P6 L5 B22
C 14 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] VSS194 VSS267 C
FDI_CTX_PRX_N7 E17 E33 PCIE_GTX_CRX_P5 DIS@ C27 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P5 L4 B19
14 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
F32
D34
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_P3
DIS@
DIS@
C28
C29
1
1
2
2
0.22U_0402_10V6K
0.22U_0402_10V6K
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_P3
L3
L2
VSS195
VSS196
VSS197
VSS VSS268
VSS269
VSS270
B17
B15
FDI_CTX_PRX_P0 A22 E31 PCIE_GTX_CRX_P2 DIS@ C30 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P2 L1 B13
14 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13] VSS198 VSS271
FDI_CTX_PRX_P1 G19 C33 PCIE_GTX_CRX_P1 DIS@ C31 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P1 K35 B11
14 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14] VSS199 VSS272
FDI_CTX_PRX_P2 E20 B32 PCIE_GTX_CRX_P0 DIS@ C32 1 2 0.22U_0402_10V6K PCIE_GTX_C_CRX_P0 K32 B9
14 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15] VSS200 VSS273
FDI_CTX_PRX_P3 G18 K29 B8
14 FDI_CTX_PRX_P3 FDI0_TX[3] PCIE_CTX_C_GRX_N[0..15] 20 VSS201 VSS274
FDI_CTX_PRX_P4 B20 M29 PCIE_CTX_GRX_N15 DIS@ C33 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N15 K26 B7
14 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0] VSS202 VSS275
FDI_CTX_PRX_P5 C19 M32 PCIE_CTX_GRX_N14 DIS@ C34 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N14 J34 B5
14 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1] VSS203 VSS276
FDI_CTX_PRX_P6 D19 M31 PCIE_CTX_GRX_N13 DIS@ C35 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N13 J31 B3
14 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2] VSS204 VSS277
FDI_CTX_PRX_P7 F17 L32 PCIE_CTX_GRX_N12 DIS@ C36 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N12 H33 B2
14 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3] VSS205 VSS278
L29 PCIE_CTX_GRX_N11 DIS@ C37 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N11 H30 A35
+VCCP FDI_FSYNC0 PEG_TX#[4] PCIE_CTX_GRX_N10 DIS@ C38 0.22U_0402_10V6K PCIE_CTX_C_GRX_N10 VSS206 VSS279
14 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2 H27 VSS207 VSS280 A32
14 FDI_FSYNC1 FDI_FSYNC1 J17 K28 PCIE_CTX_GRX_N9 DIS@ C39 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N9 H24 A29
FDI1_FSYNC PEG_TX#[6] PCIE_CTX_GRX_N8 DIS@ C40 0.22U_0402_10V6K PCIE_CTX_C_GRX_N8 VSS208 VSS281
PEG_TX#[7] J30 1 2 H21 VSS209 VSS282 A26
14 FDI_INT FDI_INT H20 J28 PCIE_CTX_GRX_N7 DIS@ C41 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N7 H18 A23
FDI_INT PEG_TX#[8] PCIE_CTX_GRX_N6 DIS@ C42 0.22U_0402_10V6K PCIE_CTX_C_GRX_N6 VSS210 VSS283
PEG_TX#[9] H29 1 2 H15 VSS211 VSS284 A20
1

14 FDI_LSYNC0 FDI_LSYNC0 J19 G27 PCIE_CTX_GRX_N5 DIS@ C43 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N5 H13 A3
R2 FDI_LSYNC1 FDI0_LSYNC PEG_TX#[10] PCIE_CTX_GRX_N4 DIS@ C44 0.22U_0402_10V6K PCIE_CTX_C_GRX_N4 VSS212 VSS285
14 FDI_LSYNC1 H17 FDI1_LSYNC PEG_TX#[11] E29 1 2 H10 VSS213
F27 PCIE_CTX_GRX_N3 DIS@ C45 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N3 H9
24.9_0402_1% PEG_TX#[12] PCIE_CTX_GRX_N2 DIS@ C46 0.22U_0402_10V6K PCIE_CTX_C_GRX_N2 VSS214
PEG_TX#[13] D28 1 2 H8 VSS215
F26 PCIE_CTX_GRX_N1 DIS@ C47 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_N1 H7
2

PEG_TX#[14] PCIE_CTX_GRX_N0 DIS@ C48 0.22U_0402_10V6K PCIE_CTX_C_GRX_N0 VSS216


PEG_TX#[15] E25 1 2 H6 VSS217
EDP_COMP A18 H5
eDP_COMPIO PCIE_CTX_C_GRX_P[0..15] 20 VSS218
A17 M28 PCIE_CTX_GRX_P15 DIS@ C49 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P15 H4
eDP_ICOMPO PEG_TX[0] PCIE_CTX_GRX_P14 DIS@ C50 0.22U_0402_10V6K PCIE_CTX_C_GRX_P14 VSS219
B16 eDP_HPD# PEG_TX[1] M33 1 2 H3 VSS220
M30 PCIE_CTX_GRX_P13 DIS@ C51 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P13 H2
PEG_TX[2] PCIE_CTX_GRX_P12 DIS@ C52 0.22U_0402_10V6K PCIE_CTX_C_GRX_P12 VSS221
eDP_COMPIO L31 1 2 H1
PEG_TX[3] PCIE_CTX_GRX_P11 DIS@ C53 0.22U_0402_10V6K PCIE_CTX_C_GRX_P11 VSS222
and ICOMPO C15 eDP_AUX PEG_TX[4] L28 1 2 G35 VSS223
signals D15 K30 PCIE_CTX_GRX_P10 DIS@ C54 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P10 G32
eDP_AUX# PEG_TX[5] PCIE_CTX_GRX_P9 DIS@ C55 0.22U_0402_10V6K PCIE_CTX_C_GRX_P9 VSS224
K27 1 2 G29
eDP

should be PEG_TX[6] PCIE_CTX_GRX_P8 DIS@ C56 0.22U_0402_10V6K PCIE_CTX_C_GRX_P8 VSS225


PEG_TX[7] J29 1 2 G26 VSS226
B shorted C17 J27 PCIE_CTX_GRX_P7 DIS@ C57 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P7 G23 B
near balls eDP_TX[0] PEG_TX[8] PCIE_CTX_GRX_P6 DIS@ C58 0.22U_0402_10V6K PCIE_CTX_C_GRX_P6 VSS227
F16 eDP_TX[1] PEG_TX[9] H28 1 2 G20 VSS228
and routed C16 G28 PCIE_CTX_GRX_P5 DIS@ C59 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P5 G17
eDP_TX[2] PEG_TX[10] PCIE_CTX_GRX_P4 DIS@ C60 0.22U_0402_10V6K PCIE_CTX_C_GRX_P4 VSS229
with G15 eDP_TX[3] PEG_TX[11] E28 1 2 G11 VSS230
typical F28 PCIE_CTX_GRX_P3 DIS@ C61 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P3 F34
PEG_TX[12] PCIE_CTX_GRX_P2 DIS@ C62 0.22U_0402_10V6K PCIE_CTX_C_GRX_P2 VSS231
impedance C18 eDP_TX#[0] PEG_TX[13] D27 1 2 F31 VSS232
E16 E26 PCIE_CTX_GRX_P1 DIS@ C63 1 2 0.22U_0402_10V6K PCIE_CTX_C_GRX_P1 F29
<25 mohms eDP_TX#[1] PEG_TX[14] PCIE_CTX_GRX_P0 DIS@ C64 0.22U_0402_10V6K PCIE_CTX_C_GRX_P0 VSS233
D16 eDP_TX#[2] PEG_TX[15] D25 1 2
F15 eDP_TX#[3]

TYCO_2013620-2_IVY BRIDGE
CONN@

TYCO_2013620-2_IVY BRIDGE

CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 4 of 61
5 4 3 2 1
5 4 3 2 1

+3V_PCH +3VALW

JCPU1B

2
PR-7
R577 R576
A28 CLK_CPU_DMI_R R18 1 2 0_0402_5% 0_0402_5% 0_0402_5%
BCLK CLK_CPU_DMI 13 +3VS
C26 A27 CLK_CPU_DMI#_R R19 1 2 0_0402_5%

MISC

CLOCKS
16 H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# 13 @

0.1U_0402_16V4Z~D
1
1
+1.5V_CPU_VDDQ
AN34 SKTOCC# 1

C65
D CLK_CPU_DPLL_R R21 1K_0402_1% D
DPLL_REF_CLK A16 1 2

1
A15 CLK_CPU_DPLL#_R R22 1 2 1K_0402_1% +VCCP R3
DPLL_REF_CLK# 10K_0402_5% R4
2
200_0402_1%
PAD T1 @ H_CATERR# AL33

2
CATERR#

5
U1

2
R9 1 2 S_PWG 1

P
14 SYSTEM_PWROK @ 0_0402_5% A VDDPWRGOOD
4

THERMAL
H_PECI H_DRAMRST# D_PWG O
40 H_PECI AN33 PECI SM_DRAMRST# R8 H_DRAMRST# 6 14 PM_DRAM_PWRGD 1 2 2 B

G
R11 0_0402_5%
74AHC1G09GW TSSOP 5P

DDR3
MISC

3
R23 1 2 PR-7
+3V_PCH
40,43 H_PROCHOT# 1 2 H_PROCHOT#_R AL32 PROCHOT# SM_RCOMP[0] AK1 SM_RCOMP0 200_0402_1% R14
56_0402_5% A5 SM_RCOMP1
SM_RCOMP[1] SM_RCOMP2
SM_RCOMP[2] A4

H_THERMTRIP# AN32
16 H_THERMTRIP# THERMTRIP# +3VS +VCCP

0.1U_0402_16V4Z

1
AP29 XDP_PRDY# 1
PRDY# XDP_PREQ# R15
PREQ# AP27

C69
75_0402_5%
AR26 XDP_TCK
TCK XDP_TMS 2
AR27

PWR MANAGEMENT

2
TMS

JTAG & BPM


H_PM_SYNC AM34 AP30 XDP_TRST#
14 H_PM_SYNC PM_SYNC TRST#

1
AR28 XDP_TDI_R U2 R17

P
TDI

NC
PR-2 AP26 XDP_TDO_R 2 4 BUFO_CPU_RST# 1 2 BUF_CPU_RST#
TDO 15,32,36,40,41 PLT_RST# A Y
16 H_CPUPWRGD H_CPUPWRGD 1 2 H_CPUPWRGD_R AP33 43_0402_1%
UNCOREPWRGOOD

G
R12 33_0402_5%
C SN74LVC1G07DCKR_SC70-5 C

1
R36 AL35 XDP_DBRESET#_R1 1 2 @
DBR# XDP_DBRESET#_R 12,14
VDDPWRGOOD 1 2 VDDPWRGOOD_R V8 R37 0_0402_5% R20
130_0402_1% SM_DRAMPWROK
0_0402_5%
AT28 XDP_BPM#0 PR-7
BPM#[0] XDP_BPM#1
AR29

2
BPM#[1] XDP_BPM#2
BPM#[2] AR30
BUF_CPU_RST# AR33 AT30 XDP_BPM#3
RESET# BPM#[3] XDP_BPM#4
BPM#[4] AP32
AR31 XDP_BPM#5
BPM#[5] XDP_BPM#6
BPM#[6] AT31
AR32 XDP_BPM#7
BPM#[7]

TYCO_2013620-2_IVY BRIDGE
CONN@
PR-17

1 2 VDDPWRGOOD_R @ 1 2 H_DRAMRST# PU/PD for JTAG signals


C72 12P_0402_50V8J C70 100P_0402_50V8J
+VCCP

Reserve for EMI please close to JCPU1 Reserve for EMI please close to JCPU1
XDP_TMS 51_0402_5% 1 2 R26

XDP_TDI_R 51_0402_5% 1 2 R27


B PR-2 1 2 H_CPUPWRGD_R +3VS B
C640 100P_0402_50V8J
XDP_DBRESET#_R1 1K_0402_5% 1 2 R24 XDP_TDO_R 51_0402_5% 1 2 R29

Reserve for EMI please close to JCPU1


H_CPUPWRGD_R 10K_0402_5%1 2 R25 XDP_TCK 51_0402_5% 1 2 R32

XDP_TRST# 51_0402_5% 1 2 R33

@ 1 2 H_PECI
C68 100P_0402_50V8J

@ 1 2 XDP_DBRESET#_R1
C71 100P_0402_50V8J
Reserve for EMI please close to JCPU1
DDR3 Compensation Signals
Reserve for EMI please close to JCPU1
PR-17
1 2 BUF_CPU_RST# SM_RCOMP0 140_0402_1%1 2 R34
C647 100P_0402_50V8J
SM_RCOMP1 25.5_0402_1%1 2 R38

SM_RCOMP2 200_0402_1%1 2 R39


Reserve for EMI please close to JCPU1

A +VCCP A
Processor Pullups

H_PROCHOT# 62_0402_5%
1 2 R16

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 5 of 61
5 4 3 2 1
5 4 3 2 1

JCPU1C

JCPU1D

10 DDR_A_D[0..63] SA_CLK[0] AB6 DDRA_CLK0 10


SA_CLK#[0] AA6 DDRA_CLK0# 10
DDR_A_D0 C5 V9 AE2
SA_DQ[0] SA_CKE[0] DDRA_CKE0 10 11 DDR_B_D[0..63] SB_CLK[0] DDRB_CLK0 11
DDR_A_D1 D5 AD2
SA_DQ[1] SB_CLK#[0] DDRB_CLK0# 11
DDR_A_D2 D3 DDR_B_D0 C9 R9
SA_DQ[2] SB_DQ[0] SB_CKE[0] DDRB_CKE0 11
DDR_A_D3 D2 DDR_B_D1 A7
DDR_A_D4 SA_DQ[3] DDR_B_D2 SB_DQ[1]
D6 SA_DQ[4] SA_CLK[1] AA5 DDRA_CLK1 10 D10 SB_DQ[2]
D DDR_A_D5 DDR_B_D3 D
C6 SA_DQ[5] SA_CLK#[1] AB5 DDRA_CLK1# 10 C8 SB_DQ[3]
DDR_A_D6 C2 V10 DDR_B_D4 A9 AE1
SA_DQ[6] SA_CKE[1] DDRA_CKE1 10 SB_DQ[4] SB_CLK[1] DDRB_CLK1 11
DDR_A_D7 C3 DDR_B_D5 A8 AD1
SA_DQ[7] SB_DQ[5] SB_CLK#[1] DDRB_CLK1# 11
DDR_A_D8 F10 DDR_B_D6 D9 R10
SA_DQ[8] SB_DQ[6] SB_CKE[1] DDRB_CKE1 11
DDR_A_D9 F8 DDR_B_D7 D8
DDR_A_D10 SA_DQ[9] DDR_B_D8 SB_DQ[7]
G10 SA_DQ[10] RSVD_TP[1] AB4 G4 SB_DQ[8]
DDR_A_D11 G9 AA4 DDR_B_D9 F4
DDR_A_D12 SA_DQ[11] RSVD_TP[2] DDR_B_D10 SB_DQ[9]
F9 SA_DQ[12] RSVD_TP[3] W9 F1 SB_DQ[10] RSVD_TP[11] AB2
DDR_A_D13 F7 DDR_B_D11 G1 AA2
DDR_A_D14 SA_DQ[13] DDR_B_D12 SB_DQ[11] RSVD_TP[12]
G8 SA_DQ[14] G5 SB_DQ[12] RSVD_TP[13] T9
DDR_A_D15 G7 DDR_B_D13 F5
DDR_A_D16 SA_DQ[15] DDR_B_D14 SB_DQ[13]
K4 SA_DQ[16] RSVD_TP[4] AB3 F2 SB_DQ[14]
DDR_A_D17 K5 AA3 DDR_B_D15 G2
DDR_A_D18 SA_DQ[17] RSVD_TP[5] DDR_B_D16 SB_DQ[15]
K1 SA_DQ[18] RSVD_TP[6] W10 J7 SB_DQ[16] RSVD_TP[14] AA1
DDR_A_D19 J1 DDR_B_D17 J8 AB1
DDR_A_D20 SA_DQ[19] DDR_B_D18 SB_DQ[17] RSVD_TP[15]
J5 SA_DQ[20] K10 SB_DQ[18] RSVD_TP[16] T10
DDR_A_D21 J4 DDR_B_D19 K9
DDR_A_D22 SA_DQ[21] DDR_B_D20 SB_DQ[19]
J2 SA_DQ[22] SA_CS#[0] AK3 DDRA_SCS0# 10 J9 SB_DQ[20]
DDR_A_D23 K2 AL3 DDR_B_D21 J10
SA_DQ[23] SA_CS#[1] DDRA_SCS1# 10 SB_DQ[21]
DDR_A_D24 M8 AG1 DDR_B_D22 K8 AD3
SA_DQ[24] RSVD_TP[7] SB_DQ[22] SB_CS#[0] DDRB_SCS0# 11
DDR_A_D25 N10 AH1 DDR_B_D23 K7 AE3
SA_DQ[25] RSVD_TP[8] SB_DQ[23] SB_CS#[1] DDRB_SCS1# 11
DDR_A_D26 N8 DDR_B_D24 M5 AD6
DDR_A_D27 SA_DQ[26] DDR_B_D25 SB_DQ[24] RSVD_TP[17]
N7 SA_DQ[27] N4 SB_DQ[25] RSVD_TP[18] AE6
DDR_A_D28 M10 DDR_B_D26 N2
DDR_A_D29 SA_DQ[28] DDR_B_D27 SB_DQ[26]
M9 SA_DQ[29] SA_ODT[0] AH3 DDRA_ODT0 10 N1 SB_DQ[27]
DDR_A_D30 N9 AG3 DDR_B_D28 M4
SA_DQ[30] SA_ODT[1] DDRA_ODT1 10 SB_DQ[28]
DDR_A_D31
DDR_A_D32
M7
AG6
SA_DQ[31] DDR SYSTEM MEMORY A RSVD_TP[9] AG2
AH2
DDR_B_D29
DDR_B_D30
N5
M2
SB_DQ[29] SB_ODT[0] AE4
AD4
DDRB_ODT0 11

DDR SYSTEM MEMORY B


SA_DQ[32] RSVD_TP[10] SB_DQ[30] SB_ODT[1] DDRB_ODT1 11
DDR_A_D33 AG5 DDR_B_D31 M1 AD5
DDR_A_D34 SA_DQ[33] DDR_B_D32 SB_DQ[31] RSVD_TP[19]
AK6 SA_DQ[34] AM5 SB_DQ[32] RSVD_TP[20] AE5
DDR_A_D35 AK5 DDR_B_D33 AM6
DDR_A_D36 SA_DQ[35] DDR_B_D34 SB_DQ[33]
AH5 SA_DQ[36] DDR_A_DQS#[0..7] 10 AR3 SB_DQ[34]
C DDR_A_D37 DDR_A_DQS#0 DDR_B_D35 C
AH6 SA_DQ[37] SA_DQS#[0] C4 AP3 SB_DQ[35]
DDR_A_D38 AJ5 G6 DDR_A_DQS#1 DDR_B_D36 AN3
SA_DQ[38] SA_DQS#[1] SB_DQ[36] DDR_B_DQS#[0..7] 11
DDR_A_D39 AJ6 J3 DDR_A_DQS#2 DDR_B_D37 AN2 D7 DDR_B_DQS#0
DDR_A_D40 SA_DQ[39] SA_DQS#[2] DDR_A_DQS#3 DDR_B_D38 SB_DQ[37] SB_DQS#[0] DDR_B_DQS#1
AJ8 SA_DQ[40] SA_DQS#[3] M6 AN1 SB_DQ[38] SB_DQS#[1] F3
DDR_A_D41 AK8 AL6 DDR_A_DQS#4 DDR_B_D39 AP2 K6 DDR_B_DQS#2
DDR_A_D42 SA_DQ[41] SA_DQS#[4] DDR_A_DQS#5 DDR_B_D40 SB_DQ[39] SB_DQS#[2] DDR_B_DQS#3
AJ9 SA_DQ[42] SA_DQS#[5] AM8 AP5 SB_DQ[40] SB_DQS#[3] N3
DDR_A_D43 AK9 AR12 DDR_A_DQS#6 DDR_B_D41 AN9 AN5 DDR_B_DQS#4
DDR_A_D44 SA_DQ[43] SA_DQS#[6] DDR_A_DQS#7 DDR_B_D42 SB_DQ[41] SB_DQS#[4] DDR_B_DQS#5
AH8 SA_DQ[44] SA_DQS#[7] AM15 AT5 SB_DQ[42] SB_DQS#[5] AP9
DDR_A_D45 AH9 DDR_B_D43 AT6 AK12 DDR_B_DQS#6
DDR_A_D46 SA_DQ[45] DDR_B_D44 SB_DQ[43] SB_DQS#[6] DDR_B_DQS#7
AL9 SA_DQ[46] AP6 SB_DQ[44] SB_DQS#[7] AP15
DDR_A_D47 AL8 DDR_B_D45 AN8
DDR_A_D48 SA_DQ[47] DDR_B_D46 SB_DQ[45]
AP11 SA_DQ[48] DDR_A_DQS[0..7] 10 AR6 SB_DQ[46]
DDR_A_D49 AN11 D4 DDR_A_DQS0 DDR_B_D47 AR5
DDR_A_D50 SA_DQ[49] SA_DQS[0] DDR_A_DQS1 DDR_B_D48 SB_DQ[47]
AL12 SA_DQ[50] SA_DQS[1] F6 AR9 SB_DQ[48] DDR_B_DQS[0..7] 11
DDR_A_D51 AM12 K3 DDR_A_DQS2 DDR_B_D49 AJ11 C7 DDR_B_DQS0
DDR_A_D52 SA_DQ[51] SA_DQS[2] DDR_A_DQS3 DDR_B_D50 SB_DQ[49] SB_DQS[0] DDR_B_DQS1
AM11 SA_DQ[52] SA_DQS[3] N6 AT8 SB_DQ[50] SB_DQS[1] G3
DDR_A_D53 AL11 AL5 DDR_A_DQS4 DDR_B_D51 AT9 J6 DDR_B_DQS2
DDR_A_D54 SA_DQ[53] SA_DQS[4] DDR_A_DQS5 DDR_B_D52 SB_DQ[51] SB_DQS[2] DDR_B_DQS3
AP12 SA_DQ[54] SA_DQS[5] AM9 AH11 SB_DQ[52] SB_DQS[3] M3
DDR_A_D55 AN12 AR11 DDR_A_DQS6 DDR_B_D53 AR8 AN6 DDR_B_DQS4
DDR_A_D56 SA_DQ[55] SA_DQS[6] DDR_A_DQS7 DDR_B_D54 SB_DQ[53] SB_DQS[4] DDR_B_DQS5
AJ14 SA_DQ[56] SA_DQS[7] AM14 AJ12 SB_DQ[54] SB_DQS[5] AP8
DDR_A_D57 AH14 DDR_B_D55 AH12 AK11 DDR_B_DQS6
DDR_A_D58 SA_DQ[57] DDR_B_D56 SB_DQ[55] SB_DQS[6] DDR_B_DQS7
AL15 SA_DQ[58] AT11 SB_DQ[56] SB_DQS[7] AP14
DDR_A_D59 AK15 DDR_B_D57 AN14
DDR_A_D60 SA_DQ[59] DDR_B_D58 SB_DQ[57]
AL14 SA_DQ[60] DDR_A_MA[0..15] 10 AR14 SB_DQ[58]
DDR_A_D61 AK14 AD10 DDR_A_MA0 DDR_B_D59 AT14
DDR_A_D62 SA_DQ[61] SA_MA[0] DDR_A_MA1 DDR_B_D60 SB_DQ[59]
AJ15 SA_DQ[62] SA_MA[1] W1 AT12 SB_DQ[60] DDR_B_MA[0..15] 11
DDR_A_D63 AH15 W2 DDR_A_MA2 DDR_B_D61 AN15 AA8 DDR_B_MA0
SA_DQ[63] SA_MA[2] DDR_A_MA3 DDR_B_D62 SB_DQ[61] SB_MA[0] DDR_B_MA1
SA_MA[3] W7 AR15 SB_DQ[62] SB_MA[1] T7
V3 DDR_A_MA4 DDR_B_D63 AT15 R7 DDR_B_MA2
SA_MA[4] DDR_A_MA5 SB_DQ[63] SB_MA[2] DDR_B_MA3
SA_MA[5] V2 SB_MA[3] T6
W3 DDR_A_MA6 T2 DDR_B_MA4
SA_MA[6] DDR_A_MA7 SB_MA[4] DDR_B_MA5
10 DDR_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 SB_MA[5] T4
B DDR_A_MA8 DDR_B_MA6 B
10 DDR_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 SB_MA[6] T3
V6 W5 DDR_A_MA9 AA9 R2 DDR_B_MA7
10 DDR_A_BS2 SA_BS[2] SA_MA[9] 11 DDR_B_BS0 SB_BS[0] SB_MA[7]
AD8 DDR_A_MA10 AA7 T5 DDR_B_MA8
SA_MA[10] 11 DDR_B_BS1 SB_BS[1] SB_MA[8]
V4 DDR_A_MA11 R6 R3 DDR_B_MA9
SA_MA[11] 11 DDR_B_BS2 SB_BS[2] SB_MA[9]
W4 DDR_A_MA12 AB7 DDR_B_MA10
SA_MA[12] DDR_A_MA13 SB_MA[10] DDR_B_MA11
10 DDR_A_CAS# AE8 SA_CAS# SA_MA[13] AF8 SB_MA[11] R1
AD9 V5 DDR_A_MA14 T1 DDR_B_MA12
10 DDR_A_RAS# SA_RAS# SA_MA[14] SB_MA[12]
AF9 V7 DDR_A_MA15 AA10 AB10 DDR_B_MA13
10 DDR_A_WE# SA_WE# SA_MA[15] 11 DDR_B_CAS# SB_CAS# SB_MA[13]
AB8 R5 DDR_B_MA14
11 DDR_B_RAS# SB_RAS# SB_MA[14]
AB9 R4 DDR_B_MA15
11 DDR_B_WE# SB_WE# SB_MA[15]

TYCO_2013620-2_IVY BRIDGE
CONN@
TYCO_2013620-2_IVY BRIDGE
CONN@
+1.5V
1

R40
1K_0402_5%
Q6
BSS138_SOT23
2
S

5 H_DRAMRST# H_DRAMRST# 3 1 DDR3_DRAMRST#_R 1 2 DDR3_DRAMRST# 10,11


R41 1K_0402_5%
G
2
1

A A
R42 1 @ 2 DRAMRST_CNTRL_PCH 9,13,40
4.99K_0402_1% 0_0402_5% R43
1 2 EC_DRAMRST_CNTRL_PCH 40
0_0402_5% R44
2

PR-7
Instant ON
C73
0.047U_0402_16V7K Security Classification Compal Secret Data Compal Electronics, Inc.
2011/08/23 2012/12/31 Title
Issued Date Deciphered Date SCHEMATIC A8222
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 6 of 61
5 4 3 2 1
5 4 3 2 1

CFG Straps for Processor


JCPU1E

CFG2
D D
VCC_DIE_SENSE AH27

1
CFG0 AK28 AH26
CFG[0] VSS_DIE_SENSE R45
AK29 CFG[1]
CFG2 AL26 1K_0402_1%
CFG[2]
AL27 CFG[3]
CFG4 AK26 L7

2
CFG5 CFG[4] RSVD28
AL29 CFG[5] RSVD29 AG7
CFG6 AL30 AE7
CFG[6] RSVD30
AM31 CFG[7] RSVD31 AK2
AM32 CFG[8]
AM30 W8

CFG
CFG10 CFG[9] RSVD32
AM28 CFG[10]
+VCC_GFXCORE_AXG CFG11 AM26 PEG Static Lane Reversal - CFG2 is for the 16x
CFG12 CFG[11]
AN28 CFG[12] RSVD33 AT26
+VCC_CORE CFG13 AN31 AM33
CFG14 CFG[13] RSVD34
AN26 CFG[14] RSVD35 AJ27 1:(Default) Normal Operation; Lane #
1

CFG15 AM27 CFG2


?? CFG16 AK31
CFG[15] definition matches socket pin map definition
R46 CFG17 CFG[16]
AN29 CFG[17] 0:Lane Reversed
1

49.9_0402_1%
R48 @
2

49.9_0402_1% T8
@ RSVD37 CFG4
RSVD38 J16
VCC_AXG_VAL_SENSE AJ31 H16
2

VAXG_VAL_SENSE RSVD39

1
VSS_AXG_VAL_SENSE AH31 G16
VCC_VAL_SENSE VSSAXG_VAL_SENSE RSVD40 @R47
@ R47
AJ33 VCC_VAL_SENSE
VSS_VAL_SENSE AH33 1K_0402_1%
VSS_VAL_SENSE
Please place as close as JCPU1

2
AJ26 RSVD5 RSVD_NCTF1 AR35
AT34

RESERVED
RSVD_NCTF2
RSVD_NCTF3 AT33
C C
RSVD_NCTF4 AP35
RSVD_NCTF5 AR34

Display Port Presence Strap


F25 RSVD8
F24 RSVD9
F23 RSVD10 1 : Disabled; No Physical Display Port
D24 RSVD11 RSVD_NCTF6 B34 CFG4 attached to Embedded Display Port
G25 RSVD12 RSVD_NCTF7 A33
G24 RSVD13 RSVD_NCTF8 A34
E23 RSVD14 RSVD_NCTF9 B35 0 : Enabled; An external Display Port device is
D23 C35
C30
RSVD15 RSVD_NCTF10 connected to the Embedded Display Port
RSVD16
A31 RSVD17
B30 RSVD18
B29 RSVD19
D30 AJ32 CFG6
RSVD20 RSVD51
B31 RSVD21 RSVD52 AK32
A30 CFG5
RSVD22
C29 RSVD23

1
?? VSS_AXG_VAL_SENSE
AN35 R49 R50
BCLK_ITP 1K_0402_1% 1K_0402_1%
J20 RSVD24 BCLK_ITP# AM35
VSS_VAL_SENSE B18 @ @
RSVD25

2
1

R51 R52 J15 AT2


49.9_0402_1% 49.9_0402_1% RSVD27 RSVD_NCTF11
RSVD_NCTF12 AT1
@ @ AR1
RSVD_NCTF13
2

B B

KEY B1 PCIE Port Bifurcation Straps

11: (Default) x16 - Device 1 functions 1 and 2 disabled


Please place as close as JCPU1
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
TYCO_2013620-2_IVY BRIDGE
disabled
CONN@ 01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

A A

Security Classification Compal Secret Data Compal Electronics, Inc.


Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 7 of 61
5 4 3 2 1
5 4 3 2 1

JCPU1F POWER
+VCCP
+VCC_CORE
8.5A
97AAG35
VCC1
AG34 VCC2 VCCIO1 AH13
AG33 VCC3 VCCIO2 AH10
D D
AG32 VCC4 VCCIO3 AG10
AG31 VCC5 VCCIO4 AC10
AG30 VCC6 VCCIO5 Y10
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF34 VCC12 VCCIO11 J12
AF33 VCC13 VCCIO12 J11
AF32 VCC14 VCCIO13 H14
AF31 VCC15 VCCIO14 H12
AF30 VCC16 VCCIO15 H11
AF29 VCC17 VCCIO16 G14
AF28 VCC18 VCCIO17 G13
AF27 G12

PEG AND DDR


VCC19 VCCIO18
AF26 VCC20 VCCIO19 F14
AD35 VCC21 VCCIO20 F13
AD34 VCC22 VCCIO21 F12
AD33 VCC23 VCCIO22 F11
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 VCC33 VCCIO31 C13
AC32 VCC34 VCCIO32 C12
AC31 VCC35 VCCIO33 C11
C C
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
AC28 VCC38 VCCIO36 A14
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
AA35 VCC41 VCCIO39 A11
AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32 VCC44
AA31 VCC45
AA30 VCC46 +VCCP
AA29 VCC47
AA28 PR-7
VCC48
AA27 VCC49
AA26 VCC50

0.1U_0402_16V4Z
Y35 H_CPU_SVIDCLK 1 2
CORE SUPPLY

VCC51 VR_SVID_CLK 50
Y34 1 R53 0_0402_5%
VCC52
Y33 VCC53 Place the PU

C74
Y32
Y31
VCC54 @ resistors close to CPU
VCC55

1
2
Y30 VCC56
Y29 R54
VCC57
Y28 VCC58 75_0402_5%
Y27 VCC59
Y26

2
VCC60
V35 VCC61
V34 AJ29 H_CPU_SVIDALRT# R55 1 2
SVID

VCC62 VIDALERT# VR_SVID_ALRT# 50


V33 AJ30 H_CPU_SVIDCLK 43_0402_1%
VCC63 VIDSCLK VR_SVID_DAT
V32 VCC64 VIDSOUT AJ28
+VCCP
V31 VCC65
V30 VCC66

0.1U_0402_16V4Z
V29 VCC67
B B
V28 VCC68 Place the PU 1
V27 VCC69 resistors close to CPU
1

V26 VCC70 R56 @ C75


U35 VCC71 130_0402_1% 2
U34 VCC72
U33 VCC73
U32
2

VCC74 VR_SVID_DAT
U31 VCC75 VR_SVID_DAT 50
U30 VCC76
U29 VCC77
U28 VCC78
U27 VCC79
U26 VCC80
R35 +VCC_CORE
VCC81
R34 VCC82
R33 VCC83
1

R32 VCC84
R31 R57
VCC85
R30 VCC86 100_0402_1%
R29 PR-7
VCC87
R28
SENSE LINES

VCC88
R27 VCC89 VCC_SENSE AJ35 VCCSENSE_R 1 2 VCCSENSE 50
R26 VCC90 VSS_SENSE AJ34 VSSSENSE_R R58 1 2 0_0402_5% VSSSENSE 50
P35 R59 0_0402_5%
VCC91 +VCCP
P34 VCC92
1

P33 R60
VCC93 R61
P32 VCC94 VCCIO_SENSE B10 2 1
P31 A10 10_0402_1% 100_0402_1%
VCC95 VSS_SENSE_VCCIO
P30 VCC96
P29
2

VCC97
P28 VCC98
P27 VCC99 VCCIO_SENSE 48
A A
P26 VCC100
1

R62
0_0402_5%

Security Classification Compal Secret Data COMPAL Electronics,Inc


2

TYCO_2013620-2_IVY BRIDGE CONN@ 2011/08/23 2012/12/31 Title


Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 8 of 61
5 4 3 2 1
5 4 3 2 1

+VCC_GFXCORE_AXG
JCPU1H

1
AT35 VSS1 VSS81 AJ22
R67 AT32 AJ19
100_0402_1% Place near CPU AT29
VSS2
VSS3
VSS82
VSS83 AJ16
AT27 VSS4 VSS84 AJ13
AT25 AJ10

2
VSS5 VSS85
VCC_AXG_SENSE 50 AT22 VSS6 VSS86 AJ7
+VCC_GFXCORE_AXG
AT19 AJ4

JCPU1G
POWER 1 2
VSS_AXG_SENSE 50
+V_SM_VREF should
AT16
AT13
AT10
VSS7
VSS8
VSS9
VSS87
VSS88
VSS89
AJ3
AJ2
AJ1
R68 100_0402_1% VSS10 VSS90
have 10 mil trace width AT7 VSS11 VSS91 AH35
33A AT4 VSS12 VSS92 AH34
AT24 AK35 AT3 AH32

SENSE
LINES
D VAXG1 VAXG_SENSE +1.5V VSS13 VSS93 D
AT23 AK34 +1.5V_CPU_VDDQ AR25 AH30
VAXG2 VSSAXG_SENSE VSS14 VSS94
AT21 VAXG3 AR22 VSS15 VSS95 AH29
AT20 VAXG4 AR19 VSS16 VSS96 AH28
AT18 VAXG5 2 1 AR16 VSS17 VSS98 AH25

1
AT17 0_0402_5% R69 @ AR13 AH22
VAXG6 R70 R71 VSS18 VSS99
AR24 VAXG7 AR10 VSS19 VSS100 AH19
AR23 1K_0402_1% 1K_0402_1% AR7 AH16
VAXG8 Q8 @ VSS20 VSS101
AR21 VAXG9 AR4 VSS21 VSS102 AH7
AR20 @ AR2 AH4

2
VAXG10 VSS22 VSS103

D
AR18 AL1 +V_SM_VREF_CNT 3 1 +V_SM_VREF AP34 AG9
VAXG11 SM_VREF VSS23 VSS104
AR17 VAXG12 1 AP31 VSS24 VSS105 AG8

1
AP24 AP28 AG4

VREF
VAXG13 VSS25 VSS106

1
0.1U_0402_16V7K R72 PMV45EN_SOT23-3

G
AP23 AP25 AF6

2
VAXG14 C149 1K_0402_1% R73 VSS26 VSS107
AP21 VAXG15 AP22 VSS27 VSS108 AF5
+V_DDR_REFA_R 2 @ 1K_0402_1%
AP20 VAXG16 SA_DIMM_VREFDQ B4 AP19 VSS28 VSS109 AF3
AP18 D1 +V_DDR_REFB_R AP16 AF2

2
VAXG17 SB_DIMM_VREFDQ RUN_ON_CPU1.5VS3 VSS29 VSS110
AP17 AP13 AE35

2
VAXG18 VSS30 VSS111
AN24 VAXG19 AP10 VSS31 VSS112 AE34
AN23 VAXG20 AP7 VSS32 VSS113 AE33
AN21 VAXG21 AP4 VSS33 VSS114 AE32
AN20 +1.5V_CPU_VDDQ AP1 AE31
VAXG22 VSS34 VSS115
AN18 AN30 AE30

DDR3 -1.5V RAILS


VAXG23 VSS35 VSS116
AN17 VAXG24 5A AN27 VSS36 VSS117 AE29
AM24 AF7 AN25 AE28

GRAPHICS
AM23
AM21
VAXG25
VAXG26
VAXG27
VDDQ1
VDDQ2
VDDQ3
AF4
AF1
AN22
AN19
VSS37
VSS38
VSS39
VSS VSS118
VSS119
VSS120
AE27
AE26

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM

330U_D2_2VM_R6M
AM20 VAXG28 VDDQ4 AC7 1 AN16 VSS40 VSS121 AE9
AM18 VAXG29 VDDQ5 AC4 1 1 1 1 1 1 AN13 VSS41 VSS122 AD7

C84

C78
AM17 AC1 + AN10 AC9
VAXG30 VDDQ6 VSS42 VSS123

C79

C80

C81

C82

C83
AL24 VAXG31 VDDQ7 Y7 AN7 VSS43 VSS124 AC8
AL23 VAXG32 VDDQ8 Y4 AN4 VSS44 VSS125 AC6
2 2 2 2 2 2 2 3
AL21 VAXG33 VDDQ9 Y1 AM29 VSS45 VSS126 AC5
AL20 VAXG34 VDDQ10 U7 AM25 VSS46 VSS127 AC3
AL18 VAXG35 VDDQ11 U4 AM22 VSS47 VSS128 AC2
AL17 VAXG36 VDDQ12 U1 AM19 VSS48 VSS129 AB35
AK24 VAXG37 VDDQ13 P7 AM16 VSS49 VSS130 AB34
C AK23 VAXG38 VDDQ14 P4 AM13 VSS50 VSS131 AB33 C
AK21 VAXG39 VDDQ15 P1 AM10 VSS51 VSS132 AB32
AK20 VAXG40 AM7 VSS52 VSS133 AB31
AK18 VAXG41 AM4 VSS53 VSS134 AB30
AK17 VAXG42 AM3 VSS54 VSS135 AB29
AJ24 VAXG43 AM2 VSS55 VSS136 AB28
AJ23 VAXG44 AM1 VSS56 VSS137 AB27
AJ21 VAXG45 AL34 VSS57 VSS138 AB26
AJ20 VAXG46 AL31 VSS58 VSS139 Y9
AJ18 VAXG47 6A AL28 VSS59 VSS140 Y8
AJ17 VAXG48 VCCSA1 M27 +VCCSA AL25 VSS60 VSS141 Y6
SA RAIL

AH24 VAXG49 VCCSA2 M26 AL22 VSS61 VSS142 Y5

10U_0805_6.3VAM

10U_0805_6.3VAM

10U_0805_6.3VAM
AH23 VAXG50 VCCSA3 L26 1 AL19 VSS62 VSS143 Y3

10U_0603_6.3V6M

330U_D2_2VM_R6M
AH21 J26 1 1 1 1 @ AL16 Y2
VAXG51 VCCSA4 + VSS63 VSS144
AH20 VAXG52 VCCSA5 J25 AL13 VSS64 VSS145 W35

C86

C87

C88

C89

C85
AH18 VAXG53 VCCSA6 J24 AL10 VSS65 VSS146 W34
AH17 VAXG54 VCCSA7 H26 AL7 VSS66 VSS147 W33
2 2 2 2 2 3
VCCSA8 H25 AL4 VSS67 VSS148 W32
AL2 VSS68 VSS149 W31
AK33 VSS69 VSS150 W30
+1.8VS AK30
AK27
VSS70 VSS151 W29
W28
VSS71 VSS152
AK25 W27
1.8V RAIL

VSS72 VSS153
VCCSA_SENSE H23 +VCCSA_SENSE 49 AK22 VSS73 VSS154 W26
1.5A AK19 VSS74 VSS155 U9
R277 AK16 U8
VSS75 VSS156

1
1 2 +1.8VS_CPU_VCCPLL B6 AK13 U6
VCCPLL1 @ R74 VSS76 VSS157
A6 C22 AK10 U5
MISC

VCCPLL2 VCCSA_VID[0] H_VCCSA_VID0 49 VSS77 VSS158


10U_0805_6.3VAM

1U_0402_6.3V6K

1U_0402_6.3V6K

0_0805_5% 1 1 1 1 A2 C24 0_0402_5% AK7 U3


VCCPLL3 VCCSA_VID[1] H_VCCSA_VID1 49 VSS78 VSS159
330U_D2_2VM_R6M

AK4 VSS79 VSS160 U2


C94

C95

C96

C97

+ AJ25
2
PR-7 VSS80
2 2 2 VCCIO_SEL +3VS
VCCIO_SEL A19
2 3

TYCO_2013620-2_IVY BRIDGE CONN@ TYCO_2013620-2_IVY BRIDGE


2

CONN@
B R75 B
10K_0402_5% @
1

+1.5V_CPU_VDDQ 5A
+1.5V_CPU_VDDQ +1.5V
+1.5V Q7 +1.5V_CPU_VDDQ
+5VALW +5VALW AO4304L_SO8
C90 2 1 0.1U_0402_16V7K 8 1
7 2

20K_0402_5%
Q9 6 3 1
1

D BSS138_SOT23

10U_0603_6.3V6M
C91 2 1 0.1U_0402_16V7K 5

C76

R64
2 DRAMRST_CNTRL_PCH 6,13,40 R63
+V_DDR_REFA G R65 36.5K_0402_1%

4
+V_DDR_REFB C92 2
S 2 1 0.1U_0402_16V7K 100K_0402_5%
3

2
R77 1 @ 2 0_0402_5% +V_DDR_REFA_R
R78 1 @ 2 0_0402_5% +V_DDR_REFB_R RUN_ON_CPU1.5VS3

3
C93 2 1 0.1U_0402_16V7K
1

Q4B
1

2
D RUN_ON_CPU1.5VS3# 5
DRAMRST_CNTRL_PCH 2 Q10 R79 R80 C77
G 1K_0402_1% 1K_0402_1% 2N7002KDWH_SOT363-6 2200P_0402_50V7K

1
S BSS138_SOT23 @ @
3

R66 Q4A
40 CPU1.5V_S3_GATE 1 2 2
M3 Circuit (Processor Generated SO-DIMM VREF_DQ) 2N7002KDWH_SOT363-6
0_0402_5%
1

A RUN_ON_CPU1.5VS3# 42 A

PR-7

Security Classification Compal Secret Data COMPAL Electronics,Inc


Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 9 of 61
5 4 3 2 1
5 4 3 2 1

+1.5V 3.56A
+1.5V +1.5V 6 DDR_A_D[0..63]

1
6 DDR_A_DQS[0..7]
R81
1K_0402_1% DDR3 SO-DIMM A 6 DDR_A_DQS#[0..7]
JDIMM1
6 DDR_A_MA[0..15]

2
+V_DDR_REFA 1 VREF_DQ VSS1 2
3 4 DDR_A_D4
VSS2 DQ4

0.1U_0402_10V6K

2.2U_0402_6.3V6M
DDR_A_D0 5 6 DDR_A_D5
DQ0 DQ5

C98

C99
1 1 DDR_A_D1 7 8
DQ1 VSS3
1

9 10 DDR_A_DQS#0
R82 VSS4 DQS#0 DDR_A_DQS0
11 DM0 DQS0 12
D D
13 VSS5 VSS6 14
1K_0402_1% 2 2 DDR_A_D2 DDR_A_D6
15 DQ2 DQ6 16
DDR_A_D3 17 18 DDR_A_D7
2

DQ3 DQ7
19 VSS7 VSS8 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
23 DQ9 DQ13 24 Layout Note:
25 VSS9 VSS10 26 Place near JDIMM1
DDR_A_DQS#1 27 28
DDR_A_DQS1 DQS#1 DM1 DDR3_DRAMRST# +1.5V
29 DQS1 RESET# 30 DDR3_DRAMRST# 6,11
31 VSS11 VSS12 32
DDR_A_D10 33 34 DDR_A_D14
DQ10 DQ14

330U_B2_2.5VM_R15M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
DDR_A_D11 35 36 DDR_A_D15
DQ11 DQ15

C100
37 VSS13 VSS14 38 1

C101

C102

C103

C104

C105

C106

C107
DDR_A_D16 39 40 DDR_A_D20 1 1 1 1 1 1 1
DDR_A_D17 DQ16 DQ20 DDR_A_D21 +
41 DQ17 DQ21 42
43 VSS15 VSS16 44
DDR_A_DQS#2 45 46 @
DDR_A_DQS2 DQS#2 DM2 2 2 2 2 2 2 2 2
47 DQS2 VSS17 48
49 50 DDR_A_D22
DDR_A_D18 VSS18 DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54
DQ19 VSS19 DDR_A_D28
55 VSS20 DQ28 56
DDR_A_D24 57 58 DDR_A_D29
DDR_A_D25 DQ24 DQ29
59 DQ25 VSS21 60
61 62 DDR_A_DQS#3
VSS22 DQS#3 DDR_A_DQS3
63 DM3 DQS3 64
65 VSS23 VSS24 66
DDR_A_D26 67 68 DDR_A_D30
DDR_A_D27 DQ26 DQ30 DDR_A_D31
69 DQ27 DQ31 70
71 VSS25 VSS26 72 Layout Note: Place these 4 Caps near
Command and Control signals of JDIMM1
C C
DDRA_CKE0 73 74 DDRA_CKE1 +1.5V
6 DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 6
75 VDD1 VDD2 76
77 78 DDR_A_MA15
DDR_A_BS2 NC1 A15 DDR_A_MA14
6 DDR_A_BS2 79 BA2 A14 80

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
81 VDD3 VDD4 82

C110

C111

C112

C113
DDR_A_MA12 83 84 DDR_A_MA11 1 1 1 1
DDR_A_MA9 A12/BC# A11 DDR_A_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_A_MA8 89 90 DDR_A_MA6
DDR_A_MA5 A8 A6 DDR_A_MA4 2 2 2 2
91 A5 A4 92
93 VDD7 VDD8 94
DDR_A_MA3 95 96 DDR_A_MA2
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD9 VDD10 100
6 DDRA_CLK0 DDRA_CLK0 101 102 DDRA_CLK1
CK0 CK1 DDRA_CLK1 6
6 DDRA_CLK0# DDRA_CLK0# 103 104 DDRA_CLK1#
CK0# CK1# DDRA_CLK1# 6 +1.5V
105 VDD11 VDD12 106
DDR_A_MA10 107 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 6
6 DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# 6

1
111 VDD13 VDD14 112
6 DDR_A_WE# DDR_A_WE# 113 114 DDRA_SCS0# R83 Layout Note:
WE# S0# DDRA_SCS0# 6
6 DDR_A_CAS# DDR_A_CAS# 115 116 DDRA_ODT0 1K_0402_1%
CAS# ODT0 DDRA_ODT0 6 Place near JDIMM1.203,204
117 VDD15 VDD16 118
DDR_A_MA13 119 120 DDRA_ODT1
DDRA_ODT1 6

2
DDRA_SCS1# A13 ODT1
6 DDRA_SCS1# 121 S1# NC2 122
123 VDD17 VDD18 124
125 126 +VREF_CA +0.75VS
NCTEST VREF_CA
127 VSS27 VSS28 128

0.1U_0402_10V6K

2.2U_0402_6.3V6M
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
C108

C109
DDR_A_D33 131 132 DDR_A_D37 1 1
DQ33 DQ37
133 VSS29 VSS30 134

1U_0402_6.3V6K
C114

1U_0402_6.3V6K
C115

1U_0402_6.3V6K
C116

1U_0402_6.3V6K
C117
B DDR_A_DQS#4 R84 B
135 DQS#4 DM4 136
DDR_A_DQS4 137 138 1K_0402_1% 1 1 1 1
DQS4 VSS31 DDR_A_D38 2 2
139 140

2
DDR_A_D34 VSS32 DQ38 DDR_A_D39
141 DQ34 DQ39 142
DDR_A_D35 143 144
DQ35 VSS33 DDR_A_D44 2 2 2 2
145 VSS34 DQ44 146
DDR_A_D40 147 148 DDR_A_D45
DDR_A_D41 DQ40 DQ45
149 DQ41 VSS35 150
151 152 DDR_A_DQS#5
VSS36 DQS#5 DDR_A_DQS5
153 DM5 DQS5 154
155 VSS37 VSS38 156
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_A_D48 163 164 DDR_A_D52
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_A_DQS#6 169 170
DDR_A_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
175 DQ50 DQ55 176
DDR_A_D51 177 178
DQ51 VSS45 DDR_A_D60
179 VSS46 DQ60 180
DDR_A_D56 181 182 DDR_A_D61
DDR_A_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_A_DQS#7
VSS48 DQS#7 DDR_A_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_A_D58 191 192 DDR_A_D62
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
195 VSS51 VSS52 196
197 SA0 EVENT# 198
A PCH_SMBDATA A
+3VS 199 VDDSPD SDA 200 PCH_SMBDATA 11,13,39,41
2.2U_0402_6.3V6M

0.1U_0402_10V6K

201 202 PCH_SMBCLK


SA1 SCL PCH_SMBCLK 11,13,39,41
C119

1 1 203 VTT1 VTT2 204 +0.75VS


1

1
C153

10K_0402_5%
R85

10K_0402_5%
R86

205 206 0.65A@0.75V


G1 G2
2 2
TYCO_2-1932323-1_204P 9.2H Security Classification Compal Secret Data Compal Electronics, Inc.
2

CONN@
Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019G8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, February 13, 2012 Sheet 10 of 61
5 4 3 2 1
5 4 3 2 1

+1.5V
+1.5V +1.5V

3.56A

1
R87
6 DDR_B_DQS#[0..7]
+V_DDR_REFB 1K_0402_1%
JDIMM2
6 DDR_B_D[0..63]
1 2

2
VREF_DQ VSS1 DDR_B_D4
0.1U_0402_10V6K 3 VSS2 DQ4 4 6 DDR_B_DQS[0..7]
R88 DDR_B_D0 5 6 DDR_B_D5
DQ0 DQ5
2.2U_0402_6.3V6M

1 1 DDR_B_D1 7 8
DQ1 VSS3 6 DDR_B_MA[0..15]

1
C120

9 10 DDR_B_DQS#0
C121 VSS4 DQS#0 DDR_B_DQS0
11 DM0 DQS0 12
13 VSS5 VSS6 14
2 2 DDR_B_D2 DDR_B_D6
15 DQ2 DQ6 16
1K_0402_1%

D DDR_B_D3 DDR_B_D7 D
17 18
2

DQ3 DQ7
19 VSS7 VSS8 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
23 DQ9 DQ13 24
25 VSS9 VSS10 26
DDR_B_DQS#1 27 28
DDR_B_DQS1 DQS#1 DM1 DDR3_DRAMRST#
29 DQS1 RESET# 30 DDR3_DRAMRST# 6,10
31 VSS11 VSS12 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS13 VSS14 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
43 VSS15 VSS16 44 Layout Note: Place these 4 Caps near Layout Note:
DDR_B_DQS#2 45 46
DDR_B_DQS2 DQS#2 DM2 Command and Control signals of JDDRH Place near JDDRH
47 DQS2 VSS17 48
49 50 DDR_B_D22
DDR_B_D18 VSS18 DQ22 DDR_B_D23 +1.5V +1.5V
51 DQ18 DQ23 52
DDR_B_D19 53 54
DQ19 VSS19

330U_B2_2.5VM_R15M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
55 56 DDR_B_D28 @
VSS20 DQ28

C122
DDR_B_D24 57 58 DDR_B_D29 1
DQ24 DQ29

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C123

C124

C125

C126

C127

C128

C129

C130
DDR_B_D25 59 60 1 1 1 1 1 1 1 1
DQ25 VSS21

C131

C132

C133

C134
61 62 DDR_B_DQS#3 +
VSS22 DQS#3 1 1 1 1
63 64 DDR_B_DQS3
DM3 DQS3 @ @
65 VSS23 VSS24 66
DDR_B_D26 DDR_B_D30 2 2 2 2 2 2 2 2 2
67 DQ26 DQ30 68
DDR_B_D27 DDR_B_D31 2 2 2 2
69 DQ27 DQ31 70
71 VSS25 VSS26 72

6 DDRB_CKE0 DDRB_CKE0 73 74 DDRB_CKE1


C CKE0 CKE1 DDRB_CKE1 6 C
75 VDD1 VDD2 76
77 78 DDR_B_MA15
DDR_B_BS2 NC1 A15 DDR_B_MA14
6 DDR_B_BS2 79 BA2 A14 80
81 VDD3 VDD4 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86
87 VDD5 VDD6 88
DDR_B_MA8 89 90 DDR_B_MA6
DDR_B_MA5 A8 A6 DDR_B_MA4
91 A5 A4 92 Layout Note:
93 VDD7 VDD8 94 Place near JDDRH.203 and 204
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 100 +0.75VS
DDRB_CLK0 VDD9 VDD10 DDRB_CLK1
6 DDRB_CLK0 101 CK0 CK1 102 DDRB_CLK1 6
6 DDRB_CLK0# DDRB_CLK0# 103 104 DDRB_CLK1#
CK0# CK1# DDRB_CLK1# 6
105 VDD11 VDD12 106
DDR_B_MA10 107 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 6 +1.5V

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K

1U_0603_10V6K
6 DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS#
BA0 RAS# DDR_B_RAS# 6

C135

C136

C137

C138
111 VDD13 VDD14 112 1 1 1 1
6 DDR_B_WE# DDR_B_WE# 113 114 DDRB_SCS0#
WE# S0# DDRB_SCS0# 6

1
6 DDR_B_CAS# DDR_B_CAS# 115 116 DDRB_ODT0
CAS# ODT0 DDRB_ODT0 6
117 118 R89
DDR_B_MA13 VDD15 VDD16 DDRB_ODT1 1K_0402_1% 2 2 2 2
119 A13 ODT1 120 DDRB_ODT1 6
6 DDRB_SCS1# DDRB_SCS1# 121 122
S1# NC2
123 124

2
VDD17 VDD18 +VREF_CB
125 NCTEST VREF_CA 126
0.1U_0402_10V6K

127 VSS27 VSS28 128

2.2U_0402_6.3V6M
DDR_B_D32 129 130 DDR_B_D36
DQ32 DQ36
C139

DDR_B_D33 131 132 DDR_B_D37 1 1


DQ33 DQ37

1
C140
133 VSS29 VSS30 134
DDR_B_DQS#4 135 136 R90
DDR_B_DQS4 DQS#4 DM4 1K_0402_1%
137 DQS4 VSS31 138
B DDR_B_D38 2 2 B
139 VSS32 DQ38 140
DDR_B_D34 141 142 DDR_B_D39

2
DDR_B_D35 DQ34 DQ39
143 DQ35 VSS33 144
145 146 DDR_B_D44
DDR_B_D40 VSS34 DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS35 DDR_B_DQS#5
151 VSS36 DQS#5 152
153 154 DDR_B_DQS5
DM5 DQS5
155 VSS37 VSS38 156
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47
159 DQ43 DQ47 160
161 VSS39 VSS40 162
DDR_B_D48 163 164 DDR_B_D52
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 VSS41 VSS42 168
DDR_B_DQS#6 169 170
DDR_B_DQS6 DQS#6 DM6
171 DQS6 VSS43 172
173 174 DDR_B_D54
DDR_B_D50 VSS44 DQ54 DDR_B_D55
175 DQ50 DQ55 176
DDR_B_D51 177 178
DQ51 VSS45 DDR_B_D60
179 VSS46 DQ60 180
DDR_B_D56 181 182 DDR_B_D61
DDR_B_D57 DQ56 DQ61
183 DQ57 VSS47 184
185 186 DDR_B_DQS#7
VSS48 DQS#7 DDR_B_DQS7
187 DM7 DQS7 188
189 VSS49 VSS50 190
DDR_B_D58 191 192 DDR_B_D62
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
1 R91 2 195 VSS51 VSS52 196
10K_0402_5% 197 198
SA0 EVENT# PCH_SMBDATA
+3VS 199 VDDSPD SDA 200 PCH_SMBDATA 10,13,39,41
0.1U_0402_10V6K

201 202 PCH_SMBCLK


SA1 SCL PCH_SMBCLK 10,13,39,41
2.2U_0402_6.3V6M

C142

A A
1 1 1 2 203 VTT1 VTT2 204 +0.75VS
R92 10K_0402_5%
0.65A@0.75V
C141

205 G1 G2 206
2 2 TYCO_2-2013287-1_204P
CONN@ 5.2H
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 11 of 61
5 4 3 2 1
5 4 3 2 1

PCH_RTCX1 +3V_PCH

0.1U_0402_16V4Z~D
Please close to JXDP2
1 2 PCH_RTCX2 1
R93 10M_0402_5% C143 JXDP2
Y1 1
XDP@ 1
1 2 2 2
+RTCVCC 2
3 3
4 4
32.768KHZ_12.5PF_9H03200019 1 2 SM_INTRUDER# 5
R94 1M_0402_5% 5
6 6
7 7
1 1 8 8
1K_0402_5% 9
C144 C145 R95 XDP@2 RSMRST#_XDP 9
14,40 PCH_RSMRST# 1 10 10
18P_0402_50V8J 18P_0402_50V8J R96 1 XDP@ 2 PCH_PWRBTN#_XDP 11
2 2 14,40 PBTN_OUT# 11
D 0_0402_5% 12 D
12
13 13
+1.05VS R97 1 XDP@ 2 14
0_0402_5% 14
15 15
+3V_PCH R98 1 XDP@ 2 +3V_PCH_XDP 16
0_0402_5% 16
CLRP1 & CLRP2 place near DIMM XDP_DBRESET#_R
17
18
17
U3A 5,14 XDP_DBRESET#_R 18
19 19
far away hot spot PCH_JTAG_TDO 20
+RTCVCC PCH_RTCX1 LPC_AD0 20
1 A20 RTCX1 FWH0 / LAD0 C38 LPC_AD0 40,41 21 21

1
CMOS A38 LPC_AD1 PCH_JTAG_TDI 22
FWH1 / LAD1 LPC_AD1 40,41 22

LPC
C146 CLRP1 PCH_RTCX2 C20 B37 LPC_AD2 PCH_JTAG_TMS 23
RTCX2 FWH2 / LAD2 LPC_AD2 40,41 23
1U_0603_10V6K SHORT PADS C37 LPC_AD3 24
LPC_AD3 40,41

2
2 PCH_RTCRST# FWH3 / LAD3 24
1 2 D20 RTCRST# 25 25 G1 27
R99 20K_0402_5% D36 LPC_FRAME# PCH_JTAG_TCK 26 28
FWH4 / LFRAME# LPC_FRAME# 40,41 26 G2
1 2 PCH_SRTCRST# G22
R100 20K_0402_5% SRTCRST# LPC_LDRQ0# ACES_87152-26051
1 LDRQ0# E36 @ T12 PAD~D

RTC
SM_INTRUDER# K22 K36 LPC_LDRQ1# @ CONN@
INTRUDER# LDRQ1# / GPIO23 T13 PAD~D
C147 CLRP2
PR-7 1U_0603_10V6K SHORT PADS PCH_INTVRMEN C17 V5 SERIRQ SERIRQ 40

2
2 ME CMOS INTVRMEN SERIRQ
40 HDA_SDO 1 2 HDA_SDOUT
R101 0_0402_5% AM3 SATA_PRX_DTX_N0 31
HDA_BIT_CLK SATA0RXN
N34 HDA_BCLK SATA0RXP AM1 SATA_PRX_DTX_P0 31
HDA for AUDIO HDD1 +3VS

SATA 6G
SATA0TXN AP7 SATA_PTX_DRX_N0 31
HDA_SYNC L34 AP5
HDA_SYNC SATA0TXP SATA_PTX_DRX_P0 31
33 HDA_BITCLK_AUDIO 1 2 HDA_BIT_CLK
R102 33_0402_5% HDA_SPKR T10 AM10 SATA_PRX_DTX_N1 31 SERIRQ R103 2 1 10K_0402_5%
SPKR SATA1RXN
SATA1RXP AM8 SATA_PRX_DTX_P1 31
1 HDA_RST# K34 AP11 HDD2 +RTCVCC PCH_GPIO21 R104 2 1 10K_0402_5%
HDA_RST# SATA1TXN SATA_PTX_DRX_N1 31
@ C148 AP10
SATA1TXP SATA_PTX_DRX_P1 31
10P_0402_50V8J PCH_SATALED#R105 2 1 10K_0402_5%
HDA_SDIN0 E34 AD7 SATA_PRX_DTX_N2 31 PCH_INTVRMEN R106 2 1 330K_0402_5%
2 33 HDA_SDIN0 HDA_SDIN0 SATA2RXN
AD5 SATA_PRX_DTX_P2 31 BBS_BIT0_R R107 2 1 10K_0402_5%
SATA2RXP
Reserve for EMI G34 HDA_SDIN1 SATA2TXN AH5 SATA_PTX_DRX_N2 31 ODD
please close to RH170 SATA2TXP AH4 SATA_PTX_DRX_P2 31
C34 HDA_SDIN2
INTVRMEN

IHDA
C SATA3RXN AB8 C

33 HDA_RST_AUDIO# 1 2 HDA_RST# A34 HDA_SDIN3 SATA3RXP AB10


AF3
* H:Integrated
L:Integrated
VRM enable
VRM disable +3VS
R108 33_0402_5% SATA3TXN
HDA_SDOUT SATA3TXP AF1
33 HDA_SDOUT_AUDIO 1 2 HDA_SDOUT
R109 33_0402_5% A36 HDA_SDO HDA_SPKR R110 @ 1 1K_0402_5%

SATA
SATA4RXN Y7 2
SATA4RXP Y5
PCH_SPI_WP C36 HDA_DOCK_EN# / GPIO33 SATA4TXN
SATA4TXP
AD3
AD1 *LOW=Default
HIGH=No Reboot
N32 HDA_DOCK_RST# / GPIO13
SATA5RXN Y3
SATA5RXP Y1
SATA5TXN AB3
+3V_PCH +3V_PCH +3V_PCH PCH_JTAG_TCK J3 AB1
JTAG_TCK SATA5TXP
PCH_JTAG_TMS H7 Y11 +1.05VS_VCC_SATA
JTAG_TMS SATAICOMPO
1

JTAG
R111 R112 R113
PCH_JTAG_TDI K5 Y10 SATA_COMP 1 2
@ @ @ JTAG_TDI SATAICOMPI R114 37.4_0402_1%
200_0402_5% 200_0402_5% 200_0402_5%
PCH_JTAG_TDO H1 JTAG_TDO +1.05VS_SATA3
AB12
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI SATA3RCOMPO


AB13 SATA3_COMP 1 2
SATA3COMPI
1

R116 R117 R118 R115 49.9_0402_1%

100_0402_1% 100_0402_1% 100_0402_1% PCH_SPI_CLK_RR T3 AH1 RBIAS_SATA3 1 2


SPI_CLK SATA3RBIAS R120 750_0402_1%
PCH_SPI_CS#_RR Y14
2

SPI_CS0# R123
T1 2 1 FLASH_EN HDA_SYNC
SPI_CS1#
SPI

P3 PCH_SATALED#
SATALED# PCH_SATALED# 39
10K_0402_5% This signal has a weak internal pull-down
R124 2 1 PCH_JTAG_TCK PCH_SPI_SI_RR V4 V14 PCH_GPIO21 On Die PLL VR is supplied by
51_0402_5% SPI_MOSI SATA0GP / GPIO21
1.5V when smapled high
PCH_SPI_SO_RR U3 P1 BBS_BIT0_R
+5VS SPI_MISO SATA1GP / GPIO19 1.8V when sampled low
Needs to be pulled High for Chief River platfrom
B PANTHER-POINT_FCBGA989 B
Please place to close to U3 +3V_PCH
2
G

33 HDA_SYNC_AUDIO 1 2 3 1 HDA_SYNC HDA_SYNC R128 2 1 1K_0402_5%


R127 33_0402_5%
S

BSS138_SOT23
1

Q11
R129
1M_0402_5%

+3V_PCH
2

+3V_SPI
SPI ROM ( 4M/8MByte ) 1
U4
VDD FLASH_EN
4 VDD SEL 12 FLASH_EN 40
+3V_SPI 9 VDD
19 VDD YA 2 +3V_SPI
R132 1 2PCH_SPI_WP# 5 PCH_SPI_CS#_R
3.3K_0402_5% YB PCH_SPI_CLK PCH_SPI_CLK_R +RTCBATT
+3VS 24 A0 YC 6 1 2
0.1U_0402_16V4Z

R131 PCH_SPI_CS#_RR 22 0_0402_5%


R134 1 B0
2PCH_SPI_HOLD# PCH_SPI_CLK_RR 1 2 PCH_SPI_CLK_RRR 18 8 PCH_SPI_SI_R R133
1 C0 YD
RTC Battery

1
3.3K_0402_5% C150 0_0402_5% PCH_SPI_SI_RR 17 11 PCH_SPI_SO_R EMI
PCH_SPI_SO_RR D0 YE R136
EMI 14 E0
PCH_SPI_WP# 2
23 3
MAX. 8000mil 1K_0402_5%
+3VALW A1 GND
39,40 KSI4 KSI4 21 7 D1

2
@ U5 KSI5 B1 GND +RTCVCC
39,40 KSI5 16 C1 GND 10
PCH_SPI_WP 1 2 PCH_WP 8 4 39,40 KSI6 KSI6 15 20 2 W=20mils
VCC VSS D1 GND
1

R137 0_0402_5% Q63 D KSI7


39,40 KSI7 13 W=20mils 1
PCH_SPI_WP# E1
40 EC_SPI_WP 1 2 2 3 W 3 +CHGRTC
R135 0_0402_5% PI3V512QE_QSOP24

0.1U_0402_16V4Z
G W=20mils
S PCH_SPI_HOLD# 7 1
3

HOLD C154 DAN202UT106_SC70-3


2N7002KW 1N SOT323-3 PCH_SPI_CS#_R 1 S
C152 R139 PCH_SPI_CLK_R 2
A 6 C A
2 1 1 2PCH_SPI_CLK_RRR
@ 33_0402_5% @ PCH_SPI_SI_R 5 2 PCH_SPI_SO_R
22P_0402_50V8J D Q
Reserve for EMI please close to U4 W25Q32BVSSIG_SO8
W7@
U5

W8@
C155
R142
2
@
1 1 2PCH_SPI_CLK_R
0_0402_5% @
Security Classification Compal Secret Data Compal Electronics, Inc.
W25Q64FVSSIG_SO8 Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title
10P_0402_50V8J 8M ROM=SA000039A20
Reserve for EMI please close to U5 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 12 of 61
5 4 3 2 1
5 4 3 2 1

SMBALERT# 2 1 +3V_PCH
R149 10K_0402_5%
SMBCLK 1 2
R150 2.2K_0402_5%
SMBDATA 1 2
U3B R151 2.2K_0402_5%
SML0CLK 1 2
D PCIE_PRX_GLANTX_N1 BG34 R152 2.2K_0402_5% D
32 PCIE_PRX_GLANTX_N1 PERN1
32 PCIE_PRX_GLANTX_P1 PCIE_PRX_GLANTX_P1 BJ34 E12 SMBALERT# SML0DATA 1 2
PERP1 SMBALERT# / GPIO11 SMBALERT# 39
10/100/1G LAN ---> C158 1 2 0.1U_0402_16V7K PCIE_PTX_GLANRX_N1_C AV32 R153 2.2K_0402_5%
32 PCIE_PTX_GLANRX_N1 PETN1
C159 1 2 0.1U_0402_16V7K PCIE_PTX_GLANRX_P1_C AU32 H14 SMBCLK PCH_SMLCLK 1 2
32 PCIE_PTX_GLANRX_P1 PETP1 SMBCLK
MEMORY R154 2.2K_0402_5%
41 PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_N2 BE34 C9 SMBDATA PCH_SMLDATA 1 2
PCIE_PRX_WLANTX_P2 PERN2 SMBDATA R155 2.2K_0402_5%
41 PCIE_PRX_WLANTX_P2 BF34 PERP2
MiniWLAN (Mini Card 1)---> C160 1 2 0.1U_0402_16V7K PCIE_PTX_WLANRX_N2_C BB32
41 PCIE_PTX_WLANRX_N2 PETN2
C161 1 2 0.1U_0402_16V7K PCIE_PTX_WLANRX_P2_C AY32 PCH_HOT# 1 2
41 PCIE_PTX_WLANRX_P2 PETP2

SMBUS
A12 DRAMRST_CNTRL_PCH R156 10K_0402_5%
SML0ALERT# / GPIO60 DRAMRST_CNTRL_PCH 6,9,40
BG36 PERN3
BJ36 C8 SML0CLK DRAMRST_CNTRL_PCH 1 2
PERP3 SML0CLK R157 1K_0402_1%
AV34 PETN3
AU34 G12 SML0DATA
PETP3 SML0DATA
36 PCIE_PRX_USB3TX_N4 PCIE_PRX_USB3TX_N4 BF36
USB30@ PCIE_PRX_USB3TX_P4 PERN4 DRAMRST_CNTRL_PCH
36 PCIE_PRX_USB3TX_P4 BE36 PERP4 2 1
USB3.0 controller ---> C1043 1 2 0.1U_0402_16V7K PCIE_PTX_USB3RX_N4_C AY34 C13 PCH_HOT# R750 100K_0402_1%
36 PCIE_PTX_USB3RX_N4 PETN4 SML1ALERT# / PCHHOT# / GPIO74
C1044 1 2 0.1U_0402_16V7K PCIE_PTX_USB3RX_P4_C BB34 @
36 PCIE_PTX_USB3RX_P4 PETP4
USB30@ E14 PCH_SMLCLK PCH_SMLCLK 20,40
SML1CLK / GPIO58

PCI-E*
BG37 PERN5 PCH_SMLDATA
EC
BH37 PERP5 SML1DATA / GPIO75 M16 PCH_SMLDATA 20,40
AY36 PETN5
BB36 PETP5
BJ38 PERN6
BG38 PERP6

Controller
AU36 M7 @ T14 PAD CLKIN_DMI2# R158 1 2 10K_0402_5%
PETN6 CL_CLK1 CLKIN_DMI2 R159 10K_0402_5%
AV36 PETP6 1 2
CLKIN_DMI# R160 1 2 10K_0402_5%

Link
BG40 T11 @ T15 PAD CLKIN_DMI R161 1 2 10K_0402_5%
PERN7 CL_DATA1 CLKIN_DOT96# R162 10K_0402_5%
BJ40 PERP7 1 2
C AY40 CLKIN_DOT96 R163 1 2 10K_0402_5% C
PETN7 @ T16 PAD CLKIN_SATA# R164 10K_0402_5%
BB40 PETP7 CL_RST1# P10 1 2
CLKIN_SATA R165 1 2 10K_0402_5%
BE38 CLK_PCH_14M R166 1 2 10K_0402_5%
PERN8
BC38 PERP8
AW38 PETN8
AY38 If use extenal CLK gen, please place close to CLK gen
PETP8 else, please place close to PCH
M10 PEG_CLKREQ#_R
PEG_A_CLKRQ# / GPIO47 PEG_CLKREQ#_R 20
R167 1 2 0_0402_5% PCIE_LAN# Y40
32 CLK_PCIE_LAN# CLKOUT_PCIE0N
10/100/1G LAN ---> R168 1 2 0_0402_5% PCIE_LAN Y39
32 CLK_PCIE_LAN CLKOUT_PCIE0P
AB37 CLK_PCIE_VGA#
CLKOUT_PEG_A_N CLK_PCIE_VGA# 20
R169 1 2 10K_0402_5% LANCLK_REQ# CLK_PCIE_VGA

CLOCKS
+3V_PCH J2 PCIECLKRQ0# / GPIO73 CLKOUT_PEG_A_P AB38 CLK_PCIE_VGA 20 VGA
32 LANCLK_REQ#
R170 2 1 0_0402_5% PCIE_WLAN# AB49 AV22 CLK_CPU_DMI#
41 CLK_PCIE_WLAN# CLKOUT_PCIE1N CLKOUT_DMI_N CLK_CPU_DMI# 5 +3VS +3VS
R171 2 1 0_0402_5% PCIE_WLAN AB47 AU22 CLK_CPU_DMI
41 CLK_PCIE_WLAN CLKOUT_PCIE1P CLKOUT_DMI_P CLK_CPU_DMI 5
MiniWLAN (Mini Card 1)---> +3VS R172 2 1 10K_0402_5%
41 WLANCLK_REQ# WLANCLK_REQ# M1 PCIECLKRQ1# / GPIO18
CLKOUT_DP_N AM12
CLKOUT_DP_P AM13

2
AA48 CLKOUT_PCIE2N
AA47 R173 R174
CLKOUT_PCIE2P CLKIN_DMI#
CLKIN_DMI_N BF18 2.2K_0402_5% 2.2K_0402_5%
+3VS R175 1 2 10K_0402_5% V10 BE18 CLKIN_DMI
PCIECLKRQ2# / GPIO20 CLKIN_DMI_P

1
2
R1054 2 USB30@ 1 0_0402_5% PCIE_USB30# Y37 BJ30 CLKIN_DMI2#
36 CLK_PCIE_USB30# CLKOUT_PCIE3N CLKIN_GND1_N
R1055 2 USB30@ 1 0_0402_5% PCIE_USB30 Y36 BG30 CLKIN_DMI2 SMBCLK 6 1
36 CLK_PCIE_USB30 CLKOUT_PCIE3P CLKIN_GND1_P PCH_SMBCLK 10,11,39,41
USB3.0 controller --->
+3V_PCH R176 2 1 10K_0402_5% A8 2N7002KDWH_SOT363-6
PCIECLKRQ3# / GPIO25 CLKIN_DOT96#
36 CLKREQ_USB30# CLKIN_DOT_96N G24 Q2A
B E24 CLKIN_DOT96 B
CLKIN_DOT_96P
Y43 CLKOUT_PCIE4N

5
Y45 CLKOUT_PCIE4P
AK7 CLKIN_SATA#
R177 CLKIN_SATA_N
+3V_PCH 2 1 10K_0402_5% L12 PCIECLKRQ4# / GPIO26 CLKIN_SATA_P AK5 CLKIN_SATA SMBDATA 3 4 PCH_SMBDATA 10,11,39,41
2N7002KDWH_SOT363-6
V45 K45 CLK_PCH_14M Q2B
CLKOUT_PCIE5N REFCLK14IN
V46 CLKOUT_PCIE5P
+3V_PCH R178 2 1 10K_0402_5% L14 H45 CLK_PCI_LPBACK
PCIECLKRQ5# / GPIO44 CLKIN_PCILOOPBACK CLK_PCI_LPBACK 15

AB42 V47 XTAL25_IN


CLKOUT_PEG_B_N XTAL25_IN XTAL25_OUT
AB40 CLKOUT_PEG_B_P XTAL25_OUT V49
@ @
R180 C162 +3V_PCH R179 1 2 10K_0402_5% PEG_B_CLKREQ# E6
CLK_PCI_LPBACK2 PEG_B_CLKRQ# / GPIO56
1 1 2
33_0402_5% 22P_0402_50V8J Y47 XCLK_RCOMP 1 2 +1.05VS_VCCDIFFCLKN
XCLK_RCOMP R181 90.9_0402_1%
Reserve for EMI please close to V40 CLKOUT_PCIE6N
U3 V42 CLKOUT_PCIE6P
+3V_PCH R182 1 2 10K_0402_5% PCIE_CLKREQ6# T13 PCIECLKRQ6# / GPIO45
XTAL25_IN V38 K43 CLK_SD_48M_R 1 2 CLK_SD_48M
CLKOUT_PCIE7N CLKOUTFLEX0 / GPIO64 CLK_SD_48M 34
R185 0_0402_5%
FLEX CLOCKS

V37 CLKOUT_PCIE7P
2 1 XTAL25_OUT F47 @ T17 PAD
1M_0402_5% R183 R184 1 CLKOUTFLEX1 / GPIO65
+3V_PCH 2 10K_0402_5% GPIO46 K12 PCIECLKRQ7# / GPIO46
H47 @ T18 PAD
PAD T48 @ CLK_BCLK_ITP# CLKOUTFLEX2 / GPIO66
Y2 AK14 CLKOUT_ITPXDP_N
PAD T49 @ CLK_BCLK_ITP AK13 K49 @ T19 PAD
CLKOUT_ITPXDP_P CLKOUTFLEX3 / GPIO67
A 1 3 A
1 3 PANTHER-POINT_FCBGA989
GND GND
2 2 4 2
C164
C163 25MHZ_10PF_ 7V25000014 12P_0402_50V8J
12P_0402_50V8J
1 1 @ @

CLK_PCH_14M
R189 C165 Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 1 2 Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title
33_0402_5% 22P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 13 of 61
5 4 3 2 1
5 4 3 2 1

PCH_ENBKL
U3C 40 PCH_ENBKL
U3D

4 DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 BC24 BJ14 FDI_CTX_PRX_N0 FDI_CTX_PRX_N0 4 1 R190 2 J47 AP43


DMI_CTX_PRX_N1 DMI0RXN FDI_RXN0 FDI_CTX_PRX_N1 100K_0402_5% M45 L_BKLTEN SDVO_TVCLKINN
4 DMI_CTX_PRX_N1 BE20 DMI1RXN FDI_RXN1 AY14 FDI_CTX_PRX_N1 4 30 PCH_ENVDD L_VDD_EN SDVO_TVCLKINP AP45
4 DMI_CTX_PRX_N2 DMI_CTX_PRX_N2 BG18 BE14 FDI_CTX_PRX_N2 FDI_CTX_PRX_N2 4
DMI_CTX_PRX_N3 DMI2RXN FDI_RXN2 FDI_CTX_PRX_N3
4 DMI_CTX_PRX_N3 BG20 DMI3RXN FDI_RXN3 BH13 FDI_CTX_PRX_N3 4 30 PCH_INV_PWM P45 L_BKLTCTL SDVO_STALLN AM42
BC12 FDI_CTX_PRX_N4 FDI_CTX_PRX_N4 4 AM40
DMI_CTX_PRX_P0 FDI_RXN4 FDI_CTX_PRX_N5 SDVO_STALLP
4 DMI_CTX_PRX_P0 BE24 DMI0RXP FDI_RXN5 BJ12 FDI_CTX_PRX_N5 4 30 PCH_LCD_CLK T40 L_DDC_CLK
4 DMI_CTX_PRX_P1 DMI_CTX_PRX_P1 BC20 BG10 FDI_CTX_PRX_N6 FDI_CTX_PRX_N6 4 K47 AP39
DMI1RXP FDI_RXN6 30 PCH_LCD_DATA L_DDC_DATA SDVO_INTN
4 DMI_CTX_PRX_P2 DMI_CTX_PRX_P2 BJ18 BG9 FDI_CTX_PRX_N7 FDI_CTX_PRX_N7 4 AP40
DMI_CTX_PRX_P3 DMI2RXP FDI_RXN7 CTRL_CLK SDVO_INTP
D 4 DMI_CTX_PRX_P3 BJ20 DMI3RXP T45 L_CTRL_CLK
D
BG14 FDI_CTX_PRX_P0 FDI_CTX_PRX_P0 4 CTRL_DATA P39
DMI_CRX_PTX_N0 FDI_RXP0 FDI_CTX_PRX_P1 L_CTRL_DATA
4 DMI_CRX_PTX_N0 AW24 DMI0TXN FDI_RXP1 BB14 FDI_CTX_PRX_P1 4
DMI_CRX_PTX_N1 AW20 BF14 FDI_CTX_PRX_P2 FDI_CTX_PRX_P2 4 2 1 LVDS_IBG AF37 P38 HDMICLK_NB
4 DMI_CRX_PTX_N1 DMI1TXN FDI_RXP2 LVD_IBG SDVO_CTRLCLK HDMICLK_NB 35
DMI_CRX_PTX_N2 BB18 BG13 FDI_CTX_PRX_P3 FDI_CTX_PRX_P3 4 R191 2.37K_0402_1%~D AF36 M39 HDMIDAT_NB
4 DMI_CRX_PTX_N2 DMI2TXN FDI_RXP3 LVD_VBG SDVO_CTRLDATA HDMIDAT_NB 35
DMI_CRX_PTX_N3 AV18 BE12 FDI_CTX_PRX_P4 FDI_CTX_PRX_P4 4 T20
4 DMI_CRX_PTX_N3 DMI3TXN FDI_RXP4

DMI
FDI
BG12 FDI_CTX_PRX_P5 FDI_CTX_PRX_P5 4 PAD~D AE48
DMI_CRX_PTX_P0 FDI_RXP5 FDI_CTX_PRX_P6 LVD_VREFH
4 DMI_CRX_PTX_P0 AY24 DMI0TXP FDI_RXP6 BJ10 FDI_CTX_PRX_P6 4 AE47 LVD_VREFL DDPB_AUXN AT49
DMI_CRX_PTX_P1 AY20 BH9 FDI_CTX_PRX_P7 FDI_CTX_PRX_P7 4 AT47
4 DMI_CRX_PTX_P1 DMI1TXP FDI_RXP7 DDPB_AUXP
DMI_CRX_PTX_P2 AY18 AT40 TMDS_B_HPD
4 DMI_CRX_PTX_P2 DMI2TXP DDPB_HPD TMDS_B_HPD 35
DMI_CRX_PTX_P3 AU18 PCH_TXCLK- AK39
4 DMI_CRX_PTX_P3 DMI3TXP 30 PCH_TXCLK- LVDSA_CLK#

LVDS
AW16 FDI_INT PCH_TXCLK+ AK40 AV42 TMDS_B_DATA2#
FDI_INT FDI_INT 4 30 PCH_TXCLK+ LVDSA_CLK DDPB_0N TMDS_B_DATA2# 35
DDPB_0P AV40 TMDS_B_DATA2 TMDS_B_DATA2 35
+1.05VS_VCC_EXP BJ24 AV12 FDI_FSYNC0 PCH_TXOUT0- AN48 AV45 TMDS_B_DATA1#
DMI_ZCOMP FDI_FSYNC0 FDI_FSYNC0 4 30 PCH_TXOUT0- LVDSA_DATA#0 DDPB_1N TMDS_B_DATA1# 35
PCH_TXOUT1- AM47 AV46 TMDS_B_DATA1
30 PCH_TXOUT1- TMDS_B_DATA1 35

Digital Display Interface


DMI_IRCOMP FDI_FSYNC1 PCH_TXOUT2- LVDSA_DATA#1 DDPB_1P
1 2 BG25 DMI_IRCOMP FDI_FSYNC1 BC10 FDI_FSYNC1 4 30 PCH_TXOUT2- AK47 LVDSA_DATA#2 DDPB_2N AU48 TMDS_B_DATA0# TMDS_B_DATA0# 35
R192 49.9_0402_1% AJ48 LVDSA_DATA#3 DDPB_2P AU47 TMDS_B_DATA0 TMDS_B_DATA0 35
1 2 RBIAS_CPY BH21 AV14 FDI_LSYNC0 AV47 TMDS_B_CLK#
DMI2RBIAS FDI_LSYNC0 FDI_LSYNC0 4 DDPB_3N TMDS_B_CLK# 35
R193 750_0402_1% PCH_TXOUT0+ AN47 AV49 TMDS_B_CLK
30 PCH_TXOUT0+ LVDSA_DATA0 DDPB_3P TMDS_B_CLK 35
4mil width and place BB10 FDI_LSYNC1 PCH_TXOUT1+ AM49
FDI_LSYNC1 FDI_LSYNC1 4 30 PCH_TXOUT1+ LVDSA_DATA1
PCH_TXOUT2+ AK49
within 500mil of the PCH 30 PCH_TXOUT2+
AJ47
LVDSA_DATA2
P46
LVDSA_DATA3 DDPC_CTRLCLK
DDPC_CTRLDATA P42
A18 DSWODVREN
DSWVRMEN PCH_TZCLK-
30 PCH_TZCLK- AF40 LVDSB_CLK#
R800 1 @ 2 0_0402_5% PCH_DPWROK PCH_TZCLK+

System Power Management


PCH_DPWROK 40 30 PCH_TZCLK+ AF39 LVDSB_CLK DDPC_AUXN AP47
40 SUSACK# R802 1 @ 2 SUSACK#_R C12 E22 PCH_DPWROK_R AP49
0_0402_5% SUSACK# DPWROK R194 1 DDPC_AUXP
2 0_0402_5% PCH_RSMRST#_R 30 PCH_TZOUT0-
PCH_TZOUT0- AH45 LVDSB_DATA#0 DDPC_HPD AT38
PCH_TZOUT1- AH47
30 PCH_TZOUT1- LVDSB_DATA#1
5,12 XDP_DBRESET#_R XDP_DBRESET#_R K3 B9 WAKE# 1 R195 2 PCIE_WAKE# 32,36,41 PCH_TZOUT2- AF49 AY47
SYS_RESET# WAKE# 30 PCH_TZOUT2- LVDSB_DATA#2 DDPC_0N
0_0402_5% AF45 AY49
PR-7 PR-7 LVDSB_DATA#3 DDPC_0P
DDPC_1N AY43
SYSTEM_PWROK 1 2 SYSTEM_PWROK_I P12 N3 PM_CLKRUN# 1 R267 2 PM_CLKRUNEC# 40 PCH_TZOUT0+ AH43 AY45
SYS_PWROK CLKRUN# / GPIO32 30 PCH_TZOUT0+ LVDSB_DATA0 DDPC_1P
R196 0_0402_5% @ 0_0402_5% PCH_TZOUT1+ AH49 BA47
30 PCH_TZOUT1+ LVDSB_DATA1 DDPC_2N
PCH_TZOUT2+ AF47 BA48
C 30 PCH_TZOUT2+ LVDSB_DATA2 DDPC_2P C
40 PCH_PWROK 1 2 PM_PWROK_R L22 G8 SUS_STAT# T22 PAD AF43 BB47
R197 0_0402_5% PWROK SUS_STAT# / GPIO61 LVDSB_DATA3 DDPC_3N
DDPC_3P BB49
PR-7 R198 1 2 0_0402_5% L10 N14 SUSCLK 2 R199 1
APWROK SUSCLK / GPIO62 SUSCLK_R 40
0_0402_5% PCH_CRT_BLU N48 M43
30 PCH_CRT_BLU CRT_BLUE DDPD_CTRLCLK
PCH_CRT_GRN P49 M36
30 PCH_CRT_GRN CRT_GREEN DDPD_CTRLDATA
PM_DRAM_PWRGD B13 D10 PM_SLP_S5# PCH_CRT_RED T49
5 PM_DRAM_PWRGD DRAMPWROK SLP_S5# / GPIO63 PM_SLP_S5# 40 30 PCH_CRT_RED CRT_RED
PR-7 AT45
DDPD_AUXN

CRT
12,40 PCH_RSMRST# 1 2 PCH_RSMRST#_R C21 H4 PM_SLP_S4# PCH_CRT_DDC_CLK T39 AT43
RSMRST# SLP_S4# PM_SLP_S4# 40 30 PCH_CRT_DDC_CLK CRT_DDC_CLK DDPD_AUXP
R200 0_0402_5% PCH_CRT_DDC_DAT M40 BH41
30 PCH_CRT_DDC_DAT CRT_DDC_DATA DDPD_HPD
R801 1 @ 2 SUSWARN#_R K16 F4 PM_SLP_S3# R201 33_0402_5% BB43
40 SUSWARN# SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# PM_SLP_S3# 40 DDPD_0N
0_0402_5% 30 PCH_CRT_HSYNC 1 2 HSYNC_PCH M47 BB45
CRT_HSYNC DDPD_0P
PR-7
30 PCH_CRT_VSYNC 1 2 VSYNC_PCH M49 CRT_VSYNC DDPD_1N BF44
12,40 PBTN_OUT# 1 2 PBTN_OUT#_R E20 G10 T23 PAD R202 33_0402_5% BE44
R203 0_0402_5% PWRBTN# SLP_A# DDPD_1P
DDPD_2N BF42
D2 CRT_IREF T43 BE42
AC_PRESENT_R T24 PAD DAC_IREF DDPD_2P
40,44 ACIN 1 2 H20 ACPRESENT / GPIO31 SLP_SUS# G16 T42 CRT_IRTN DDPD_3N BJ42
@ BG42
DDPD_3P

1
RB751V-40_SOD323-2
PCH_GPIO72 E10 AP14 H_PM_SYNC PANTHER-POINT_FCBGA989
BATLOW# / GPIO72 PMSYNCH H_PM_SYNC 5
Reserve 40 AC_PRESENT R751 1 2 0_0402_5% R204
1K_0402_0.5%
RI# A10 K14 PCH_GPIO29 T25 PAD

2
PR-7 RI# SLP_LAN# / GPIO29

PANTHER-POINT_FCBGA989

@ 1 2 XDP_DBRESET#_R
C166 100P_0402_50V8J

B +3VS B

Reserve for EMI please close to U3


1 2 PCH_CRT_DDC_CLK
R206 2.2K_0402_5%
1 2 PCH_CRT_DDC_DAT
R207 2.2K_0402_5%
+3VS 1 2 CTRL_CLK
R208 2.2K_0402_5%
5

PR-7 U7 1 2 CTRL_DATA +3VS


1 2 2 +RTCVCC R209 2.2K_0402_5%
P

50 VGATE
R210 0_0402_5% B 4 SYSTEM_PWROK R211 1 2 2.2K_0402_5% PCH_LCD_CLK
Y SYSTEM_PWROK 5
PCH_PWROK 1 A R212 1 2 2.2K_0402_5% PCH_LCD_DATA
G

DSWODVREN R213 2 1 330K_0402_5%


NC7SZ08P5X_NL_SC70-5
3

DSWODVREN R214 2 @ 1 330K_0402_5%

+3V_PCH DSWODVREN - On Die DSW VR Enable


* H:Enable
L:Disable 1 2 PCH_CRT_BLU
PCH_GPIO29 R230 1 2 10K_0402_5% R215 150_0402_1%~D
1 2 PCH_CRT_GRN
R216 150_0402_1%~D
PCH_GPIO72 R217 1 2 10K_0402_5% 1 2 PCH_CRT_RED
R218 150_0402_1%~D
RI# R219 1 2 10K_0402_5% 1 2 PCH_ENVDD
R220 @ 100K_0402_5%~D
WAKE# R221 1 2 10K_0402_5% +3VS

AC_PRESENT_R R222 1 2 200K_0402_5%


1

SUSWARN#_R R223 1 2 10K_0402_5%


R224
@ 8.2K_0402_5%
A A
PCH_DPWROK R803 2 @ 1 100K_0402_5%
2

PCH_RSMRST# R225 1 2 10K_0402_5% PM_CLKRUN#


2

R130
PM_PWROK_R 2 1 10K_0402_5%

SYSTEM_PWROK_I
R226 10K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
2 1 Issued Date 2011/10/19 Deciphered Date 2012/12/31 Title
1

@ R227 100K_0402_5% Intel CRB EMRLDLKE2 Rev1.0


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC A8222
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 14 of 61
5 4 3 2 1
5 4 3 2 1

U3E

RSVD1 AY7
RSVD2 AV7
BG26 TP1 RSVD3 AU3
BJ26 TP2 RSVD4 BG4
BH25
BJ16
TP3
AT10
GPIO19 => BBS_BIT0
TP4 RSVD5
BG16
AH38
TP5 RSVD6 BC8 GPIO51 => BBS_BIT1
TP6
AH37 TP7 RSVD7 AU2 Boot BIOS Strap
AK43 TP8 RSVD8 AT4
AK45 TP9 RSVD9 AT3 BBS_BIT0 BBS_BIT1 Boot BIOS
C18 AT1
N30
TP10 RSVD10
AY3
Location
TP11 RSVD11
D
H3 TP12 RSVD12 AT5 0 0 LPC D
AH12 TP13 RSVD13 AV3
AM4 TP14 RSVD14 AV1 0 1 Reserved(NAND)
AM5 TP15 RSVD15 BB1
Y13 TP16 RSVD16 BA3 Panther Point USB Port Mapping 1 0 Reserved
K24 TP17 RSVD17 BB5
L24 TP18 RSVD18 BB3 1 1 SPI *
AB46 TP19 RSVD19 BB7
AB45 TP20 RSVD20 BE8 USB 2.0 Port Number USB 3.0 Port Number

RSVD
RSVD21 BD4
RSVD22 BF6
0 1
B21 AV5 NV_ALE
TP21 RSVD23
M20 TP22 RSVD24 AV10
AY16 TP23 1 2 Intel Anti-Theft Techonlogy
BG46 TP24 RSVD25 AT8
High=Endabled
RSVD26 AY5 2 3 NV_ALE
BA2 Low=Disable(floating)
37 USB3_RX1_N BE28 USB3Rn1
RSVD27 *
37 USB3_RX2_N BC30 USB3Rn2 RSVD28 AT12 3 4 +1.8VS
BE32 USB3Rn3 RSVD29 BF3
BJ32 USB3Rn4
37 USB3_RX1_P BC28 NV_ALE @ R228 1 2 1K_0402_5%
USB3Rp1
37 USB3_RX2_P BE30 USB3Rp2
BF32 USB3Rp3
BG32 C24 USB20_N0
USB3Rp4 USBP0N USB20_N0 37
AV26 A24 USB20_P0 USB2/3 port 1
37 USB3_TX1_N USB3Tn1 USBP0P USB20_P0 37
BB26 C25 USB20_N1
37 USB3_TX2_N USB3Tn2 USBP1N USB20_N1 37
AU28 B25 USB20_P1 USB2/3 port 2
USB3Tn3 USBP1P USB20_P1 37
AY30 C26 USB20_N2
USB3Tn4 USBP2N USB20_N2 33
AU26 A26 USB20_P2 USB2 Conn. R
37 USB3_TX1_P USB3Tp1 USBP2P USB20_P2 33
AY26 K28 USB20_N3
C 37 USB3_TX2_P USB3Tp2 USBP3N USB20_N3 30 C
AV28 H28 USB20_P3 Camera
USB3Tp3 USBP3P USB20_P3 30
AW30 E28 USB20_N4 USB20_N4 34
USB3Tp4 USBP4N USB20_P4
USBP4P D28
USB20_N5
USB20_P4 34 Card Reader
USBP5N C28 USB20_N5 33
A28 USB20_P5 USB20_P5 33 USB2 Conn. R
USBP5P
USBP6N C29
USBP6P B29
PCI_PIRQA# K40 N28 HM76 not Support USB Port6,7 +3V_PCH
PCI_PIRQB# PIRQA# USBP7N
K38 PIRQB# USBP7P M28

PCI
PCI_PIRQC# H38 L30
PCI_PIRQD# PIRQC# USBP8N USB_OC0# 10K_0402_5% R76
G38 PIRQD# USBP8P K30
USB_OC2# 10K_0402_5%
1 2
R229
Over Current Pin Default Usage
USBP9N G30 1 2
DGPU_HOLD_RST# C46 E30 USB_OC7# 10K_0402_5% 1 2 R582
REQ1# / GPIO50 USBP9P

USB
PCH_GPIO52 C44 C30 USB20_N10 USB_OC5# 10K_0402_5% 1 2 R725
REQ2# / GPIO52 USBP10N USB20_N10 41
29,53 DGPU_PWR_EN
DGPU_PWR_EN E40 A30 USB20_P10
USB20_P10 41 Mini Card(WLAN) Bluetooth OC Pin PCH Mapping
REQ3# / GPIO54 USBP10P
USBP11N L32
D47 GNT1# / GPIO51 USBP11P K32
E42 GNT2# / GPIO53 USBP12N G32 0 Port 0 & 1
41 PCH_WAN_RADIO_OFF# PCH_WAN_RADIO_OFF# F46 E32 USB_OC1# 10K_0402_5% 1 2 R780
GNT3# / GPIO55 USBP12P USB_OC4# 10K_0402_5% R781
USBP13N C32 1 2
USBP13P A32 USB_OC3# 10K_0402_5% 1 2 R782 1 Port 2 & 3
C167 PCH_GPIO2 G42 USB_OC6# 10K_0402_5% 1 2 R783
@ ODD_DA# ODD_DA# PIRQE# / GPIO2
1 2 31 ODD_DA# G40 PIRQF# / GPIO3 Within 500 mils
0.1U_0402_16V4Z~D PCH_GPIO4 C42 PIRQG# / GPIO4 USBRBIAS# C33 USBRBIAS 1 2 2 Port 4 & 5
PCH_GPIO5 D44 R231 22.6_0402_1%
PIRQH# / GPIO5
Reserve for EMI please close to U3
USBRBIAS B33 3 Port 6 & 7
PAD T26 @ K10 PME#
PCH_PLTRST# C6 PLTRST# OC0# / GPIO59 A14 USB_OC0#
USB_OC0# 37 (For USB Port0, 1) 4 Port 8 & 9
K20 USB_OC1# (For USB Port2)
OC1# / GPIO40 USB_OC1# 37
B17 USB_OC2# (For USB Port5)
OC2# / GPIO41 USB_OC2# 37
B
13 CLK_PCI_LPBACK
CLK_PCI_LPBACK R232 2 1 22_0402_5% CLK_PCI0 H49 CLKOUT_PCI0 OC3# / GPIO42 C16 USB_OC3# 5 Port 10 & 11 B
CLK_PCI_LPC R233 1 2 22_0402_5% CLK_PCI1 H43 L16 USB_OC4#
40 CLK_PCI_LPC CLKOUT_PCI1 OC4# / GPIO43
CLK_LPC_DEBUG1 R234 1 2 22_0402_5% CLK_PCI3 J48 A16 USB_OC5#
41 CLK_LPC_DEBUG1 CLKOUT_PCI2 OC5# / GPIO9
K42 CLKOUT_PCI3 OC6# / GPIO10 D14 USB_OC6# 6 Port 12 & 13
PR-8 @ H40 C14 USB_OC7#
CLKOUT_PCI4 OC7# / GPIO14
+3V_PCH +3VS
PANTHER-POINT_FCBGA989

1
R445 R444
0_0402_5% @ 0_0402_5%
1 @ 2
+3VS R236 0_0402_5%
2

2
PCH_GPIO4 8.2K_0402_5% 1 2 R784 +3VS PR-8 +3VS
PCI_PIRQB# 8.2K_0402_5% 1 2 R785
2

PCI_PIRQD# 8.2K_0402_5% 1 2 R786 @ C168 C169 DIS@


PCI_PIRQC# 8.2K_0402_5% 1 2 R787 R238 1 2 1 2
10K_0402_5% 0.1U_0402_16V4Z~D 0.1U_0402_16V4Z~D
5

5
U8 U9
DIS@ PCH_PLTRST#
B 2

P
VCC
1

1 PCH_PLTRST# 2 1 R240 4
IN1 20 DGPU_RST# Y
PCH_WAN_RADIO_OFF# 8.2K_0402_5% 1 2 R788 4 100_0402_5% 1 DGPU_HOLD_RST#
5,32,36,40,41 PLT_RST# OUT A

G
PCI_PIRQA# 8.2K_0402_5% 1 2 R789 2
GND

IN2

1
ODD_DA# 8.2K_0402_5% 1 2 R790 DIS@ NC7SZ08P5X_NL_SC70-5

3
PCH_GPIO5 8.2K_0402_5% 1 2 R791 R241
100K_0402_5%
3

MC74VHC1G08DFT2G_SC70-5 DIS@

2
PCH_GPIO52 8.2K_0402_5% 1 2 R792
A PCH_GPIO2 8.2K_0402_5% 1 2 R793 A
1 @ 2
DGPU_HOLD_RST# 1 R244 2 10K_0402_5% R235 0_0402_5%
@
1 R443 2 10K_0402_5%
1

DGPU_PWR_EN
Security Classification Compal Secret Data Compal Electronics, Inc.
1 R288 2 10K_0402_5% R243
Issued Date 2011/08/23 Deciphered Date 2012/12/31 Title
@ 100K_0402_5%
SCHEMATIC A8222
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019G8
Date: Monday, February 13, 2012 Sheet 15 of 61
5 4 3 2 1
5 4 3 2 1

+3VS

CRT_DET 1 @ 2 10K_0402_5%
R245 U3F
ODD_DETECT# 1 2 200K_0402_5%
R246 CRT_DET T7 C40 ODD_EN#
BMBUSY# / GPIO0 TACH4 / GPIO68 ODD_EN# 31
PCH_GPIO16 1 2 10K_0402_5% DMI Termination Voltage
R247 PCH_GPIO1 A42 B41 PCH_GPIO69 @ T27 PAD
PCH_BT_ON TACH1 / GPIO1 TACH5 / GPIO69
1 2 10K_0402_5% Set to Vcc when HIGH
R248 USB30_SMI# H36 C41 GPIO70 @ T28 PAD +3VS NV_CLE
KB_RST# 36 USB30_SMI# TACH2 / GPIO6 TACH6 / GPIO70
1 2 10K_0402_5% Set to Vss when LOW
R249 40 EC_SCI# EC_SCI# E38 A40 GPIO71 @ T29 PAD
TACH3 / GPIO7 TACH7 / GPIO71

2
D PCH_GPIO48 1 2 10K_0402_5% D
R250 EC_SMI# C10 R251 +1.8VS
40 EC_SMI# GPIO8
PCH_GPIO22 1 @ 2 10K_0402_5% 10K_0402_5%
R252 C4 LAN_PHY_PWR_CTRL / GPIO12

1
ODD_EN# 1 2 10K_0402_5%

1
R253 EC_LID_OUT# 1 2 PCH_LID_SW_IN# G2 P4 GATEA20
40 EC_LID_OUT# GPIO15 A20GATE GATEA20 40
DGPU_PWROK 1 2 10K_0402_5% 0_0402_5% R579