8 Channel Capacitive Touch Sensor CAP1088

CAP1088
8 Channel Capacitive
Touch Sensor with 8
LED Drivers
PRODUCT FEATURES Datasheet
General Description Applications

The CAP1088 is a multiple channel Capacitive Touch Desktop and Notebook PC’s
sensor with multiple power LED drivers. It contains eight LCD Monitors
(8) individual Capacitive Touch sensor inputs with Printers
programmable sensitivity for use in touch sensor Appliances
applications. Each sensor automatically recalibrates to
compensate for gradual environmental changes. Features
Eight (8) Capacitive Touch Sensor Inputs
The CAP1088 also contains eight (8) LED drivers that — Programmable sensitivity
offer full-on / off, variable rate blinking, dimness controls, — Automatic recalibration
and breathing. Each of the LED drivers may be linked to — Individual thresholds for each button
one of the sensors to be actuated when a touch is Flexible Capacitive Touch Sense algorithm
detected. As well, each LED driver may be individually Multiple Communication interfaces
controlled via a host controller. — SMBus / I2C compliant interface
— SMSC BC-Link interface
The CAP1088 offers multiple power states operating at — SPI communications
low quiescent currents. — Pin selectable communications protocol and multiple
slave addresses (SMBus / I2C only)
During the Standby mode of operation, one or more Low Power operation
Capacitive Touch Sensors are active and all LEDs may — 5 uA quiescent current in Deep Sleep
be used. If a touch is detected, then it will wake the — Samples one or more channels in Standby
system using the WAKE/SPI_MOSI pin. Eight (8) LED Driver Outputs
— Open Drain or Push-Pull
The Deep Sleep mode of operation is the lowest power — Programmable blink, breathe, and dimness controls
state available drawing 5 uA of current. During this — Can be linked to Capacitive Touch Sensors
mode, no sensors are active though all LEDs may be Dedicated Wake output flags touches in low power
u s e d . D r i v i n g t h e WA K E / S P I _ M O S I p i n o r mode
communications will wake the device. System RESET pin
Available in 24-pin 4mm x 4mm RoHS compliant
QFN package
Block Diagram
LED1 LED2 LED3 LED4 RESET VDD GND WAKE / SPI_MOSI

SPI_CS#
SMCLK / BC_CLK /
SMBus / SPI_CLK
BC-Link SMDATA / BC_DATA /
LED Driver, Breathe, or SPI
Capacitive Sensing Algorithm SPI_MSIO / SPI_MISO
and Dimness control Slave
Protocol ALERT# / BC_IRQ#
ADDR_COMM
LED5 LED6 LED7 LED8 CS1 CS2 CS3 CS4 CS5 CS6 CS7 CS8
Note: I2C is a trademark of NXP semiconductor. BC-Link is a trademark of SMSC.
SMSC CAP1088 DATASHEET Revision 1.0 (06-16-09)

8 Channel Capacitive Touch Sensor with 8 LED Drivers
Datasheet
ORDERING INFORMATION
ORDERING NUMBER PACKAGE FEATURES
CAP1088-1-CP-TR 24-pin QFN 4mm x 4mm Eight Capacitive Touch Sensors, Eight
(Lead Free RoHS compliant) LED drivers, Dedicated Wake, Reset,
SMBus / BC-Link / SPI interfaces
REEL SIZE IS 4,000 PIECES
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
Copyright © 2009 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.0 (06-16-09) 2 SMSC CAP1088

DATASHEET
Datasheet
Table of Contents
Chapter 1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 3 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.1 SMBus (I2C) Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2 SPI Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.3 BC-Link Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 System Management Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.3 SMBus Data Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.4 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.5 SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.6 SMBus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.7 SMBus and I2C Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1 SMBus Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.2 Block Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.3 SMBus Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.4 Block Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.5 SMBus Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.6 SMBus Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.1 SPI Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4.2 SPI Bi-Directional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.3 SPI_CS# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.4 Address Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.5 SPI Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5 Normal SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.1 Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.2 Set Address Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.3 Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.4 Read Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 Bi-Directional SPI Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6.1 Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6.2 Set Address Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6.3 Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6.4 Read Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7 BC-Link Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1 Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 WAKE/SPI_MOSI Pin Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4 LED Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4.1 Linking LEDs to Capacitive Touch Sensors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5 Capacitive Touch Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5.1 Sensing Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5.2 Recalibrating Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SMSC CAP1088 3 Revision 1.0 (06-16-09)

DATASHEET
Datasheet
4.6 ALERT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.6.1 Sensor Interrupt Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Chapter 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.1 Main Status Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.1 Sensor Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.2 LED Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3 Noise Flag Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.4 Sensor Delta Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.5 Sensitivity Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.6 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.7 Sensor Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.8 Sensor Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.9 Sensor Configuration 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.10 Averaging and Sampling Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.11 Calibration Activate Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.12 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.13 Repeat Rate Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.14 Multiple Touch Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.15 Recalibration Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.16 Sensor Threshold Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.17 Sensor Noise Threshold Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.17.1 Sensor Noise Threshold 1 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.17.2 Sensor Noise Threshold 2 Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.18 Standby Channel Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.19 Standby Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.20 Standby Sensitivity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.21 Standby Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.22 Sensor Base Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.23 LED Output Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.24 Sensor LED Linking Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.25 LED Polarity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.26 LED Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.27 LED Behavior Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.27.1 LED Behavior 1 - 81h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.27.2 LED Behavior 2 - 82h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.28 LED Pulse 1 Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.29 LED Pulse 2 Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.30 LED Breathe Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.31 LED Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.32 LED Duty Cycle Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.33 LED Direct Ramp Rates Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.34 LED Off Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5.35 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.36 Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
5.37 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Chapter 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

6.1 CAP1088 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.2 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Chapter 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

DATASHEET
Datasheet
List of Figures
Figure 1.1 CAP1088 Pin Diagram (24-Pin QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3.1 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3.1 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3.1 Example SPI Bus Communication - Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3.2 SPI Reset Interface Command - Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3.3 SPI Set Address Pointer Command - Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 3.4 SPI Write Command - Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3.5 SPI Read Command - Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3.6 SPI Read Command - Normal Mode - Full . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3.7 SPI Reset Interface Command - Bi-directional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3.8 SPI Set Address Pointer Command - Bi-directional Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3.9 SPI Write Data Command - Bi-directional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 3.10 SPI Read Data Command - Bi-directional Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4.1 System Diagram for CAP1088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4.2 Sensor Interrupt Behavior - Repeat Rate Enabled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 4.3 Sensor Interrupt Behavior - No Repeat Rate Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 5.1 Pulse Behavior with Non-Inverted Polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 5.2 Pulse Behavior with Inverted Polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 5.3 Pulse 2 Behavior with Non-Inverted Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 5.4 Pulse 2 Behavior with Inverted Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 5.5 Direct Mode Behavior for Non-Inverted Polarity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 5.6 Direct Mode Behavior for Inverted Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 6.1 CAP1088 Package Drawing - 24-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 6.2 CAP1088 Package Dimensions - 24-Pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 6.3 CAP1088 PCB Footprint - 24-pin QFN 4mm x 4mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 6.4 CAP1088 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

DATASHEET
Datasheet
List of Tables
Table 1.1 Pin Description for CAP1088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 1.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3.1 ADDR_COMM Pin Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3.2 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3.3 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3.4 Block Write Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3.5 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3.6 Block Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3.7 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3.8 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5.1 Register Set in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 5.2 Main Status Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 5.3 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 5.4 Noise Flag Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5.5 Sensor Delta Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 5.6 Data Scaling Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.7 DELTA_SENSE Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 5.8 BASE_SHIFT Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 5.9 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 5.10 Sensor Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5.11 Sensor Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5.12 MAX_DUR Bit Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 5.13 RPT_RATE Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 5.14 Sensor Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 5.15 Averaging and Sampling Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 5.16 AVG Bit Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 5.17 CYCLE_TIME Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5.18 Calibration Activate Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 5.19 Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5.20 Repeat Rate Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5.21 Multiple Touch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 5.22 B_MULT_T Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 5.23 Recalibration Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 5.24 NEG_DELTA_CNT Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 5.25 CAL_CFG Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 5.26 Sensor Threshold Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 5.27 Sensor Noise Threshold Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 5.28 CSx_BN_TH Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 5.29 Standby Channel Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 5.30 Standby Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 5.31 STBY_AVG Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 5.32 STBY_CY_TIME Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 5.33 Standby Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5.34 STBY_SENSE Bit Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5.35 Standby Threshold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 5.36 Sensor Base Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 5.37 LED Output Type Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 5.38 Sensor LED Linking Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 5.39 LED Polarity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 5.40 LED Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

DATASHEET
Datasheet
Table 5.41 LED Polarity Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 5.42 LED Behavior Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 5.43 LEDx_CTL Bit Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 5.44 LED Pulse 1 Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 5.45 LED Pulse / Breathe Period Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 5.46 LED Pulse 2 Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 5.47 LED Behavior Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 5.48 LED Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 5.49 PULSEX_CNT Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 5.50 LED Duty Cycle Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 5.51 LED Duty Cycle Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 5.52 LED Direct Ramp Rates Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 5.53 Rise / Fall Rate and Off Delay Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 5.54 LED Off Delay Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 5.55 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 5.56 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 5.57 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 7.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

DATASHEET
Datasheet
Chapter 1 Pin Description
RESET
VDD
CS1
CS2
CS3
CS4
24
23
22
21
20
19
SPI_CS# 1 18 CS5
WAKE / SPI_MOSI 2 17 CS6

SMDATA / BC_DATA /
SPI_MSIO / SPI_MISO 3 16 CS7
CAP1088
SMCLK / BC_CLK /
4 24 pin QFN 15 CS8
SPI_CLK
LED1 5 14 ADDR_COMM
LED2 6 13 ALERT# / BC_IRQ#
10
11
12
7
GND
LED3
LED4
LED5
LED6
LED7
LED8
Figure 1.1 CAP1088 Pin Diagram (24-Pin QFN)
Table 1.1 Pin Description for CAP1088
PIN
NUMBER PIN NAME PIN FUNCTION PIN TYPE
1 SPI_CS# Active low chip-select for SPI bus DI (5V)
WAKE - Active high wake / interrupt output -

DO
Standby power state
WAKE / WAKE - Active high wake input - requires pull-down resistor

2 DI
SPI_MOSI Deep Sleep power state
SPI_MOSI - SPI Master-Out-Slave-In port when used in

DI (5V)
normal mode

DATASHEET
Datasheet
Table 1.1 Pin Description for CAP1088 (continued)
PIN
SMDATA - Bi-directional, open-drain SMBus data - requires

DIOD (5V)
pull-up resistor
SMDATA / BC_DATA - Bi-directional, open-drain BC-Link data -

DIO
BC_DATA / requires pull-up resistor
3
SPI_MSIO /
SPI_MSIO - SPI Master-Slave-In-Out bidirectional port
SPI_MISO DIO
when used in bi-directional mode
SPI_MISO - SPI Master-In-Slave-Out port when used in

DO
normal mode
SMCLK - SMBus clock input - requires pull-up resistor DI (5V)

SMCLK /
4 BC_CLK / BC_CLK - BC-Link clock input DI (5V)
SPI_CLK
SPI_CLK - SPI clock input DI (5V)
Open drain LED 1 driver (default) OD (5V)

5 LED1
Push-pull LED 1 driver DO

6 LED2

7 LED3

8 LED4

9 LED5

10 LED6

11 LED7

12 LED8
ALERT# - Active low alert / interrupt output for SMBus alert

OD (5V)
ALERT# / or SPI interrupt
13
BC_IRQ#
BC_IRQ# - Active low interrupt / optional for BC-Link OD (5V)
Address / communications select pin - pull-down resistor

14 ADDR_COMM AI
determines address / communications mechanism
15 CS8 Capacitive Touch Sensor 8 AIO

DATASHEET
Datasheet
Table 1.1 Pin Description for CAP1088 (continued)
PIN
23 VDD Positive Power supply Power
Active high soft reset for system - resets all registers to

24 RESET DI (5V)
default values
Bottom Pad GND Ground Power
The pin types are described in detail below. All pins labelled with (5V) are 5V tolerant.
APPLICATION NOTE: For the 5V tolerant pins that have a pull-up resistor, the pull-up voltage must not exceed 3.6V
when the CAP1088 is unpowered.
.
Table 1.2 Pin Types
PIN TYPE DESCRIPTION
Power This pin is used to supply power or ground to the

device.
DI Digital Input - This pin is used as a digital input. This

pin is 5V tolerant.
AIO Analog Input / Output -This pin is used as an I/O for

analog signals.
DIOD Digital Input / Open Drain Output- This pin is used as a

digital I/O. When it is used as an output, it is open drain
and requires a pull-up resistor. This pin is 5V tolerant.
OD Open Drain Digital Output - this pin is used as a digital

output. It is open drain and requires a pull-up resistor.
This pin is 5V tolerant.
DO Push-pull Digital Output - This pin is used as a digital

output and can sink and source current.
DIO Push-pull Digital Input / Output - This pin is used as an

I/O for digital signals.

DATASHEET
Datasheet
Chapter 2 Electrical Specifications
Table 2.1 Absolute Maximum Ratings
Voltage on 5V tolerant pins (VPULLUP) -0.3 to 5.5 V
Voltage on 5V tolerant pins (VPULLUP - VDD) Note 2.2 -0.3 to 3.6 V
Voltage on VDD pin -0.3 to 4 V
Voltage on any other pin to GND -0.3 to VDD + 0.3 V
Package Power Dissipation up to TA = 85°C for 24 pin QFN 0.9 W

(see Note 2.3)
Junction to Ambient (θJA) (see Note 2.4) 58 °C/W
Operating Ambient Temperature Range -40 to 125 °C
Storage Temperature Range -55 to 150 °C
ESD Rating, All Pins, HBM 8000 V
Note 2.1 Stresses above those listed could cause permanent damage to the device. This is a stress
rating only and functional operation of the device at any other condition above those
indicated in the operation sections of this specification is not implied.
Note 2.2 For the 5V tolerant pins that have a pull-up resistor, the voltage difference between
VPULLUP and VDD must never exceed 3.6V.
Note 2.3 The Package Power Dissipation specification assumes a recommended thermal via design
consisting of a 3x3 matrix of 0.3mm (12mil) vias at 1.0mm pitch connected to the ground
plane with a 2.5 x 2.5mm thermal landing.
Note 2.4 Junction to Ambient (θJA) is dependent on the design of the thermal vias. Without thermal
vias and a thermal landing, the θJA is approximately 60°C/W including localized PCB
temperature increase.
Table 2.2 Electrical Specifications
VDD = 3V to 3.6V, TA = 0°C to 100°C, all Typical values at TA = 27°C unless otherwise noted.
CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS
DC Power
Supply Voltage VDD 3.0 3.3 3.6 V

DATASHEET
Datasheet
Table 2.2 Electrical Specifications (continued)
Supply Current ISTBY 135 170 uA Standby state active,

2 sensors monitored
1 LED active
Default conditions (8 avg, 70ms
cycle time)
IDSLEEP TBD TBD uA Deep Sleep state active

LEDs at 100% or 0% Duty Cycle
No communications
TA < 85°C
IDD 300 500 uA Average current

Capacitive Sensing Active,
LEDs enabled
Capacitive Touch Sensor
Base Capacitance CBASE 5 50 pF Pad untouched
Detectable ΔCTOUCH 0.1 2 pF Pad touched

Capacitive Shift
LED Drivers
Duty Cycle DUTYLED 0 100 % Programmable
Sinking Current ISINK 24 mA VOL = 0.4
Sourcing Current ISOURCE 24 mA VOH = VDD - 0.4
I/O Pins - SPI_CS#, RESET, WAKE / SPI_MOSI, and ALERT# pins
Output Low Voltage VOL 0.4 V ISINK_IO = 4mA
Output High Voltage VOH VDD - V WAKE pin only

0.4 ISOURCE_IO = 4mA
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Leakage Current ILEAK ±5 uA powered or unpowered

TA < 85°C
SMDATA / BC_DATA / SPI_MSIO / SPI_MISO and SMCLK / BC_CLK / SPI_CLK pins
Output Low Voltage VOL 0.4 V ISINK_IO = 8mA
Output High Voltage VOH VDD - V ISOURCE_IO = 8mA

0.4
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Leakage Current ILEAK ±5 uA powered or unpowered

TA < 85°C
pull-up voltage < 3.6V
SMBus First tSMB 15 ms

Communication

DATASHEET
Datasheet
Table 2.2 Electrical Specifications (continued)
SMBus Timing
Input Capacitance CIN 5 pF
Clock Frequency fSMB 10 400 kHz
Spike Suppression tSP 50 ns
Bus free time Start to tBUF 1.3 us

Stop
Setup Time: Start tSU:STA 0.6 us
Setup Time: Stop tSU:STP 0.6 us
Data Hold Time tHD:DAT 0.6 6 us
Data Setup Time tSU:DAT 0.6 72 us
Clock Low Period tLOW 1.3 us
Clock High Period tHIGH 0.6 us
Clock/Data Fall time tFALL 300 ns Min = 20+0.1CLOAD ns
Clock/Data Rise time tRISE 300 ns Min = 20+0.1CLOAD ns
Capacitive Load CLOAD 400 pF per bus line
BC-Link Timing
Clock Period tCLK 250 ns
Data Hold Time tHD:DAT 0 ns
Data Setup Time tSU:DAT 30 ns Data must be valid before clock
Clock Duty Cycle Duty 40 50 60 %
SPI Timing
Clock Period tP 250 ns
Clock Low Period tLOW 0.4 x tP 0.6 x tP ns
Clock High Period tHIGH 0.4 x tP 0.6 x tP ns
Clock Rise / Fall tRISE / 0.1 x tP ns

time tFALL
Data Output Delay tD:CLK 10 ns
Data Setup Time tSU:DAT 20 ns
Data Hold Time tHD:DAT 20 ns
SPI_CS# to tSU:CS 0 ns
SPI_CLK setup time
Wake Time tWAKE 10 20 us SPI_CS# asserted to CLK assert

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Datasheet
Chapter 3 Communications
3.1 Communications
The CAP1088 communicates using the 2-wire SMBus or I2C bus, the 2-wire proprietary BC-Link, or
the SPI bus. Regardless of communication mechanism, the device functionality remains unchanged.
The communications mechanism as well as the SMBus (or I2C) slave address is determined by the
resistor connected between the ADDR_COMM pin and ground as shown in Table 3.1.
.
Table 3.1 ADDR_COMM Pin Decode
PULL-DOWN RESISTOR PROTOCOL USED SMBUS ADDRESS
<= 47k SPI Communications using

n/a
Normal 4-wire Protocol Used
56k SPI Communications using Bi-

n/a
Directional 3-wire Protocol Used
68k BC-Link Communications n/a
82k SMBus / I2C 0101_100(r/w)
100k SMBus / I2C 0101_011(r/w)
120k SMBus / I2C 0101_010(r/w)
150k SMBus / I2C 0101_001(r/w)
VDD SMBus / I2C 0101_000(r/w)
3.1.1 SMBus (I2C) Communications

When configured to communicate via the SMBus, the CAP1088 supports the following protocols: Send
Byte, Receive Byte, Read Byte, and Write Byte. In addition, the device supports I2C formatting for block
read and block write protocols. The SPI_CS# pin is not used and any data presented to this pin will
be ignored.
See Section 3.2 and Section 3.3 for more information on the SMBus bus and protocols respectively.
3.1.2 SPI Communications

When configured to communicate via the SPI bus, the CAP1088 supports both bi-directional 3-wire
and normal 4-wire protocols and uses the SPI_CS# pin to enable communications.
See Section 3.4 and Section 3.6 for more information on the SPI bus and protocols respectively.
3.1.3 BC-Link Communications

When BC-Link communications are used, the CAP1088 supports the read byte protocol and the write
byte protocol.
See Section 3.7 for more information on the BC-Link Bus and protocols respectively.
APPLICATION NOTE: Upon power up, the CAP1088 will not respond to any communications for up to 15ms. After
this time, full functionality is available.

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3.2 System Management Bus

The CAP1088 communicates with a host controller, such as an SMSC SIO, through the SMBus. The
SMBus is a two-wire serial communication protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in Figure 3.1. Stretching of the SMCLK signal is supported;
however, the CAP1088 will not stretch the clock signal.
TLOW THIGH THD:STA

TSU:STO
TRISE TFALL
SMCLK
THD:STA THD:DAT TSU:DAT TSU:STA
SMDATA
TBUF
P S S - Start Condition S P - Stop Condition P
Figure 3.1 SMBus Timing Diagram
3.2.1 SMBus Start Bit

The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic
‘0’ state while the SMBus Clock line is in a logic ‘1’ state.
3.2.2 SMBus Address and RD / WR Bit

The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If
this RD / WR bit is a logic ‘0’, then the SMBus Host is writing data to the client device. If this RD / WR
bit is a logic ‘1’, then the SMBus Host is reading data from the client device.
See Table 3.1 for available SMBus addresses.
3.2.3 SMBus Data Bytes

All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information.
3.2.4 SMBus ACK and NACK Bits

The SMBus client will acknowledge all data bytes that it receives. This is done by the client device
pulling the SMBus Data line low after the 8th bit of each byte that is transmitted. This applies to both
the Write Byte and Block Write protocols.
The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the
SMBus data line high after the 8th data bit has been sent. For the Block Read protocol, the Host will
ACK each data byte that it receives except the last data byte.
3.2.5 SMBus Stop Bit

The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic
‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the CAP1088 detects an SMBus Stop
bit, and it has been communicating with the SMBus protocol, it will reset its client interface and prepare
to receive further communications.

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3.2.6 SMBus Timeout

The CAP1088 includes an SMBus timeout feature. Following a 30ms period of inactivity on the SMBus
where the SMCLK pin is held low, the device will timeout and reset the SMBus interface.
The timeout function defaults to disabled. It can be enabled by setting the TIMEOUT bit in the
Configuration register (see Section 5.6).
3.2.7 SMBus and I2C Compliance

The major difference between SMBus and I2C devices is highlighted here. For complete compliance
information refer to the SMBus 2.0 specification.
1. Minimum frequency for SMBus communications is 10kHz.
2. The client protocol will reset if the clock is held low longer than 30ms.
3. The client protocol will reset if both the clock and the data line are high for longer than 150us (idle
condition).
4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus).
5. I2C devices support block read and write differently. I2C protocol allows for unlimited number of
bytes to be sent in either direction. The SMBus protocol requires that an additional data byte
indicating number of bytes to read / write is transmitted. The CAP1088 supports I2C formatting only.
3.3 SMBus Protocols

The CAP1088 is SMBus 2.0 compatible and supports Send Byte, Read Byte, Block Read, Receive
Byte as valid protocols as shown below. The CAP1088 also supports the I2C block read and block
write protocols. Finally, it will respond to the Alert Response Address protocol but is not in full
compliance.
All of the below protocols use the convention in Table 3.2.
Table 3.2 Protocol Format
DATA SENT DATA SENT TO

TO DEVICE THE HOST
Data sent Data sent
3.3.1 SMBus Write Byte

The Write Byte is used to write one byte of data to a specific register as shown in Table 3.3.
Table 3.3 Write Byte Protocol
SLAVE REGISTER REGISTER

START ADDRESS WR ACK ADDRESS ACK DATA ACK STOP
1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1
3.3.2 Block Write

The Block Write is used to write multiple data bytes to a group of contiguous registers as shown in
Table 3.4. It is an extension of the Write Byte Protocol.

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APPLICATION NOTE: When using the Block Write protocol, the internal address pointer will be automatically
incremented after every data byte is received. It will wrap from FFh to 00h.
Table 3.4 Block Write Protocol
SLAVE REGISTER REGISTER

START ADDRESS WR ACK ADDRESS ACK DATA ACK
1 ->0 YYYY_YYY 0 0 XXh 0 XXh 0
REGISTER REGISTER REGISTER

DATA ACK DATA ACK ... DATA ACK STOP
XXh 0 XXh 0 ... XXh 0 0 -> 1
3.3.3 SMBus Read Byte

The Read Byte protocol is used to read one byte of data from the registers as shown in Table 3.5.
Table 3.5 Read Byte Protocol
START SLAVE WR ACK REGISTER ACK START CLIENT RD ACK REGISTER NACK STOP
ADDRESS ADDRESS ADDRESS DATA
1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh 1 0 -> 1
3.3.4 Block Read

The Block Read is used to read multiple data bytes from a group of contiguous registers as shown in
Table 3.6. It is an extension of the Read Byte Protocol.
APPLICATION NOTE: When using the Block Read protocol, the internal address pointer will be automatically
incremented after every data byte is received. It will wrap from FFh to 00h.
Table 3.6 Block Read Protocol
START SLAVE WR ACK REGISTER ACK START SLAVE RD ACK REGISTER

ADDRESS ADDRESS ADDRESS DATA
1->0 YYYY_YYY 0 0 XXh 0 1 ->0 YYYY_YYY 1 0 XXh

ACK REGISTER ACK REGISTER ACK REGISTER ACK ... REGISTER NACK STOP
DATA DATA DATA DATA
0 XXh 0 XXh 0 XXh 0 ... XXh 1 0 -> 1
3.3.5 SMBus Send Byte

The Send Byte protocol is used to set the internal address register pointer to the correct address
location. No data is transferred during the Send Byte protocol as shown in Table 3.7.
Table 3.7 Send Byte Protocol
SLAVE REGISTER
START ADDRESS WR ACK ADDRESS ACK STOP
1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1

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3.3.6 SMBus Receive Byte

The Receive Byte protocol is used to read data from a register when the internal register address
pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads
of the same register as shown in Table 3.8.
Table 3.8 Receive Byte Protocol
SLAVE
START ADDRESS RD ACK REGISTER DATA NACK STOP
1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1
3.4 SPI Interface

The SMBus has a predefined packet structure, the SPI does not. The SPI Bus can operate in two
modes of operation, normal 4-wire mode and bi-directional 3-wire mode. All SPI commands consist of
8-bit packets set to a specific slave device (identified by the CS pin).
The SPI bus will latch data on the rising edge of the clock and the clock and data both idle high.
All commands are supported via both operating modes. The supported commands are: Reset Serial
interface, set address pointer, write command and read command. Note that all other codes received
during the command phase are ignored and have no effect on the operation of the device.
tP
tHIGH
tLOW
SPI_CLK tFALL
tRISE
tSU:DAT
SPI_MSIO or
SPI_MOSI or tD:CLK
tHD:DAT
SPI_MISO
Figure 3.1 SPI Timing
3.4.1 SPI Normal Mode

The SPI Bus can operate in two modes of operation, normal and bi-directional mode. In the normal
mode of operation, there are dedicated input and output data lines. The host communicates by sending
a command along the CAP1088 SPI_MOSI data line and reading data on the SPI_MISO data line.
Both communications occur simultaneously which allows for larger through put of data transactions.
All basic transfers consist of two 8 bit transactions from the Master device while the slave device is
simultaneously sending data at the current address pointer value.
Data writes consist of two or more 8-bit transactions. The host sends a specific write command
followed by the data to write the address pointer. Data reads consist of one or more 8-bit transactions.

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The host sends the specific read data command and continues clocking for as many data bytes as it
wishes to receive.
3.4.2 SPI Bi-Directional Mode

In the bi-directional mode of operation, the SPI data signals are combined into the SPI_MSIO line,
which is shared for data received by the device and transmitted by the device. The protocol uses a
simple handshake and turn around sequence for data communications based on the number of clocks
transmitted during each phase.
All basic transfers consist of two 8 bit transactions. The first is an 8 bit command phase driven by the
Master device. The second is by an 8 bit data phase driven by the Master for writes, and by the
CAP1088 for read operations.
The auto increment feature of the address pointer allows for successive reads or writes. The address
pointer will return to 00h after reaching FFh.
3.4.3 SPI_CS# Pin

The SPI Bus is a single master, multiple slave serial bus. Each slave has a dedicated CS pin (chip
select) that the master asserts low to identify that the slave is being addressed. There are no formal
addressing options.
3.4.4 Address Pointer

All data writes and reads are accessed from the current address pointer. In both Bi-directional mode
and Full Duplex mode, the Address pointer is automatically incremented following every read
command or every write command.
The address pointer will return to 00h after reaching FFh.
3.4.5 SPI Timeout

The CAP1088 does not detect any timeout conditions on the SPI bus.
3.5 Normal SPI Protocols

When operating in normal mode, the SPI bus internal address pointer is incremented depending upon
which command has been transmitted. Multiple commands may be transmitted sequentually so long
as the SPI_CS# pin is asserted low. Figure 3.1 shows an example of this operation.

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Revision 1.0 (06-16-09)

SPI_CS#
SPI_MOSI 7Ah 7Ah 7Dh 41h 7Eh 66h 7Dh 41h 7Fh 7Fh 7Fh 7Fh 7Fh 7Fh 7Dh 40h 7Fh 7Fh
XXh XXh YYh YYh XXh AAh AAh 55h XXh

SPI_MISO 45h 66h AAh AAh 55h 80h 43h 78h 56h
(invalid) (invalid) (invalid) (invalid) (invalid) (invalid) (invalid) (invalid) (invalid)
SPI Address Pointer 00h 41h 42h 41h 41h 42h 43h 44h 45h 46h 40h 40h
SPI Data output buffer XXh 45h AAh 55h 66h AAh 55h 80h 43h 78h 80h 56h
Register Address / 40h / 56h 40h / 56h 40h / 56h 40h / 56h 40h / 56h 40h / 56h 40h / 56h 40h / 56h 40h / 56h 40h / 56h
Data 41h / 45h 41h / 45h 41h / 66h 41h / 66h 41h / 66h 41h / 66h 41h / 66h 41h / 66h 41h / 66h 41h / 66h
42h / AAh 42h / AAh 42h / AAh 42h / AAh 42h / AAh 42h / AAh 42h / AAh 42h / AAh 42h / AAh 42h / AAh
43h / 55h 43h / 55h 43h / 55h 43h / 55h 43h / 55h 43h / 55h 43h / 55h 43h / 55h 43h / 55h 43h / 55h
46h / 78h 46h / 78h 46h / 78h 46h / 78h 46h / 78h 46h / 78h 46h /78h 46h /78h 46h / 78h 46h /78h
Indicates SPI Address pointer incremented
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Figure 3.1 Example SPI Bus Communication - Normal Mode
20
3.5.1 Reset Interface
Resets the Serial interface whenever two successive 7Ah codes are received. Regardless of the current phase of the transaction - command or data,
the receipt of the successive reset commands resets the Serial communication interface only. All other functions are not affected by the reset operation.
SMSC CAP1088
Datasheet
SPI_CS#
SPI_CLK
Master SPDOUT ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’
SPI_MOSI
Reset - 7Ah Reset - 7Ah
SPI_MISO Invalid register data 00h – Internal Data buffer empty
Master Drives Slave Drives
Figure 3.2 SPI Reset Interface Command - Normal Mode
3.5.2 Set Address Pointer

The Set Address Pointer command sets the Address pointer for subsequent reads and writes of data.
The pointer is set on the rising edge of the final data bit. At the same time, the data that is to be read
is fetched and loaded into the internal output buffer but is not transmitted.
SPI_CS#
SPI_CLK
Master SPDOUT
SPI_MOSI ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ Register Address
Set Address Pointer – 7Dh
SPI_MISO Unknown, Invalid Data Unknown, Invalid Data
Master Drives Slave Drives Address pointer set
Figure 3.3 SPI Set Address Pointer Command - Normal Mode
3.5.3 Write Data

The Write Data protocol updates the contents of the register referenced by the address pointer. As the
command is processed, the data to be read is fetched and loaded into the internal output buffer but
not transmitted. Then, the register is updated with the data to be written. Finally, the address pointer
is incremented.

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SPI_CS#
SPI_CLK
Master SPDOUT
SPI_MOSI Write Command – 7Eh Data to Write
SPI_MISO Unknown, Invalid Data Old Data at Current Address Pointer

1. Data written at current
address pointer
2. Address pointer incremented
Figure 3.4 SPI Write Command - Normal Mode
3.5.4 Read Data

The Read Data protocol is used to read data from the device. During the normal mode of operation,
while the device is receiving data, the CAP1088 is simultaneously transmitting data to the host. For
the Set Address commands and the Write Data commands, this data may be invalid and it is
recommended that the Read Data command is used.
SPI_CS#
SPI_CLK
Master SPDOUT
‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
SPI_MOSI
Subsequent Read
First Read Command – 7Fh
Commands – 7F
SPI_MISO Invalid, Unknown Data * Data at Current Address Pointer
Master Drives Slave Drives Address Pointer

Incremented **
* The first read command after any other command will return invalid data for the first
byte. Subsequent read commands will return the data at the Current Address Pointer
** The Address Pointer is incremented 8 clocks after the Read Command has been
received. Therefore continually sending Read Commands will result in each command
reporting new data. Once Read Commands have been finished, the last data byte will be
read during the next 8 clocks for any command
Figure 3.5 SPI Read Command - Normal Mode

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1. Register Read Address

updated to Current SPI Read
Address pointer.
1. Register Read Address 1. Register Read Address 2. Register Read Address
updated to Current SPI Read incremented = current address incremented = current address
Address pointer pointer + 1 pointer +1 – end result =
register address pointer doesn’t
change
SPI_CS#
SPI_MISO ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
XXh
Read Command – 7Fh Subsequent Read Commands – 7Fh
Master SPDOUT Data at previously set register address = current Data at previously set register address = current Data at previously set register address = current
SPI_MOSI SPI_CLK address pointer address pointer (SPI) address pointer (SPI)

1. Output buffer transmitted =
data at previous address Register Data loaded into
1. Register data loaded into Output buffer = data at current 1. Register data loaded into
pointer + 1 = current address
output buffer = data at current address pointer + 1 output buffer = data at current
pointer
address pointer 1. SPI Read Address address pointer
1. Output buffer transmitted = Incremented = new current 1. Output buffer transmitted =
data at current address pointer address pointer data at current address pointer
+1 2. Register Read Address +1
2. Flag set to increment SPI Incremented = current address 1. Output buffer transmitted = 2. Flag set to increment SPI
Read Address at end of next 8 pointer +1 data at previous register Read Address at end of next 8
clocks address pointer + 1 = current clocks
address pointer
Figure 3.6 SPI Read Command - Normal Mode - Full
3.6 Bi-Directional SPI Protocols
3.6.1 Reset Interface

Resets the Serial interface whenever two successive 7Ah codes are received. Regardless of the
current phase of the transaction - command or data, the receipt of the successive reset commands
resets the Serial communication interface only. All other functions are not affected by the reset
operation.
SPI_CS#
SPI_CLK
Master SPDOUT ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’ ‘0’
SPI_MSIO
Reset - 7Ah Reset - 7Ah
Figure 3.7 SPI Reset Interface Command - Bi-directional Mode
3.6.2 Set Address Pointer

Sets the address pointer to the register to be accessed by a read or write command. This command
overrides the auto-incrementing of the address pointer.

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SPI_CS#
SPI_CLK
Master SPDOUT Register Address

‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ ‘1’
SPI_MSIO
Set Address Pointer – 7Dh
Figure 3.8 SPI Set Address Pointer Command - Bi-directional Mode
3.6.3 Write Data

Writes data value to the register address stored in the address pointer. Performs auto increment of
address pointer after the data is loaded into the register.
SPI_CS#
SPI_CLK
Master SPDOUT
‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘0’ Register Write Data
SPI_MSIO
Write Command – 7Eh
Figure 3.9 SPI Write Data Command - Bi-directional Mode
3.6.4 Read Data

Reads data referenced by the address pointer. Performs auto increment of address pointer after the
data is transferred to the Master.
SPI_CS#
SPI_CLK
Master SPDOUT
SPI_MSIO ‘0’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ Register Read Data
Read Command – 7Fh

Master Drives Slave Drives Indeterminate
Figure 3.10 SPI Read Data Command - Bi-directional Mode

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3.7 BC-Link Interface

The BC-Link is a proprietary bus developed to allow communication between a host controller device
to a companion device. This device uses this serial bus to read and write registers and for interrupt
processing. The interface uses a data port concept, where the base interface has an address register,
data register and a control register, defined in the SMSC’s 8051’s SFR space.
Refer to documentation for the BC-Link comptabile host controller for details on how to access the
CAP1088 via the BC-Link Interface.

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Chapter 4 General Description
The CAP1088 is a multiple channel Capacitive Touch sensor with multiple power LED drivers. It
contains eight (8) individual Capacitive Touch sensor inputs with programmable sensitivity for use in
touch sensor applications. Each sensor automatically recalibrates to compensate for gradual
environmental changes.
The CAP1088 also contains eight (8) low side (or push-pull) LED drivers that offer full-on / off, variable
rate blinking, dimness controls, and breathing. Each of the LED drivers may be linked to one of the
sensors to be actuated when a touch is detected. As well, each LED driver may be individually
controlled via a host controller.
Finally, the device contains a dedicated RESET pin to act as a soft reset by the system.
The CAP1088 offers multiple power states operating at low quiescent currents during its Deep Sleep
state. The device also contains a wake pin (WAKE/SPI_MOSI) output to wake the system when a
touch is detected in Standby and to wake the device from Deep Sleep. It can monitor one or more
channels while in a lower power state and respond to communications normally.
The device communicates with a host controller using the SPI bus, SMSC BC-Link bus, or via SMBus
/ I2C. The host controller may poll the device for updated information at any time or it may configure
the device to flag an interrupt whenever a touch is detected on any sensor.
A typical system diagram is shown in Figure 4.1.

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VDD Embedded Controller
SMCLK / BC_CLK / SPI_CLK
ALERT# / BC_IRQ#
SPI_CS#
RESET
SMDATA / BC_DATA / SPI_MSIO / SPI_MISO
WAKE / SPI_MOSI
ADDR_COMM
3.3V – 5V 3.3V – 5V
LED1 LED8
Touch
CAP1088 Touch
Button CS1 CS8 Button
LED2 LED7
Touch Touch
Button CS2 CS7
Button
LED3 LED6
Touch Touch
LED4 LED5
Touch Touch
Figure 4.1 System Diagram for CAP1088
4.1 Power States

The CAP1088 has three operating states depending on the status of the STBY and DSLEEP bits.
When the device transitions between power states, previously detected touches (for inactive channels)
are cleared and the status bits reset.

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1. Fully Active - The device is fully active. It is monitoring all active Capacitive Sensor channels and
driving all LED channels as defined.
2. Standby - The device is in a lower power state. It will measure a programmable number of channels
(as determined by the Standby Channel register - default none). Interrupts will still be generated
based on the active channels. The device will still respond to communications normally and can
be returned to the Fully Active state of operation by clearing the STBY bit.
3. Deep Sleep - The device is in its lowest power state. It is not monitoring any Capacitive Sensor
channels. It can be awakened by SMBus or SPI communications targeting the device (which will
cause the DSLEEP bit to be automatically cleared).
If the device is not communicating via the 4-wire SPI bus, then during this state of operation, if the
WAKE/SPI_MOSI pin is driven high by an external source, the device will clear the DSLEEP bit
and return to Fully Active.
APPLICATION NOTE: The Deep Sleep state does not change LED drive behavior so it is It is the user’s
responsibility to ensure that the LEDs are driven to the desired state prior to entering Deep
Sleep. This is best achieved by unlinking the LEDs from the sensors and driving the LEDs
to the desired state using the LED Output Control register.
APPLICATION NOTE: If the CAP1088 is configured to communicate using the BC-Link protocol, the device does
not support Deep Sleep.
4.2 RESET Pin

The RESET pin is an active high reset that is driven from an external source. While it is asserted high,
all the internal blocks will be held in reset including the communications protocol used essentially
placing the device into its lowest power state.
All configuration settings will be reset to default states (thus waking the device from Deep Sleep) and
all readings will be cleared. Once the RESET pin is pulled low, the CAP1088 will begin operation as
if a power-on-reset had occurred.
4.3 WAKE/SPI_MOSI Pin Operation

When the CAP1088 is placed in Standby, and is not communicating using the 4-wire SPI protocol,it
will assert the WAKE/SPI_MOSI pin when a touch is detected on one of its sampled sensors. The pin
will remain asserted until the INT bit has been cleared and then it will be de-asserted.
When the CAP1088 is placed in Deep Sleep and it is not commuicating using the 4-wire SPI protocol,
the WAKE/SPI_MOSI pin is monitored by the device as an input. If the WAKE/SPI_MOSI pin is driven
high by an external source, the CAP1088 will clear the DSLEEP bit.
When the device is placed in Deep Sleep, this pin is a High-Z input and must have a pull-down resistor
to GND for proper operation.
4.4 LED Drivers

The CAP1088 contains eight (8) LED Drivers. Each LED driver can be configured to operate in one of
the following modes with either push-pull or open drain drive. Additionally, each LED driver can be
linked to the respective Capacitive Touch sensor input.
1. Direct - The LED is configured to be on or off when the corresponding input stimulus is on or off
(or inverted). The brightness of the LED can be programmed from full off to full on (default).
Additionally, the LED contains controls to individually configure ramping on, off, and turn-off delay.
2. Pulse 1 - The LED is configured to fade ON-OFF-ON a programmable number of times with
programmable rate and min / max brightness. This behavior may be actuated when a press is
detected, or when a release is detected.

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3. Pulse 2 - The LED is configured to “Breathe” while actuated and then “Pulse” when the sensor is
released.
4. Breathe - The LED is configured to fade continuously ON-OFF-ON (i.e. to "Breathe”) with a
programmable rate and min / max brightness.
In addition to these four behaviors, all LED drivers support host initiated LED actuation. All LEDs also
have an option to assert the ALERT# pin when the initated behavior has reached its maximum or
minimum brightness levels.
4.4.1 Linking LEDs to Capacitive Touch Sensors

All LEDs can be linked to the corresponding Capacitive Touch Sense input channel so that when the
sensor detects a touch, the corresponding LED will be actuated at one of the programmed responses.
4.5 Capacitive Touch Sensing

The CAP1088 contains eight (8) independent Capacitive Touch Sensor inputs. Each sensor has
dynamic range to detect a change of capacitance due to a touch. Additionally, each sensor can be
configured to be automatically and routinely re-calibrated.
4.5.1 Sensing Cycle

Each Capacitive Touch Sensor has controls to be activated and included in the sensing cycle. When
the device is active, it automatically initiates a sensing cycle and repeats the cycle every time it
finishes. The cycle polls through each active Sensor starting with CS1 and extending through CS8. As
each Capacitive Touch Sensor is polled, its measurement is compared against a baseline “not touched”
measurement. If the delta measurement is large enough, then a touch is detected and an interrupt
generated.
The sensing cycle time is programmable (see Section 4.6).
4.5.2 Recalibrating Sensors

Each sensor is regularly recalibrated at an adjustable rate. By default, the recalibration routine stores
the average 256 previous measurements and periodically updates the base “Not Touched” setting for
the Capacitive Touch Sensor input.
It is possible that the device loses sensitivity to a touch. This may happen as a result of a noisy
environment, an accidental recalibration during a touch, or other environmental changes. When this
occurs, then the base untouched sensor may generate negative delta count values. The device will
detect this condition based on a programmable number of consecutive negative delta readings. When
it detects the condition, the CAP1088 will automatically re-calibrate the base-count settings. During this
recalibration, the device will not respond to touches.
4.6 ALERT# Pin

The ALERT# pin is an active low output that is driven when an interrupt event is detected.
Whenever an interrupt is generated, the INT bit (see Section 5.1) is set. The ALERT# pin is cleared
when INT bit is cleared by the user. Additionally, when the INT bit is cleared by the user, status bits
are only cleared if no touch is detected.
4.6.1 Sensor Interrupt Behavior

The sensor interrupts are generated in one of two ways:
1. An interrupt is generated when a touch is detected and when a release is detected (see Figure 4.3).

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2. If the repeat rate is enabled (see Section 5.6), then, so long as the touch is held, another interrupt
will be generated based on the programmed repeat rate (see Figure 4.2).
When the repeat rate is enabled, the device uses an additional control called MPRESS that determines
whether a touch is flagged as a simple “touch” or a “press and hold”. The MPRESS[3:0] bits set a
minimum press timer. When the button is touched the timer begins. If the sensor is released before
the minimum press timer expires, then it is flagged as a touch and an interrupt is generated upon the
release. If the sensor detects a touch for longer than this timer value, then it is flagged as a “press
and hold” event. So long as the touch is held, interrupts will be generated at the programmed repeat
rate and upon a release.
Polling Cycle
Interrupt on (35ms)
Touch Interrupt on
Release
Touch Detected Button Repeat Rate Button Repeat Rate Button Repeat Rate
(175ms) (175ms) (175ms)
ALERT Pin / INT bit
Button Status
SMBus Write to INT bit
Figure 4.2 Sensor Interrupt Behavior - Repeat Rate Enabled
APPLICATION NOTE: The host may need to poll the device twice to determine that a release has been detected.
Polling Cycle
Interrupt on (35ms)
Touch Interrupt on
Release
Touch Detected
ALERT Pin /
INT bit
Button Status
SMBus Write to
INT bit
Figure 4.3 Sensor Interrupt Behavior - No Repeat Rate Enabled

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Chapter 5 Register Description
The registers shown in Table 5.1 are accessible through the communications protocol. An entry of ‘-’
indicates that the bit is not used and will always read ‘0’.
Table 5.1 Register Set in Hexadecimal Order
REGISTER DEFAULT
ADDRESS R/W REGISTER NAME FUNCTION VALUE PAGE
Controls general power states and

00h R/W Main Status Control 00h Page 34
power dissipation
Returns the state of the sampeld

03h R Sensor Status 00h Page 35
Capacative Touch Sensor
04h R LED Status Stores status bits for LEDs 00h Page 35
0Ah R Noise Flag Status Stores the noise flags for sensors 00h Page 36
10h R Sensor 1 Delta Count Stores the delta count for CS1 00h Page 36
Controls the sensitivity of the

1Fh R/W Sensitivity Control threshold and delta counts and data 2Fh Page 37
scaling of the base counts
Controls general functionality and

20h R/W Configuration 20h Page 38
LED controls
Controls whether the Capacitive

21h R/W Sensor Enable FFh Page 39
Touch Sensor inputs are sampled
Controls reset delay and auto-repeat

22h R/W Sensor Configuration delay for sensors operating in the full A4h Page 40
power state
Sensor Configuration Controls the MPRESS controls for all

23h R/W 07h Page 41
2 sensors
Averaging and Controls averaging and sampling

24h R/W 1Dh Page 42
Sampling Config window
Activates manual re-calibration for

26h R/W Calibration Activate FFh Page 43
Capacative Touch Sensors
Enables Interrupts associated with

27h R/W Interrupt Enable FFh Page 44
Capacative Touch Sensors
Enables repeat rate for Capacative

28h R/W Repeat Rate Enable FFh Page 44
Touch Sensors

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Table 5.1 Register Set in Hexadecimal Order (continued)
REGISTER DEFAULT
Determines the number of

Multiple Press
2Ah R/W simultaneous touches to flag a 80h Page 45
Configuration
multiple touch condition
Recalibration Determines re-calibration timing and

2Fh R/W 8Bh Page 46
Configuration sampling window
Stores the delta count threshold to

30h R/W Sensor 1 Threshold determine a touch for Capacitive 40h Page 47
Touch Sensor 1

Touch Sensor 2

Touch Sensor 3

Touch Sensor 4

Touch Sensor 5

Touch Sensor 6

Touch Sensor 7

Touch Sensor 8
Sensor Noise Stores controls for selecting the

38h R/W 55h Page 48
Threshold 1 noise threshold for sensors 1 - 4
Sensor Noise Stores controls for selecting the

39h R/W 55h Page 48
Threshold 2 noise threshold for sensors 5 - 8
Standby Configuration Registers
Controls which sensors are enabled

40h R/W Standby Channel 00h Page 49
while in standby
Controls averaging and cycle time

41h R/W Standby Configuration 1Dh Page 49
while in standby
Controls sensitivity settings used

42h R/W Standby Sensitivity 02h Page 51
while in standby
Stores the touch detection threshold

43h R/W Standby Threshold 40h Page 51
for active sensors in standby
Stores the reference count value for

50h R Sensor 1 Base Count C8h Page 52
sensor 1

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REGISTER DEFAULT

sensor 2

sensor 3

sensor 4

sensor 5

sensor 6

sensor 7

sensor 8
Controls the output type for the LED

71h R/W LED Output Type 00h Page 52
outputs
Controls linking of sensors to LED

72h R/W Sensor LED Linking 00h Page 55
channels
73h R/W LED Polarity Controls the output polarity of LEDs 00h Page 56
74h R/W LED Output Control Controls the output state of the LEDs 00h Page 53
Controls the behavior and response

81h R/W LED Behavior 1 00h Page 56
of LEDs 1 - 4
Controls the behavior and response

82h R/W LED Behavior 2 00h Page 56
of LEDs 5 - 8
Controls the period of each breathe

84h R/W LED Pulse 1 Period 20h Page 58
during a pulse
Controls the period of the breathing

85h R/W LED Pulse 2 Period 14h Page 59
during breathe and pulse operation
Controls the period of an LED

86h R/W LED Breathe Period 5Dh Page 60
breathe operation
88h R/W LED Config Controls LED configuration 04h Page 61
LED Pulse 1 Duty Determines the min and max duty

90h R/W F0h Page 62
Cycle cycle for the pulse operation
Determines the min and max duty

LED Pulse 2 Duty
91h R/W cycle for breathe and pulse F0h Page 62
Cycle
operation
LED Breathe Duty Determines the min and max duty

92h R/W F0h Page 62
Cycle cycle for the breathe operation
Determines the min and max duty

93h R/W LED Direct Duty Cycle F0h Page 62
cycle for Direct mode LED operation
LED Direct Ramp Determines the rising and falling

94h R/W 00h Page 63
Rates edge ramp rates of the LEDs

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REGISTER DEFAULT
Determines the off delay for all LED

95h R/W LED Off Delay 00h Page 64
behaviors
Stores a fixed value that identifies

FDh R Product ID 40h Page 65
each product
Stores a fixed value that identifies

FEh R Manufacturer ID 5Dh Page 65
SMSC
Stores a fixed value that represents

FFh R Revision 80h Page 65
the revision number
During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when
power is first applied to the part and the voltage on the VDD supply surpasses the POR level as
specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to
undefined registers will not have an effect.
5.1 Main Status Control Register
Table 5.2 Main Status Control Register
ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT
Main Status
00h R/W - - STBY DSLEEP - - - INT 00h
Control
The Main Status and Control register controls the primary power state of the device.
Bit 5 - STBY - Enables Standby.

‘0’ (default) - Sensor scanning is active and LEDs are functional.
‘1’ - Capacitive Touch Sensor scanning is limited to the sensors set in the Standby Channel register
(see Section 5.18). The status registers will not be cleared until read. LEDs that are linked to
Capacitive Touch sensors will remain linked and active. Sensors that are no longer sampled will
flag a release and then remain in a non-touched state. LEDs that are manually controlled will be
unaffected.
Bit 4 - DSLEEP - Enables Deep Sleep by deactivating all functions. This bit will be cleared when the
WAKE pin is driven high or when SPI or SMBus are received targeting the CAP1088. If the CAP1088
is configured to communicate using the BC-Link protocol, then this bit is ignored.
‘0’ (default) - Sensor scanning is active and LEDs are functional.
‘1’ - All sensor scanning is disabled and all LEDs are disabled. The status registers are
automatically cleared and the INT bit is cleared.
Bit 0 - INT - Indicates that there is an interrupt. This bit is only set if the ALERT# pin has been asserted.
If a channel detects a touch and its associated interrupt enable bit is not set to a logic ‘1’ then no
action is taken.
This bit is cleared by writing a logic ‘0’ to it. When this bit is cleared, the ALERT# pin will be deasserted
and all status registers will be cleared if the condition has been removed. If the WAKE/SPI_MOSI pin
is asserted as a result of a touch detected while in Standby, it will likewise be deasserted when this
bit is cleared.
Note that this pin is not driven when communicating via the 4-wire SPI protocol

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‘0’ - No interrupt pending.

‘1’ - A touch has been detected on one or more channels and the interrupt has been asserted.
5.2 Status Registers
Table 5.3 Status Registers
03h R Sensor Status CS8 CS7 CS6 CS5 CS4 CS3 CS2 CS1 00h
04h R LED Status LED8_ LED7_ LED6_ LED5_ LED4_ LED3_ LED2_ LED1_ 00h
DN DN DN DN DN DN DN DN
The Sensor Status Registers store status bits that indicate a touch has been detected. A value of ‘0’
in any bit indicates that no touch has been detected. A value of ‘1’ in any bit indicates that a touch
has been detected.
All status bits are cleared when the device enters the Deep Sleep (DSLEEP = ‘1’ - see Section 5.1).
All status bits are cleared when the INT bit is cleared and if a touch on the respective Capacitive Touch
Sensor is no longer present. If a touch is still detected, then the bits will not be cleared (but this will
not cause the interrupt to be asserted - see Section 5.6).
5.2.1 Sensor Status

Bit 7 - CS8 - Indicates that a touch was detected on Sensor 8. This sensor can be linked to LED8.
5.2.2 LED Status

Bit 7 - LED8_DN - Indicates that LED8 has finished its ramping behavior as determined by the
LED8_CTL bits.
LED7_CTL bits.
LED6_CTL bits.
LED5_CTL bits.
LED4_CTL bits.
LED3_CTL bits.

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LED2_CTL bits.
LED1_CTL bits.
5.3 Noise Flag Status Registers
Table 5.4 Noise Flag Status Registers
0Ah R Noise Flag Status CS8_ CS7_ CS6_ CS5_ CS4_ CS3_ CS2_ CS1_ 00h
NOISE NOISE NOISE NOISE NOISE NOISE NOISE NOISE
The Noise Flag Status registers store status bits that are generated from the analog block if the
detected noise is above the operating region of the analog detector. These bits indicate that the most
recently received data from the sensor is invalid and should not be used for touch detection.
Furthermore, so long as the bit is set for a particular channel, no decisions are made with the data. A
touch is not detected, and a release is not detected.
These bits are not sticky and will be cleared automatically if the analog block does not report a noise
error.
5.4 Sensor Delta Count Registers
Table 5.5 Sensor Delta Count Registers
Sensor 1 Delta
10h R Sign 64 32 16 8 4 2 1 00h
Count
Sensor 2 Delta
11h R Sign 64 32 16 8 4 2 1 00h
Count
Sensor 3 Delta
12h R Sign 64 32 16 8 4 2 1 00h
Count
Sensor 4 Delta
13h R Sign 64 32 16 8 4 2 1 00h
Count
Sensor 5 Delta
14h R Sign 64 32 16 8 4 2 1 00h
Count
Sensor 6 Delta
15h R Sign 64 32 16 8 4 2 1 00h
Count
Sensor 7 Delta
16h R Sign 64 32 16 8 4 2 1 00h
Count
Sensor 8 Delta
17h R Sign 64 32 16 8 4 2 1 00h
Count
The Sensor Delta Count registers store the delta count that is compared against the threshold used to
determine if a touch has been detected. The count value represents a change in input due to the
capacitor associated with a touch on one of the sensors and is referenced to a calibrated base “Not

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touched” count value. The delta is an instantaneous change and is updated once per sensor per
sensing cycle (see Section 4.5.1 - sensor cycle).
The value presented is a standard 2’s complement number. In addition, the value is capped at a value
of 7Fh. A reading of 7Fh indicates that the sensitivity settings are too high and should be adjusted
accordingly (see Section 5.5).
The value is also capped at a negative value of FFh for negative delta counts which may result upon
a release.
5.5 Sensitivity Control Register
Table 5.6 Data Scaling Register
1Fh R/W Sensitivity Control - DELTA_SENSE[2:0] BASE_SHIFT[3:0] 2Fh
The Sensitivity Control register controls the sensitivity of a touch detection.
Bits 6- 4 DELTA_SENSE[2:0] - Controls the sensitivity of a touch detection. The sensitivity settings act
to scale the relative delta count value higher or lower based on the system parameters. A setting of
000b is the most sensitive while a setting of 111b is the least sensitive. At the more sensitive settings,
touches are detected for a smaller delta C corresponding to a “lighter” touch. These settings are more
sensitive to noise however and a noisy environment may flag more false touches than higher sensitivity
levels.
APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the
MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch
of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base
capacitance). Conversely a value of 1x is the least sensitive setting available. At these
settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts
out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance
(or a ΔC of 3.33pF from a 10pF base capacitance).
Table 5.7 DELTA_SENSE Bit Decode
DELTA_SENSE[2:0]
2 1 0 SENSITIVITY MULTIPLIER
0 0 0 128x (most sensitive)
0 0 1 64x
0 1 0 32x (default)
0 1 1 16x
1 0 0 8x
1 0 1 4x
1 1 0 2x
1 1 1 1x - (least sensitive)
Bits 3 - 0 - BASE_SHIFT[3:0] - Controls the scaling and data presentation of the Base Count registers.
The higher the value of these bits, the larger the range and the lower the resolution of the data

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presented. The scale factor represents the multiplier to the bit-weighting presented in these register
descriptions.
APPLICATION NOTE: The BASE_SHIFT[3:0] bits normally do not need to be updated. These settings will not affect
touch detection or sensitivity. These bits are sometimes helpful in analyzing the Cap Sensing
board performance and stability.
Table 5.8 BASE_SHIFT Bit Decode
BASE_SHIFT[3:0]
DATA SCALING
3 2 1 0 FACTOR
0 0 0 0 1x
0 0 0 1 2x
0 0 1 0 4x
0 0 1 1 8x
0 1 0 0 16x
0 1 0 1 32x
0 1 1 0 64x
0 1 1 1 128x
1 0 0 0 256x
256x
All others
(default = 1111b)
5.6 Configuration Register
Table 5.9 Configuration Register
WAKE_ BLK_ DIG_ BLK_ ANA_ MAX_DUR_

20h R/W Configuration TIMEOUT - - - 20h
CFG NOISE NOISE EN
The Configuration register controls general global functionality that affects the entire device.
Bit 7 - TIMEOUT - Enables the timeout and idle functionality of the SMBus protocol.
‘0’ (default) - The SMBus timeout and idle functionality are disabled. The SMBus interface will not
time out if the clock line is held low. Likewise, it will not reset if both the data and clock lines are
held high for longer than 150us. This is used for I2C compliance.
‘1’ - The SMBus timeout and idle functionality are enabled. The SMBus interface will time out if the
clock line is held low for longer than 30ms. Likewise, it will reset if both the data and clock lines
are held high for longer than 150us.
Bit 6 - WAKE_CFG - Configures the operation of the WAKE pin.

‘0’ (default) - The WAKE pin is not asserted when a touch is detected while the device is in Standby.
It will still be used to wake the device from Deep Sleep when driven high.

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‘1’ - The WAKE pin will be asserted high when a touch is detected while the device is in Standby.
It will also be used to wake the device from Deep Sleep when driven high.
Bit 5 - BLK_DIG_NOISE - Determines whether the digital noise threshold is used by the device.
‘0’ - The digital noise threshold is used. If a delta count value exceeds the noise threshold but does
not exceed the touch threshold, then the sample is discarded and not used for the automatic re-
calibration routine.
‘1’ (default) - The noise threshold is not used. Any delta count that is less than the touch threshold
is used for the automatic re-calibration routine.
Bit 4 - BLK_ANA_NOISE - Determines whether the analog noise flag setting will block a touch
detection as well as the analog calibration routine.
‘0’ (default) - If the analog noise bit is set, then a touch is blocked on the corresponding channel
and will force the analog calibration routine to retry.
‘1’ - A touch is not blocked even if the analog noise bit is set. Likewise, the analog calibration
routine will not retry if the analog noise bit is set.
Bit 3 - MAX_DUR_EN - Determines whether the maximum duration recalibration is enabled for non-
grouped sensors.
‘0’ (default) - The maximum duration recalibration functionality is disabled. A touch may be held
indefinitely and no re-calibration will be performed on any sensor.
‘1’ - The maximum duration recalibration functionality is enabled. If a touch is held for longer than
the MAX_DUR bit settings, then the re-calibration routine will be restarted (see Section 5.8).
5.7 Sensor Enable Registers
Table 5.10 Sensor Enable Registers
21h R/W Sensor Enable CS8_EN CS7_EN CS6_EN CS5_EN CS4_EN CS3_EN CS2_EN CS1_EN FFh
The Sensor Enable registers determine whether a Capacitive Touch Sensor input is included in the
sampling cycle. The length of the sampling cycle is not affected by the number of sensors measured.
Bit 7 - CS8_EN - Enables the CS8 input to be included during the sampling cycle.
‘0’ - The CS8 input is not included in the sampling cycle.
‘1’ (default) - The CS8 input is included in the sampling cycle.

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5.8 Sensor Configuration Register
Table 5.11 Sensor Configuration Register
Sensor
22h R/W MAX_DUR[3:0] RPT_RATE[3:0] A4h
Configuration
The Sensor Configuration Register controls timings associated with the Capacitive Sensor channels 1
- 8.
Bits 7 - 4 - MAX_DUR[3:0] - (default 1010b) - Determines the maximum time that a sensor is allowed
to be touched until the Capacitive Touch sensor is recalibrated as shown in Table 5.12.
Table 5.12 MAX_DUR Bit Decode
MAX_DUR[3:0]
3 2 1 0 TIME BEFORE RECALIBRATION
0 0 0 0 560ms
0 0 0 1 840ms
0 0 1 0 1120ms
0 0 1 1 1400ms
0 1 0 0 1680ms
0 1 0 1 2240ms
0 1 1 0 2800ms
0 1 1 1 3360ms
1 0 0 0 3920ms
1 0 0 1 4480ms
1 0 1 0 5600ms
1 0 1 1 6720ms
1 1 0 0 7840ms
1 1 0 1 8906ms
1 1 1 0 10080ms
1 1 1 1 11200ms
Bits 3 - 0 - RPT_RATE[3:0] - (default 0100b) Determines the time duration between interrupt assertions
when auto repeat is enabled. The resolution is 35ms the range is from 35ms to 560ms as shown in
Table 5.13.

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Table 5.13 RPT_RATE Bit Decode
RPT_RATE[3:0] OR M_PRESS[3:0]
INTERRUPT REPEAT RATE
3 2 1 0 OR M_PRESS TIME
0 0 0 0 35ms
0 0 0 1 70ms
0 0 1 0 105ms
0 0 1 1 140ms
0 1 0 0 175ms
0 1 0 1 210ms
0 1 1 0 245ms
0 1 1 1 280ms
1 0 0 0 315ms
1 0 0 1 350ms
1 0 1 0 385ms
1 0 1 1 420ms
1 1 0 0 455ms
1 1 0 1 490ms
1 1 1 0 525ms
1 1 1 1 560ms
5.9 Sensor Configuration 2 Register
Table 5.14 Sensor Configuration 2 Register
Sensor
23h R/W - - - - M_PRESS[3:0] 07h
Configuration 2
Bits 3- 0 - M_PRESS[3:0] - (default 0111b) - Determines the minimum amount of time that sensors
configured to use auto repeat must detect a sensor touch to detect a “press and hold” event. If the
sensor detects a touch for longer than the M_PRESS[3:0] settings, then a “press and hold” event is
detected.
This is the maximum amount of time that sensors can detect a sensor touch to differentiate between
a “touch” and a “press and hold”. If a sensor detects a touch for less than or equal to the
M_PRESS[3:0] settings, then a touch event is detected.
The resolution is 35ms the range is from 35ms to 560ms as shown in Table 5.13.

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5.10 Averaging and Sampling Configuration Register
Table 5.15 Averaging and Sampling Configuration Register
24h R/W Averaging and AVG[2:0] SAMP_ CYCLE_TIME 1Dh

Sampling Config TIME [1:0]
The Averaging and Sampling Configuration register controls the number of samples taken and the total
sensor cycle time for all active sensors while the device is functioning normally.
Bits 5 - 3 - AVG[2:0] - Determines the number of samples that are taken for all active channels during
the sensor cycle as shown in Table 5.16. All samples are taken consecutively on the same channel
before the next channel is sampled and the result is averaged over the number of samples measured
before updating the measured results.
For example, if CS1, CS2, and CS3 are sampled during the sensor cycle, and the AVG[2:0] bits are
set to take 4 samples per channel, then the full sensor cycle will be: CS1, CS1, CS1, CS1, CS2, CS2,
CS2, CS2, CS3, CS3, CS3, CS3.
Table 5.16 AVG Bit Decode
AVG[2:0]
NUMBER OF SAMPLES TAKEN
2 1 0 PER MEASUREMENT
0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8 (default)
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128
Bit 2 - SAMP_TIME - Determines the sampling time.

‘0’ - The sampling time is ~2.56ms for each sensor.
‘1’ (default) - The sampling time is ~1.28ms for each sensor.
Bits 1 - 0 - CYCLE_TIME[1:0] - Determines the overall cycle time for all measured channels during
normal operation as shown in Table 5.17. All measured channels are sampled at the beginning of the
cycle time. If additional time is remaining, then the device is placed into a lower power state for the
remaining duration of the cycle.

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Table 5.17 CYCLE_TIME Bit Decode
CYCLE_TIME[1:0]
1 0 OVERALL CYCLE TIME
0 0 35ms
0 1 70ms (default)
1 0 105ms
1 1 140ms
APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is
less than the programmed cycle. The AVG[2:0] bits will take priority so that if more samples
are required than would normally be allowed during the cycle time, the cycle time will be
extended as necessary to accommodate the number of samples to be measured.
5.11 Calibration Activate Registers
Table 5.18 Calibration Activate Registers
Calibration
26h R/W CS8_CAL CS7_CAL CS6_CAL CS5_CAL CS4_CAL CS3_CAL CS2_CAL CS1_CAL FFh
Activate
The Calibration Activate register force the respective sensors to be re-calibrated. When a bit is set,
the corresponding Capacitive Touch Sensor will be re-calibrated and the bit will be automatically
cleared once the re-calibration routine has finished. During the re-calibration routine, the sensors will
not detect a press for up to 600ms and the Sensor Base Count register values will be invalid. During
this time, any press on the corresponding sensors will invalidate the re-calibration.
Bit 7 - CS8_CAL - When set, the CS8 input is re-calibrated. This bit is automatically cleared once the
sensor has been re-calibrated successfully.

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5.12 Interrupt Enable Register
Table 5.19 Interrupt Enable Register
27h R/W Interrupt CS8_ CS7_ CS6_ CS5_ CS4_ CS3_ CS2_ CS1_ FFh
Enable INT_EN INT_EN INT_EN INT_EN INT_EN INT_EN INT_EN INT_EN
The Interrupt Enable registers determine whether a sensor touch or release causes the interrupt pin
to be asserted.
Bit 7 - CS8_INT_EN - Enables the interrupt pin to be asserted if a touch is detected on CS8
(associated with the CS8 status bit).
‘0’ - The interrupt pin will not be asserted if a touch is detected on CS8 (associated with the CS8
status bit).
‘1’ (default) - The interrupt pin will be asserted a touch is detected on CS8 (associated with the
CS8 status bit).
5.13 Repeat Rate Enable Register
Table 5.20 Repeat Rate Enable Register
Repeat Rate CS8_ CS7_ CS6_ CS5_ CS4_ CS3_ CS2_ CS1_
28h R/W Enable RPT_EN RPT_EN RPT_EN RPT_EN RPT_EN RPT_EN RPT_EN RPT_EN FFh
The Repeat Rate Enable register determines the interrupt behavior of the buttons as described in
Section 4.6.1.
Bit 7 - CS8_RPT_EN - Enables the repeat rate for Capacitive Touch Sensor 8.
‘0’ - The repeat rate for CS8 is disabled. It will only generate an interrupt when a touch is detected
and when a release is detected no matter how long the touch is held for.
‘1’ (default) - The repeat rate for CS8 is enabled. In the case of a “touch” event, it will generate an
interrupt when a touch is detected and a release is detected. In the case of a “press and hold”
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event, it will generate an interrupt when a touch is detected and at the repeat rate so long as the
touch is held. It will not generate an interrupt when a release is detected.
5.14 Multiple Touch Configuration Register
Table 5.21 Multiple Touch Configuration
2Ah R/W Multiple Touch MULT_ - - - B_MULT_T[1:0] - - 80h

Config BLK_EN
The Multiple Touch Configuration register controls the settings for the multiple touch detection circuitry.
These settings determine the number of simultaneous buttons that may be pressed before action is
taken.
Bit 7 - MULT_BLK_EN - Enables the multiple button blocking circuitry.

‘0’ - The multiple touch circuitry is disabled. The device will not block multiple touches.
‘1’ (default)- The multiple touch circuitry is enabled. The device will accept the number of touches
equal to programmed multiple touch threshold and block all others. It will remember which sensor
is valid and block all others until that sensor has been released.
Bits 3 - 2 - B_MULT_T[1:0] - Determines the number of simultaneous touches on all sensors before a
Multiple Touch Event is flagged. If the number of multiple sensors touched is greater than the threshold
value then a Multiple Touch Event is flagged. The bit decode is given by Table 5.22.
Table 5.22 B_MULT_T Bit Decode
B_MULT_T[1:0]
1 0 NUMBER OF SIMULTANEOUS TOUCHES
0 0 1 (default)
0 1 2
1 0 3
1 1 4

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5.15 Recalibration Configuration Register
Table 5.23 Recalibration Configuration Registers
Recalibration BUT_ NEG_DELTA_

2Fh R/W - - CAL_CFG[2:0] 8Bh
Configuration LD_TH CNT[1:0]
The Recalibration Configuration register controls the automatic re-calibration routine settings as well
as advanced controls to program the Sensor Threshold register settings.
Bit 7 - BUT_LD_TH - Enables setting all Sensor Threshold registers by writing to the Sensor 1
Threshold register.
‘0’ - Each Sensor X Threshold register is updated individually.
‘1’ (default) - Writing the Sensor 1 Threshold register will automatically overwrite the Sensor
Threshold registers for all sensors (Sensor Threshold 1 through Sensor Threshold 8). The
individual Sensor X Threshold registers (Sensor 2 Threshold through Sensor 8 Threshold) can be
individually updated at any time.
Bits 4 - 3 - NEG_DELTA_CNT[1:0] - Determines the number of negative delta counts necessary to

trigger a digital re-calibration as shown in Table 5.24.
Table 5.24 NEG_DELTA_CNT Bit Decode
NEG_DELTA_CNT[1:0]
NUMBER OF CONSECUTIVE NEGATIVE DELTA
1 0 COUNT VALUES
0 0 8
0 1 16 (default)
1 0 32
1 1 None (disabled)
Bits 2 - 0 - CAL_CFG[2:0] - Determines the update time and number of samples of the automatic re-
calibration routine. The settings applies to all sensors universally (though individual sensors can be
configured to support re-calibration - see Section 5.11).
Table 5.25 CAL_CFG Bit Decode
CAL_CFG[2:0] RECALIBRATION
SAMPLES (SEE UPDATE TIME (SEE
2 1 0 Note 5.1) Note 5.2)
0 0 0 16 16
0 0 1 32 32
0 1 0 64 64
0 1 1 256 256 (default)
1 0 0 256 1024

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Datasheet
Table 5.25 CAL_CFG Bit Decode (continued)
CAL_CFG[2:0] RECALIBRATION
SAMPLES (SEE UPDATE TIME (SEE
2 1 0 Note 5.1) Note 5.2)
1 0 1 256 2048
1 1 0 256 4096
1 1 1 256 7936
Note 5.1 Recalibration Samples refers to the number of samples that are measured and averaged
before the Base Count is updated.
Note 5.2 Update Time refers to the amount of time (in polling cycle periods) that elapses before the
Base Count is updated.
5.16 Sensor Threshold Registers
Table 5.26 Sensor Threshold Registers
Sensor 1
30h R/W - 64 32 16 8 4 2 1 40h
Threshold
Sensor 2
31h R/W - 64 32 16 8 4 2 1 40h
Threshold
Sensor 3
32h R/W - 64 32 16 8 4 2 1 40h
Threshold
Sensor 4
33h R/W - 64 32 16 8 4 2 1 40h
Threshold
Sensor 5
34h R/W - 64 32 16 8 4 2 1 40h
Threshold
Sensor 6
35h R/W - 64 32 16 8 4 2 1 40h
Threshold
Sensor 7
36h R/W - 64 32 16 8 4 2 1 40h
Threshold
Sensor 8
37h R/W - 64 32 16 8 4 2 1 40h
Threshold
The Sensor Threshold registers store the delta threshold that is used to determine if a touch has been
detected. When a touch occurs, the input signal of the corresponding sensor changes due to the
capacitance associated with a touch. If the sensor input change exceeds the threshold settings, then
a touch is detected.
When the BUT_LD_TH bit is set (see Section 5.15 - bit 7), writing data to the Sensor 1 Threshold
register will update all of the sensor threshold registers (31h - 37h inclusive).

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5.17 Sensor Noise Threshold Registers
Table 5.27 Sensor Noise Threshold Registers
Sensor Noise CS4_BN_TH CS3_BN_TH CS2_BN_TH CS1_BN_TH

38h R/W 55h
Threshold 1 [1:0] [1:0] [1:0] [1:0]
Sensor Noise CS8_BN_TH CS7_BN_TH CS6_BN_TH CS5_BN_TH

39h R/W 55h
Threshold 2 [1:0] [1:0] [1:0] [1:0]
The Sensor Noise Threshold registers control the value of a secondary internal threshold to detect
noise and improve the automatic recalibration routine. If a Capacitive Touch Sensor output exceeds
the Sensor Noise Threshold but does not exceed the sensor threshold, then it is determined to be
caused by a noise spike. That sample is not used by the automatic re-calibration routine.
The Sensor Noise Threshold is proportional to the programmed threshold as shown in Table 5.28.
Table 5.28 CSx_BN_TH Bit Decode
CSX_BN_TH[1:0]
1 0 THRESHOLD DIVIDE SETTING
0 0 25%
0 1 37.5% (default)
1 0 50%
1 1 62.5%
5.17.1 Sensor Noise Threshold 1 Register

The Sensor Noise Threshold 1 register controls the noise threshold for Capacitive Touch Sensors 1-4.
Bits 7-6 - CS4_BN_TH[1:0] - Controls the noise threshold for Capacitive Touch Sensor 4.
5.17.2 Sensor Noise Threshold 2 Register

The Sensor Noise Threshold 2 register controls the noise threshold for Capacitive Touch Sensors 5 - 8.

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5.18 Standby Channel Register
Table 5.29 Standby Channel Register
Standby CS8_ CS7_ CS6_ CS5_ CS4_ CS3_ CS2_ CS1_

40h R/W 00h
Channel STBY STBY STBY STBY STBY STBY STBY STBY
The Standby Channel register controls which (if any) Capacitive Touch Sensors are active during
Standby.
Bit 7 - CS8_STBY - Controls whether the CS8 channel is active in Standby.

‘0’ (default) - The CS8 channel not be sampled during Standby.
‘1’ - The CS8 channel will be sampled during Standby. It will use the Standby threshold setting, and
the standby averaging and sensitivity settings.
5.19 Standby Configuration Register
Table 5.30 Standby Configuration Register
STBY_
Standby AVG_ STBY_CY_TIME
41h R/W Configuration SUM - STBY_AVG[2:0] SAMP_ [1:0] 1Dh
TIME
The Standby Configuration register controls averaging and cycle time for those sensors that are active
in Standby.
Bit 7 - AVG_SUM - Determines whether the active sensors will average the programmed number of
samples or whether they will accumulate for the programmed number of samples.
‘0’ - (default) - The active sensor delta count values will be based on the average of the
programmed number of samples when compared against the threshold.
‘1’ - The active sensor delta count values will be based on the summation of the programmed
number of samples when compared against the threshold.
Bits 5 - 3 - STBY_AVG[2:0] - Determines the number of samples that are taken for all active channels
during the sensor cycle as shown in Table 5.31. All samples are taken consecutively on the same
channel before the next channel is sampled and the result is averaged over the number of samples
measured before updating the measured results.

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Table 5.31 STBY_AVG Bit Decode
STBY_AVG[2:0]
NUMBER OF SAMPLES TAKEN
2 1 0 PER MEASUREMENT
0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8 (default)
1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128
Bit 2 - STBY SAMP_TIME - Determines the sampling time used while in Standby.
‘0’ - The sampling time is ~2.56ms for each sensor.
‘1’ (default) - The sampling time is ~1.28ms for each sensor.
Bits 1 - 0 - STBY_CY_TIME[2:0] - Determines the overall cycle time for all measured channels during
normal operation as shown in Table 5.17. All measured channels are sampled at the beginning of the
cycle time. If additional time is remaining, then the device is placed into a lower power state for the
remaining duration of the cycle.
Table 5.32 STBY_CY_TIME Bit Decode
STBY_CY_TIME[1:0]
1 0 OVERALL CYCLE TIME
0 0 35ms
0 1 70ms (default)
1 0 105ms
1 1 140ms
APPLICATION NOTE: The programmed cycle time is only maintained if the total averaging time for all samples is
less than the programmed cycle. The STBY_AVG[2:0] bits will take priority so that if more
samples are required than would normally be allowed during the cycle time, the cycle time
will be extended as necessary to accommodate the number of samples to be measured.

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5.20 Standby Sensitivity Register
Table 5.33 Standby Configuration Register
Standby
42h R/W - - - - - STBY_SENSE[2:0] 02h
Sensitivity
The Standby Sensitivity register controls the sensitivity for sensors that are active in Standby.
Bits 2 - 0 - STBY_SENSE[2:0] - Controls the sensitivity for sensors that are active in Standby. The
sensitivity settings act to scale the relative delta count value higher or lower based on the system
parameters. A setting of 000b is the most sensitive while a setting of 111b is the least sensitive. At the
more sensitive settings, touches are detected for a smaller delta C corresponding to a “lighter” touch.
These settings are more sensitive to noise however and a noisy environment may flag more false
touches than higher sensitivity levels.
APPLICATION NOTE: A value of 128x is the most sensitive setting available. At the most sensitivity settings, the
MSB of the Delta Count register represents 64 out of ~25,000 which corresponds to a touch
of approximately 0.25% of the base capacitance (or a ΔC of 25fF from a 10pF base
capacitance). Conversely a value of 1x is the least sensitive setting available. At these
settings, the MSB of the Delta Count register corresponds to a delta count of 8192 counts
out of ~25,000 which corresponds to a touch of approximately 33% of the base capacitance
(or a ΔC of 3.33pF from a 10pF base capacitance).
Table 5.34 STBY_SENSE Bit Decode
STBY_SENSE[2:0]
2 1 0 SENSITIVITY MULTIPLIER
0 0 0 128x (most sensitive)
0 0 1 64x
0 1 0 32x (default)
0 1 1 16x
1 0 0 8x
1 0 1 4x
1 1 0 2x
1 1 1 1x - (least sensitive)
5.21 Standby Threshold Register
Table 5.35 Standby Threshold Register
Standby
43h R/W - 64 32 16 8 4 2 1 40h
Threshold

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The Standby Threshold registers stores the delta threshold that is used to determine if a touch has
been detected. When a touch occurs, the input signal of the corresponding sensor changes due to the
capacitance associated with a touch. If the sensor input change exceeds the threshold settings, then
a touch is detected.
5.22 Sensor Base Count Registers
Table 5.36 Sensor Base Count Registers
Sensor 1 Base
50h R 128 64 32 16 8 4 2 1 C8h
Count
Sensor 2 Base
51h R 128 64 32 16 8 4 2 1 C8h
Count
Sensor 3 Base
52h R 128 64 32 16 8 4 2 1 C8h
Count
Sensor 4 Base
53h R 128 64 32 16 8 4 2 1 C8h
Count
Sensor 5 Base
54h R 128 64 32 16 8 4 2 1 C8h
Count
Sensor 6 Base
55h R 128 64 32 16 8 4 2 1 C8h
Count
Sensor 7 Base
56h R 128 64 32 16 8 4 2 1 C8h
Count
Sensor 8 Base
57h R 128 64 32 16 8 4 2 1 C8h
Count
The Sensor Base Count registers store the calibrated “Not Touched” input value from the Capacitive
Touch Sensor inputs. These registers are periodically updated by the re-calibration routine.
The routine uses an internal adder to add the current count value for each reading to the sum of the
previous readings until sample size has been reached. At this point, the upper 16 bits are taken and
used as the Sensor Base Count. The internal adder is then reset and the re-calibration routine
continues.
The data presented is determined by the BASE_SHIFT[3:0] bits (see Section 5.5).
5.23 LED Output Type Register
Table 5.37 LED Output Type Register
LED Output LED8_ LED7_ LED6_ LED5_ LED4_ LED3_ LED2_ LED1_
71h R/W 00h
Type OT OT OT OT OT OT OT OT
The LED Output Type register controls the type of output for the LED pins. Each pin is controlled by
a single bit.

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Bit 7 - LED8_OT - Determines the output type of the LED8 pin.

‘0’ (default) - The LED8 pin is an open-drain output with an external pull-up resistor. When the
appropriate pin is set to the “active“ state (logic ‘1’) then the pin will be driven low. Conversely,
when the pin is set to the “inactive” state (logic ‘0’), then the pin will be left in a High Z state and
pulled high via an external pull-up resistor.
‘1’ - The LED8 pin is a push-pull output. When driving a logic ‘1’ the pin is driven high. When driving
a logic ‘0’ the pin is driven low.
5.24 Sensor LED Linking Register
Table 5.38 Sensor LED Linking Register
Sensor LED CS8_ CS7_ CS6_ CS5_ CS4_ CS3_ CS2_ CS1_
72h R/W Linking LED8 LED7 LED6 LED5 LED4 LED3 LED2 LED1 00h
The Sensor LED Linking registers control whether a Capacitive Touch Sensor is linked to an LED
output or not. If the corresponding bit is set, then the appropriate LED output will change states defined
by the LED Behavior controls (see Section 5.27) in response to the Capacitive Touch sensor.
Bit 7 - CS8_LED8 - Links the LED8 output to a detected touch on the CS8 sensor. When a touch is
detected, the LED is actuated and will behave as determined by the LED Behavior controls.
‘0’ (default) - The LED8 output is not associated with a the CS8 input. If a touch is detected on the
CS8 input, then the LED will not automatically be actuated. The LED is enabled and controlled via
the LED Output Configuration register (see Section 5.24) and the LED Behavior registers (see
Section 5.27).
‘1’ - The LED8 output is associated with the CS8 input. If a touch is detected on the CS8 input
then the LED will be actuated and behave as defined in Table 5.43.

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5.25 LED Polarity Register
Table 5.39 LED Polarity Register
LED8_ LED7_ LED6_ LED5_ LED4_ LED3_ LED2_ LED1_

73h R/W LED Polarity POL POL POL POL POL POL POL POL 00h
The LED Polarity registers control the logical polarity of the LED outputs.
APPLICATION NOTE: The polarity controls determine the final LED pin drive. A touch on a linked Capacitive Touch
Sensor is treated in the same way as the LED Output Control bit being set to a logic ‘1’.
APPLICATION NOTE: For LED operation, the duty cycle settings determine the % of time that the LED pin will be
driven to a logic ‘1’ state in a non-inverted system or to a logic ‘0’ state in an inverted system.
The duty cycle settings operate independently of the polarity controls. Therefore, the Max
Duty Cycle settings define the maximum % of time that the LED pin will be driven high in a
non-inverted system while the Min Duty Cycle settings determine the minimum % of time that
the LED pin will be driven high in a non-inverted system.
The LED drive assumes that the LEDs are configured such that if the LED pin is driven to
a logic ‘0’ then the LED will be on and that the CAP1088 LED pin is sinking the LED current.
Conversely, if the LED pin is driven to a logic ‘1’ then the LED will be off and there is no
current flow.
Finally, the breathe operations will always ramp the duty cycle from the minimum duty cycle
to the maximum duty cycle and then back down to the minimum duty cycle.
The LED Polarity controls lead to two conditions that have the apparent effect of changing
the duty cycle settings. If an LED output is non-inverted then the Maximum Duty Cycle
settings will define the maximum % of time that the LED is off. Conversely the Minimum
Duty Cycle settings will define the minimum % of time that the LED is off. As well, when
there is no touch detected or the LED Output Control register bit is at a logic ‘0’ then the
LED output will be driven at the minimum duty cycle setting. The relative brightness will then
ramp from maximum to minimum and back.
If an LED output is inverted, then the Maximum Duty Cycle settings will define the maximum
% of time that the LED is on and the Minimum Duty Cycle settings will determine the
minimum % of time that the LED is on. As well, when there is no touch detected, or the LED
Output Control register bit is at a logic ‘0’, then the LED output will be driven at the minimum
duty cycle setting. The relative brightness will then ramp from minimum to maximum and
back.
Bit 7 - LED8_POL - Determines the polarity of the LED8 output.

‘0’ (default) - The LED8 output is inverted. A setting of ‘1’ in the LED Output Control register will
cause the output to be driven to a logic ‘0’ as determined by the LED behavior. Similarly, the duty
cycles corresponding to Pulse and Breathe operations will indicate the amount of time that the LED
is driven to a logic ‘0’ state (corresponding to “active”).
‘1’ - The LED8 output is non-inverted. A setting of ‘1’ in the LED Output Control register will cause
the output to be driven to a logic ‘1’ or left in the high-z state as determined by its output type and

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LED behavior. Similarly, the duty cycles corresponding to Pulse and Breathe operations will indicate
to the amount of time that the LED is driven to a logic ‘1’ state (corresponding to “inactive”).
5.26 LED Output Control Register
Table 5.40 LED Output Control Register
74h R/W LED Output LED8_ LED7_ LED6_ LED5_ LED4_ LED3_ LED2_ LED1_ 00h
Control DR DR DR DR DR DR DR DR
The LED Output Control Register controls the output state of the LED pins.
All LEDs that are associated with a Capacitive Touch Sensor channel are automatically enabled and
will be actuated per the LED Behavior.
For those LEDs that are not linked with a Capacitive Touch Sensor channel, then the bit state
determines whether the LED is actuated or not actuated.
The LED Polarity Control register will determine the non actuated state of the LED pins.
Table 5.41 shows the interaction between the polarity controls, output controls and relative brightness.
Table 5.41 LED Polarity Behavior
LED
OUTPUT
CONTROL LED LED
REGISTER POLARITY MAX DUTY MIN DUTY BEHAVIORS BRIGHTNESS APPEARANCE
maximum % of minimum % of
maximum brightness at on at minimum
0 inverted time that the LED time that the LED off
minimum duty cycle duty cycle
is on (logic 0) is on (logic 0)
maximum % of minimum % of maximum brightness at

according to
1 inverted time that the LED time that the LED on max duty cycle. Brightness
LED behavior
is on (logic 0) is on (logic 0) ramps from min to max
maximum % of minimum % of on at 100 - min

non- maximum brightness at 100
0 time that the LED time that the LED off duty cycle
inverted - min duty cycle
is off (logic 1) is off (logic 1) (Note 5.3)
maximum % of minimum % of maximum brightness at 100

non- according to
1 time that the LED time that the LED on - min duty cycle. Brightness
inverted LED behavior
is off (logic 1) is off (logic 1) ramps from max to min

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Datasheet
Note 5.3 For example: when polarity is non-inverted, if min duty cycle is 0, then the LED would be
at logic 1 (off) 0% of the time. It will be at logic 0 (on), 100% of the time (100 - min duty
cycle).
Bit 7 - LED8_DR - Determines whether the LED8 output is driven high or low.
‘0’ (default) - The LED8 output is driven at the minimum duty cycle or not actuated.
‘1’ - The LED8 output is driven at the maximum duty cycle or is actuated.
Bit 6 - LED7_DR - Determines whether LED7 output is driven high or low.
Bit 1 - LED2_DR - Determines whether LED2 output is driven high or low.Bit 0 - LED1_DR -
Determines whether LED1 output is driven high or low.
5.27 LED Behavior Registers
Table 5.42 LED Behavior Registers
81h R/W LED Behavior 1 LED4_CTL[1:0] LED3_CTL[1:0] LED2_CTL[1:0] LED1_CTL[1:0] 00h
82h R/W LED Behavior LED8_CTL[1:0] LED7_CTL[1:0] LED6_CTL[1:0] LED5_CTL[1:0] 00h
The LED Behavior registers control the operation of LEDs. Each LED pin is controlled by a 2-bit field
and the behavior is determined by whether the LED is linked to a Capacitive Touch Sensor or not.
If the corresponding LED output is linked to a Capacitive Touch Sensor than the Start and Stop triggers
are used. The defined behavior will activate when the Start Trigger is met and will stop when the Stop
Trigger is met.
If the LED output is not associated with a a Capacitive Touch Sensor, then the appropriate behavior
will be enabled / disabled by the LED Output Control register. If the respective LEDx_DR bit is set to
a logic ‘1’ then this will be associated as a “touch” and if the LEDx_DR bit is set to a logic ‘0’ then this
will be associated as a “release”.
The LED Polarity Control register will determine the non actuated state of the LED outputs. If the LED
Polarity Control register is set to be inverted (default), then an non actuated LED pin will be driven to
a logic ‘1’ state and the LED will be off. If the LED Polarity Control register is set to be non-inverted,
then the non actuated LED pin will be driven to the logic ’0’ state and the LED will be on.
APPLICATION NOTE: If an LED is not linked to a Capacitive Touch Sensor and is breathing (via the Breathe or
Pulse behaviors), it will finish its current “breath” before any changes to behavior are
processed.
APPLICATION NOTE: If an LED is not linked to the Capacitive Touch Sensor and configured to operate using Pulse
1 Behavior, then the circuitry will only be actuated when the corresponding bit is set. It will
not check the bit condition until the Pulse 1 behavior is finished. The device will not
remember if the bit was cleared and reset while it was actuated.
APPLICATION NOTE: If an LED is actuated and it is switched from linked to a Capacitive Touch Sensor to unlinked
(or vice versa), then the LED will respond to the new command source immediately. For

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example, if a linked LED was actuated by a touch and the control is changed so that it is
unlinked, it will check the status of the corresponding LED Output Control bit. If that bit is ‘0’,
then the LED will behave as if a release was detected. LIkewise, if an unlinked LED was
actuated by the LED Output Control register and the control is changed so that it is linked
and no touch is detected, then the LED will behave as if a release was detected.
APPLICATION NOTE: If the period for any breathe operation is changed while the LED is actuated, then the LED
output will be reset to 0% drive and any breathing will re-initiate at the new settings. For
Pulse 1 and Pulse 2 behaviors, the number of pulses will be retained.
5.27.1 LED Behavior 1 - 81h

Bits 7 - 6 - LED4_CTL[1:0] - Determines the behavior of LED4 as shown in Table 5.43.
5.27.2 LED Behavior 2 - 82h

Table 5.43 LEDx_CTL Bit Decode
LEDX_CTL
[1:0]
START STOP
1 0 OPERATION DESCRIPTION TRIGGER TRIGGER
Release
Touch Detected
The LED is driven to the programmed state Detected or
0 0 Direct or LED Control
(active or inactive). See Figure 5.5 LED Control
bit set
bit cleared
The LED will “Pulse” a programmed Touch or

number of times. During each “Pulse” the Release
LED will breathe up to the maximum Detected (See
0 1 Pulse 1 n/a
brightness and back down to the minimum Section 5.31) or
brightness so that the total “Pulse” period LED Control bit
matches the programmed value. set
The LED will Breathe when the start trigger Release

Touch Detected
is detected. When the stop trigger is Detected or
1 0 Pulse 2 or LED Control
detected, it will “Pulse” a number of times LED Control
bit set
then return to its minimum brightness. bit cleared
The LED will breathe. It will be driven with

a duty cycle that ramps up from the
programmed minimum duty cycle (default
Release
0%) to the programmed maximum duty Touch Detected
Detected or
1 1 Breathe cycle duty cycle (default 100%) and then or LED Control
LED Control
back down. Each ramp takes up 50% of the bit set
bit cleared
programmed period. The total period of
each “breath” is determined by the LED
Breathe Period controls - see Section 5.30.

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APPLICATION NOTE: The PWM frequency is determined based on the selected LED behavior, the programmed
breathe period, and the programmed min and max duty cycles. For the Direct Mode, the
PWM frequency is calculated based on the programmed Rise and Fall times. If these are
set at 0, then the maximum PWM frequency will be used based on the programmed duty
cycle settings.
5.28 LED Pulse 1 Period Register
Table 5.44 LED Pulse 1 Period Register
LED Pulse 1 ST_ P1_ P1_ P1_ P1_ P1_ P1_ P1_
84h R/W Period TRIG PER6 PER5 PER4 PER3 PER2 PER1 PER0 20h
The LED Pulse Period register determines the overall period of a pulse operation as determined by
the LED_CTL registers (see Table 5.43 - setting 01b). Each LSB represents 32ms so that a setting of
14h (20d) would represent a period of 640ms. The total range is from 32ms to 4.06 seconds as shown
in Table 5.45.
Bit 7 - ST_TRIG - Determines the start trigger for the LED Pulse behavior.
‘0’ (default) - The LED will Pulse when a touch is detected.
‘1’ - The LED will Pulse when a release is detected.
The Pulse 1 operation is shown in Figure 5.1 when the LED output is configured for non-inverted
polarity and in Figure 5.2 for inverted polarity.
.
Touch Detected or
Release Detected
X pulses after touch or after release
Normal – untouched Normal – untouched
operation (100% - Pulse 1 Min Duty Cycle) * Brightness operation
LED
Brightness
(100% - Pulse 1 Max Duty Cycle) * Brightness
Pulse 1 Period
(P1_PER)
Figure 5.1 Pulse Behavior with Non-Inverted Polarity

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Datasheet
Touch Detected or
Release Detected
X pulses after touch or after release
Pulse 1 Max Duty Cycle * Brightness
LED
Brightness
Normal – untouched
operation
Normal – untouched
operation Pulse 1 Min Duty Cycle * Brightness
Pulse Period
(P1_PER)
Figure 5.2 Pulse Behavior with Inverted Polarity
Table 5.45 LED Pulse / Breathe Period Example
SETTING TOTAL BREATHE / PULSE

(HEX) SETTING (DECIMAL) PERIOD (MS)
00h 0 32
01h 1 32
02h 2 64
03h 3 96
04h 4 128
... ... ...
7Ch 124 3,968
7Dh 125 4,000
7Eh 126 4,032
7Fh 127 4.064
5.29 LED Pulse 2 Period Register
Table 5.46 LED Pulse 2 Period Register
85h R/W LED Pulse 2 - P2_ P2_ P2_ P2_ P2_ P2_ P2_ 14h
Period PER6 PER5 PER4 PER3 PER2 PER1 PER0

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Datasheet
The LED Pulse 2 Period register determines the overall period of a pulse operation as determined by
the LED_CTL registers (see Table 5.43 - setting 10b). Each LSB represents 32ms so that a setting of
14h (20d) would represent a period of 640ms. The total range is from 32ms to 4.06 seconds (see
Table 5.45).
The Pulse 2 Behavior is shown in Figure 5.3 for non-inverted polarity and in Figure 5.4 for inverted
polarity.
Release Detected
Touch Detected
operation X additional pulses after release operation
(100% - Pulse 2 Min Duty Cycle) *
Brightness
LED
Brightness ...
Breathe (100% - Pulse 2 Max Duty Cycle) * Brightness

and Pulse
Period
(P2_PER)
Figure 5.3 Pulse 2 Behavior with Non-Inverted Polarity
Release Detected
Touch Detected
operation X additional pulses after release operation
Pulse 2 Max Duty Cycle * Brightness
LED
Brightness ...
Breathe Pulse 2 Min Duty Cycle * Brightness

and Pulse
Period
Figure 5.4 Pulse 2 Behavior with Inverted Polarity
5.30 LED Breathe Period Register
Table 5.47 LED Behavior Registers
LED Breathe BR_ BR_ BR_ BR_ BR_ BR_ BR_

86h R/W - 5Dh
Period PER6 PER5 PER4 PER3 PER2 PER1 PER0
The LED Breathe Period register determines the overall period of a breathe operation as determined
by the LED_CTL registers (see Table 5.43 - setting 11b). Each LSB represents 32ms so that a setting

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Datasheet
of 14h (20d) would represent a period of 640ms. The total range is from 32ms to 4.06 seconds (see
Table 5.45).
5.31 LED Configuration Register
Table 5.48 LED Configuration Registers
88h R/W LED Config - RAMP_ PULSE2_CNT[2:0] PULSE1_CNT[2:0] 04h

ALERT
The LED Configuration register controls general LED behavior as well as the number of pulses that
are sent for the PULSE LED output behavior.
Bit 6 - RAMP_ALERT - Determines whether the device will assert the ALERT# pin when LEDs
actuated by the LED Output Control register bits have finished their respective behaviors.
‘0’ (default) - The ALERT# pin will not be asserted when LEDs actuated by the LED Output Control
register have finished their programmed behaviors.
‘1’ - The ALERT# pin will be asserted whenever any LED that is actuated by the LED Output
Control register has finished its programmed behavior.
Bits 5 - 3 - PUSLE2_CNT[2:0] - Determines the number of pules used for the Pulse 2 behavior as
shown in Table 5.49.
Bits 2 - 0 - PULSE1_CNT[2:0] - Determines the number of pulses used for the Pulse 1 behavior as
Table 5.49 PULSEX_CNT Decode
PULSEX_CNT[2:0]
2 1 0 NUMBER OF BREATHS
0 0 0 1 (default - Pulse 2)
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5 (default - Pulse 1)
1 0 1 6
1 1 0 7
1 1 1 8

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5.32 LED Duty Cycle Registers
Table 5.50 LED Duty Cycle Registers
LED Pulse 1
90h R/W P1_MAX_DUTY[3:0] P1_MIN_DUTY[3:0] F0h
Duty Cycle
LED Pulse 2
91h R/W P2_MAX_DUTY[3:0] P2_MIN_DUTY[3:0] F0h
Duty Cycle
LED Breathe
92h R/W BR_MAX_DUTY[3:0] BR_MIN_DUTY[3:0] F0h
Duty Cycle
Direct Duty
93h R/W DR_MAX_DUTY[3:0] DR_MIN_DUTY[3:0] F0h
Cycle
The LED Duty Cycle registers determine the minimum and maximum duty cycle settings used for the
LED for each LED behavior. These settings affect the brightness of the LED when it is fully off and
fully on.
The LED driver duty cycle will ramp up from the minimum duty cycle (see Section 5.32) to the
maximum duty cycle and back down again.
APPLICATION NOTE: Changes to the Duty Cycle settings will be applied immediately. When the respective register
is written, the LED output will be reset to the minimum (or maximum) setting and restarted
at the updated settings.
APPLICATION NOTE: Upon power on reset (or upon release of the RESET pin), the first breath will breathe from
100% (or 0% duty cycle as determined by the polarity registers) to the programmed minimum
(or maximum as determined by the polarity registers) and then proceed normally.
Bits 7 - 4 - X_MAX_DUTY[3:0] - Determines the maximum PWM duty cycle for the LED drivers as
shown in Table 5.51
Bits 3 - 0 - X_MIN_DUTY[3:0] - Determines the minimum PWM duty cycle for the LED drivers as
Table 5.51 LED Duty Cycle Decode
X_MAX/MIN_DUTY [3:0]
3 2 1 0 DUTY CYCLE
0 0 0 0 1%
0 0 0 1 2%
0 0 1 0 3%
0 1 1 1 4%
0 1 0 0 5%
0 1 0 1 6%
0 1 1 0 7%
0 1 1 1 9%

DATASHEET
Datasheet
Table 5.51 LED Duty Cycle Decode (continued)
X_MAX/MIN_DUTY [3:0]
3 2 1 0 DUTY CYCLE
1 0 0 0 11%
1 0 0 1 14%
1 0 1 0 18%
1 0 1 1 25%
1 1 0 0 35%
1 1 0 1 50%
1 1 1 0 70%
1 1 1 1 99%
5.33 LED Direct Ramp Rates Register
Table 5.52 LED Direct Ramp Rates Register
LED Direct
94h R/W - - RISE_RATE[2:0] FALL_RATE[2:0] 00h
Ramp Rates
The LED Direct Ramp Rates register control the rising and falling edge time of an LED that is
configured to operate in Direct mode. The rising edge time corresponds to the amount of time the LED
takes to transition from its minimum duty cycle to its maximum duty cycle. Conversely, the falling edge
time corresponds to the amount of time that the LED takes to transition from its maximum duty cycle
to its minimum duty cycle.
Bits 5 - 3 - RISE_RATE[2:0] - Determines the rising edge time of an LED when it transitions from its
minimum drive state to its maximum drive state as shown in Table 5.53.
Bits 2 - 0 - FALL_RATE[2:0] - Determines the falling edge time of an LED when it transitions from its
maximum drive state to its minimum drive state as shown in Table 5.53.
Table 5.53 Rise / Fall Rate and Off Delay Decode
RISE_RATE/ FALL_RATE / DIR_OFF_DLY [2:0]

RISE / FALL TIME (TRISE / TFALL), OFF DELAY
2 1 0 (TOFF)
0 0 0 0
0 0 1 250ms
0 1 0 500ms
1 1 1 750ms
1 0 0 1s
1 0 1 1.25s

DATASHEET
Datasheet
Table 5.53 Rise / Fall Rate and Off Delay Decode (continued)
RISE_RATE/ FALL_RATE / DIR_OFF_DLY [2:0]

RISE / FALL TIME (TRISE / TFALL), OFF DELAY
2 1 0 (TOFF)
1 1 0 1.5s
1 1 1 2s
5.34 LED Off Delay Register
Table 5.54 LED Off Delay Register
LED Off Delay

95h R/W - - - - DIR_OFF_DLY [2:0] 00h
Register
The LED Off Delay register determines the amount of time an LED In Direct Mode remains active after
it is no longer actuated (such as after a release has been detected or the drive state has been
changed).
Bits 2 - 0 - DIR_OFF_DLY[2:0] - Determines the turn-off delay for all LEDs that are configured to
operate in Direct Mode as shown in Table 5.53.
The Direct Mode operation is determined by the combination of programmed Rise Time, Fall Time, Min
and Max Duty cycles, Off Delay, and polarity. Figure 5.5 shows the behavior for Non-Inverted polarity
while Figure 5.6 shows the behavior for inverted polarity.
N orm al – R elease
Touch Norm al –
untouched Detected
Detected untouched
operation
operation
(100% - M in D uty Cycle) *
LE D Brightness
Brightness
RISE _RATE (100% - M ax Duty

Setting (t RISE ) Cycle) * Brightness
O ff D elay FALL_RA TE
(t OFF _DLY ) Setting (t FA LL )
Figure 5.5 Direct Mode Behavior for Non-Inverted Polarity

DATASHEET
Datasheet
Touch R elease
D etected D etected
M ax D uty Cycle * B rightness

LE D
B rightness N orm al –
untouched
N orm al – M in D uty C ycle * B rightness operation
untouched
operation R IS E_R A TE
Setting (t R IS E ) O ff D elay FA LL_R A TE
(t O FF_D LY ) S etting (t FA LL )
Figure 5.6 Direct Mode Behavior for Inverted Polarity
5.35 Product ID Register
Table 5.55 Product ID Register
FDh R Product ID 0 1 0 0 0 0 0 0 40h
The Product ID register stores a unique 8-bit value that identifies the device.
5.36 Manufacturer ID Register
Table 5.56 Vendor ID Register
FEh R Manufacturer ID 0 1 0 1 1 1 0 1 5Dh
The Vendor ID register stores an 8-bit value that represents SMSC.
5.37 Revision Register
Table 5.57 Revision Register
FFh R Revision 1 0 0 0 0 0 0 0 80h
The Revision register stores an 8-bit value that represents the part revision.

DATASHEET
Datasheet
Chapter 6 Package Information

6.1 CAP1088 Package Drawings
Figure 6.1 CAP1088 Package Drawing - 24-Pin QFN 4mm x 4mm

DATASHEET
Datasheet
Figure 6.2 CAP1088 Package Dimensions - 24-Pin QFN 4mm x 4mm
Figure 6.3 CAP1088 PCB Footprint - 24-pin QFN 4mm x 4mm

DATASHEET
Datasheet
6.2 Package Marking
TOP
0.41
LINE: 1 – SMSC Logo without circled (R) symbol

3x 0.56
LINE: 2 – Device Number 1 0 8 8 - 1
LINE: 3 – Last 7 digits of Lot Number 1 2 3 4 5 6 a
LINE: 4 – Revision and Country Code (RCC) RCC e3
PIN 1 PB-FREE/GREEN SYMBOL

(Matte Sn)
LINES 1 to 3: CENTER HORIZONTAL ALIGNMENT
LINE 4: LEFT HORIZONTAL ALIGNMENT
BOTTOM
BOTTOM MARKING NOT ALLOWED
Figure 6.4 CAP1088 Package Markings

DATASHEET
Datasheet
Chapter 7 Revision History
Table 7.1 Customer Revision History
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION
Rev. 1.0 Section 3.1, Updated paragraph to describe proper

(06-11-09) "Communications" ADDR_COMM pin function
Rev. 1.0 Section 4.3, Updated text for wake pin during Deep Sleep
(06-11-09) "WAKE/SPI_MOSI Pin
Operation"
Rev. 1.0 Chapter 1, Pin Description Updated pin description for WAKE/SPI_MOSI pin
(06-11-09) to identify that it can be an input during Deep
Sleep.
Rev. 1.0 Figure 4.1, "System Updated system diagram for proper ADDR_COMM
(06-11-09) Diagram for CAP1088" pin usage. Changed from pull-up to VDD to pull-
down to GND
Rev. 1.0 Grammar and/or formatting changes throughout document

(06-11-09)
Rev. 1.0 Features and General Description modified

(06-10-09)
Rev. 1.0 Section 3.7, "BC-Link Removed “8051” from 2nd paragraph
(06-10-09) Interface"
Rev. 1.0 Pin Description Pin tables modified adding SPI to “ALERT# /
(06-10-09) BC_IRQ#” pin
Rev. 1.0 Table 3.1, "ADDR_COMM “/I2C” added “SMBus” in “Protocol Used” column
(06-10-09) Pin Decode"
y/Rev. 1.0 Chapter 4, General Second to last paragraph removed, not needed as
(06-10-09) Description clarification follows
Rev. 1.0 Section 4.1, "Power States" Removed mention of LED driver outputs
(06-10-09)
Rev. 1.0 Section 4.2, "RESET Pin" Modified to indicate all communication buses
(06-10-09)
Rev. 1.0 Section 4.4, "LED Drivers" “Pulse 1” modified

(06-10-09)
Rev. 1.0 Section 4.4, "LED Drivers" Updated text for # of LEDs
(06-04-09)
Rev. 1.0 Table 5.1, "Register Set in Updated text and register descriptions for incorrect
(06-04-09) Hexadecimal Order" #’s Cap Sense channels
Rev 1.0 Figure 3.1, "SPI Timing" Updated figure

(06-04-09)
Rev. 1.0 Note following Table 2.1, Text modified from “0.3 (12mil)” to “0.3mm (12mil)”
(06-02-09) "Absolute Maximum
Ratings"
Rev. 0.56 (5/1/09) General Fixed typos and updated text as necessary.
Cleaned up system diagrams

DATASHEET
Datasheet
Table 7.1 Customer Revision History (continued)
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY CORRECTION
Rev. 0.54 (4/24/09) Figure 4.1, "System Updated figures for pin names
Diagram for CAP1088"
Rev. 0.54 (4/24/09) General Fixed typos
Rev. 0.54 (4/24/09) Section 5.5, "Sensitivity Renamed bit fields

Control Register"
Rev. 0.54 (4/24/09) Section 5.6, "Configuration Renamed bits 5 and 6

Register"
Rev. 0.53 (4/23/09) Section 3.4, "SPI Interface" Updated section to describe Normal operation
Rev. 0.52 (4/17/09) General Initial document creation

DATASHEET

8 Channel Capacitive Touch Sensor CAP1088

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CAP1088

PRODUCT FEATURES Datasheet

General Description Applications

LED1 LED2 LED3 LED4 RESET VDD GND WAKE / SPI_MOSI

SMSC CAP1088 DATASHEET Revision 1.0 (06-16-09)

ORDERING NUMBER PACKAGE FEATURES

REEL SIZE IS 4,000 PIECES

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Copyright © 2009 SMSC or its subsidiaries. All rights reserved.

Revision 1.0 (06-16-09) 2 SMSC CAP1088

Chapter 1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Chapter 2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chapter 4 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

SMSC CAP1088 3 Revision 1.0 (06-16-09)

4.6 ALERT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Chapter 5 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Chapter 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Revision 1.0 (06-16-09) 4 SMSC CAP1088

SMSC CAP1088 5 Revision 1.0 (06-16-09)

Revision 1.0 (06-16-09) 6 SMSC CAP1088

Table 5.41 LED Polarity Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

SMSC CAP1088 7 Revision 1.0 (06-16-09)

Chapter 1 Pin Description

WAKE / SPI_MOSI 2 17 CS6

Figure 1.1 CAP1088 Pin Diagram (24-Pin QFN)

Table 1.1 Pin Description for CAP1088

1 SPI_CS# Active low chip-select for SPI bus DI (5V)

WAKE - Active high wake / interrupt output -

WAKE / WAKE - Active high wake input - requires pull-down resistor

SPI_MOSI - SPI Master-Out-Slave-In port when used in

Revision 1.0 (06-16-09) 8 SMSC CAP1088

Table 1.1 Pin Description for CAP1088 (continued)

SMDATA - Bi-directional, open-drain SMBus data - requires

SMDATA / BC_DATA - Bi-directional, open-drain BC-Link data -

SPI_MISO - SPI Master-In-Slave-Out port when used in

SMCLK - SMBus clock input - requires pull-up resistor DI (5V)

Open drain LED 1 driver (default) OD (5V)

Open drain LED 2 driver (default) OD (5V)

Open drain LED 3 driver (default) OD (5V)

Open drain LED 4 driver (default) OD (5V)

Open drain LED 5 driver (default) OD (5V)

Open drain LED 6 driver (default) OD (5V)

Open drain LED 7 driver (default) OD (5V)

Open drain LED 8 driver (default) OD (5V)

ALERT# - Active low alert / interrupt output for SMBus alert

Address / communications select pin - pull-down resistor

15 CS8 Capacitive Touch Sensor 8 AIO

16 CS7 Capacitive Touch Sensor 7 AIO

17 CS6 Capacitive Touch Sensor 6 AIO

SMSC CAP1088 9 Revision 1.0 (06-16-09)

Table 1.1 Pin Description for CAP1088 (continued)

18 CS5 Capacitive Touch Sensor 5 AIO

19 CS4 Capacitive Touch Sensor 4 AIO

20 CS3 Capacitive Touch Sensor 3 AIO

21 CS2 Capacitive Touch Sensor 2 AIO

22 CS1 Capacitive Touch Sensor 1 AIO

23 VDD Positive Power supply Power

Active high soft reset for system - resets all registers to

Bottom Pad GND Ground Power

Table 1.2 Pin Types

PIN TYPE DESCRIPTION

Power This pin is used to supply power or ground to the

DI Digital Input - This pin is used as a digital input. This