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USER'S MANUAL S3C6410X RISC Microprocessor Aug 22, 2008 REV 1.10 Confidential Proprietary of Samsung Electronics

USER'S MANUAL

S3C6410X

RISC Microprocessor Aug 22, 2008

REV 1.10

Confidential Proprietary of Samsung Electronics Co., Ltd Copyright © 2008 Samsung Electronics, Inc. All Rights Reserved

Important Notice

The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.

Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.

This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.

"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.

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S3C6410X RISC Microprocessor User's Manual, Revision 1.10

Copyright © 2008 Samsung Electronics Co.,Ltd.

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics Co.,Ltd.

Samsung Electronics Co., Ltd. San #24 Nongseo-Dong, Giheung-Gu Yongin-City Gyeonggi-Do, Korea

446-711

Home Page: http://www.samsungsemi.com/

E-Mail: mobilesol.cs@samsung.com

Printed in the Republic of Korea

Revision History

Revision No

Description of Change

Refer to

Author(s)

 

Date

1.00

- Public Release

-

W.J.Kim

July

18, 2008

1.10

Overview, System Controller, GPIO, CAMIF, IISBUSI/F, Key I/F, IIS Multi Audio I/F, Electrical Data has been modified

Errata Rev00

W.J.Kim

Aug

22, 2008

Table of Contents

Chapter 1

Product Overview

1.1 Architectural Overview

1-1

1.2 Features

1-2

1.2.1 S3C6410X RISC Microprocessor Features Summary

1-3

1.2.2 Microprocessor

1-4

1.2.3 Memory Subsystem

1-5

1.2.3.1 SROM Memory Port configurable to support the following memory types:

1-5

1.2.3.2 DRAM port configurable to support the following memory types:

1-6

1.2.4

Multimedia Acceleration

1-6

1.2.4.1 Camera Interface

1-6

1.2.4.2 Multi Format Codec (MFC)

1-7

1.2.4.3 JPEG Codec

1-7

1.2.5

2D

Graphics

Accelerator

1-7

1.2.6

3D

Graphics

Accelerator

1-8

1.2.6

Image Rotator

1-8

1.2.7

Display Control

1-9

1.2.7.1 TFT LCD Interface

1-9

1.2.7.2 Video Post Processor

1-9

1.2.7.3 TV (NTSC/PAL) Video Encoder with Image Enhancer

1-9

1.2.8

Audio Interface

1-9

1.2.8.1 AC97 Controller

1-9

1.2.8.2 PCM serial Audio Interface

1-9

1.2.8.3 IIS-Bus Interface

1-10

1.2.9

USB Support

1-10

1.2.9.1 USB OTG 2.0 High Speed

1-10

1.2.9.2 USB

Host

1-10

1.2.10 IrDA v1.1

1-10

1.2.11 Serial Communication

1-10

1.2.11.1 UART

1-10

1.2.11.2 IIC-Bus Interface

1-11

1.2.11.3 SPI Interface

1-11

1.2.11.4 MIPI HSI

1-11

1.2.12

Modem & HOST Interface

1-11

1.2.12.1

Parallel Modem Chip Interface

1-11

1.2.12.1

Host Interface

1-11

1.2.13 GPIO (General Purpose I/O)

1-12

1.2.14 Input Devices

1-12

1.2.14.1 Keypad Interface

1-12

1.2.14.2 A/D Converter and Touch Screen Interface

1-12

Table of Contents

Chapter 1

Product Overview

1.2.15

Storage Devices

 

1-12

1.2.15.1

SD/MMC Host Controller

1-12

1.2.16

System Peripherals

 

1-12

1.2.16.1 DMA controller

1-12

1.2.16.2 Vectored Interrupt Controller

1-13

1.2.16.3 TrustZone Protection Controller

1-13

1.2.16.4 Timer with PWM (Pulse Width Modulation)

1-13

1.2.16.5 16-bit

Watchdog

Timer

1-13

1.2.16.6 RTC (Real Time Clock)

1-13

1.2.17 security sub-system

1-13

1.2.18 System

Management

1-14

1.2.19 System Operating Frequencies

1-14

1.3 Power Management

 

1-15

1.4 Electrical Characteristics

1-15

1.5 Package

1-15

1.6 Pin Assignments

1-16

1.7 Pin Description

1-36

1.7.1 External Memory Interface

 

1-36

1.7.2 Serial Communication

1-39

1.7.3 Parallel

Communication

1-43

1.7.4 Modem Interface

1-44

1.7.5 Image/Video Processing

1-46

1.7.6 Display Control

1-47

1.7.7 Storage Devices

1-49

1.7.8 System Management

1-51

1.8

Power-supply Groups

1-53

Chapter 2

Memory Map

2.1 Memory System Block Diagram

 

2-1

2.2 Device Specific Address Space

2-3

Chapter 3

System Controller

3.1 Overview

3-1

3.2 Features

3-2

3.3 Functional description

 

3-2

3.3.1 Hardware architecture

3-2

3.3.2 Clock Architecture

3-3

3.3.3 Clock

source selection

3-4

Table of Contents (Continued)

Chapter 3

System Controller

3.3.4

Phase Locked Loop (PLL)

3-4

3.3.4.1 Clock selection between PLLs and input reference clock

3-5

3.3.4.2 ARM and AXI/AHB/APB bus clock generation

3-6

3.3.4.3 MFC

clock generation

3-7

3.3.4.4 Camera I/F clock

generation

3-8

3.3.4.5 Clock generation for display (POST, LCD, and scaler)

3-8

3.3.4.6 Clock generation for audio (IIS and PCM)

3-8

3.3.4.7 Clock generation for UART, SPI, and MMC

3-9

3.3.4.8 Clock generation for IrDA, USB host

3-10

3.3.4.9 Clock

ON/OFF control

3-10

3.3.4.10

Clock output

3-10

3.3.5

Synchronous 667MHz operating mode

3-10

3.3.5.1 Clock divider structure

3-10

3.3.5.2 Transition to synchronous 667MHz operating mode

3-11

3.3.5.3 Limitation of synchronous 667MHz operating mode

3-12

3.3.6

Low Power Mode Operation

3-12

3.3.6.1 Power domain in S3C6410X

3-13

3.3.6.2 NORMAL/IDLE mode

3-13

3.3.6.3 STOP mode

3-14

3.3.6.4 DEEP-STOP mode

3-15

3.3.6.5 SLEEP mode

3-15

3.3.6.6 Wakeup

3-17

3.3.6.7 Reset

3-17

3.3.6.8 Hardware reset

3-17

3.3.6.9 Watchdog reset

3-18

3.3.6.10

Wakeup reset

3-19

3.3.7

misceleneous.

3-19

3.4

register description

3-20

3.4.1 Memory map

3-20

3.4.2 individual register descriptions

3-22

3.4.2.1 PLL Control Registers

3-22

3.4.2.2 Clock source control register

3-27

3.4.2.3 Clock divider control register

3-29

Clock

3.4.2.4 configuration register

output

3-31

Clock

3.4.2.5 control register

gating

3-32

3.4.2.6 AHB bus control register

3-36

3.4.2.7 Secure DMA control register

3-40

3.4.2.8 System

ID register

3-41

3.4.2.9 System

Others register

3-41

3.4.2.10 Memory controller status register

3-42

3.4.2.11 Power mode control register

3-46

3.4.2.12 System stabilization

counter

3-49

3.4.2.13 Cacheable bus transaction selection register

3-50

3.4.2.14 Others control register

3-51

3.4.2.15 Status register

3-53

3.4.2.16 Information register

3-54

Table of Contents (Continued)

Chapter 4

Memory Sub-system

4.1. Overview

4-1

4.2. Introduction

4-1

4.3. Structure

4-2

4.4. AHB slave interface (SFR)

4-2

4.5. AHB slave interface (SPINE)

4-3

4.6. EBI Multiplexing

4-5

4.7. Configuration Options

4-7

4.8. Use of wide address spaces for SROM Controller (Using dram 1 PORT)

4-8

4.9. Sharing Chip Select for memory port 0

4-9

4.10.Remapping

4-15

4.11.Address decoding

4-16

Chapter 5

DRAM Controller

5.1 Overview

5-1

5.2 Features

5-2

5.3 SDRAM Memory interface

5-3

5.4 SDRAM Initialization Sequence

5-4

5.4.1 DRAM Controller Initialization Sequence

5-4

5.4.2 SDR/mobile SDR SDRAM Initialization Sequence

5-4

5.4.3 DDR/mobile DDR SDRAM Initialization Sequence

5-4

5.5

Register Description

5-5

5.5.1 DRAM Controller Status Register

5-5

5.5.2 DRAM Controller Command Register

5-5

5.5.3 Direct Command Register

5-6

5.5.4 Memory Configuration Register

5-7

5.5.5 Refresh Period Register

5-8

5.5.6 CAS Latency Register

5-8

5.5.7 T_DQSS Register

5-9

5.5.8 T_MRD Register

5-9

5.5.9 T_RAS Register

5-9

5.5.10 T_RC Register

5-10

5.5.11 T_RCD Register

5-10

5.5.12 T_RFC Register

5-10

5.5.13 T_RP Register

5-10

5.5.14 T_RRD Register

5-11

5.5.15 T_WR Register

5-11

5.5.16 T_WTR Register

5-11

5.5.17 T_XP Register

5-12

5.5.18 T_XSR

Register

5-12

5.5.19 T_ESR

Register

5-12

5.5.20 Memory configuration 2 register

5-13

5.5.21 Memory configuration 3 register

5-14

5.5.22 ID_N_CFG Register

5-14

5.5.23 CHIP_N_CFG Register

5-15

5.5.24 USER_STATUS Register

5-16

5.5.25 USER_CONFIG Register

5-16

Table of Contents (Continued)

Chapter 6

SROM Controller

 

6.1 Overview

6-1

6.2 Feature

6-1

6.3 Block Diagram

6-2

6.4 SROM Controller Function Description

6-2

 

6.4.1

nWAIT Pin Operation

6-2

6.5 Programmable Access Cycle

6-3

6.6 Special Function Registers

6-4

 

6.6.1 SROM Bus Width & Wait Contrl Register(SROM_BW)

6-4

6.6.2 SROM Bank Control Register (SROM_BC : XrCSn0 ~ XrCSn2)

6-6

Chapter 7

OneNAND Controller

7.1 Overview

7-1

7.2 Feature

7-1

7.3 Block Diagram

7-2

7.4 Signal Description

7-3

 

7.4.1

External Memory Interface

7-3

7.5 Input Clocks

7-4

7.6 Memory Address Mapping

7-5

7.7 Command

Mapping

7-5

 

7.7.1

"00" = Map 00 Commands

7-5

7.7.2 "01" = MAP 01 COMMANDS

7-6

7.7.3

"10" = Map 10 Commands

7-7

7.7.3.1 Erase Operation

7-7

7.7.3.2 Lock, Unlock and Lock-Tight Operations

7-8

7.7.3.3 Copy

Back Operations

7-9

7.7.3.4 OTP and Spare Area Access Operations

7-9

7.7.3.5 Verify Read Operations

7-10

7.7.3.6 Pipeline Read-Ahead or Write-Ahead Operations

7-10

7.7.3.7 Read/Modify/Write Operations

7-11

7.7.4

"11" = Map 11 Commands

7-11

7.8

Pipeline Read/Write Ahead Command

7-12

7.8.1 Set Up a Single Area for Pipelined Read-Ahead

7-12

7.8.2 Set Up Multiple Areas for Pipelined Read-Ahead

7-13

7.9

controller Usage Exception

7-14

7.10 Boot with OneNAND Controller

7-14

7.11 Register Description

7-15

 

7.11.1

Memory Map

7-15

Table of Contents (Continued)

Chapter 7

OneNAND Controller

7.12 Individual Register Descriptions

7-18

7.12.1

Memory Device Configuration Register

7-18

7.12.2

Burst Length Register

7-20

7.12.3

Memory Reset Register

7-20

7.12.4

Interrupt Error Status Register

7-21

7.12.5

Interrupt Error Mask Register

7-22

7.12.6

Interrupt Error Acknowledge Register

7-23

7.12.7

Ecc Error Status Register

7-23

7.12.8

Manufacturer Id Register

7-24

7.12.8

Device Id Register

7-24

7.12.10 Data Buffer Size Register

7-25

7.12.11 Boot Buffer Size Register

7-25

7.12.12 Amount Of Buffer Register

7-25

7.12.13 Technology Register

 

7-26

7.12.14 FBA Width Register

7-26

7.12.15 FPA Width Register

7-26

7.12.16 FSA Width Register

7-27

7.12.17 Revision Register

7-27

7.12.18 Dataram0

Code

Register

7-27

7.12.19 Dataram1

Code

Register

7-28

7.12.20 Synchronous Mode Register

7-28

7.12.21 Transfer Spare Register

 

7-29

7.12.22 DBS-DFS Width Register

7-29

7.12.23 Page Count Register

 

7-29

7.12.24 Error Page Address Register

7-30

7.12.25 Burst Read Latency Register

7-30

7.12.26 Interrupt Pin Enable Register

7-30

7.12.27 Interrupt Monitor Cycle Register

7-31

7.12.28 Access Clock Register

 

7-31

7.12.29 Slow Read Path Register

7-32

7.12.30 Error Block Address Register

7-32

7.12.31 Flash Version Id Register

7-32

7.12.32 Flash Auxiliary Control Register

7-33

7.12.33 Flash Asynchronous Fifo Count Register

7-33

Table of Contents (Continued)

Chapter 8

NAND Flash Controller

8.1 Overview

8-1

8.2 Features

8-1

8.3 Block Diagram

8-2

8.4 Nand Flash Memory Timing

8-3

8.5 NAND Flash access

8-4

8.6 Data Register Configuration

8-4

8.7 STEPPINGSTONE (8KB SRAM)

8-4

8.8 1-bit / 4-bit / 8-BIT ECC (Error Correction Code)

8-5

8.8.1 ECC module features

8-6

8.8.2 1-bit ECC Programming Encoding and decoding

8-7

8.8.3 4-bit ECC Programming guide (Encoding)

8-7

8.8.4 4-bit ECC Programming guide (DEcoding)

8-8

8.8.5 8-bit ECC Programming guide (ENcoding)

8-8

8.8.6 8-bit ECC Programming guide (DEcoding)

8-9

8.9 Memory mapping(NOR-flash boot)

8-11

8.10 Nand Flash Memory Configuration

8-12

8.11 Nand Flash Controller Special Registers

8-13

8.11.1 NAND Flash controller Register map

8-13

8.11.2 Nand Flash configuration Register

8-14

8.11.3 Control Register

8-15

8.11.4 Command Register

8-17

8.11.5 Address Register

8-17

8.11.6 Data

Register

8-17

8.11.7 Main data area ECC Register

8-18

8.11.8 Spare area ECC Register

8-18

8.11.9 progrmmable block address Register

8-19

8.11.10 NFCon Status Register

8-21

8.11.11 ECC0/1 Error status Register

8-22

8.11.12 Main data area ECC0 status Register

8-24

8.11.13 spare area ECC status Register

8-25

8.11.14 4-bit ECC Error patten Register

8-25

8.11.15 ECC 0/1/2 FOR 8bit ECC STATUS Register

8-26

8.11.16 8-bit ECC MAIN DATA ECC 0/1/2/3 STATUS REGISTER

8-28

8.11.17 8-bit ECC ERROR PATTERN REGISTER

8-29

Table of Contents (Continued)

Chapter 9

CF Controller

9.1 Overview

 

9-1

9.2 Features

9-1

9.2.1 The CF controller features:

9-1

9.2.2 The PC card controller features:

9-1

9.2.3 The ATA controller features:

9-2

9.3 I/O description

 

9-3

9.4 Block Diagram

9-5

9.4.1 CF Controller Block Diagram

9-5

9.5

Timing Diagram

 

9-6

9.5.1 PC Card Mode

9-6

9.5.2 True-IDE Mode

9-7

9.5.3 UDMA Mode

 

9-8

9.6

Special Function Registers

9-11

9.6.1 Memory Map

 

9-11

9.6.2 Register address Table

9-12

9.6.3 Individual Register Descriptions

9-13

 

9.6.3.1

MUX_REG

9-13

9.6.3.2

PCCARD_CNFG&STATUS

9-14

9.6.3.3

PCCARD_INTMSK&SRC

9-15

9.6.3.3

PCCARD_INTMSK&SRC

9-15

9.6.3.4

PCCARD_ATTR

9-16

9.6.3.5

PCCARD_I/O

9-16

9.6.3.6

PCCARD_COMM

9-17

9.6.3.7

ATA_CONTROL

9-18

9.6.3.7

ATA_CONTROL

9-18

9.6.3.8

ATA_STATUS

9-18

9.6.3.9

ATA_COMMAND

9-19

9.6.3.9

ATA_COMMAND

9-19

9.6.3.10

ATA_SWRST

9-20

9.6.3.11

ATA_IRQ

9-20

9.6.3.12

ATA_IRQ_MASK

9-21

9.6.3.13

ATA_CFG

9-22

9.6.3.13

ATA_CFG

9-22

9.6.3.14

ATA_PIO_TIME

9-23

9.6.3.15

ATA_UDMA_TIME

9-24

9.6.3.16

ATA_XFR_NUM

9-25

9.6.3.17

ATA_XFR_CNT

9-25

9.6.3.18

ATA_TBUF_START

9-25

9.6.3.19

ATA_TBUF_SIZE

9-26

9.6.3.20

ATA_SBUF_START

9-26

9.6.3.21

ATA_SBUF_SIZE

9-26

9.6.3.22

ATA_CADDR_TBUR

9-27

9.6.3.23

ATA_CADDR_SBUF

9-27

9.6.3.24

ATA_PIO_DTR

9-27

9.6.3.25

ATA_PIO_FED

9-28

Table of Contents (Continued)

Chapter 9

CF Controller

 

9.6.3.26 ATA_PIO_SCR

9-28

9.6.3.27 ATA_PIO_LLR

9-28

9.6.3.28 ATA_PIO_LMR

9-29

9.6.3.29 ATA_PIO_LHR

9-29

9.6.3.30 ATA_PIO_DVR

9-29

9.6.3.31 ATA_PIO_CSD

9-30

9.6.3.32 ATA_PIO_DAD

9-30

9.6.3.33 ATA_PIO_RDATA

9-30

9.6.3.34 BUS_FIFO_STATUS

9-31

9.6.3.35 ATA_FIFO_STATUS

9-31

Chapter 10

GPIO

10.1 Overview

10-1

 

10.2 Features

10-1

10.3 Description

10-2

10.4 Register Description

10-3

 

10.4.1

Memory Map

10-3

10.5

Individual Register

Descriptions

10-7

10.5.1 Port A Control Register

10-7

10.5.2 Port B Control Register

10-9

10.5.3 Port C Control Register

10-11

10.5.4 Port D Control Register

10-13

10.5.5 Port E Control Registers

10-15

10.5.6 Port F Control Registers

10-17

10.5.7 Port G Control Registers

10-19

10.5.8 Port H Control Registers

10-21

10.5.9 Port I Control Registers

10-23

10.5.10 Port J Control Registers

10-25

10.5.11 Port K Control Registers

10-27

10.5.12 Port L Control Registers

10-30

10.5.13 Port M Control Registers

10-33

10.5.14 Port N Control Registers

10-34

10.5.15 Port O Control Registers

10-36

10.5.16 Port P Control Registers

10-38

10.5.17 Port Q Control Registers

10-40

10.5.18 Special Port Control Register

10-42

10.5.19 Memory Interface Pin Configuration Register in Stop Mode

10-46

10.5.20 Memory Interface Pin Configuration Register in Sleep Mode

10-48

10.5.21 Memory Interface Drive Strength Control Register

10-51

10.5.22 External Interrupt Control Registers

10-53

10.6

Current Service REGISTER (SERVICE)

10-73

10.6.1

Extern Pin Configuration Register in Sleep Mode

10-74

Table of Contents (Continued)

Chapter 11

DMA Controller

11.1 Overview

11-1

11.2 Features

11-2

11.3 block diagram

11-3

11.4 DMA sources

11-4

11.5 DMA interface

11-5

11.5.1 DMA request signals

111-5

11.5.2 DMA

response signals

11-5

11.5.3 Transfer types

11-5

11.5.3.1 Peripheral-to-memory transaction under DMA controller flow control

11-6

11.5.3.2 Memory-to- Peripheral transaction under DMA controller flow control

11-6

11.5.3.3 Memory-to-memory transaction under DMA controller flow control

11-6

11.5.3.4 Peripheral-to-peripheral transaction under DMA controller flow control

11-7

11.5.4

Signal timing

11-8

11.6 Functional timing diagram

11-9

11.7 Programmer's model

11-9

11.7.1 Programming the DMA controller

11-9

11.7.2 Enabling the DMA controller

11-9

11.7.3 Disabling the DMA controller

11-9

11.7.4 Enabling a DMA channel

11-9

11.7.5 Disabling a DMA channel

11-10

11.7.5.1 Disabling a DMA channel and losing data in the FIFO:

11-10

11.7.5.2 Disabling a DMA channel without losing data in the FIFO:

11-10

11.7.6 Set up a new DMA transfer

11-10

11.7.7 Halting a DMA channel

11-10

11.7.8 Programming a DMA channel

11-11

11.8

Register Description

11-12

11.8.1 DMA register location

11-12

11.8.2 Interrupt status register, DMACIntStatus

11-15

11.8.3 Interrupt terminal count status register, DMACIntTCStatus

11-15

11.8.4 Interrupt terminal count clear register, DMACIntTCClear

11-15

11.8.5 Interrupt error status register, DMACIntErrorStatus

11-16

11.8.6 Interrupt error clear register, DMACIntErrClr

11-16

11.8.7 Raw interrupt terminal counter status register, DMACRawIntTCStatus

11-16

11.8.8 Raw error interrupt status register, DMACRawIntErrorStatus

11-17

11.8.9 Enable channel register, DMACEnbldChns

11-17

11.8.10

Software burst request register, DMACSoftBReq

11-17

11.8.11

Software single request register, DMACSoftSReq

11-18

11.8.14

Configuration register, DMACConfiguration

11-19

11.8.15

Synchronization register, DMACSync

11-19

11.8.16

Channel source address register, DMACCxSrcAddr

11-20

11.8.17

Channel destination address register, DMACCxDestAddr

11-20

11.8.18

Channel linked list item register, DMACCxLLI

11-21

11.8.19

Channel control register, DMACCxControl0

11-21

11.8.20

Channel control register, DMACCxControl1

11-24

11.8.21

Channel configuration register, DMACCxConfiguration

11-25

11.8.22

Channel configuration expansion register, DMACCxConfigurationExp

11-27

Table of Contents (Continued)

Chapter 12

Vectored Interrupt Controllers

12.1

Overview

12.2

12.3

12.4

Features

Interrupt Sources

Function

12.4.1 Block Diagram

12.5 Summary of VIC registers

12.6 Register Descriptions

12-1

12-1

12-2

12-5

12-5

12-6

12-9

12.6.1 IRQ Status Register, VICIRQSTATUS

12.6.2 FIQ Status Register, VICFIQSTATUS

12.6.3 Raw Interrupt Status Register, VICRAWINTR

12.6.4 Interrupt Select Register, VICINTSELECT

12.6.5 Interrupt Enable Register, VICINTENABLE

12.6.6 Interrupt Enable Clear, VICINTENCLEAR

12.6.7 Software Interrupt Register, VICSOFTINT

12.6.8 Software Interrupt Clear Register, VICSOFTINTCLEAR 12-12

12-12

12-9

12-9

12-10

12-10

12-11

12-11

12.6.9 Protection Enable Register, VICPROTECTION

12-13

12.6.10 Software Priority Mask Register, VICSWPRIORITYMASK

12-13

12.6.11 Vector Priority Register for Daisy Chain

12-14

12.6.12 Vector Address Regisgers, VICVECTADDR[0-31] 12-15

12.6.13 Vector Priority Registers, VICVECTPRIORITY[0-31]

12-15

12.6.14 Vector Address Register, VICADDRESS

12-16

 

Chapter 13

Security SUB-Systems

13.1 Overview

13-1

 

13.2 Features

13-1

13.3 Programming Guide

13-3

 

13.3.1 AES

13-3

13.3.2 TDES

13-4

13.3.3 SHA-1 & PRNG

13-5

13.4

Special Function Registers

13-6

13.4.1

Security Sub-system Register Map

13-6

13.5

DMA & Interrupt control module

13-11

13.5.1

Security sub-system DMA & interrupt register

13-11

13.6

Security sub-system RX FIFO module

13-12

13.6.1 FIFO-RX Control Register

13-12

13.6.2 FIFO-RX Message Length Register

13-13

13.6.3 FIFO-RX

Block Size Register

13-13

13.6.4 FIFO-RX Destination Address Register

13-13

13.6.5 Message Length Counter

FIFO-RX

13-14

FIFO-RX

13.6.6 Write Buffer

13-14

Table of Contents (Continued)

Chapter 13

Security SUB-Systems

13.7

Security sub-system TX FIFO module

13-15

13.7.1 FIFO-TX Control Register

13-15

13.7.2 FIFO-TX Message Length Register

13-16

13.7.3 FIFO-TX Block Size Register

13-16

13.7.4 FIFO-TX Source Address Register

13-16

13.7.5 FIFO-TX Message Length Counter

13-16

13.7.6 FIFO-TX Read Buffer

13-17

13.8

Security sub-system AES module

13-18

13.8.1 AES_CTRL

 

13-18

13.8.2 AES_RX_DIN_01 ~ AES_RX_DIN_01

13-19

13.8.3 AES_RX_DOUT_01 ~ AES_RX_DOUT_04 / AES_TX_DOUT_01 ~ AES_TX_DOUT_04

13-19

13.8.4 AES_RX_KEY_01 ~ AES_RX_KEY_08

13-20

13.8.5 AES_RX_IV_01 ~ AES_RX_IV_04

13-20

13.8.6 AES_RX_CTR_01 ~ AES_RX_CTR_04

13-20

13.9

Security sub-system DES/3DEs module

13-21

13.9.1 TDES_RX_CTRL

 

13-21

13.9.2 TDES_RX_KEY1_0

13-22

13.9.3 TDES_RX_INPUT_0 / TDES_RX_INPUT_1

13-22

13.9.4 TDES_RX_IV_0 / TDES_RX_IV_1

13-23

13.10 Security sub-system SHA-1/PRNG module

13-24

13.10.1 HASH_CONTROL

 

13-24

13.10.2 HASH_DATA

13-24

13.10.3 SEED_DATA_01 ~ SEED_DATA_10

13-25

13.10.4 HASH_STATUS

 

13-25

13.10.5 HASH_OUTPUT_01 (PRNG_OUTPUT_01) ~ HASH_OUTPUT_10 (PRNG_OUTPUT_10)

13-26

13.10.6 HASH_MIDOUT_01 ~ HASH_MIDOUT_05

13-27

13.10.7 PRE_MSG_LENGTH_01 / PRE_MSG_LENGTH_02

13-28

Chapter 14

Display Controller

14.1 Overview

 

14-1

14.2 Block Diagram

14-1

14.3 Features

14-2

14.4 Functional Description

14-3

14.4.1 Brief of the sub-block

14-3

14.4.2 Data

Flow

 

14-3

14.4.3 Interface

14-4

14.4.4 Overview of the Color Data

14-5

 

14.4.4.1 RGB Data format

14-5

Table of Contents (Continued)

Chapter 14

Display Controller

14.4.5

Palette usage

 

14-16

 

14.4.5.1

Palette Configuration and Format Control

14-16

14.4.6

Window Blending

 

14-18

 

14.4.6.1

Overview

14-18

14.4.6.2 Blending Diagram/Details

14-20

14.4.7 COLOR-KEY Function

 

14-22

14.4.8 VTIME CONTROLLER OPERATION

14-25

 

14.4.8.1 RGB Interface

14-25

14.4.8.2 I80 Interface Controller

14-26

14.4.9

LDI Command Control

 

14-27

 

14.4.9.1 Auto Command

14-27

14.4.9.2 Normal Command

14-27

14.4.10

I80 CPU Interface Trigger

14-29

14.4.11

Interrupt

 

14-29

14.4.12

Virtual Display

14-29

14.4.13

RGB Interface

IO

14-31

14.4.14

LCD I80 INTERFACE IO

14-32

14.4.14

ITU-R BT.601 INTERFACE IO

14-33

14.4.15

LCD DaTA PiN MAP

 

14-34

14.4.16

LCD NORMAL/BY-PASS MODE SELECTION

14-36

14.5

Programmer’s Model

14-37

14.5.1 Overview

 

14-37

14.5.2 SFR Memory Map

14-37

14.6

Individual Register Descriptions

14-40

14.6.1 Video Main Control 0 Register

14-40

14.6.2 Video Main Control 1 Register

14-42

14.6.3 Video Main Control 2 Register

14-43

14.6.4 VIDEO Time Control 0 Register

14-43

14.6.5 Video Time Control 1 Register

14-44

14.6.6 VIDEO Time Control 2 Register

14-44

14.6.7 Window 0 Control Register

14-44

14.6.8 Window 1 Control Register

14-46

14.6.9

Window 2 Control Register

14-48

14.6.10 Window 3 Control Register

14-50

14.6.11 Window 4 Control Register

14-51

14.6.12 Window 0 Position Control A Register

14-52

14.6.13 Window 0 Position Control B Register

14-52

14.6.14 Window 0 Position Control C Register

14-52

14.6.15 Window 1 Position Control A Register

14-53

14.6.16 Window 1 Position Control B Register

14-53

14.6.17 Window 1 Position Control C Register

14-54

14.6.18 Window 1 Position Control D Register

14-54

14.6.19 Window 2 Position Control A Register

14-54

Table of Contents (Continued)

Chapter 14

Display Controller

14.6.20

Window 2 Position Control B Register

14-55

14.6.21

Window 2 Position Control C Register

14-55

14.6.22

Window 2 Position Control D Register

14-55

14.6.23

Window 3 Position Control A Register

14-56

14.6.24

Window 3 Position Control B Register

14-56

14.6.25

Window 3 Position Control C Register

14-57

14.6.26

Window 4 Position Control a Register

14-57

14.6.27

Window 4 Position Control B Register

14-58

14.6.28

Window 4 Position Control C Register

14-58

14.6.29

FRAME Buffer Address 0 Register

14-59

14.6.30

FRAME Buffer Address 1 Register

14-59

14.6.31

FRAME Buffer Address 2 Register

14-60

14.6.32

VIDEO interrupt Control 0 Register

14-60

14.6.33

VIDEO interrupt Control 1 Register

14-61

14.6.34

Win1 Color Key 0 Register

14-62

14.6.35

WIN 1 Color key 1 Register

14-62

14.6.36

Win2 Color Key 0 Register

14-63

14.6.37

WIN2 Color key 1 Register

14-63

14.6.38

Win3 Color Key 0 Register

14-64

14.6.39

WIN3 Color key 1 Register

14-64

14.6.40

Win4 Color Key 0 Register

14-65

14.6.41

WIN4 Color key 1 Register

14-66

14.6.42

Dithering Control 1 Register

14-67

14.6.43

WIN0 Color MAP

14-67

14.6.44

WIN1 Color MAP

14-68

14.6.44

WIN1 Color MAP

14-68

14.6.45

WIN2 Color MAP

14-68

14.6.46

WIN3 Color MAP

14-68

14.6.47

WIN4 Color MAP

14-69

14.6.48

Window Palette control Register

14-69

14.6.49

I80 / RGB Trigger Control Register

14-70

14.6.50

ITU 601 Interface control 0

14-70

14.6.51

LCD I80 Interface Control 0

14-71

14.6.52

LCD I80 Interface Control 1

14-72

14.6.53

LCD I80 Interface Command Control 0

14-72

14.6.54

LCD I80 Interface Command Control 1

14-74

14.6.55

I80 System Interface Manual Command Control 0

14-74

14.6.56

I80 System Interface Manual Command Control 1

14-75

14.6.57

I80 System Interface Manual Command Control 2

14-75

14.6.58

LCD I80 Interface Command

14-76

14.6.59

Window 2’s Palette Data

14-76

14.6.60

Window 3’s Palette Data

14-77

14.6.61

Window 4’s Palette Data

14-77

14.6.62

WIN0 Palette Ram Access Address (not SFR)

14-77

14.6.63

WIN1 Palette Ram Access Address (not SFR)

14-78

Table of Contents (Continued)

Chapter 15

Post Processor

15.1 Overview

 

15-1

15.2 Features

15-2

15.3 A Source and Destination Image Data Format

15-3

15.3.1 DMA Mode Operation

15-4

15.3.2 FIFO

Mode

Operation

15-7

15.4 Image Size and Scale Ratio

15-7

15.5 DMA operation of Source and Destination Image

15-9

15.5.1 Start address

 

15-10

15.5.2 End address

15-10

15.6

Frame Management of POST Processor

15-12

15.6.1 Per Frame Management Mode

15-12

15.6.2 Free Run Mode

 

15-12

15.7

Register File Lists

15-13

15.7.1

MODE Control Register

15-15

15.7.3

Pre-Scale Image Size Register

15-17

15.7.4

Source Image Size Register

15-18

15.7.5

Horizontal Main Scale Ratio Register

15-18

15.7.6

Vertical Main Scale Ratio Register

15-18

15.7.7

Destination Image Size Register

15-19

15.7.8

Pre-Scale Shift Factor Register

15-19

15.7.9

DMA Start Address Register

20

15.7.10 DMA End Address Register

15-21

15.7.11 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register

15-22

15.7.12 Next Frame DMA Start Address Register

15-23

15.7.13 Next Frame DMA End Address Register

15-24

15.7.14 DMA Start address Register for Output Cb and Cr

15-24

15.7.15 DMA End Address Register for Output Cb and Cr

15-25

15.7.16 Current Frame(Buffer0) and Next Frame(Buffer1) Offset Register for Output Cb and Cr

15-25

15.7.17 15.26 Next Frame DMA Start Address Register for Output Cb and Cr

15-25

15.7.18 Next Frame DMA End Address Register for Output Cb and Cr

15-26

15.7.19 POSTENVID Register to Enable Video Processing

15-26

15.7.20 MODE Control Register 2

15-27

Table of Contents (Continued)

Chapter 16

TV Scaler

16.1 Overview

 

16-1

16.2 Features

16-2

16.3 A Source and Destination Image Data Format

16-3

16.3.1 DMA Mode Operation

16-4

16.3.2 FIFO

Mode

Operation

16-7

16.4 Image Size and Scale Ratio

16-7

16.5 DMA operation of Source and Destination Image

16-9

16.5.1 Start address

 

16-10

16.5.2 End address

16-10

16.6

Frame Management of TV Scaler

16-12

16.6.1 Per Frame Management Mode

16-12

16.6.2 Free Run Mode

 

16-12

16.7

Register File Lists

16-13

16.7.1

MODE Control Register

16-15

16.7.3

Pre-Scale Image Size Register

16-17

16.7.4

Source Image Size Register

16-18

16.7.5

Horizontal Main Scale Ratio Register

16-18

16.7.6

Vertical Main Scale Ratio Register

16-18

16.7.7

Destination Image Size Register

16-19

16.7.8

Pre-Scale Shift Factor Register

16-19

16.7.9

DMA Start Address Register

16-20

16.7.10 DMA End Address Register

16-20

16.7.11 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register

16-21

16.7.12 Next Frame DMA Start Address Register

16-21

16.7.13 Next Frame DMA End Address Register

16-22

16.7.14 DMA Start Address Register for Output Cb and Cr

16-22

16.7.15 DMA End Address Register for Output Cb and Cr

16-23

16.7.16 Current Frame (Buffer0) and Next Frame (Buffer1) Offset Register for Output Cb and Cr

16-23

16.7.17 Next Frame DMA Start Address Register for Output Cb and Cr

16-23

16.7.18 Next Frame DMA End Address Register for Output Cb and Cr

16-24

16.7.19 POSTENVID Register for Enable Video Processing

16-24

16.7.20 MODE Control Register 2

16-25

Table of Contents (Continued)

Chapter 17

TV Encoder

17.1 Overview

17-1

17.2 Feature

17-1

17.3 Block Diagram

17-2

17.4 Functional Descriptions

17-3

17.4.1 Composition Of Analog Composite Signal

17-4

17.4.2 Common

Ntsc System

17-5

17.4.3 Common

Pal System

17-6

17.4.4 Composition Of Screen

17-7

17.4.5 Requested

Horizontal Timing

17-8

17.4.6 Requested

Vertical Timing

17-9

17.4.7 Macrovision (Anti Taping)

17-10

17.5 Dac Board Configure Guide

17-11

17.6 Tv Encoder Register Summary

17-12

17.7 Individual Register Descriptions

17-13

17.7.1 TVENCREG1

17-13

17.7.2 TVENCREG2

17-14

17.7.3 TVENCREG3

17-14

17.7.4 TVENCREG4

17-14

17.7.5 TVENCREG5

17-15

17.7.6 TVENCREG6

17-15

17.7.7 TVENCREG7

17-15

17.7.8 TVENCREG8

17-16

17.7.9 TVENCREG9

17-16

17.7.10 TVENCREG10

17-17

17.7.11 TVENCREG11

17-17

17.7.12 TVENCREG12

17-17

17.7.13 TVENCREG14

17-18

17.7.14 TVENCREG15

17-18

17.7.15 TVENCREG18

17-20

17.7.16 TVENCREG19

17-20

17.7.17 TVENCREG20

17-21

17.7.18 TVENCREG21

17-22

17.7.19 TVENCREG23

17-22

17.7.20 TVENCREG25

17-23

17.7.21 TVENCREG26

17-24

17.7.22 TVENCREG27

17-24

17.7.23 TVENCREG28

17-25

17.7.24 TVENCREG29

17-25

17.7.25 TVENCREG30

17-25

17.7.26 TVENCREG31

17-26

17.7.27 TVENCREG32

17-26

17.7.28 TVENCREG33

17-26

Table of Contents (Continued)

Chapter 18

GRAPHICS 2D

18.1

Overview

18-1

18.1.1

Features

18-1

18.2 Color Format Conversion

18-2

18.3 Command Fifo

18-3

18.4 Rendering pipeline

18-3

18.4.1

Primitive Drawing

18-3

18.4.1.1Line/Point Drawing

18-3

18.4.1.2 Bit Block Transfer

18-4

18.4.1.3 Color Expansion (Font Drawing)

18-6

 

18.4.2 Rotation

18-7

18.4.3 Clipping

18-8

18.4.4 Stencil Test

18-9

18.4.5 Raster Operation

18-9

18.4.6 Alpha Blending

18-10

18.5

REGISTER DESCRIPTION