EXPERIMENT: 1 Page 1.

OPERATIONAL AMPLIFIER APPLICATIONS

1 Equipments Required:
a) Function Generator 0 – 10 V pk-pk, 0-1 Mhz, Min Sin wave and 1
Square wave out put
b) Cathode Ray Oscilloscope Min 10 MHz Bandwidth 1
c) Dual output Regulated Power +/- 15V Minimum 1
Supply
2 Specific Knowledge required for conducting experiment:
Equipments Function Generator:
• Learn the functioning of “offset knob” adjustment. This knob is used to
add DC component to the AC signal.
• Pure AC signal is produced by the oscillator by locking the “Offset knob”
• Note that it is not possible to set the exact frequency and the r.m.s. /
peak voltage output using the controls available on the function
generator. Additional equipment or circuits are required to measure
these parameters.

Oscilloscope:
• Learn using Oscilloscope for the approximate measurement of amplitude
(peak), frequency and Phase difference between two wave forms.
• Set the Oscilloscope in DC mode.
• Connect any signal of (say) 1KHZ, 0.2V peak to peak Sine wave from
Oscillator to any channel of C.R.O.
• Check if the signal contains any DC offset. This is checked by switching
the oscilloscope mode between DC and AC. If the displayed waveform
does not shift while switching these modes back and forth, then the
signal does not have DC offset. Lock Offset adjust or adjust the offset on
the oscillator such a way that the displayed waveform does not have any
offset.

a) Frequency Measurement:
• Set the Oscilloscope in AC mode.
• Adjust the time/div knob such a way that the oscilloscope displays
one cycle or little over one cycle. To measure the given waveform
frequency, observe the horizontal divisions per cycle and multiply
with time per division and then calculate frequency using formulae
f = 1/T.

b) Voltage Peak –Peak measurement

• Set the Oscilloscope in AC mode.
• Decrease the voltage range (gain) on the oscilloscope to the lowest
level that will still display any one of the peaks of the wave form to
measure the peak. Now measure the voltage (one) peak.

3 Component Identifying the Pin-1 of given 741. Lean 741 technical details like
s bandwidth, gain, CMRR, Virtual ground, Maximum operating voltages,
Distinguishing Single ended and differential power supply constraints of
741, etc.
 IC 741 comes in two different packages. A) Round (8 pin) and DIP (Dual in
line pack) (8 pin)

Bandwidth 1 Mhz.
Slew Rate 0.5 Volts/usec
Supply Min 10 Volt
Supply Max 36V
(Differential)
Offset Voltage max, 6, 5 mV
25C
CMRR 90 db
Saturation Voltage ± 13V
Output Impedance 75Ω
Virtual Ground:
It is a node of the circuit that is maintained at a steady reference potential,
without being connected directly to the reference potential. In some cases
the reference potential is considered to be that of the surface of the earth,
and the reference node is called "ground" or "earth" as a consequence.
Once the virtual ground is created, it has to be kept steady since the input
sources and the loads connected to this point affect it by "injecting" or
"sinking" a current. This is the well-known problem of keeping up a constant
voltage (zero voltage is also a voltage).

Practical circuit Diagrams:

1. Inverting and Non-Inverting Amplifiers (AC and DC)

Theoretically no current flows into either of the input terminals. However, in reality, a
small current flows into both inputs to bias the input transistors. This bias current
gets converted into a voltage and this result in an output error in the circuit. The
solution for this i to introduce a resistor to ground from + input to ground. Assume
that the bias currents are equal Ib+ = Ib- = Ib.

Ib ∙ R3 ∙ ( R2 / R1 + 1 ) = Ib ∙ R2
Solve for R3 in terms of R1 and R2, we get
R3 = ( R2 ∙ R1 ) / ( R1 + R2 ) = R1 || R2
However not in reality, the input currents are not exactly matched. They could differ
by 10% or more and hence the error correction is partial.
2. Inverting Adder (AC and DC):

Design procedure:
Using KCL,
V1/R1+ V2/R2+ V0/R5 =0
V0= -R5 (V1/R1+ V2/R2)
Select R1= R2= R5= R

V0 = -(V1+ V2)

V1 and V2 are the input voltages and Vo is the output voltages R4= R1//R2//R5
NON INVRTING ADDER:

AC and DC non-inverting Adder:

Design procedure:

V1-Va +V2-Va = 0
R1 R2
If R1=R2=R
Va=(V1+V2) /2
Vo = (1+Rf/R1) Va
Therefore,

Vo=V1+V2
SUBTRACTOR:

Design procedure:
Using superposition theorem,
V2=0,
Vo1= -(Rf/R1)V1
If Rf=R1,then Vo1= -V1

Similarlly,V1=0,
V02=(1+ Rf/R1)Va,
Va=(V2*R3)/(R3+R2)

If R3=R2=R,
Va=V2/2
Therefore,Vo2=V2
Vo=Vo1+Vo2=V2-V1

COMPARATOR:

Design procedure:
V1 and V2 are the input voltages ,V1 as input voltage and V2 as reference voltages.
If V1> Vref, Vo= -Vsat
If V1< Vref, Vo= +Vsat
Tabular form;

S.No V1(Volts) V2(Volts) Vo=V1+V2 Vo=-(V1+V2) V0=V1-V2

(Non-inverting (Inverting (Subtractor)
adder) Adderer)

Theoretical Practic Theor Practi Theoreti Practica

al etical cal cal l
Comparator:

Vin Vref Vo

Model Greaphs for comparator;

V0

+Vsat

Vid

-Vsat

Typical Example:
Deter mone the output voltage for the circuit shown in fig.1 R1= R2 =R3= 1KΩ ; R4=1KΩ ,
AssumeV1=1,V2=3V
 R4

1.0kΩ

4 U1 3
R3
GND 2
2
1.0kΩ
R1 6
GND
4 1 3
1.0kΩ
V1 R2 7 1 5 741
1V
5
1.0kΩ
V2
GND
1V

GND

V1-Va +V2-Va =0
R1 R2

If R1=R2=R= 1KΩ
Va=( 1+3)/2=2V
Vo=(1+Rf/R1) Va=(1+1)*2=4v
Vary the power supply V1 and V2 but donot exceed the op-amp supply voltages ± 12v

Inverting adder;
VEE
R5 -12V

VEE
1.0kΩ
1
4 U1
R1 XMM1
3
2
V1 1.0kΩ
6
1V
3
R2 5
2 4
7 1 5 741
V2 1.0kΩ VCC
2V
R4
1.0kΩ VCC
GND 12V

GND

Using KCL,
V1/R1+ V2/R2+ V0/R5 =0
V0= -R5 (V1/R1+ V2/R2)
Select R1= R2= R5= R=1KΩ
Subtractor:
V EE
-12V

R4

1.0kΩ VEE XMM1

U1 VEE
4 3
R1 -12V
4 1
2
V1 1.0kΩ
6
3V R2
2 3

1.0kΩ 741
7 1 5
5
VCC
R3
1.0kΩ
VCC
V2
6V 12V
GND

GND

Design procedure:
If R1=R2=1KΩ ;
Using superposition theorem,
V2=0,
Vo1= -(R4/R1)V1=-
If R4=R1,=then Vo1= -V1

Similarlly,V1=0,
V02=(1+ R4/R1)Va,=2Va
Va=(V2*R3)/(R3+R2)

If R3=R2=R=1KΩ ,
Va=V2/2
Therefore,Vo2=V2
Vo=Vo1+Vo2=V2-V1

Vary the power supply V1 and V2 but donot exceed the op-amp supply voltages ± 12v

VEE

-12V
VEE

4 U1 XMM1
R1
3 1

1.0kΩ 2
V1 R2
2 6
4V 5
4
1.0kΩ 3

V2 7 1 5 741
5V VCC
GND
VCC
12V
GND

V1 and V2 are the input voltages ,V1 as input voltage and V2 as reference voltages.
If V1> Vref, Vo= -Vsat= -Vcc+1=11v
If V1< Vref, Vo= +Vsat= Vcc-1=11v

EXCISE PROBLEMS:
1.Design a circuit which gives output of –(V1+2V2+5V3)=0
2.design a ckt which gives out put of V1+V2-4V3-V4=0

What does the student learn after doing this experiment:

Operational amplifier as the name it self indicates that it is used for the Linear applications
like adder,subtractor and Non-linear applications like comparator,Schmitt trigger.
Theory:
Adder: If the input voltages are given to the inverting input terminal and Non-inverting
terminal is grounded.the that circuit called as inverting adder.It can able to add N input
voltages but output. Output voltage is negetive sum voltage.
V0=-(V1+V2)
If the input voltages are given to the Non-inverting input terminal and inverting terminal is
grounded.the that circuit called as Non- inverting adder.It can able to add N input voltages
but output voltage does not exceed the supply voltage of op-amp. voltage does not exceed
the supply voltage of op-amp.Output voltage is positive sum voltage.

Vo=V1+V2

Subtractor:
Output voltage is the difference of the inputn voltage.If V2>V1 the V0 is positive
difference.If V2<V1 then Vo is negetave difference.
Comparator:
Basic comparator compares two signals.Vin is the input signal and Vref is the reference
signal.there is no feedback resistor that is op-amp works in open-loop configuration.so that
the output ± Vsat that depends on Vid deference voltage at the input of op-amp.

Zero cross detector:

 Vo
+Vsat

Vid

-Vsat

Modelgragh:

Negetive comparator
V0

+Vsat

-Vref Vid

-Vsat

Vo
Positive comparator
+vsat

+Vref

Vid

-Vsat

Procedure:
1.connect the ckt on braed board as per the circuit diagram.
2.Apply input voltages from regulated power supplywhich ranges from 0-30 V.
3.Measure output voltages on the digital multimeter by keeping rotary Knob in DC voltage
options.tabulate the output values.

4.for AC Input signal, same procedure is followed except output observed on CRO.

What does the student learn after doing this experiment:

Operational amplifier as the name it self indicates that it is used for the Linear applications
like adder, Subtractor and Non-linear applications like comparator, Schmitt trigger.

EXPERIMENT: 2 Page 1.1

ACTIVE FILTER APPLICATIONS

Aim: To design a Lowpass and high pass filter with different cutoff frequencys and gain.

1 Equipments Required:
a) Function Generator 0 – 10 V pk-pk, 0-1 Mhz, Min Sin wave and 1
Square wave out put
b) Cathode Ray Oscilloscope Min 10 MHz Bandwidth 1
c) Dual output Regulated Power +/- 15V Minimum 1
Supply
2 Specific Knowledge required for conducting experiment:
 Equipments Function Generator:
• Learn the functioning of “offset knob” adjustment. This knob is used to
add DC component to the AC signal.
• Pure AC signal is produced by the oscillator by locking the “Offset knob”
• Note that it is not possible to set the exact frequency and the r.m.s. /
peak voltage output using the controls available on the function
generator. Additional equipment or circuits are required to measure
these parameters.

Oscilloscope:
• Learn using Oscilloscope for the approximate measurement of amplitude
(peak), frequency and Phase difference between two wave forms.
• Set the Oscilloscope in DC mode.
• Connect any signal of (say) 1KHZ, 0.2V peak to peak Sine wave from
Oscillator to any channel of C.R.O.
• Check if the signal contains any DC offset. This is checked by switching
the oscilloscope mode between DC and AC. If the displayed waveform
does not shift while switching these modes back and forth, then the
signal does not have DC offset. Lock Offset adjust or adjust the offset on
the oscillator such a way that the displayed waveform does not have any
offset.

c) Frequency Measurement:
• Set the Oscilloscope in AC mode.
• Adjust the time/div knob such a way that the oscilloscope displays
one cycle or little over one cycle. To measure the given waveform
frequency, observe the horizontal divisions per cycle and multiply
with time per division and then calculate frequency using formulae
f = 1/T.

d) Voltage Peak –Peak measurement

• Set the Oscilloscope in AC mode.
• Decrease the voltage range (gain) on the oscilloscope to the lowest
level that will still display any one of the peaks of the wave form to
measure the peak. Now measure the voltage (one) peak.

3 Component Identifying the Pin-1 of given 741. Lean 741 technical details like
s bandwidth, gain, CMRR, Virtual ground, Maximum operating voltages,
Distinguishing Single ended and differential power supply constraints of
741, etc.
 IC 741 comes in two different packages. A) Round (8 pin) and DIP (Dual in
line pack) (8 pin)

Bandwidth 1 Mhz.
Slew Rate 0.5 Volts/usec
Supply Min 10 Volt
Supply Max 36V
(Differential)
Offset Voltage max, 6, 5 mV
25C
CMRR 90 db
Saturation Voltage ± 13V
Output Impedance 75Ω
Virtual Ground:
It is a node of the circuit that is maintained at a steady reference potential,
without being connected directly to the reference potential. In some cases
the reference potential is considered to be that of the surface of the earth,
and the reference node is called "ground" or "earth" as a consequence.
Once the virtual ground is created, it has to be kept steady since the input
sources and the loads connected to this point affect it by "injecting" or
"sinking" a current. This is the well-known problem of keeping up a constant
voltage (zero voltage is also a voltage).

Practical circuit Diagrams:

2. Inverting and Non-Inverting Amplifiers (AC and DC)

Theoretically no current flows into either of the input terminals. However, in reality, a
small current flows into both inputs to bias the input transistors. This bias current
gets converted into a voltage and this result in an output error in the circuit. The
solution for this i to introduce a resistor to ground from + input to ground. Assume
that the bias currents are equal Ib+ = Ib- = Ib.
Ib ∙ R3 ∙ ( R2 / R1 + 1 ) = Ib ∙ R2
Solve for R3 in terms of R1 and R2, we get
R3 = ( R2 ∙ R1 ) / ( R1 + R2 ) = R1 || R2
However not in reality, the input currents are not exactly matched. They could differ
by 10% or more and hence the error correction is partial.

Design procedure:
 Analysis of the filter circuit :
The impedance of the capacitor C is –JXC where Xc is the capacitive reactance i.e 1/2∏C

Va at Non-inverting input terminal

Va = (-jXc)/(R1-jxC1)Vin

Va= Vin
1+j2∏fRC
As op-amp is in the Non-inverting[ Vo= (1+Rf/R2)Va = (1+Rf/R2) [ Vin /(1+j2∏fRC) ]
V0/Vin=AF[ j f/fL /(1+jf/fL)]
MagnitudeVo/Vin= AF/√1+(f/fH)2 ; wheref H= 1/2∏RC
Where f=operating frequency
fh=Higher cutoff frequency of lowpass filter =1/2∏RC
Af= Gain of the filter in passband =(1+Rf/R2)
Φ =phase= -tan-( f/fh )
Designing steps:
Designing steps for the first order High pass butterworth filter,
1.Choose the cutoff frequency,fL
2.choose the capacitance C usually C is 0.01µ f,
3.For Rc circuit, fL= 1/2∏RC, Hence fL and C are known,calculate R.
4. Select Rf,and R2 depending on passband gain Af,so Af=( 1+Rf/R2)
EXAMPLE:

Design a first order butterworth low pass filter having fh=10Khz,gain of 10,c=.01µ f,
Af= Gain of the filter in passband=11
(i) Af= (1+Rf/R2)=11;
Rf/R2=10 => Rf = 10R2;
(ii) fh=1/2∏RC =10 Khz

R=1/2∏Cfh=16kΩ

CIRCUIT DIAGRAM:

Procedure:
a. Make connections as per the circuit diagram.
b. connect input signal to one channel of the CRO and output signal to other
channel.
c. Adjust the power supplies VCC=12v and VEE=-12V.
d. Adjust both the channels to of CRO to ground position.
e. Apply input sinewave of 2Vp-p from function generator vary the amplitude of
input signal and observe output signal amplitude.
f. Draw the graph on semlog graphsheet between fin and magnitude of the gain
AF in dB.

S.No Frequency in Hz Vo in volts Gain Av=Vo/Vin Gain in dB=20 log Av

Design procedure:

FIRST ORDER HIGH PASS FILTER:

 Analysis of the filter circuit :
The impedance of the capacitor C is –JXC where Xc is the capacitive reactance i.e 1/2∏C

Va at Non-inverting input terminal

Va = [ (R)/(R1-jxC1) Vin ]

Va= Vin ( j2∏fRC)

1+j2∏fRC
As op-amp is in the Non-inverting[ Vo= (1+Rf/R2)Va = (1+Rf/R2) [ Vin ( j2∏fRC) /(1+2∏fRC) ]
V0/Vin=( jf/fh AF /(1+jf/fh))
MagnitudeVo/Vin= AF/√1+( f/fL )2; where fL= 1/2∏fRC
Where f=operating frequency
FL=Lower cutoff frequency of Highpass filter =1/2∏fRC
Af= Gain of the filter in passband =1+ Rf/R2
Φ =phase= -tan-( f/fh )
Designing steps:
Designing steps for the first order High pass butterworth filter,
1.Choose the cutoff frequency,fH
2.choose the capacitance C usually C is 0.01µ f,
3.For Rc circuit, fL = 1/2∏RC, Hence C are known,calculate R.
4. Select Rf,and R2 depending on passband gain Af,so Af=( 1+Rf/R2)

EXAMPLE:
Design a first order butterworth High pass filter having fh=10Khz,gain of 10,c=0.01µ f,
Af= Gain of the filter in passband=11
(i) Af= (1+Rf/R2)=11;
 Rf/R2=10 => Rf = 10R2;
(ii) fh=1/2∏RC =10 Khz

R=1/2∏Cfh=16kΩ

CIRCUIT DIAGRAM:

Procedure:
g. Make connections as per the circuit diagram.
h. connect input signal to one channel of the CRO and output signal to other
channel.
i. Adjust the power supplies VCC=12v and VEE=-12V.
j. Adjust both the channels to of CRO to ground position.
k. Apply input sinewave of 2Vp-p from function generator vary the amplitude of
input signal and observe output signal amplitude.
l. Draw the graph on semlog graphsheet between fin and magnitude of the gain
AF in dB.
S.No Frequency in Hz Vo Gain Av=Vo/Vin Gain in Db=20 log Av

What does the student learn after doing this experiment:

How to design active filters using op-amp,design of different other active filters like wide
band bandpass filter and band rejection filter.

EXPERIMENT: 3 Page 1.1

FUNCTION GENERATOR USING OP-AMP

AIM:TO DESIGN A FUNCTION GENERATOR TO GENERATE SINEWAVE,SQUAREWAVE AND
TRIANGULAR WAVE
1 Equipments Required:
b) Cathode Ray Oscilloscope Min 10 MHz Bandwidth 1
c) Dual output Regulated Power +/- 15V Minimum 1
Supply
2 Specific Knowledge required for conducting experiment:
Equipments Oscilloscope:
• Learn using Oscilloscope for the approximate measurement of amplitude
(peak), frequency and Phase difference between two wave forms.
• Set the Oscilloscope in DC mode.
• Connect any signal of (say) 1KHZ, 0.2V peak to peak Sine wave from
Oscillator to any channel of C.R.O.
• Check if the signal contains any DC offset. This is checked by switching
the oscilloscope mode between DC and AC. If the displayed waveform
does not shift while switching these modes back and forth, then the
signal does not have DC offset. Lock Offset adjust or adjust the offset on
the oscillator such a way that the displayed waveform does not have any
offset.

e) Frequency Measurement:
• Set the Oscilloscope in AC mode.
• Adjust the time/div knob such a way that the oscilloscope displays
one cycle or little over one cycle. To measure the given waveform
frequency, observe the horizontal divisions per cycle and multiply
with time per division and then calculate frequency using formulae
f = 1/T.

f) Voltage Peak –Peak measurement

• Set the Oscilloscope in AC mode.
• Decrease the voltage range (gain) on the oscilloscope to the lowest
level that will still display any one of the peaks of the wave form to
measure the peak. Now measure the voltage (one) peak.

3 Component Identifying the Pin-1 of given 741. Lean 741 technical details like
s bandwidth, gain, CMRR, Virtual ground, Maximum operating voltages,
Distinguishing Single ended and differential power supply constraints of
741, etc.
IC 741 comes in two different packages. A) Round (8 pin) and DIP (Dual in
line pack) (8 pin)

Bandwidth 1 Mhz.
Slew Rate 0.5 Volts/usec
Supply Min 10 Volt
Supply Max 36V
(Differential)
 Offset Voltage max, 6, 5 mV
25C
CMRR 90 db
Saturation Voltage ± 13V
Output Impedance 75Ω
Virtual Ground:
It is a node of the circuit that is maintained at a steady reference potential,
without being connected directly to the reference potential. In some cases
the reference potential is considered to be that of the surface of the earth,
and the reference node is called "ground" or "earth" as a consequence.
Once the virtual ground is created, it has to be kept steady since the input
sources and the loads connected to this point affect it by "injecting" or
"sinking" a current. This is the well-known problem of keeping up a constant
voltage (zero voltage is also a voltage).

THEORY:

I.SQUREWAVE GENERATION:

In this circuit a fraction R2/ (R1 +R2) = of the output is feedback to the
non-inverting input terminal. The operation of the circuit can be explained as
follows:

Assume that the output voltage is +Vsat. The capacitor will charge exponentially
toward +Vsat. The feedback voltage is +Vsat. When capacitor voltage exceeds
+Vsat the output switches from +Vsat to -Vsat. The feedback voltage becomes
-Vsat and the output will remain ?Vsat. Now the capacitor charges in the reverse
direction. When capacitor voltage decreases below ?Vsat (more negative than ?
Vsat ) the output again switches to +Vsat.This process continues and it produces a
square wave. Under steady state conditions, the output voltage and capacitor
voltage are shown in FIG.The frequency of the output can be obtained as follows:
DESIGN PROCEDURE FOR SQUARE WAVE:

The capacitor charges from -β Vsat to +β Vsat during time period T/2. The capacitor
charging voltage expression is given by
TRIANGULAR WAVE GENERATION:

PRACTICAL TRIANGULAR WAVE GENERATOR:

In this circuit an OPAMP integrator is used to supply a constant current to C so that the output is
linear. Because of inversion through the integrator, this voltage is fedback to the non-inverting
terminal of the comparator rather than to the inverting terminal. The inverter behaves as a non-
inverting schmitt trigger. The voltage vR is used to shift the dc level of the triangular wave and
voltage vs is used to change the slopes of the triangular wave form is shown in fig. 2.
Fig. 2
To find the maximum value of the triangular waveform assume that the square wave voltage vOis
at its negative value = -Vsat. With a negative input, the output v (t) of the integrator is an
increasing ramp. The voltage at the non-inverting comparator input v1 is given by

When v1 rises to VR, the comparator changes state from - Vsat to +Vsat and v(t) starts decreasing
linearly similarly, when v1 falls below vR the comparator output changes from +vsat to -vsat. Hence
the minimum value of triangular vmin occurs for v1 = vR. Hence the peak value Vmax of the
triangular waveform occurs for v1 = VR.

DESIGN PROCEDURE FOR TRIANGULAR WAVE:

The peak to peak swing is given by
-

The average output voltage is given by.

If VR = 0, the waveform extends between -Vsat (R2 / R1 ) and +Vsat (R2 /R1).
The sweep times T1 and T2 for Vs = 0 can be calculated as follows:
The capacitor charging current is given by
where, vc = -vout is the capacitor voltage.

For vout = -Vsat, . Therefore

When the output voltage of first OPAMP is +Vsat, then, the voltage v1 is given by

As triangular voltage increases the voltage v1 also increases. At t = T1, when the voltage vout
becomes Vmax, the voltage v1 becomes equal to VR and switching takes place. Therefore,

Similarly, when output voltage is +Vsat, the voltage v1 is given by

As triangular voltage decreases the voltage v1 also decreases. At t = T2, when the voltage vout
becomes Vmin, the voltage v1 becomes equal to VR and switching takes place. Therefore,

Therefore,
, we get
The frequency f is independent of VO, maximum frequency is limited either by slew rate or its
maximum output current which determines the charging rate of C. Slowest speed is limited by
the bias current of OPAMP.
If unequal sweep intervals T1≠ T2 are desired, then VS can be changed. The positive sweep speed
is given by (Vsat + VS) / RC and the negative sweep speed is given by (V sat -VS)/ RC. The peak-
to-peak
Solving the above equations triangular amplitude is unaffected by the voltage VS.

Therefore,

Similarly, when the output voltage of first OPAMP is ?Vsat, then

Therfore,

Therefore,

The oscillation frequency is given by

and the duty cycle is given by

practical circuit:

substituted all the parameters in the equation,caliculated frequency.

III. Wien Bridge Oscillator:

The Wien Bridge oscillator is a standard oscillator circuit for low to moderate
frequencies, in the range 5Hz to about 1MHz. It is mainly used in audio frequency
generators.
The gain of the feedback circuit is given by
 The phase angle between Vout and Vinis given by

PRACTICAL SINEWAVE GENERATOR:

Tabular form;
WAVEFORM FREQUENCY AMPLITUDE
THEORITICA PRACTCALY HEORITICAL PRACTCALY
LY Y
SQUARE
WAVE
TRIANGULA
R WAVE
SINE WAVE

What does the student learn after doing this experiment:

How to generate different types of waveforms of different amplitude and different

frequencys
using op-amp.

EXPERIMENT: 4 Page 1.1

A
ASTABLE AND MONOSTABLE MULTIVIBRATOR
AIM: TO DESIGN A MONOSTABLE AND ASTABLE MULTIVIBRATOR USING IC 555
1 Equipments Required:
a) Function Generator 0 – 10 V pk-pk, 0-1 Mhz, Min Sin wave and Square
wave out put
b) Cathode Ray Oscilloscope Min 10 MHz Bandwidth 1
c) Dual output Regulated Power +/- 15V Minimum 1
Supply
2 Specific Knowledge required for conducting experiment:
Equipments Function Generator:
• Learn the functioning of “offset knob” adjustment. This knob is used to
add DC component to the AC signal.
• Pure AC signal is produced by the oscillator by locking the “Offset knob”
• Note that it is not possible to set the exact frequency and the r.m.s. /
peak voltage output using the controls available on the function
generator. Additional equipment or circuits are required to measure
these parameters.

Oscilloscope:
• Learn using Oscilloscope for the approximate measurement of amplitude
(peak), frequency and Phase difference between two wave forms.
• Set the Oscilloscope in DC mode.
• Connect any signal of (say) 1KHZ, 0.2V peak to peak Sine wave from
Oscillator to any channel of C.R.O.
• Check if the signal contains any DC offset. This is checked by switching
the oscilloscope mode between DC and AC. If the displayed waveform
does not shift while switching these modes back and forth, then the
signal does not have DC offset. Lock Offset adjust or adjust the offset on
the oscillator such a way that the displayed waveform does not have any
offset.

g) Frequency Measurement:
• Set the Oscilloscope in AC mode.
• Adjust the time/div knob such a way that the oscilloscope displays
one cycle or little over one cycle. To measure the given waveform
frequency, observe the horizontal divisions per cycle and multiply
with time per division and then calculate frequency using formulae
f = 1/T.
h) Voltage Peak –Peak measurement
• Set the Oscilloscope in AC mode.
• Decrease the voltage range (gain) on the oscilloscope to the lowest
level that will still display any one of the peaks of the wave form to
measure the peak. Now measure the voltage (one) peak.

3 Component Identifying the Pin-1 of given 555. Learn 555 Technical details like
s bandwidth, gain, CMRR, Virtual ground, Maximum operating voltages,
Distinguishing Single ended and differential power supply constraints of555,
etc.
Pin1: Ground. All voltages are measured with respect to this terminal.

Pin2: Trigger. The output of the timer depends on the amplitude of the external
trigger pulse applied to this pin. The output is low if the voltage at this pin is
greater than 2/3 VCC. When a negative going pulse of amplitude greater than 1/3
VCC is applied to this pin, comparator 2 output goes low, which inturn switches
the output of the timer high. The output remains high as long as the trigger
terminal is held at a low voltage.

Pin3: Output. There are two ways by which a load can be connected to the
output terminal: either between pin 3 and ground or between pin3 and supply
voltage +VCC. When the output is low the load current flows through the load
connected between pin3 and +VCC into the output terminal and is called sink
current. The current through the grounded load is zero when the output is low.
For this reason the load connected between pin 3 and +VCC is called the
normally on load and that connected between pin 3 and ground is called
normally off-load. On the other hand, when the output is high the current
through the load connected between pin 3 and +VCC is zero. The output terminal
supplies current to the normally off load. This current is called source current.
The maximum value of sink or source current is 200mA.

Pin4: Reset. The 555 timer can be reset (disabled) by applying a negative pulse
to this pin. When the reset function is not in use, the reset terminal should be
connected to +VCC to avoid any possibility of false triggering.

Pin5: Control Voltage. An external voltage applied to this terminal changes the
threshold as well as trigger voltage. Thus by imposing a voltage on this pin or
by connecting a pot between this pin and ground, the pulse width of the output
waveform can be varied. When not used, the control pin should be bypassed to
ground with a 0.01µF Capacitor to prevent any noise problems.

Pin6: Threshold. This is the non-inverting input of comparator 1, which

monitors the voltage across the external capacitor. When the voltage at this pin
 is greater than or equal to the threshold voltage 2/3 VCC, the output of
comparator 1 goes high, which inturn switches the output of the timer low.

Pin7: Discharge. This pin is connected internally to the collector of transistor

Q1. When the output is high Q1 is OFF and acts as an open circuit to external
capacitor C connected across it. On the other hand, when the output is low, Q1
is saturated and acts as a short circuit, shorting out the external capacitor C to
ground.

Pin8: +VCC. The supply voltage of +5V to + 18V is applied to this pin with
respect to ground.

Specificatio
ns of IC555 Supply voltage (VCC) 4.5 to 15 V

Supply current (VCC = +5 V) 3 to 6 mA

Supply current (VCC = +15V) 10 to 15 mA

Output current (maximum) 200 mA

Power dissipation 600 mW

Operating temperature 0 to 70 °C

THEORY:

Designing procedure of astable multivibrator:

The circuit diagram for the astable multivibrator using IC 555 is shown here. The astable
multivibrator generates a square wave, the period of which is determined by the circuit external
to IC 555. The astable multivibrator does not require any external trigger to change the state of
the output. Hence the name free running oscillator. The time during which the output is either
high or low is determined by the two resistors and a capacitor which are externally connected to
the 555 timer.
The above figure shows the 555 timer connected as an astable multivibrator. Initially when the
output is high capacitor C starts charging towards Vcc through RA and RB
However as soon as the voltage across the capacitor equals 2/3 Vcc, comparator1 triggers the flip-
flop and the output switches to low state. Now capacitor C discharges through RB and the
transistor Q1. When voltage across C equals 1/3 Vcc, comparator 2’s output triggers the flip-flop
and the output goes high. Then the cycle repeats.
The capacitor is periodically charged and discharged between 2/3 Vcc and 1/3 Vcc respectively.
The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the time the
output remains high and is given by

where RA and RB are in ohms and C is in Farads. Similarly the time during which the capacitor
discharges from 2/3 Vcc to 1/3 Vcc is equal to the time the output is low and is given by

Thus the total time period of the output waveform is

Therefore the frequency of oscillation

The output frequency, f is independent of the supply voltage Vcc.
This circuit diagram shows how a 555 timer IC is configured to function as an astable multivibrator. An
astable multivibrator is a timing circuit whose 'low' and 'high' states are both unstable. As such, the
output of an astable multivibrator toggles between 'low' and 'high' continuously, in effect generating a
train of pulses. This circuit is therefore also known as a 'pulse generator' circuit.

In this circuit, capacitor C1 charges through R1 and R2, eventually building up enough voltage to trigger
an internal comparator to toggle the output flip-flop. Once toggled, the flip-flop discharges C1 through
R2 into pin 7, which is the discharge pin. When C1's voltage becomes low enough, another internal
comparator is triggered to toggle the output flip-flop. This once again allows C1 to charge up through R1
and R2 and the cycle starts all over again.

C1's charge-up time t1 is given by: t1 = 0.693(R1+R2)C1. C1's discharge time t2 is given by: t2 =
0.693(R2)C1. Thus, the total period of one cycle is t1+t2 = 0.693 C1(R1+2R2). The frequency f of the
output wave is the reciprocal of this period, and is therefore given by: f = 1.44/(C1(R1+2R2)), wherein f
is in Hz if R1 and R2 are in megaohms and C1 is in microfarads.
DESIGN PROCEDURE OF MONOSTABLE MULTIVIBRATOR:
 555 monostable output, a single pulse

555 Monostable
A monostable circuit produces a single
output pulse when triggered. It is called a
monostable because it is stable in just
one state: 'output low'. The 'output high'
state is temporary.

The duration of the pulse is called the

time period (T) and this is determined by
resistor R1 and capacitor C1:

time period, T = 1.1 × R1 × C1 555 monostable circuit with manual trigger

T = time period in seconds (s)

R1 = resistance in ohms ( )
C1 = capacitance in farads (F)
The maximum reliable time period is about 10 minutes.

Why 1.1? The capacitor charges to 2/3 = 67% so it is a bit longer than the time constant (R1 × C1) which
is the time taken to charge to 63%.

• Choose C1 first (there are relatively few values available).

• Choose R1 to give the time period you need. R1 should be in the range 1k to
1M , so use a fixed resistor of at least 1k in series if R1 is variable.
• Beware that electrolytic capacitor values are not accurate, errors of at least 20%
are common.
• Beware that electrolytic capacitors leak charge which substantially increases the
time period if you are using a high value resistor - use the formula as only a very
rough guide

Monostable operation:
The timing period is triggered (started) when the trigger input (555 pin 2) is less than
1
/3 Vs, this makes the output high (+Vs) and the capacitor C1 starts to charge through
resistor R1. Once the time period has started further trigger pulses are ignored.

The threshold input (555 pin 6) monitors the voltage across C1 and when this reaches
2
/3 Vs the time period is over and the output becomes low. At the same time discharge
(555 pin 7) is connected to 0V, discharging the capacitor ready for the next trigger.
The reset input (555 pin 4) overrides all other inputs and the timing may be cancelled at any
time by connecting reset to 0V, this instantly makes the output low and discharges the capacitor.
If the reset function is not required the reset pin should be connected to +Vs.

Procedure for astable multivibrator:

1.Connect the circuit as per the circuit diagram.
2.Apply +Vcc equal to 6V from regulated power supply.
3.Observe out put wave form at pin3 of channel-1 on CRO.
4.Obsserve the charging and discharging of capasitor or other channels on CRO.
5. Calculate the duty cycle on time,off time,frequency of out put wave form.

PRACTICAL CIRCUIT OF ASTABLE MULTIVIBRATOR:

Design apractical astable circuit with on time0 .42msec,off time 0.27msec,with 60%duty cycle
of assume c=0.1µsec
 =offtime=0.27msec=dischargetime
=on time=0.42msec=chaging time
=0.69msec=total time

Astable multivibrator Model waveforms:

Monostable multivibrator Practical circuit:

Design a monostable multivibrator with time period of .42msec.assume c=0.1µsec

time period, T = 1.1 × R1 × C1
Procedure for monostable multivibrator:

1. Connect the circuit as per the circuit diagram.

2. Apply the triggering input of 3V p-p 1 khz square wave at pin number2.

3. Vary the duty cycle of triggering input signal &observe output wave form at pin3and also charging and discharging
capacitor at the other channel of CRO.

What does the student learn after doing this experiment:

Students are able to design monostable multivibrators and atable multivibrators of different
tc and td, with different duty cycles.

EXPERIMENT: 5 Page 1.1

ai
Digital to Analog converter
Aim: To design a R-2R LADDER TYPE DAC
1 Equipments Required:
a) Dual output Regulated Power +/- 15V Minimum 2
Supply
b) Multimeter meco 1
2 Specific Knowledge required for conducting experiment:
Equipments • .

3 Component Identifying the Pin-1 of given 741. Lean 741 technical details like
s bandwidth, gain, CMRR, Virtual ground, Maximum operating voltages,
Distinguishing Single ended and differential power supply constraints of
741, etc.
 IC 741 comes in two different packages. A) Round (8 pin) and DIP (Dual in
line pack) (8 pin)

Bandwidth 1 Mhz.
Slew Rate 0.5 Volts/usec
Supply Min 10 Volt
Supply Max 36V
(Differential)
Offset Voltage max, 6, 5 mV
25C
CMRR 90 db
Saturation Voltage ± 13V
Output Impedance 75Ω
Virtual Ground:
It is a node of the circuit that is maintained at a steady reference potential,
without being connected directly to the reference potential. In some cases
the reference potential is considered to be that of the surface of the earth,
and the reference node is called "ground" or "earth" as a consequence.
Once the virtual ground is created, it has to be kept steady since the input
sources and the loads connected to this point affect it by "injecting" or
"sinking" a current. This is the well-known problem of keeping up a constant
voltage (zero voltage is also a voltage).

THEORY:

Designing procedure of R-2R Ladder type Digital to Analog converter :

T
Five-bit R-2R resistor ladder:

A basic R-2R resistor ladder network is shown in Figure 1. Bit4 MSB (most significant bit) to
Bit0 LSB (least significant bit) are driven from digital logic gates. Ideally, the bits are switched
between 0 volts (digital 0) and Vref (digital 1). The R-2R network causes the digital bits to be
weighted in their contribution to the output voltage Vout. In this circuit 5 bits are shown, giving
32 possible outputs. Depending on which bits are set to 1 and which to 0 the output voltage (out)
will be a stepped value between 0 volts and (Vref minus the value of the minimum step, Bit0).
The actual value of Vref (and 0 volts) will depend on the type (technology) of the digital logic
gates used to drive Bit4-0[1].

For a digital value VAL, of a R-2R DAC of N bits of 0 V/Vref, the output voltage Vout is:

Vout = Vref × VAL / 2N

In the example shown, N = 5 and hence 2N = 32. With Vref = 3.3 V (typical TTL logic 1 voltage),
Vout will vary between 00000, VAL = 0 and 11111, VAL = 31.

Minimum (single step) VAL = 1, we have

Vout = 3.3 × 1 / 32 = 0.1 volts

Maximum output (11111 VAL = 31, we have

Vout = 3.3 × 31 / 25 = 3.2 volts

The R-2R ladder is inexpensive and relatively easy to manufacture since only two resistor values
are required (or 1, if R is made by placing a pair of 2R in parallel, or if 2R is made by placing a
pair of R in series). It is fast and has fixed output impedance R. The R-2R ladder operates as a
string of current dividers whose output accuracy is solely dependent on how well each resistor is
matched to the others. Small inaccuracies in the higher significant bit resistors can entirely
overwhelm the contribution of the less significant bits. This may result in non-monotonic
behavior at major crossings, such as from 01111 to 10000. Depending on the type of logic gates
used and design of the logic circuits, there may be transitional voltage spikes at such major
crossings even with perfect resistor values. These can be filtered, with capacitance at the output
node for instance (the consequent reduction in bandwidth may be significant in some
applications). Finally, the 2R resistance is in series with the digital output impedance. High
output impedance gates (e.g., LVDS) may be unsuitable in some cases. For all of the above
reasons (and doubtless others), this type of DAC tends to be restricted to a relatively small
number of bits, although integrated circuits may push the number of bits to 14 or even more, the
home constructor will typically limit themselves to 8 or less.

Execesises proble:
Practical circuit diagrams:
 Result observed
on
multimeter

FOR 1010
R9

4 .7 kΩ

V EE
1
VE E -12V XMM1

4 U1
Result observed on
4
R1
3
R2
2
R3 multimeter
2
4 .7 kΩ 4 .7 kΩ 4 .7 kΩ 10
6
R8 3
1 0 kΩ R4 R6
1 0 kΩ R7 R5 0
1 0 kΩ 7 1 5 741
1 0 kΩ 1 0 kΩ
0
5 VCC
8
6 7
J1
V CC
J2 J3 J4 1 2V
Key = A Key = B Key = C Key = D
a
0
V1
9

0
12 V
Procedure:
1. Connect the circuit diagram as shown figure.
2. Change the the switch position corresponds to to the input bit value i.e for bit ‘1’ move
the switch position to v1 of 12v,for bit ‘0’ move switch to ground position.similarly
adjust all input bits.
3. Observed output on multimeter for all combinations of input.
4.Draw the graph for input digital bits versus analog output observed on multimeter.

MODEL GRAPH:

What does the student learn after doing this experiment:

After completing this experiment students are able to design R-2R Ladder type DAC
EXPERIMENT: 6
Page 1.1
VOLTAGE REGULATOR DESIGN USING IC 723
AIM :TO DESIGN A VOLTAGE REGULAR USING IC 723
1 Equipments Required:
a) Cathode Ray Oscilloscope Min 10 MHz Bandwidth 1
b) Dual output Regulated Power +/- 15V Minimum 1
Supply
2 Specific Knowledge required for conducting experiment:
Ammeter:(0-50 mA) DC ammeter
3 Voltmeter(0-20v) DC VOLTEMETER
 Specifications of IC723 Typical Performance
Regulated Output Voltage 5V
Line Regulation (DVIN = 3V) 0.5mV

Load Regulation (DIL = 50 mA) 1.5mV

pulse Voltage from V+ to V− (50 ms) 50V

Current from VREF: 15 mA Internal Power Dissipation

Metal Can (Note 2) 800 mW
Continuous Voltage from V+ to V− 40V
Molded DIP −55˚C to +150˚C
Input-Output Voltage Differential 40V Lead
Temperature (Soldering, 4 sec. max.)
Maximum Amplifier Input Voltage
(Either Input) 8.5V
Maximum Amplifier Input Voltage Plastic
Package 260˚C
Current from VZ 25 mA
Pulse Voltage from V+ to V− (50 ms) 50V Storage
Temperature Range
Metal Can −65˚C to +150˚C
Continuous Voltage from V+ to V− 40V
Molded DIP −55˚C to +150˚C
Input-Output Voltage Differential 40V
Maximum Amplifier Input Voltage:8.5V
Maximum Amplifier Input Voltage (Differential) 5V
Current from V: 25 mA(Human body model, 1.5
Z

kΩ in series with 100 pF)

Current from V:15 mA Internal Power Dissipation
Metal Can (Note 2): 800 mW

THEORY:

VOLAGE REGULATOR

The three terminal regulator discussed earlier have the following limitations:
1. No short circuit protection.
2. Out put voltage (positive or negative)is fixed.
These limitations have been overcome in the 723 general purpose regulator, which can be
adjusted over a wide range of both positive or negative regulated voltage. This IC is inherently
low current device, but can be boosted to provide 5 amps or more current by connecting external
components. The limitation of 723 is that it has no in-built thermal protection. It also has no
short circuit current limits.

shows the functional block diagram of a 723 regulator IC. It has two separate sections. The zener
diode,a constant current source and reference amplifier produce a fixed voltage of 7 volts at the
terminal Vref the constant current source forces the zener to operate at a fixed point so that the
zener outputs a fixed voltage.

The other section of the IC consist of an error amplifier, a series pass transistor Q1 and a current
limit transistor Q2 . The error amplifier compares a sample of the output voltage applied at the
INV input terminals to the reference voltage Vref applied at the NI input terminal. The error
signal control the conduction of Q1 these two sections are not internally connected but the
various points are brought out the IC package. 723 regulated IC is available in a14-pin dual-in –
line or 10-pin metal-can as shown figure. The important futures and electrical characteristics are
given in table.

Pactical circuit: VOLAGE REGULATOR

The three terminal regulator discussed earlier have the following limitations:
1. No short circuit protection.
2. Out put voltage (positive or negative)is fixed.
These limitations have been overcome in the 723 general purpose regulator, which can be
adjustted over a wide range of both positive or negative regulated voltage. This IC is inherently
low current device, but can be boosted to provide 5 amps or more current by connecting external
components. The limitation of 723 is that it has no in-built thermal protection. It also has no
short circuit current limits.

shows the functional block diagram of a 723 regulator IC. It has two separate sections. The zener
diode,a constant current source and reference amplifier produce a fixed voltage of 7 volts at the
terminal Vref the constant current source forces the zener to operate at a fixed point so that the
zener outputs a fixed voltage.

The other section of the IC consist of an error amplifier, a series pass transistor Q1 and a current
limit transistor Q2 . The error amplifier compares a sample of the output voltage applied at the
INV input terminals to the reference voltage Vref applied at the NI input terminal. The error
signal control the conduction of Q1 these two sections are not internally connected but the
various points are brought out the IC package. 723 regulated IC is available in a14-pin dual-in –
line or 10-pin metal-can as shown figure. The important futures and electrical characteristics are
given in table.
LM723/LM723C
Voltage Regulator
General Description
The LM723/LM723C is a voltage regulator designed primarily for series regulator applications.
By itself, it will supply output currents up to 150 mA; but external transistors can be added to
provide any desired load current. The circuit features extremely low standby current drain, and
provision is made for either linear or foldback current limiting.The LM723/LM723C is also
useful in a wide range of other applications such as a shunt regulator, a current regulator or
a temperature controller.The LM723C is identical to the LM723 except that the LM723C has its
performance guaranteed over a 0°C to +70°C temperature range, instead of −55°C to +125°C.

Features
150 mA output current without external pass transistor Output currents in excess of 10A
possible by adding external transistors Input voltage 40V max Output voltage adjustable from
2V to 37V Can be used as either a linear or a switching regulator

Equivalent Circuit

PRACTICAL CIRCUIT:
PROCEDURE

1.Connect the circuit as shown in figure

2.Set the DC VOLTAGE vin =10v.
3.Measure and record the voltage reference at pin no.5
4.Remove load RL Maximum and Minimum VL BY ROTATING 1kΩ
5. Now adjust the potentiometer to 1kΩ pot with respect to ground.
6. Adjust load RL until the load current IL=1Ma.record vL .
7.Repeat the same procedure for different values of IL i.e 5mA,10mA, 15mA,18mA.
8.Gradually increase IL above 18mA and 20mA.
9.view the voltage across resistor 33Ω enough to limit the current input.measure and record few
valuesv of load current Il and load voltage VL.
10. plot the graph between IL and VL..
TABULAR FORM

S.No. IL (mA) VL (volts)

Model graph

Some important lab objective type question

 Question 1:

Calculate the voltage gain for each stage of this amplifier circuit (both as a ratio and in
units of decibels), then calculate the overall voltage gain:

AV = 4.3 = 12.669 dB Stage

2: AV = 6.745 = 16.579 Db, Overall: AV = 29.002 = 29.249 dB

Question 2:

Predict how the operation of this operational amplifier circuit will be affected as
a result of the following faults. Consider each fault independently (i.e. one at a
time, no multiple faults):

Resistor R1 fails open:

Solder bridge (short) across resistor R1:
Resistor R2 fails open:
Solder bridge (short) across resistor R2:
Broken wire between R1/R2 junction and inverting opamp input:
For each of these conditions, explain why the resulting effects will occur

Answer: Resistor R1 fails open: Output saturates positive

Solder bridge (short) across resistor R1: Vout = Vin
Resistor R2 fails open: Vout = Vin.
Solder bridge (short) across resistor R2: Output saturates positive
Broken wire between R1/R2 junction and inverting opamp input: Output voltage unpredictable
 Question3: What possible benefit is there to adding a voltage buffer to the front end of an
inverting amplifier, as shown in the following schematic?

Answer:The voltage buffer raises the amplifier's input impedance without altering voltage gain.
question 4:
The junction between the two resistors and the inverting input of the operational amplifier is often
referred to as a virtual ground, the voltage between it and ground being (almost) zero over a
wide range of circuit conditions:

If the operational amplifier is driven into saturation, though, the "virtual ground" will no longer
be at ground potential. Explain why this is, and what condition(s) may cause this to happen.
Hint: analyze all currents and voltage drops in the following circuit, assuming an opamp with
the ability to swing its output voltage rail-to-rail.

Answer: Any input signal causing the operational amplifier to try to output a voltage beyond
either of its supply rails will cause the "virtual ground" node to deviate substantially from
ground potential
Question 5:The same problem of input bias current affecting the precision of opamp voltage
buffer circuits also affects noninverting opamp voltage amplifier circuits:

To fix this problem in the voltage buffer circuit, we added a "compensating" resistor:

To fix the same problem in the noninverting voltage amplifier circuit, we must carefully choose
resistors R1 and R2 so that their parallel equivalent equals the source resistance:

R1 || R2 = Rsource
Of course, we must also be sure the values of R1 and R2 are such that the voltage gain of the
circuit is what we want it to be.
Determine values for R1 and R2 to give a voltage gain of 7 while compensating for a source
resistance of 1.45 kΩ.
 R1 = 1.692 kΩ R2 = 10.15 kΩ
Question6:There is something wrong with this amplifier circuit. Note the relative amplitudes of
the input and output signals as measured by an oscilloscope:

This circuit used to function perfectly, but then began to malfunction in this manner: producing
a "clipped" output waveform of excessive amplitude. Determine the approximate amplitude
that the output voltage waveform should be for the component values given in this circuit, and
then identify possible causes of the problem and also elements of the circuit that you know
cannot be at fault
Answer: Vout (ideal) = 1.01 volts RMS
I'll let you determine possible faults in the circuit! From what we see here, we know the power
supply is functioning (both +V and -V rails) and that there is good signal getting to the
noninverting input of the opamp.

Question:
Suppose a technician is checking the operation of the following
electronic circuit:

She decides to measure the voltage on either side of resistor R1 with

reference to ground, and obtains these readings:
On the top side of R1, the voltage with reference to ground is -5.04 volts. On the bottom side of
R1, the voltage with reference to ground is -1.87 volts. The color code of resistor R1 is Yellow,
Violet, Orange, Gold. From this information, determine the following:
Voltage across R1 (between top to bottom):
Polarity (+ and -) of voltage across R1:
Current (magnitude) through R1:
Direction of current through R1:
Additionally, explain how this technician would make each one of these determinations. What
rules or laws of electric circuits would she apply?
Voltage across R1 (between top to bottom):
Answer: Voltage across R1 (between top to bottom): 3.17 volts
Polarity (+ and -) of voltage across R1: (-) on top, (+) on bottom
Current (magnitude) through R1: 67.45 μA
Direction of current through R1: upward, following conventional flow

Follow-up question: calculate the range of possible currents, given the specified tolerance of
resistor R1 (67.45 μA assumes 0% error).
Challenge question: if you recognize the type of circuit this is (by the part number of the IC
"chip": TL082), identify the voltage between pin 3 and ground
3.17 volts
 Question 7:
Determine the output voltage polarity of this op-amp (with reference to ground), given the
following input conditions:

Answer:

In these illustrations, I have likened the op-amp's action to that of a single-pole, double-
throw switch, showing the "connection" made between power supply terminals and the output
terminal.
 Notes:
Determining which "way" the output of an op-amp drives under different input voltage
conditions is confusing to many students. Discuss this with them, and ask them to
present any principles or analogies they use to remember "which way is which

An operational amplifier is a particular type of differential amplifier. Most op-amps receive

two input voltage signals and output one voltage signal:

Here is a single op-amp, shown under two different conditions (different input voltages).
Determine the voltage gain of this op-amp, given the conditions shown:
Also, write a mathematical formula solving for differential voltage gain (AV) in terms of an op-
amp's input and output voltages.

Answer: AV = 530,000
∆Vout
AV =
∆(Vin2 − Vin1)

Follow-up question: convert this voltage gain figure (as a ratio) into a voltage gain
figure in decibels
Notes:
The calculations for voltage gain here are not that different from the voltage gain calculations
for any other amplifier, except that here we're dealing with a differential amplifier instead of a
single-ended amplifier.
A differential voltage gain of 530,000 is not unreasonable for a modern operational amplifier! A
gain so extreme may come as a surprise to many students, but they will discover later the
utility of such a high gain.
Question9: In this circuit, an op-amp turns on an LED if the proper input voltage conditions are
met:

Trace the complete path of current powering the LED. Where, exactly, does the LED get its
power from?
Answer:
The arrows shown in this diagram trace "conventional" current flow, not electron flow:

Notes:
The important thing to note here is that the load current does not pass through either of
the op-amp's input terminals. All load current is sourced by the op-amp's power supply!
Discuss the importance of this fact with your students.
Use circuit simulation software to verify your predicted and measured parameter values.

Notes:
Use a dual-voltage, regulated power supply to supply power to the opamp. I recommend
using a ßlow" op-amp to make the slewing more easily noticeable. If a student chooses a
relatively fast-slew op-amp such as the TL082, their signal frequency may have to go up
into the megahertz range before the slewing becomes evident. At these speeds, parasitic
inductance and capacitance in their breadboards and test leads will cause bad "ringing" and
other artifacts muddling the interpretation of the circuit's performance.
I have had good success using the following values:

Answer:+V = +12 volts; -V = -12 volts ; Vin = 4 V peak-to-peak, at 300 kHz U1 = one-
half of LM1458 dual operational amplifier
 An extension of this exercise is to incorporate troubleshooting
questions. Whether using this exercise as a performance assessment
or simply as a concept-building lab, you might want to follow up your
students' results by asking them to predict the consequences of certain
circuit faults
Question 12:

Reveal Answer Use circuit simulation software to verify your predicted and measured parameter
values.

Notes:
The purpose of this exercise is to empirically determine the gain-bandwidth product (GBW)
of a closed-loop opamp amplifier circuit by setting it up for three different closed-loop gains
(ACL), measuring the cutoff frequency (f−3dB) at those gains, and calculating the product of
the two (ACL f−3dB) at each gain. Since this amplifier is DC-coupled, there is no need to
measure a lower cutoff frequency in order to calculate bandwidth, just the high cutoff
frequency.
What GBW tells us is that any opamp has the tendency to act as a low-pass filter, its cutoff
frequency being dependent on how much gain we are trying to get out of the opamp. We
can have large gain at modest frequencies, or a high bandwidth at modest gain, but not
both! This lab exercise is designed to let students see this limitation. As they set up their
opamp circuits with greater and greater gains ([(R2)/(R1)] + 1), they will notice the opamp
"cut off" like a low-pass filter at lower and lower frequencies.
For the "given" value of unity-gain frequency, you must consult the datasheet for the opamp
you choose. I like to use the popular TL082 BiFET opamp for a lot of AC circuits, because it
delivers good performance at a modest price and excellent availability. However, the GBW
for the TL082 is so high (3 MHz typical) that breadboard and wiring layout become issues
when testing at low gains, due to the resulting high frequencies necessary to show cutoff.
The venerable 741 is a better option because its gain-bandwidth product is significantly
lower (1 to 1.5 MHz typical).
It is very important in this exercise to maintain an undistorted opamp output, even when
the closed-loop gain is very high. Failure to do so will result in the f−3dB points being skewed
by slew-rate limiting. What we're looking for here are the cutoff frequencies resulting from
loss of small-signal open-loop gain (AOL) inside the opamp. To maintain small-signal status,
we must ensure the signal is not being distorted!
Some typical values I was able to calculate for GBW product are 3.8 ×106 for the BiFET
TL082, 1.5 ×106 for the LM1458, and around 800 ×103 for the LM741C.
An extension of this exercise is to incorporate troubleshooting questions. Whether using this
exercise as a performance assessment or simply as a concept-building lab, you might want
to follow up your students' results by asking them to predict the consequences of certain
circuit faults.
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