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(2) The adder-subtractor circuit (shown

in next slide) has the following values
for mode input M and the data inputs A
and B. M
A B
(a) 0 0111 0101
(b) 0 1011 1001
(c) 1 1100 1000
(d) 1 0101 1010
(e) 1 0000 0001

In each case, determine the values of four

SUM outputs, the carry C and overflow V.
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Boolean Function implementation

1. F (X,Y,Z) = ∑ (1, 3, 5, 6, 7) using (a) 4:1

MUX and (b) 2:1 MUX

2. F (A, B, C, D) = ∑ (1, 3, 4, 11, 12, 13, 14, 15)

Using (a) 8:1 MUX and (b) 4:1 MUX

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3. The logic function implemented by the

circuit below is (Note : Ground implies logic
‘0’)

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4. The Boolean function realized by logic

function shown is

(A) F = ∑ (0,1,3,5,9,10,14) (B) F = ∑ (2,3,5,7,8,12,13)

(C) F = ∑ (1,2,4,5,11,14,15) (D) F = ∑ (2,3,5,7,8,9,12)

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(5) Design a Full-adder using two 4:1 Multiplexers

(6) In digital system it is often necessary to have

circuits that can shift the bits of a vector by one
or more bit positions to the right or left.
Design a circuit that can shift a four bit vector
W = w3w2w1w0 one bit position to the right
when a control signal shift is equal to 1.
Hint : Implement with 2:1 multiplexers and use
shift signal as the select input to each multiplier

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(7) Design a 4 to 16 decoder by using a
minimum number of 2 to 4 decoders. The 2
to 4 decoders have an enable input (‘1’ =
enabled). Name the inputs A3A2A1A0 and the
outputs D15……D0. Do not draw the internal
circuit diagrams for the decoders.

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Solution
Let the outputs of the circuit to be a four bit
vector Y = y3y2y1y0 and a signal k, such that if shift
= 1 then y3 = 0, y2 = w3, y1 = w2, y0 = w1 and k = w0

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If shift = o then Y = W and k = 0

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(8) Design a magnitude comparator circuit for 2-
bit binary numbers A = A1A0 and B = B1B0.
The outputs are G, E and L, where G is 1 if
A>B, E = 1, if A=B and L=1 if A<B.

(i) Fill in the truth table for the three

outputs of the comparator and
determine their functions as sum of
minterms

(ii) Implement the comparator design using

a 4 to 16 decoder
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Thank You

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