The Ministry of Education and Science of Ukraine

National Aviation University

Electronic department

Course project

Digital voltmeter

Made by: Hamza Oun

Group: IAN406

Supervisor: Bidniy M.S.

Kiev-2017
 CONTENT

1. Introduction to digital voltmeter (DVM)................................................................1

2. RAMP TYPE DVM...................................................................................................1
2.1. Principle and Construction..........................................................................1
2.2. Timing Diagram of Ramp type DVM.........................................................1
3. DIGITAL VOLTMETER.........................................................................................1
4. CHOOSING MICROCONTROLLER AND REVIEWING ITS
ARCHITECTURE AND OTHER CIRCUIT ELEMENTS........................................1
4.1. Overview of the microcontroller ATmega 8...............................................1
4.1.1. Pin Configurations.........................................................................................1
4.1.2. Atmel AVR CPU Core.............................................................................1
4.1.3. Status Register..........................................................................................1
4.1.4. General Purpose Register File..................................................................1
4.2. 7-Segment LED Controller..........................................................................1
4.2.1. Features and Overview.............................................................................1
4.2.2. Functional Description.............................................................................1
References........................................................................................................................1
Appendix A.......................................................................................................................1
Listing of the program....................................................................................................1
Appendix B.......................................................................................................................1
Principal scheme in Proteus...........................................................................................1
Appendix C.......................................................................................................................1
Layout of the circuit board in Proteus..........................................................................1

1
 1. Introduction to digital voltmeter (DVM)

It is a device used for measuring the magnitude of direct current (DC) voltage.
alternating current (AC) voltage can be measured after rectification and conversion to
DC forms. DC/AC currents can be measured by passing them through a known
resistance (internally or externally connected) and determining the voltage developed
across the resistance (V=I*R).
The result of the measurement is displayed on a digital readout in numeric form
as in the case of the counters. Most DVMs use the principle of time period
measurement. Hence, the voltage is converted into a time interval ''t'' first. No frequancy
division is involved. Input range selection automatically changes the position of the
decimal point on the display. The unit of measure is also highlighted in most devices to
simplify the reading and annotation.
The working of a digital voltmeter as follows (the block diagram of the
voltmeter is shown in Fig.1):
 Unknown voltage signal is fed to the pulse generator which generates a
pulse whose width is proportional to the input signal.
 Output of pulse generator is fed to one leg of the AND gate.
 The input signal to the other leg of the AND gate is a train of pulses.
 Output of AND gate is positive triggered train of duration same as the
width of the pulse generated by the pulse generator.
 This positive triggered train is fed to the inverter which converts it into a
negative triggered train.
 Output of the inverter is fed to a counter which counts the number of
triggers in the duration which is proportional to the input signal i.e. voltage under
measurement.
 Thus, counter can be calibrated to indicate voltage in volts directly.
We can see the working of digital voltmeter that it is nothing but an analog to
digital converter which converts an analog signal into a train of pulses, the number of

2
which is proportional to the input signal. So a digital voltmeter can be made by using
any one of the A/D conversion methods.

Fig.1. Block diagram voltmeter

On the basis of A/D conversion method used digital voltmeters can be classified as:
 Ramp type digital voltmeter
 Integrating type voltmeter
 Potentiometric type digital voltmeters
 Successive approximation type digital voltmeter
 Continuous balance type digital voltmeter

Advantages

 Read out of DVM is easy as it eliminates observational errors in

measurement committed by operators.
 Error on account of parallax and approximation is entirely eliminated.
 Reading can be taken very fast.
 Output can be fed to memory devices for storage and future computations.
 Versatile and accurate
 Compact and cheap
 Low power requirements
 Portability increased

3
 2. RAMP TYPE DVM

The block diagram of the Ramp type ADC is given below (Fig.2). The principle
and working of the Ramp type ADC is explained in a simplified manner in this post.
The merits and demerits of the Ramp type ADC is also listed at the end of the
post.

Fig.2. Block diagram Ramp type DVM.

2.1. Principle and Construction

Principle:
Input voltage is converted into digital equivalent by counting the time taken for
the ramp wave to decrease from the magnitude of input voltage to 0V.
Construction:
The block diagram of the Ramp-type ADC can be divided into two sections as
follows:
1. Voltage to time conversion section;
2. Time measurement section.
The ramp type DVM (digital voltmeter) uses a linear ramp or staircase ramp
technique. The staircase ramp technique is a simpler version of linear ramp technique.
The ramp type DVM consists of linear ramp this ramp may be positive or negative
going. The swing of ramp take place between + 12 V and – 12 V. As shown in above

4
figure the attenuator is placed at the input side and the output of attenuator is connected
to input comparator. The ramp signal generated by the ramp generator which is given to
both the comparator first and second respectively. The output signal of two comparators
is given to the logic control unit which is used to open or close the gate. The number of
pulses which has to be counted is given by the local oscillator. The output of logic gate
is connected across to the counter and digital readout.
It counts the numbers of impulses and hence the duration and display the value of
voltage on LED or LCD display after calibrating it.

2.2. Timing Diagram of Ramp type DVM

The working principle i.e., the Conversion from a voltage to a time interval is
illustrated by the waveform in (Fig.3).

Fig.3. Timing Diagram of Ramp type DVM

At the start of the measurement cycle, a ramp voltage is initiated; this voltage can
be positive-going or negative-going. The negative-going ramp, see in (Fig.3) is
continuously compared with the unknown input voltage. At the instant that the ramp
voltage equals the unknown voltage, a coincidence circuit, or comparator, generates a
pulse which opens a gate. The ramp voltage continues to decrease with time until it
finally reaches 0 V (or ground potential) and a second comparator generates an output
pulse which closes the gate. An oscillator generates clock pulses which are allowed to
5
pass through the gate to a number of decade counting units (DCUs) which totalize the
number of pulses passed through the gate. The decimal number, displayed by the
indicator tubes associated with the DCUs, is a measure of the magnitude of the input
voltage.
The sample-rate multivibrator determines the rate at which the measurement
cycles are initiated. The oscillation of this multivibrator can usually be adjusted by a
front-panel control, marked rate, from a few cycles per second to as high 1,000 or more.
The sample-rate circuit provides an initiating pulse for the ramp generator to start its
next ramp voltage. At the same time, a reset pulse is generated which returns all the
DCUs to their 0 state, removing the display momentarily from the indicator tubes.
Analog to Digital Converter Block Schematic Operation is shown in Fig.4.

6
Fig.4

7
 3. DIGITAL VOLTMETER

A digital voltmeter, or DVM, is used to take highly accurate voltage

measurements. These instruments measure the electrical potential difference between
two conductors in a circuit. DVMs are electric voltmeters, and the preferred standard, as
they offer several benefits over their analog counterparts.
Voltmeters are used to measure the gain or loss of voltage between two points in a
circuit. The leads are connected in parallel on each side of the circuit being tested. The
positive terminal of the meter should be connected closest to the power supply. In turn,
the negative terminal would be connected after the circuit being tested. The analog dial
or digital display will exhibit the voltage measurement.
A digital voltmeter typically consists of an analog to digital converter (A/D) with
a digital display. The analog signal is converted into a digital code proportionate to the
magnitude of the signal. Voltages from picovolts to megavolts are measurable, though
the scale usually graduates in millivolts, volts, or kilovolts. Frequencies between zero
and several megahertz may also be measured. DVMs measure both alternating current
(AC) and direct current (DC) in electronics.
Common laboratory and commercial applications involve electromechanical
machinery with a current flowing through wires and circuits. Often, a digital voltmeter
is used to monitor a unit, such as a generator.
Portable or handheld devices, such as the digital multimeter (DMM), for example,
may combine several functions into one instrument measuring voltage, current, and
resistance. This is the preferred tool of an electrician. Many DVMs integrate outputs for
monitoring, controlling, transmitting, and printing of data.
Advanced systems are often connected to computers, allowing for automation,
optimization of processes, and prevention of malfunctions and critical failure safeties.
Chemical plants can convert measurements to voltage, and control and monitor
temperature, pressure, level, or flow. Medical equipment, such as x-ray machines, may
use a digital voltmeter to make sure the voltage of the equipment is in the proper range.

8
 4. CHOOSING MICROCONTROLLER AND REVIEWING ITS
ARCHITECTURE AND OTHER CIRCUIT ELEMENTS

The digital voltmeter design uses a microcontroller which is said to be highly

efficient in handling the data carrier operation in terms of being faster, error-free and
accurate. Rather than using the absolute analog ways of finding out the voltages, the
digital voltmeter provides much more precise and accurate values of voltages in a given
circuit in the range of the voltmeter.
In our case, to build a digital voltmeter we will use the microcontroller of the
company Atmel – ATmega8.

4.1. Overview of the microcontroller ATmega 8

Introduction

The Atmel® ATmega8A is a low-power CMOS 8-bit microcontroller based on

the AVR® enhanced RISC architecture. By executing powerful instructions in a single
clock cycle, the ATmega8A achieves throughputs close to 1MIPS per MHz. This
empowers system designer to optimize the device for power consumption versus
processing speed.
Features:

• High-performance, Low-power Atmel AVR 8-bit Microcontroller

• Advanced RISC Architecture
– 130 Powerful Instructions - Most Single-clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16MIPS Throughput at 16MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments
– 8KBytes of In-System Self-programmable Flash program memory
– 512Bytes EEPROM
– 1KByte Internal SRAM
9
 – Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• Atmel QTouch® library support
– Capacitive touch buttons, sliders and wheels
– Atmel QTouch and QMatrix acquisition
– Up to 64 sense channels
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and
Capture Mode
– Real Time Counter with Separate Oscillator
– Three PWM Channels
– 8-channel ADC in TQFP and QFN/MLF package
• Eight Channels 10-bit Accuracy
– 6-channel ADC in PDIP package
• Six Channels 10-bit Accuracy
– Byte-oriented Two-wire Serial Interface
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources

10
 – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Standby
• I/O and Packages
– 23 Programmable I/O Lines
– 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
• Operating Voltages
– 2.7 - 5.5V
• Speed Grades
– 0 - 16MHz
• Power Consumption at 4MHz, 3V, 25°C
– Active: 3.6mA
– Idle Mode: 1.0mA
– Power-down Mode: 0.5μA

4.1.1. Pin Configurations

In fig. 5 shows a chart of foam placement, and the table shows their description:

Fig.5.

11
Pin Descriptions
VCC Digital supply voltage
GND Ground.
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors
XTAL1/XTAL2/TOSC1 (selected for each bit). The Port B output buffers have symmetrical drive
/ TOSC2 characteristics with both high sink and source capability. As inputs, Port B
pins that are externally pulled low will source current if the pull-up resistors
are activated. The Port B pins are tri-stated when a reset condition becomes
active, even if the clock is not running. Depending on the clock selection
fuse settings, PB6 can be used as input to the inverting Oscillator amplifier
and input to the internal clock operating circuit. Depending on the clock
selection fuse settings, PB7 can be used as output from the inverting
Oscillator amplifier. If the Internal Calibrated RC Oscillator is used as chip
clock source, PB7..6 is used as TOSC2..1 input for the Asynchronous
Timer/Counter2 if the AS2 bit in ASSR is set.
Port C (PC5..PC0) Port C is an 7-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port C output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port C
pins that are externally pulled low will source current if the pull-up resistors
are activated. The Port C pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
´
PC6/ RESET If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that
the electrical characteristics of PC6 differ from those of the other pins of
Port C. If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset
input. A low level on this pin for longer than the minimum pulse length will
generate a Reset, even if the clock is not running.
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port D output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port D
pins that are externally pulled low will source current if the pull-up resistors
are activated. The Port D pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
´
RESET Reset input. A low level on this pin for longer than the minimum pulse
length will generate a reset, even if the clock is not running.
AVCC AVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and
ADC (7..6). It should be externally connected to V CC, even if the ADC is not
used. If the ADC is used, it should be connected to V CC through a low-pass
filter.
AREF AREF is the analog reference pin for the A/D Converter.
ADC7..6 (TQFP and In the TQFP and QFN/MLF package, ADC7..6 serve as analog inputs to the
QFN/MLF Package A/D converter. These pins are powered from the analog supply and serve as
Only) 10-bit ADC channels

12
 4.1.2. Atmel AVR CPU Core

The main function of the CPU core is to ensure correct program execution. The
CPU must therefore be able to access memories, perform calculations, control
peripherals, and handle interrupts.
In Fig. 6. shows block diagram of the AVR MCU Architecture:

Fig.6

In order to maximize performance and parallelism, the AVR uses a Harvard

architecture – with separate memories and buses for program and data. Instructions in
the Program memory are executed with a single level pipelining. While one instruction
is being executed, the next instruction is pre-fetched from the Program memory. This
concept enables instructions to be executed in every clock cycle. The Program memory
is In-System Reprogrammable Flash memory.

13
 The fast-access Register File contains 32 × 8-bit general purpose working
registers with a single clock cycle access time. This allows single-cycle Arithmetic
Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from
the Register File, the operation is executed, and the result is stored back in the Register
File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register
pointers for Data Space addressing – enabling efficient address calculations. One of
these address pointers can also be used as an address pointer for look up tables in Flash
Program memory. These added function registers are the 16-bit X-register, Y-register,
and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a
constant and a register. Single register operations can also be executed in the ALU.
After an arithmetic operation, the Status Register is updated to reflect information about
the result of the operation.
The Program flow is provided by conditional and unconditional jump and call
instructions, able to directly address the whole address space. Most AVR instructions
have a single 16-bit word format. Every Program memory address contains a 16-bit or
32-bit instruction.
Program Flash memory space is divided in two sections, the Boot program
section and the Application program section. Both sections have dedicated Lock Bits for
write and read/write protection. The SPM instruction that writes into the Application
Flash memory section must reside in the Boot program section.
During interrupts and subroutine calls, the return address Program Counter (PC)
is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and
consequently the Stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O
space. The data SRAM can easily be accessed through the five different addressing
modes supported in the AVR architecture.

14
 The memory spaces in the AVR architecture are all linear and regular memory
maps.
A flexible interrupt module has its control registers in the I/O space with an
additional global interrupt enable bit in the Status Register. All interrupts have a
separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in
accordance with their Interrupt Vector position. The lower the Interrupt Vector address,
the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as
Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed
directly, or as the Data Space locations following those of the Register File, 0x20 -
0x5F.

4.1.3. Status Register

The Status Register contains information about the result of the most recently
executed arithmetic instruction. This information can be used for altering program flow
in order to perform conditional operations. Note that the Status Register is updated after
all ALU operations, as specified in the Instruction Set Reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster
and more compact code. The Status Register is not automatically stored when entering
an interrupt routine and restored when returning from an interrupt. This must be handled
by software. The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set
for the interrupts to be enabled. The individual interrupt enable control is then
performed in separate control registers. If the Global Interrupt Enable Register is

15
cleared, none of the interrupts are enabled independent of the individual interrupt enable
settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and
cleared by the application with the SEI and CLI instructions, as described in the
Instruction Set Reference.
• Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and
BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a
register in the Register File can be copied into T by the BST instruction, and a bit in T
can be copied into a bit in a register in the Register File by the BLD instruction.
• Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in
some arithmetic operations. Half Carry is useful in BCD arithmetic.
• Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the
Negative Flag N and the Two’s Complement Overflow Flag V.
• Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement
Overflow Flag V supports two’s complement arithmetics.
• Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an
arithmetic or logic operation.
Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or
logic operation.
• Bit 0 – C: Carry Flag The Carry Flag C indicates a Carry in an arithmetic or
logic operation.

4.1.4. General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In
order to achieve the required performance and flexibility, the following input/output
schemes are supported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input

16
 • Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input Figure 7 shows the
structure of the 32 general purpose working registers in the CPU.

Fig.7. AVR CPU General Purpose Working Registers

4.2. 7-Segment LED Controller

4.2.1. Features and Overview

Supports 1 to 8 Digits
Any combination of individual displays up to 8 total digits
Displays both hex and integer values
Supports decimal points built into 7-Segment display
Supports both common cathode and common anode displays
Configurable for both Active High and Active Low segment and digit drives
In Fig. 8. shows LED7SEG Block Diagram:

17
 Fig.8

4.2.2. Functional Description

The LED7SEG User Module is capable of multiplexing up to eight 7-segment

displays. This user module is compatible with common cathode, common anode, or any
drive polarity. This allows a wide range of flexibility with various displays. Digits and
segments may be driven directly by PSoC pins without the use of transistors or drivers
as long as the current sinking and sourcing limits of the PSoC pins are not exceeded.
The following diagram shows how common anode and cathode 7-segment displays are
configured (Fig.9):

Fig.9. 7-Segment Display Configurations

The project using the LED7SEG User Module that manipulates pins on a port
shared with an instance of the LED7SEG must avoid direct PRTxDR writes. Use
Shadow Registers for such manipulation to prevent incorrect LED7SEG operation.
In our case we will use the 7seg-mpx4-cc.
Listing of the program is given in Appendix A. The software is written in C,
compilation and debugging done in AVR Studio.

18
 References
1. https://www.electrical4u.com/digital-voltmeters-working-principle-of-
digital-voltmeter/
2. https://www.snscourseware.org/snsct/files/CW_595a0f395d88c/DIGITAL
%20VOLTMETER.pdf
3. http://bu.edu.eg/portal/uploads/Engineering,%20Shoubra/Electrical
%20Engineering/823/crs-14019/Files/lecture1_DVM_handout.pdf
4. ATmega8 Datasheet Complete.
5. www.cypress.com/file/132516. 7-Segment LED Controller.

19
Appendix A
Listing of the program

// AVR Core Clock frequency: 4,000000 MHz

#include <mega8.h>

#include <delay.h>

#define ADC_VREF_TYPE 0xC0

unsigned int read_adc(unsigned char adc_input)

ADMUX=adc_input | (ADC_VREF_TYPE & 0xff);

delay_us(10);

ADCSRA|=0x40;

while ((ADCSRA & 0x10)==0);

ADCSRA|=0x10;

return ADCW;

unsigned int in=0;

float c=0;

static flash unsigned char digit[] = {

(0b00111111), // 0

(0b00000110), // 1

(0b01011011), // 2

(0b01001111), // 3

(0b01100110), // 4

(0b01101101), // 5

(0b01111101), // 6
20
 (0b00000111), // 7

(0b01111111), // 8

(0b01101111), // 9

};

void indf(int first1){

int first2=0;

int first3=0;

int first4=0;

if (first1>=1000) {

while (first1>=1000){

first1-=1000;

first4++;

if (first1>=100) {

while (first1>=100){

first1-=100;

first3++;

if (first1>=10) {

while (first1>=10){

first1-=10;

first2++;

21
 }

PORTC.1=1;

PORTB=digit[first4];

delay_ms(5);

PORTC.1=0;

PORTC.2=1;

PORTD.0=1;

PORTB=digit[first3];

delay_ms(5);

PORTC.2=0;

PORTC.3=1;

PORTD.0=0;

PORTB=digit[first2];

delay_ms(5);

PORTC.3=0;

PORTC.4=1;

PORTD.0=0;

PORTB=digit[first1];

delay_ms(5);

PORTC.4=0;

PORTD.0=0;

void main(void)

PORTB=0x00;

22
DDRB=0b01111111;

PORTC=0x00;

DDRC=0b01111110;

PORTD=0x00;

DDRD=0x00;

MCUCR=0x00;

ADMUX=ADC_VREF_TYPE & 0xff;

ADCSRA=0x85;

while (1)

c=(int)read_adc(0);

in=(int) c*9.68;

indf(in);

};

23
Appendix B
Principal scheme in Proteus

RV1(2)
VCC

RV1 R4
RV2 10k
88%

R5 Q1
1k
100%

BC547
10k
U1
10k 14 23
15
PB0/ICP1 PC0/ADC0
24
R3
PB1/OC1A PC1/ADC1
16 25 10k
PB2/SS/OC1B PC2/ADC2
17 26
PB3/MOSI/OC2 PC3/ADC3
18 27
PB4/MISO PC4/ADC4/SDA
19 28
PB5/SCK PC5/ADC5/SCL
+88.8 R10 9
PB6/TOSC1/XTAL1 PC6/RESET
1
R6 Q2
Volts 100k 10 BC547
PB7/TOSC2/XTAL2
2 10k
PD0/RXD
3
PD1/TXD
4
PD2/INT0
5
PD3/INT1
6
PD4/T0/XCK
11
R2
PD5/T1
21 12 10k
AREF PD6/AIN0
20 13
VCC

AVCC PD7/AIN1
ATMEGA8
C1 R7 Q3
100n BC547
10k
R11
2k7
R1
10k

R8 Q4
BC547
10k

RV1(2)
VCC

RV1 R4
RV2 10k
100%

R5 Q1
1k
100%

BC547
10k
U1
10k 14 23
15
PB0/ICP1 PC0/ADC0
24
R3
PB1/OC1A PC1/ADC1
16 25 10k
PB2/SS/OC1B PC2/ADC2
17 26
PB3/MOSI/OC2 PC3/ADC3
18 27
PB4/MISO PC4/ADC4/SDA
19 28
PB5/SCK PC5/ADC5/SCL
+99.0 R10 9
PB6/TOSC1/XTAL1 PC6/RESET
1
R6 Q2
Volts 100k 10 BC547
PB7/TOSC2/XTAL2
2 10k
PD0/RXD
3
PD1/TXD
4
PD2/INT0
5
PD3/INT1
6
PD4/T0/XCK
11
R2
PD5/T1
21 12 10k
AREF PD6/AIN0
20 13
VCC

AVCC PD7/AIN1
ATMEGA8
C1 R7 Q3
100n BC547
10k
R11
2k7
R1
10k

R8 Q4
BC547
10k

24
Appendix C
Layout of the circuit board in Proteus

25
 Поз.познач
Найменування Кіл. Примітка
.

Microcontroller
ATmega8 1

Transistor
Q1, Q2,Q3,Q4 4

Рotentiometer
RV1 1kOm 1
RV2 10kOm 1
Resistor
R1-R8 10k Ом±1,0% 8

R10 100k Ом±1,0% 1

R11 100k Ом±1,0% 1

Capacitor

C1 100 nF±5% 1

National Aviation University

Змн. Арк. № докум. Підпис Дата
Розроб. Oun H.A. Літ. Арк. Аркушів
Перевір. Bidniy M.S. SPECIFICATION
Реценз. 26
Н. Контр. 406 6.050802
Затверд.