Registers and Counters

In this topic we will be covering

• Registers
• Counters
PIPO (Parallel in/Parallel Out Register)
• The operation of most digital systems involves the transfer of
data from one part of the system to another, manipulating the
data and sending the modified data on to the next processing
stage. Register
Data 0 Data
1
1
0

• A register allows the data to be temporarily stored so that it

may be accessed by a processing circuit.

• Note with parallel data transmission all bits are sent at the
same time
PIPO (Parallel in/Parallel Out Register)
As an example, we show a 4-bit transparent register1 made by connecting in
parallel four clocked D-type latches.
Q0 Q1 Q2 Q3

D Q D Q D Q D Q
CLK C C C C
(load)

D0 D1 D2 D3

The clock inputs of the latches are tied together and are controlled from one
clock source. The data input of this register comprises D0–D3. These are
presented at the same time to the D inputs of the latches. The data is loaded
into (or transferred across) the register at the low-to-high transition of the
clock.
1It is transparent because what is placed at the D input appears at the output when the clock goes high.
PIPO (Parallel in/Parallel Out Register)
Registers of this type are called parallel-in/parallel-out registers (PIPO).

Commercially available devices are the 74174 (6-bit) and 74373 (octal D-type
transparent latches with tri-state output).

OC
OC 1 20 VCC
C
1Q 2 19 8Q
1D 3 18 8D G
1Q
2D 4 17 7D 1D D
2Q 5 16 7Q
3Q 6 15 6Q
3D 7 14 6D
4D 8 13 5D
4Q 9 12 5Q
G
GND 10 11 C 8Q
8D D

Output control input is used to latch the input data across to the output. This
signal is active low and therefore a 0 at OC latches the data from the input to
the output. A 1 at this pin causes the output lines to be put in the high-
impedance state (tri-state).
Shift Registers
• As an alternative to moving data in a parallel word format,
with one signal line for each bit of the word, we can use serial
transmission where the bits of the word are sent sequentially
along one line.

• A shift register provides a means of storing data and

converting between parallel and serial format.

Q3 Q2 Q1 Q0

D in D Q D Q D Q D Q
CLK C C C C
(load)
Shift Registers
The D-type flip-flops in this register are initially reset, that is, initially Q0 =
Q1 = Q2 = Q3 = 0. Let Din = 1 for two clock cycles and D = 0 after that.
Figure 3.6 shows what happens for a number of clock cycles.

T1 T2 T3 T4 T5 T6
1
CLK
0
1
D in
0
1
Q3
0
1
Q2
0
1
Q1
0
1
Q0
0
Shift Registers
At each clock transition, each bit of data is shifted one place to the right.

By the sixth clock transition, all the data is shifted out of Q0 in this 4-bit register
and this data is lost.

The following functions can be performed

• Serial loading - A sequence of data values applied to the Din input can be clocked
in to fill the register. In this context, the clock input is often called the load signal.

• Serial output - If the register is originally loaded with data, this data appears one
bit at a time at Q0 as each clock pulse is applied.

• Parallel output - By connecting Q0 to Q3 to an external device or devices, the

register is able to give parallel output of its contents.

• Parallel loading - If each of the flip-flops in the register has DC set and reset
controls, then we may perform parallel loading of the register.